1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Herobrine board device tree source 4 * 5 * Copyright 2022 Google LLC. 6 */ 7 8/dts-v1/; 9 10#include "sc7280-herobrine.dtsi" 11 12/ { 13 model = "Google Herobrine (rev1+)"; 14 compatible = "google,herobrine", "qcom,sc7280"; 15}; 16 17/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ 18 19&ap_spi_fp { 20 status = "okay"; 21}; 22 23/* 24 * Although the trackpad is really part of the herobrine baseboard, we'll 25 * put the actual definition in the board device tree since different boards 26 * might hook up different trackpads (or no i2c trackpad at all in the case 27 * of tablets / detachables). 28 */ 29ap_tp_i2c: &i2c0 { 30 status = "okay"; 31 clock-frequency = <400000>; 32 33 trackpad: trackpad@15 { 34 compatible = "elan,ekth3000"; 35 reg = <0x15>; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&tp_int_odl>; 38 39 interrupt-parent = <&tlmm>; 40 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 41 42 vcc-supply = <&pp3300_z1>; 43 44 wakeup-source; 45 }; 46}; 47 48/* 49 * The touchscreen connector might come off the Qcard, at least in the case of 50 * eDP. Like the trackpad, we'll put it in the board device tree file since 51 * different boards have different touchscreens. 52 */ 53ts_i2c: &i2c13 { 54 status = "okay"; 55 clock-frequency = <400000>; 56 57 ap_ts: touchscreen@5c { 58 compatible = "hid-over-i2c"; 59 reg = <0x5c>; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; 62 63 interrupt-parent = <&tlmm>; 64 interrupts = <55 IRQ_TYPE_LEVEL_LOW>; 65 66 post-power-on-delay-ms = <500>; 67 hid-descr-addr = <0x0000>; 68 69 vdd-supply = <&ts_avdd>; 70 }; 71}; 72 73/* For nvme */ 74&pcie1 { 75 status = "okay"; 76}; 77 78/* For nvme */ 79&pcie1_phy { 80 status = "okay"; 81}; 82 83/* For eMMC */ 84&sdhc_1 { 85 status = "okay"; 86}; 87 88/* For SD Card */ 89&sdhc_2 { 90 status = "okay"; 91}; 92 93/* PINCTRL - BOARD-SPECIFIC */ 94 95/* 96 * Methodology for gpio-line-names: 97 * - If a pin goes to herobrine board and is named it gets that name. 98 * - If a pin goes to herobrine board and is not named, it gets no name. 99 * - If a pin is totally internal to Qcard then it gets Qcard name. 100 * - If a pin is not hooked up on Qcard, it gets no name. 101 */ 102 103&pm8350c_gpios { 104 gpio-line-names = "FLASH_STROBE_1", /* 1 */ 105 "AP_SUSPEND", 106 "PM8008_1_RST_N", 107 "", 108 "", 109 "", 110 "PMIC_EDP_BL_EN", 111 "PMIC_EDP_BL_PWM", 112 ""; 113}; 114 115&tlmm { 116 gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ 117 "AP_TP_I2C_SCL", 118 "SSD_RST_L", 119 "PE_WAKE_ODL", 120 "AP_SAR_SDA", 121 "AP_SAR_SCL", 122 "PRB_SC_GPIO_6", 123 "TP_INT_ODL", 124 "HP_I2C_SDA", 125 "HP_I2C_SCL", 126 127 "GNSS_L1_EN", /* 10 */ 128 "GNSS_L5_EN", 129 "SPI_AP_MOSI", 130 "SPI_AP_MISO", 131 "SPI_AP_CLK", 132 "SPI_AP_CS0_L", 133 /* 134 * AP_FLASH_WP is crossystem ABI. Schematics 135 * call it BIOS_FLASH_WP_OD. 136 */ 137 "AP_FLASH_WP", 138 "", 139 "AP_EC_INT_L", 140 "", 141 142 "UF_CAM_RST_L", /* 20 */ 143 "WF_CAM_RST_L", 144 "UART_AP_TX_DBG_RX", 145 "UART_DBG_TX_AP_RX", 146 "", 147 "PM8008_IRQ_1", 148 "HOST2WLAN_SOL", 149 "WLAN2HOST_SOL", 150 "MOS_BT_UART_CTS", 151 "MOS_BT_UART_RFR", 152 153 "MOS_BT_UART_TX", /* 30 */ 154 "MOS_BT_UART_RX", 155 "PRB_SC_GPIO_32", 156 "HUB_RST_L", 157 "", 158 "", 159 "AP_SPI_FP_MISO", 160 "AP_SPI_FP_MOSI", 161 "AP_SPI_FP_CLK", 162 "AP_SPI_FP_CS_L", 163 164 "AP_EC_SPI_MISO", /* 40 */ 165 "AP_EC_SPI_MOSI", 166 "AP_EC_SPI_CLK", 167 "AP_EC_SPI_CS_L", 168 "LCM_RST_L", 169 "EARLY_EUD_N", 170 "", 171 "DP_HOT_PLUG_DET", 172 "IO_BRD_MLB_ID0", 173 "IO_BRD_MLB_ID1", 174 175 "IO_BRD_MLB_ID2", /* 50 */ 176 "SSD_EN", 177 "TS_I2C_SDA_CONN", 178 "TS_I2C_CLK_CONN", 179 "TS_RST_CONN", 180 "TS_INT_CONN", 181 "AP_I2C_TPM_SDA", 182 "AP_I2C_TPM_SCL", 183 "PRB_SC_GPIO_58", 184 "PRB_SC_GPIO_59", 185 186 "EDP_HOT_PLUG_DET_N", /* 60 */ 187 "FP_TO_AP_IRQ_L", 188 "", 189 "AMP_EN", 190 "CAM0_MCLK_GPIO_64", 191 "CAM1_MCLK_GPIO_65", 192 "WF_CAM_MCLK", 193 "PRB_SC_GPIO_67", 194 "FPMCU_BOOT0", 195 "UF_CAM_SDA", 196 197 "UF_CAM_SCL", /* 70 */ 198 "", 199 "", 200 "WF_CAM_SDA", 201 "WF_CAM_SCL", 202 "", 203 "", 204 "EN_FP_RAILS", 205 "FP_RST_L", 206 "PCIE1_CLKREQ_ODL", 207 208 "EN_PP3300_DX_EDP", /* 80 */ 209 "SC_GPIO_81", 210 "FORCED_USB_BOOT", 211 "WCD_RESET_N", 212 "MOS_WLAN_EN", 213 "MOS_BT_EN", 214 "MOS_SW_CTRL", 215 "MOS_PCIE0_RST", 216 "MOS_PCIE0_CLKREQ_N", 217 "MOS_PCIE0_WAKE_N", 218 219 "MOS_LAA_AS_EN", /* 90 */ 220 "SD_CD_ODL", 221 "", 222 "", 223 "MOS_BT_WLAN_SLIMBUS_CLK", 224 "MOS_BT_WLAN_SLIMBUS_DAT0", 225 "HP_MCLK", 226 "HP_BCLK", 227 "HP_DOUT", 228 "HP_DIN", 229 230 "HP_LRCLK", /* 100 */ 231 "HP_IRQ", 232 "", 233 "", 234 "GSC_AP_INT_ODL", 235 "EN_PP3300_CODEC", 236 "AMP_BCLK", 237 "AMP_DIN", 238 "AMP_LRCLK", 239 "UIM1_DATA_GPIO_109", 240 241 "UIM1_CLK_GPIO_110", /* 110 */ 242 "UIM1_RESET_GPIO_111", 243 "PRB_SC_GPIO_112", 244 "UIM0_DATA", 245 "UIM0_CLK", 246 "UIM0_RST", 247 "UIM0_PRESENT_ODL", 248 "SDM_RFFE0_CLK", 249 "SDM_RFFE0_DATA", 250 "WF_CAM_EN", 251 252 "FASTBOOT_SEL_0", /* 120 */ 253 "SC_GPIO_121", 254 "FASTBOOT_SEL_1", 255 "SC_GPIO_123", 256 "FASTBOOT_SEL_2", 257 "SM_RFFE4_CLK_GRFC_8", 258 "SM_RFFE4_DATA_GRFC_9", 259 "WLAN_COEX_UART1_RX", 260 "WLAN_COEX_UART1_TX", 261 "PRB_SC_GPIO_129", 262 263 "LCM_ID0", /* 130 */ 264 "LCM_ID1", 265 "", 266 "SDR_QLINK_REQ", 267 "SDR_QLINK_EN", 268 "QLINK0_WMSS_RESET_N", 269 "SMR526_QLINK1_REQ", 270 "SMR526_QLINK1_EN", 271 "SMR526_QLINK1_WMSS_RESET_N", 272 "PRB_SC_GPIO_139", 273 274 "SAR1_IRQ_ODL", /* 140 */ 275 "SAR0_IRQ_ODL", 276 "PRB_SC_GPIO_142", 277 "", 278 "WCD_SWR_TX_CLK", 279 "WCD_SWR_TX_DATA0", 280 "WCD_SWR_TX_DATA1", 281 "WCD_SWR_RX_CLK", 282 "WCD_SWR_RX_DATA0", 283 "WCD_SWR_RX_DATA1", 284 285 "DMIC01_CLK", /* 150 */ 286 "DMIC01_DATA", 287 "DMIC23_CLK", 288 "DMIC23_DATA", 289 "", 290 "", 291 "EC_IN_RW_ODL", 292 "HUB_EN", 293 "WCD_SWR_TX_DATA2", 294 "", 295 296 "", /* 160 */ 297 "", 298 "", 299 "", 300 "", 301 "", 302 "", 303 "", 304 "", 305 "", 306 307 "", /* 170 */ 308 "MOS_BLE_UART_TX", 309 "MOS_BLE_UART_RX", 310 "", 311 "", 312 ""; 313}; 314