1*ef4fc701SSheng-Liang Pan// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*ef4fc701SSheng-Liang Pan/* 3*ef4fc701SSheng-Liang Pan * Google Evoker board device tree source 4*ef4fc701SSheng-Liang Pan * 5*ef4fc701SSheng-Liang Pan * Copyright 2022 Google LLC. 6*ef4fc701SSheng-Liang Pan */ 7*ef4fc701SSheng-Liang Pan 8*ef4fc701SSheng-Liang Pan#include "sc7280-herobrine.dtsi" 9*ef4fc701SSheng-Liang Pan 10*ef4fc701SSheng-Liang Pan/* 11*ef4fc701SSheng-Liang Pan * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES 12*ef4fc701SSheng-Liang Pan * 13*ef4fc701SSheng-Liang Pan * Sort order matches the order in the parent files (parents before children). 14*ef4fc701SSheng-Liang Pan */ 15*ef4fc701SSheng-Liang Pan 16*ef4fc701SSheng-Liang Pan&pp3300_codec { 17*ef4fc701SSheng-Liang Pan status = "okay"; 18*ef4fc701SSheng-Liang Pan}; 19*ef4fc701SSheng-Liang Pan 20*ef4fc701SSheng-Liang Pan/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ 21*ef4fc701SSheng-Liang Pan 22*ef4fc701SSheng-Liang Panap_tp_i2c: &i2c0 { 23*ef4fc701SSheng-Liang Pan status = "okay"; 24*ef4fc701SSheng-Liang Pan clock-frequency = <400000>; 25*ef4fc701SSheng-Liang Pan 26*ef4fc701SSheng-Liang Pan trackpad: trackpad@2c { 27*ef4fc701SSheng-Liang Pan compatible = "hid-over-i2c"; 28*ef4fc701SSheng-Liang Pan reg = <0x2c>; 29*ef4fc701SSheng-Liang Pan pinctrl-names = "default"; 30*ef4fc701SSheng-Liang Pan pinctrl-0 = <&tp_int_odl>; 31*ef4fc701SSheng-Liang Pan 32*ef4fc701SSheng-Liang Pan interrupt-parent = <&tlmm>; 33*ef4fc701SSheng-Liang Pan interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 34*ef4fc701SSheng-Liang Pan 35*ef4fc701SSheng-Liang Pan hid-descr-addr = <0x20>; 36*ef4fc701SSheng-Liang Pan vcc-supply = <&pp3300_z1>; 37*ef4fc701SSheng-Liang Pan 38*ef4fc701SSheng-Liang Pan wakeup-source; 39*ef4fc701SSheng-Liang Pan }; 40*ef4fc701SSheng-Liang Pan}; 41*ef4fc701SSheng-Liang Pan 42*ef4fc701SSheng-Liang Pants_i2c: &i2c13 { 43*ef4fc701SSheng-Liang Pan status = "okay"; 44*ef4fc701SSheng-Liang Pan clock-frequency = <400000>; 45*ef4fc701SSheng-Liang Pan 46*ef4fc701SSheng-Liang Pan ap_ts: touchscreen@10 { 47*ef4fc701SSheng-Liang Pan compatible = "elan,ekth6915"; 48*ef4fc701SSheng-Liang Pan reg = <0x10>; 49*ef4fc701SSheng-Liang Pan pinctrl-names = "default"; 50*ef4fc701SSheng-Liang Pan pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; 51*ef4fc701SSheng-Liang Pan 52*ef4fc701SSheng-Liang Pan interrupt-parent = <&tlmm>; 53*ef4fc701SSheng-Liang Pan interrupts = <55 IRQ_TYPE_LEVEL_LOW>; 54*ef4fc701SSheng-Liang Pan 55*ef4fc701SSheng-Liang Pan reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; 56*ef4fc701SSheng-Liang Pan 57*ef4fc701SSheng-Liang Pan vcc33-supply = <&ts_avdd>; 58*ef4fc701SSheng-Liang Pan }; 59*ef4fc701SSheng-Liang Pan}; 60*ef4fc701SSheng-Liang Pan 61*ef4fc701SSheng-Liang Pan&ap_sar_sensor_i2c { 62*ef4fc701SSheng-Liang Pan status = "okay"; 63*ef4fc701SSheng-Liang Pan}; 64*ef4fc701SSheng-Liang Pan 65*ef4fc701SSheng-Liang Pan&ap_sar_sensor0 { 66*ef4fc701SSheng-Liang Pan status = "okay"; 67*ef4fc701SSheng-Liang Pan}; 68*ef4fc701SSheng-Liang Pan 69*ef4fc701SSheng-Liang Pan&ap_sar_sensor1 { 70*ef4fc701SSheng-Liang Pan status = "okay"; 71*ef4fc701SSheng-Liang Pan}; 72*ef4fc701SSheng-Liang Pan 73*ef4fc701SSheng-Liang Pan&mdss_edp { 74*ef4fc701SSheng-Liang Pan status = "okay"; 75*ef4fc701SSheng-Liang Pan}; 76*ef4fc701SSheng-Liang Pan 77*ef4fc701SSheng-Liang Pan&mdss_edp_phy { 78*ef4fc701SSheng-Liang Pan status = "okay"; 79*ef4fc701SSheng-Liang Pan}; 80*ef4fc701SSheng-Liang Pan 81*ef4fc701SSheng-Liang Pan/* For nvme */ 82*ef4fc701SSheng-Liang Pan&pcie1 { 83*ef4fc701SSheng-Liang Pan status = "okay"; 84*ef4fc701SSheng-Liang Pan}; 85*ef4fc701SSheng-Liang Pan 86*ef4fc701SSheng-Liang Pan/* For nvme */ 87*ef4fc701SSheng-Liang Pan&pcie1_phy { 88*ef4fc701SSheng-Liang Pan status = "okay"; 89*ef4fc701SSheng-Liang Pan}; 90*ef4fc701SSheng-Liang Pan 91*ef4fc701SSheng-Liang Pan&pwmleds { 92*ef4fc701SSheng-Liang Pan status = "okay"; 93*ef4fc701SSheng-Liang Pan}; 94*ef4fc701SSheng-Liang Pan 95*ef4fc701SSheng-Liang Pan/* For eMMC */ 96*ef4fc701SSheng-Liang Pan&sdhc_1 { 97*ef4fc701SSheng-Liang Pan status = "okay"; 98*ef4fc701SSheng-Liang Pan}; 99*ef4fc701SSheng-Liang Pan 100*ef4fc701SSheng-Liang Pan/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ 101*ef4fc701SSheng-Liang Pan 102*ef4fc701SSheng-Liang Pan&ts_rst_conn { 103*ef4fc701SSheng-Liang Pan bias-disable; 104*ef4fc701SSheng-Liang Pan}; 105*ef4fc701SSheng-Liang Pan 106*ef4fc701SSheng-Liang Pan/* PINCTRL - BOARD-SPECIFIC */ 107*ef4fc701SSheng-Liang Pan 108*ef4fc701SSheng-Liang Pan/* 109*ef4fc701SSheng-Liang Pan * Methodology for gpio-line-names: 110*ef4fc701SSheng-Liang Pan * - If a pin goes to herobrine board and is named it gets that name. 111*ef4fc701SSheng-Liang Pan * - If a pin goes to herobrine board and is not named, it gets no name. 112*ef4fc701SSheng-Liang Pan * - If a pin is totally internal to Qcard then it gets Qcard name. 113*ef4fc701SSheng-Liang Pan * - If a pin is not hooked up on Qcard, it gets no name. 114*ef4fc701SSheng-Liang Pan */ 115*ef4fc701SSheng-Liang Pan 116*ef4fc701SSheng-Liang Pan&pm8350c_gpios { 117*ef4fc701SSheng-Liang Pan gpio-line-names = "FLASH_STROBE_1", /* 1 */ 118*ef4fc701SSheng-Liang Pan "AP_SUSPEND", 119*ef4fc701SSheng-Liang Pan "PM8008_1_RST_N", 120*ef4fc701SSheng-Liang Pan "", 121*ef4fc701SSheng-Liang Pan "", 122*ef4fc701SSheng-Liang Pan "", 123*ef4fc701SSheng-Liang Pan "PMIC_EDP_BL_EN", 124*ef4fc701SSheng-Liang Pan "PMIC_EDP_BL_PWM", 125*ef4fc701SSheng-Liang Pan ""; 126*ef4fc701SSheng-Liang Pan}; 127*ef4fc701SSheng-Liang Pan 128*ef4fc701SSheng-Liang Pan&tlmm { 129*ef4fc701SSheng-Liang Pan gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ 130*ef4fc701SSheng-Liang Pan "AP_TP_I2C_SCL", 131*ef4fc701SSheng-Liang Pan "SSD_RST_L", 132*ef4fc701SSheng-Liang Pan "PE_WAKE_ODL", 133*ef4fc701SSheng-Liang Pan "AP_SAR_SDA", 134*ef4fc701SSheng-Liang Pan "AP_SAR_SCL", 135*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_6", 136*ef4fc701SSheng-Liang Pan "TP_INT_ODL", 137*ef4fc701SSheng-Liang Pan "HP_I2C_SDA", 138*ef4fc701SSheng-Liang Pan "HP_I2C_SCL", 139*ef4fc701SSheng-Liang Pan 140*ef4fc701SSheng-Liang Pan "GNSS_L1_EN", /* 10 */ 141*ef4fc701SSheng-Liang Pan "GNSS_L5_EN", 142*ef4fc701SSheng-Liang Pan "SPI_AP_MOSI", 143*ef4fc701SSheng-Liang Pan "SPI_AP_MISO", 144*ef4fc701SSheng-Liang Pan "SPI_AP_CLK", 145*ef4fc701SSheng-Liang Pan "SPI_AP_CS0_L", 146*ef4fc701SSheng-Liang Pan /* 147*ef4fc701SSheng-Liang Pan * AP_FLASH_WP is crossystem ABI. Schematics 148*ef4fc701SSheng-Liang Pan * call it BIOS_FLASH_WP_OD. 149*ef4fc701SSheng-Liang Pan */ 150*ef4fc701SSheng-Liang Pan "AP_FLASH_WP", 151*ef4fc701SSheng-Liang Pan "", 152*ef4fc701SSheng-Liang Pan "AP_EC_INT_L", 153*ef4fc701SSheng-Liang Pan "", 154*ef4fc701SSheng-Liang Pan 155*ef4fc701SSheng-Liang Pan "UF_CAM_RST_L", /* 20 */ 156*ef4fc701SSheng-Liang Pan "WF_CAM_RST_L", 157*ef4fc701SSheng-Liang Pan "UART_AP_TX_DBG_RX", 158*ef4fc701SSheng-Liang Pan "UART_DBG_TX_AP_RX", 159*ef4fc701SSheng-Liang Pan "", 160*ef4fc701SSheng-Liang Pan "PM8008_IRQ_1", 161*ef4fc701SSheng-Liang Pan "HOST2WLAN_SOL", 162*ef4fc701SSheng-Liang Pan "WLAN2HOST_SOL", 163*ef4fc701SSheng-Liang Pan "MOS_BT_UART_CTS", 164*ef4fc701SSheng-Liang Pan "MOS_BT_UART_RFR", 165*ef4fc701SSheng-Liang Pan 166*ef4fc701SSheng-Liang Pan "MOS_BT_UART_TX", /* 30 */ 167*ef4fc701SSheng-Liang Pan "MOS_BT_UART_RX", 168*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_32", 169*ef4fc701SSheng-Liang Pan "HUB_RST_L", 170*ef4fc701SSheng-Liang Pan "", 171*ef4fc701SSheng-Liang Pan "", 172*ef4fc701SSheng-Liang Pan "AP_SPI_FP_MISO", 173*ef4fc701SSheng-Liang Pan "AP_SPI_FP_MOSI", 174*ef4fc701SSheng-Liang Pan "AP_SPI_FP_CLK", 175*ef4fc701SSheng-Liang Pan "AP_SPI_FP_CS_L", 176*ef4fc701SSheng-Liang Pan 177*ef4fc701SSheng-Liang Pan "AP_EC_SPI_MISO", /* 40 */ 178*ef4fc701SSheng-Liang Pan "AP_EC_SPI_MOSI", 179*ef4fc701SSheng-Liang Pan "AP_EC_SPI_CLK", 180*ef4fc701SSheng-Liang Pan "AP_EC_SPI_CS_L", 181*ef4fc701SSheng-Liang Pan "LCM_RST_L", 182*ef4fc701SSheng-Liang Pan "EARLY_EUD_N", 183*ef4fc701SSheng-Liang Pan "", 184*ef4fc701SSheng-Liang Pan "DP_HOT_PLUG_DET", 185*ef4fc701SSheng-Liang Pan "IO_BRD_MLB_ID0", 186*ef4fc701SSheng-Liang Pan "IO_BRD_MLB_ID1", 187*ef4fc701SSheng-Liang Pan 188*ef4fc701SSheng-Liang Pan "IO_BRD_MLB_ID2", /* 50 */ 189*ef4fc701SSheng-Liang Pan "SSD_EN", 190*ef4fc701SSheng-Liang Pan "TS_I2C_SDA_CONN", 191*ef4fc701SSheng-Liang Pan "TS_I2C_CLK_CONN", 192*ef4fc701SSheng-Liang Pan "TS_RST_CONN", 193*ef4fc701SSheng-Liang Pan "TS_INT_CONN", 194*ef4fc701SSheng-Liang Pan "AP_I2C_TPM_SDA", 195*ef4fc701SSheng-Liang Pan "AP_I2C_TPM_SCL", 196*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_58", 197*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_59", 198*ef4fc701SSheng-Liang Pan 199*ef4fc701SSheng-Liang Pan "EDP_HOT_PLUG_DET_N", /* 60 */ 200*ef4fc701SSheng-Liang Pan "FP_TO_AP_IRQ_L", 201*ef4fc701SSheng-Liang Pan "", 202*ef4fc701SSheng-Liang Pan "AMP_EN", 203*ef4fc701SSheng-Liang Pan "CAM0_MCLK_GPIO_64", 204*ef4fc701SSheng-Liang Pan "CAM1_MCLK_GPIO_65", 205*ef4fc701SSheng-Liang Pan "WF_CAM_MCLK", 206*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_67", 207*ef4fc701SSheng-Liang Pan "FPMCU_BOOT0", 208*ef4fc701SSheng-Liang Pan "UF_CAM_SDA", 209*ef4fc701SSheng-Liang Pan 210*ef4fc701SSheng-Liang Pan "UF_CAM_SCL", /* 70 */ 211*ef4fc701SSheng-Liang Pan "", 212*ef4fc701SSheng-Liang Pan "", 213*ef4fc701SSheng-Liang Pan "WF_CAM_SDA", 214*ef4fc701SSheng-Liang Pan "WF_CAM_SCL", 215*ef4fc701SSheng-Liang Pan "", 216*ef4fc701SSheng-Liang Pan "", 217*ef4fc701SSheng-Liang Pan "EN_FP_RAILS", 218*ef4fc701SSheng-Liang Pan "FP_RST_L", 219*ef4fc701SSheng-Liang Pan "PCIE1_CLKREQ_ODL", 220*ef4fc701SSheng-Liang Pan 221*ef4fc701SSheng-Liang Pan "EN_PP3300_DX_EDP", /* 80 */ 222*ef4fc701SSheng-Liang Pan "SC_GPIO_81", 223*ef4fc701SSheng-Liang Pan "FORCED_USB_BOOT", 224*ef4fc701SSheng-Liang Pan "WCD_RESET_N", 225*ef4fc701SSheng-Liang Pan "MOS_WLAN_EN", 226*ef4fc701SSheng-Liang Pan "MOS_BT_EN", 227*ef4fc701SSheng-Liang Pan "MOS_SW_CTRL", 228*ef4fc701SSheng-Liang Pan "MOS_PCIE0_RST", 229*ef4fc701SSheng-Liang Pan "MOS_PCIE0_CLKREQ_N", 230*ef4fc701SSheng-Liang Pan "MOS_PCIE0_WAKE_N", 231*ef4fc701SSheng-Liang Pan 232*ef4fc701SSheng-Liang Pan "MOS_LAA_AS_EN", /* 90 */ 233*ef4fc701SSheng-Liang Pan "SD_CD_ODL", 234*ef4fc701SSheng-Liang Pan "", 235*ef4fc701SSheng-Liang Pan "", 236*ef4fc701SSheng-Liang Pan "MOS_BT_WLAN_SLIMBUS_CLK", 237*ef4fc701SSheng-Liang Pan "MOS_BT_WLAN_SLIMBUS_DAT0", 238*ef4fc701SSheng-Liang Pan "HP_MCLK", 239*ef4fc701SSheng-Liang Pan "HP_BCLK", 240*ef4fc701SSheng-Liang Pan "HP_DOUT", 241*ef4fc701SSheng-Liang Pan "HP_DIN", 242*ef4fc701SSheng-Liang Pan 243*ef4fc701SSheng-Liang Pan "HP_LRCLK", /* 100 */ 244*ef4fc701SSheng-Liang Pan "HP_IRQ", 245*ef4fc701SSheng-Liang Pan "", 246*ef4fc701SSheng-Liang Pan "", 247*ef4fc701SSheng-Liang Pan "GSC_AP_INT_ODL", 248*ef4fc701SSheng-Liang Pan "EN_PP3300_CODEC", 249*ef4fc701SSheng-Liang Pan "AMP_BCLK", 250*ef4fc701SSheng-Liang Pan "AMP_DIN", 251*ef4fc701SSheng-Liang Pan "AMP_LRCLK", 252*ef4fc701SSheng-Liang Pan "UIM1_DATA_GPIO_109", 253*ef4fc701SSheng-Liang Pan 254*ef4fc701SSheng-Liang Pan "UIM1_CLK_GPIO_110", /* 110 */ 255*ef4fc701SSheng-Liang Pan "UIM1_RESET_GPIO_111", 256*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_112", 257*ef4fc701SSheng-Liang Pan "UIM0_DATA", 258*ef4fc701SSheng-Liang Pan "UIM0_CLK", 259*ef4fc701SSheng-Liang Pan "UIM0_RST", 260*ef4fc701SSheng-Liang Pan "UIM0_PRESENT_ODL", 261*ef4fc701SSheng-Liang Pan "SDM_RFFE0_CLK", 262*ef4fc701SSheng-Liang Pan "SDM_RFFE0_DATA", 263*ef4fc701SSheng-Liang Pan "WF_CAM_EN", 264*ef4fc701SSheng-Liang Pan 265*ef4fc701SSheng-Liang Pan "FASTBOOT_SEL_0", /* 120 */ 266*ef4fc701SSheng-Liang Pan "SC_GPIO_121", 267*ef4fc701SSheng-Liang Pan "FASTBOOT_SEL_1", 268*ef4fc701SSheng-Liang Pan "SC_GPIO_123", 269*ef4fc701SSheng-Liang Pan "FASTBOOT_SEL_2", 270*ef4fc701SSheng-Liang Pan "SM_RFFE4_CLK_GRFC_8", 271*ef4fc701SSheng-Liang Pan "SM_RFFE4_DATA_GRFC_9", 272*ef4fc701SSheng-Liang Pan "WLAN_COEX_UART1_RX", 273*ef4fc701SSheng-Liang Pan "WLAN_COEX_UART1_TX", 274*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_129", 275*ef4fc701SSheng-Liang Pan 276*ef4fc701SSheng-Liang Pan "LCM_ID0", /* 130 */ 277*ef4fc701SSheng-Liang Pan "LCM_ID1", 278*ef4fc701SSheng-Liang Pan "", 279*ef4fc701SSheng-Liang Pan "SDR_QLINK_REQ", 280*ef4fc701SSheng-Liang Pan "SDR_QLINK_EN", 281*ef4fc701SSheng-Liang Pan "QLINK0_WMSS_RESET_N", 282*ef4fc701SSheng-Liang Pan "SMR526_QLINK1_REQ", 283*ef4fc701SSheng-Liang Pan "SMR526_QLINK1_EN", 284*ef4fc701SSheng-Liang Pan "SMR526_QLINK1_WMSS_RESET_N", 285*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_139", 286*ef4fc701SSheng-Liang Pan 287*ef4fc701SSheng-Liang Pan "SAR1_IRQ_ODL", /* 140 */ 288*ef4fc701SSheng-Liang Pan "SAR0_IRQ_ODL", 289*ef4fc701SSheng-Liang Pan "PRB_SC_GPIO_142", 290*ef4fc701SSheng-Liang Pan "", 291*ef4fc701SSheng-Liang Pan "WCD_SWR_TX_CLK", 292*ef4fc701SSheng-Liang Pan "WCD_SWR_TX_DATA0", 293*ef4fc701SSheng-Liang Pan "WCD_SWR_TX_DATA1", 294*ef4fc701SSheng-Liang Pan "WCD_SWR_RX_CLK", 295*ef4fc701SSheng-Liang Pan "WCD_SWR_RX_DATA0", 296*ef4fc701SSheng-Liang Pan "WCD_SWR_RX_DATA1", 297*ef4fc701SSheng-Liang Pan 298*ef4fc701SSheng-Liang Pan "DMIC01_CLK", /* 150 */ 299*ef4fc701SSheng-Liang Pan "DMIC01_DATA", 300*ef4fc701SSheng-Liang Pan "DMIC23_CLK", 301*ef4fc701SSheng-Liang Pan "DMIC23_DATA", 302*ef4fc701SSheng-Liang Pan "", 303*ef4fc701SSheng-Liang Pan "", 304*ef4fc701SSheng-Liang Pan "EC_IN_RW_ODL", 305*ef4fc701SSheng-Liang Pan "HUB_EN", 306*ef4fc701SSheng-Liang Pan "WCD_SWR_TX_DATA2", 307*ef4fc701SSheng-Liang Pan "", 308*ef4fc701SSheng-Liang Pan 309*ef4fc701SSheng-Liang Pan "", /* 160 */ 310*ef4fc701SSheng-Liang Pan "", 311*ef4fc701SSheng-Liang Pan "", 312*ef4fc701SSheng-Liang Pan "", 313*ef4fc701SSheng-Liang Pan "", 314*ef4fc701SSheng-Liang Pan "", 315*ef4fc701SSheng-Liang Pan "", 316*ef4fc701SSheng-Liang Pan "", 317*ef4fc701SSheng-Liang Pan "", 318*ef4fc701SSheng-Liang Pan "", 319*ef4fc701SSheng-Liang Pan 320*ef4fc701SSheng-Liang Pan "", /* 170 */ 321*ef4fc701SSheng-Liang Pan "MOS_BLE_UART_TX", 322*ef4fc701SSheng-Liang Pan "MOS_BLE_UART_RX", 323*ef4fc701SSheng-Liang Pan "", 324*ef4fc701SSheng-Liang Pan ""; 325*ef4fc701SSheng-Liang Pan}; 326