1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sc7280 CRD 3+ board device tree source
4 *
5 * Copyright 2022 Google LLC.
6 */
7
8/dts-v1/;
9
10#include "sc7280-herobrine.dtsi"
11#include "sc7280-herobrine-audio-wcd9385.dtsi"
12
13/ {
14	model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
15	compatible = "google,hoglin", "qcom,sc7280";
16
17	/* FIXED REGULATORS */
18
19	/*
20	 * On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL.
21	 * However, on CRD there's an extra regulator in the way. Since this
22	 * is expected to be uncommon, we'll leave the "vreg_edp_bl" label
23	 * in the baseboard herobrine.dtsi point at "ppvar_sys" and then
24	 * make a "_crd" specific version here.
25	 */
26	vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
27		compatible = "regulator-fixed";
28		regulator-name = "vreg_edp_bl_crd";
29
30		gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>;
31		enable-active-high;
32		pinctrl-names = "default";
33		pinctrl-0 = <&edp_bl_reg_en>;
34
35		vin-supply = <&ppvar_sys>;
36	};
37};
38
39/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
40
41&apps_rsc {
42	pmg1110-regulators {
43		compatible = "qcom,pmg1110-rpmh-regulators";
44		qcom,pmic-id = "k";
45
46		vreg_s1k_1p0: smps1 {
47			regulator-min-microvolt = <1010000>;
48			regulator-max-microvolt = <1170000>;
49		};
50	};
51};
52
53ap_tp_i2c: &i2c0 {
54	status = "okay";
55	clock-frequency = <400000>;
56
57	trackpad: trackpad@15 {
58		compatible = "hid-over-i2c";
59		reg = <0x15>;
60		pinctrl-names = "default";
61		pinctrl-0 = <&tp_int_odl>;
62
63		interrupt-parent = <&tlmm>;
64		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
65
66		post-power-on-delay-ms = <20>;
67		hid-descr-addr = <0x0001>;
68		vdd-supply = <&pp3300_z1>;
69
70		wakeup-source;
71	};
72};
73
74&ap_sar_sensor_i2c {
75	status = "okay";
76};
77
78&ap_sar_sensor0 {
79	status = "okay";
80};
81
82&ap_sar_sensor1 {
83	status = "okay";
84};
85
86ap_ts_pen_1v8: &i2c13 {
87	status = "okay";
88	clock-frequency = <400000>;
89
90	ap_ts: touchscreen@5c {
91		compatible = "hid-over-i2c";
92		reg = <0x5c>;
93		pinctrl-names = "default";
94		pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
95
96		interrupt-parent = <&tlmm>;
97		interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
98
99		post-power-on-delay-ms = <500>;
100		hid-descr-addr = <0x0000>;
101
102		vdd-supply = <&pp3300_left_in_mlb>;
103	};
104};
105
106&mdss_edp {
107	status = "okay";
108};
109
110&mdss_edp_phy {
111	status = "okay";
112};
113
114/* For nvme */
115&pcie1 {
116	status = "okay";
117};
118
119/* For nvme */
120&pcie1_phy {
121	status = "okay";
122};
123
124&pm8350c_pwm_backlight {
125	power-supply = <&vreg_edp_bl_crd>;
126};
127
128/* For eMMC */
129&sdhc_1 {
130	status = "okay";
131};
132
133/* For SD Card */
134&sdhc_2 {
135	status = "okay";
136};
137
138/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
139
140/*
141 * This pin goes to the display panel but then doesn't actually do anything
142 * on the panel itself (it doesn't connect to the touchscreen controller).
143 * We'll set a pullup here just to park the line.
144 */
145&ts_rst_conn {
146	bias-pull-up;
147};
148
149/* PINCTRL - BOARD-SPECIFIC */
150
151/*
152 * Methodology for gpio-line-names:
153 * - If a pin goes to CRD board and is named it gets that name.
154 * - If a pin goes to CRD board and is not named, it gets no name.
155 * - If a pin is totally internal to Qcard then it gets Qcard name.
156 * - If a pin is not hooked up on Qcard, it gets no name.
157 */
158
159&pm8350c_gpios {
160	gpio-line-names = "FLASH_STROBE_1",		/* 1 */
161			  "AP_SUSPEND",
162			  "PM8008_1_RST_N",
163			  "",
164			  "",
165			  "EDP_BL_REG_EN",
166			  "PMIC_EDP_BL_EN",
167			  "PMIC_EDP_BL_PWM",
168			  "";
169
170	edp_bl_reg_en: edp-bl-reg-en {
171		pins = "gpio6";
172		function = "normal";
173		bias-disable;
174		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
175	};
176};
177
178&tlmm {
179	gpio-line-names = "AP_TP_I2C_SDA",		/* 0 */
180			  "AP_TP_I2C_SCL",
181			  "PCIE1_RESET_N",
182			  "PCIE1_WAKE_N",
183			  "APPS_I2C_SDA",
184			  "APPS_I2C_SCL",
185			  "",
186			  "TPAD_INT_N",
187			  "",
188			  "",
189
190			  "GNSS_L1_EN",			/* 10 */
191			  "GNSS_L5_EN",
192			  "QSPI_DATA_0",
193			  "QSPI_DATA_1",
194			  "QSPI_CLK",
195			  "QSPI_CS_N_1",
196			  /*
197			   * AP_FLASH_WP is crossystem ABI. Schematics call it
198			   * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the
199			   * signal is active high).
200			   */
201			  "AP_FLASH_WP",
202			  "",
203			  "AP_EC_INT_N",
204			  "",
205
206			  "CAM0_RST_N",			/* 20 */
207			  "CAM1_RST_N",
208			  "SM_DBG_UART_TX",
209			  "SM_DBG_UART_RX",
210			  "",
211			  "PM8008_IRQ_1",
212			  "HOST2WLAN_SOL",
213			  "WLAN2HOST_SOL",
214			  "MOS_BT_UART_CTS",
215			  "MOS_BT_UART_RFR",
216
217			  "MOS_BT_UART_TX",		/* 30 */
218			  "MOS_BT_UART_RX",
219			  "",
220			  "HUB_RST",
221			  "",
222			  "",
223			  "",
224			  "",
225			  "",
226			  "",
227
228			  "EC_SPI_MISO_GPIO40",		/* 40 */
229			  "EC_SPI_MOSI_GPIO41",
230			  "EC_SPI_CLK_GPIO42",
231			  "EC_SPI_CS_GPIO43",
232			  "",
233			  "EARLY_EUD_EN",
234			  "",
235			  "DP_HOT_PLUG_DETECT",
236			  "AP_BRD_ID_0",
237			  "AP_BRD_ID_1",
238
239			  "AP_BRD_ID_2",		/* 50 */
240			  "NVME_PWR_REG_EN",
241			  "TS_I2C_SDA_CONN",
242			  "TS_I2C_CLK_CONN",
243			  "TS_RST_CONN",
244			  "TS_INT_CONN",
245			  "AP_I2C_TPM_SDA",
246			  "AP_I2C_TPM_SCL",
247			  "",
248			  "",
249
250			  "EDP_HOT_PLUG_DET_N",		/* 60 */
251			  "",
252			  "",
253			  "AMP_EN",
254			  "CAM0_MCLK_GPIO_64",
255			  "CAM1_MCLK_GPIO_65",
256			  "",
257			  "",
258			  "",
259			  "CCI_I2C_SDA0",
260
261			  "CCI_I2C_SCL0",		/* 70 */
262			  "",
263			  "",
264			  "",
265			  "",
266			  "",
267			  "",
268			  "",
269			  "",
270			  "PCIE1_CLK_REQ_N",
271
272			  "EN_PP3300_DX_EDP",		/* 80 */
273			  "US_EURO_HS_SEL",
274			  "FORCED_USB_BOOT",
275			  "WCD_RESET_N",
276			  "MOS_WLAN_EN",
277			  "MOS_BT_EN",
278			  "MOS_SW_CTRL",
279			  "MOS_PCIE0_RST",
280			  "MOS_PCIE0_CLKREQ_N",
281			  "MOS_PCIE0_WAKE_N",
282
283			  "MOS_LAA_AS_EN",		/* 90 */
284			  "SD_CARD_DET_CONN",
285			  "",
286			  "",
287			  "MOS_BT_WLAN_SLIMBUS_CLK",
288			  "MOS_BT_WLAN_SLIMBUS_DAT0",
289			  "",
290			  "",
291			  "",
292			  "",
293
294			  "",				/* 100 */
295			  "",
296			  "",
297			  "",
298			  "H1_AP_INT_N",
299			  "",
300			  "AMP_BCLK",
301			  "AMP_DIN",
302			  "AMP_LRCLK",
303			  "UIM1_DATA_GPIO_109",
304
305			  "UIM1_CLK_GPIO_110",		/* 110 */
306			  "UIM1_RESET_GPIO_111",
307			  "",
308			  "UIM1_DATA",
309			  "UIM1_CLK",
310			  "UIM1_RESET",
311			  "UIM1_PRESENT",
312			  "SDM_RFFE0_CLK",
313			  "SDM_RFFE0_DATA",
314			  "",
315
316			  "SDM_RFFE1_DATA",		/* 120 */
317			  "SC_GPIO_121",
318			  "FASTBOOT_SEL_1",
319			  "SC_GPIO_123",
320			  "FASTBOOT_SEL_2",
321			  "SM_RFFE4_CLK_GRFC_8",
322			  "SM_RFFE4_DATA_GRFC_9",
323			  "WLAN_COEX_UART1_RX",
324			  "WLAN_COEX_UART1_TX",
325			  "",
326
327			  "",				/* 130 */
328			  "",
329			  "",
330			  "SDR_QLINK_REQ",
331			  "SDR_QLINK_EN",
332			  "QLINK0_WMSS_RESET_N",
333			  "SMR526_QLINK1_REQ",
334			  "SMR526_QLINK1_EN",
335			  "SMR526_QLINK1_WMSS_RESET_N",
336			  "",
337
338			  "SAR1_INT_N",			/* 140 */
339			  "SAR0_INT_N",
340			  "",
341			  "",
342			  "WCD_SWR_TX_CLK",
343			  "WCD_SWR_TX_DATA0",
344			  "WCD_SWR_TX_DATA1",
345			  "WCD_SWR_RX_CLK",
346			  "WCD_SWR_RX_DATA0",
347			  "WCD_SWR_RX_DATA1",
348
349			  "DMIC01_CLK",			/* 150 */
350			  "DMIC01_DATA",
351			  "DMIC23_CLK",
352			  "DMIC23_DATA",
353			  "",
354			  "",
355			  "EC_IN_RW_N",
356			  "EN_PP3300_HUB",
357			  "WCD_SWR_TX_DATA2",
358			  "",
359
360			  "",				/* 160 */
361			  "",
362			  "",
363			  "",
364			  "",
365			  "",
366			  "",
367			  "",
368			  "",
369			  "",
370
371			  "",				/* 170 */
372			  "MOS_BLE_UART_TX",
373			  "MOS_BLE_UART_RX",
374			  "",
375			  "",
376			  "";
377};
378