1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sc7280 CRD 3+ board device tree source 4 * 5 * Copyright 2022 Google LLC. 6 */ 7 8/dts-v1/; 9 10#include "sc7280-herobrine.dtsi" 11#include "sc7280-herobrine-audio-wcd9385.dtsi" 12 13/ { 14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; 15 compatible = "google,hoglin", "qcom,sc7280"; 16 17 /* FIXED REGULATORS */ 18 19 /* 20 * On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL. 21 * However, on CRD there's an extra regulator in the way. Since this 22 * is expected to be uncommon, we'll leave the "vreg_edp_bl" label 23 * in the baseboard herobrine.dtsi point at "ppvar_sys" and then 24 * make a "_crd" specific version here. 25 */ 26 vreg_edp_bl_crd: vreg-edp-bl-crd-regulator { 27 compatible = "regulator-fixed"; 28 regulator-name = "vreg_edp_bl_crd"; 29 30 gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>; 31 enable-active-high; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&edp_bl_reg_en>; 34 35 vin-supply = <&ppvar_sys>; 36 }; 37}; 38 39/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ 40 41&apps_rsc { 42 pmg1110-regulators { 43 compatible = "qcom,pmg1110-rpmh-regulators"; 44 qcom,pmic-id = "k"; 45 46 vreg_s1k_1p0: smps1 { 47 regulator-min-microvolt = <1010000>; 48 regulator-max-microvolt = <1170000>; 49 }; 50 }; 51}; 52 53ap_tp_i2c: &i2c0 { 54 status = "okay"; 55 clock-frequency = <400000>; 56 57 trackpad: trackpad@15 { 58 compatible = "hid-over-i2c"; 59 reg = <0x15>; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&tp_int_odl>; 62 63 interrupt-parent = <&tlmm>; 64 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 65 66 post-power-on-delay-ms = <20>; 67 hid-descr-addr = <0x0001>; 68 vdd-supply = <&pp3300_z1>; 69 70 wakeup-source; 71 }; 72}; 73 74&ap_sar_sensor_i2c { 75 status = "okay"; 76}; 77 78&ap_sar_sensor0 { 79 status = "okay"; 80}; 81 82&ap_sar_sensor1 { 83 status = "okay"; 84}; 85 86ap_ts_pen_1v8: &i2c13 { 87 status = "okay"; 88 clock-frequency = <400000>; 89 90 ap_ts: touchscreen@5c { 91 compatible = "hid-over-i2c"; 92 reg = <0x5c>; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; 95 96 interrupt-parent = <&tlmm>; 97 interrupts = <55 IRQ_TYPE_LEVEL_LOW>; 98 99 post-power-on-delay-ms = <500>; 100 hid-descr-addr = <0x0000>; 101 102 vdd-supply = <&pp3300_left_in_mlb>; 103 }; 104}; 105 106&mdss_edp { 107 status = "okay"; 108}; 109 110&mdss_edp_phy { 111 status = "okay"; 112}; 113 114/* For nvme */ 115&pcie1 { 116 status = "okay"; 117}; 118 119/* For nvme */ 120&pcie1_phy { 121 status = "okay"; 122}; 123 124&pm8350c_pwm_backlight { 125 power-supply = <&vreg_edp_bl_crd>; 126}; 127 128/* For eMMC */ 129&sdhc_1 { 130 status = "okay"; 131}; 132 133/* For SD Card */ 134&sdhc_2 { 135 status = "okay"; 136}; 137 138/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ 139 140/* 141 * This pin goes to the display panel but then doesn't actually do anything 142 * on the panel itself (it doesn't connect to the touchscreen controller). 143 * We'll set a pullup here just to park the line. 144 */ 145&ts_rst_conn { 146 bias-pull-up; 147}; 148 149/* PINCTRL - BOARD-SPECIFIC */ 150 151/* 152 * Methodology for gpio-line-names: 153 * - If a pin goes to CRD board and is named it gets that name. 154 * - If a pin goes to CRD board and is not named, it gets no name. 155 * - If a pin is totally internal to Qcard then it gets Qcard name. 156 * - If a pin is not hooked up on Qcard, it gets no name. 157 */ 158&lpass_dmic01_clk { 159 drive-strength = <8>; 160 bias-disable; 161}; 162 163&lpass_dmic01_clk_sleep { 164 drive-strength = <2>; 165}; 166 167&lpass_dmic01_data { 168 bias-pull-down; 169}; 170 171&lpass_dmic23_clk { 172 drive-strength = <8>; 173 bias-disable; 174}; 175 176&lpass_dmic23_clk_sleep { 177 drive-strength = <2>; 178}; 179 180&lpass_dmic23_data { 181 bias-pull-down; 182}; 183 184&lpass_rx_swr_clk { 185 drive-strength = <2>; 186 slew-rate = <1>; 187 bias-disable; 188}; 189 190&lpass_rx_swr_clk_sleep { 191 bias-pull-down; 192}; 193 194&lpass_rx_swr_data { 195 drive-strength = <2>; 196 slew-rate = <1>; 197 bias-bus-hold; 198}; 199 200&lpass_rx_swr_data_sleep { 201 bias-pull-down; 202}; 203 204&lpass_tx_swr_clk { 205 drive-strength = <2>; 206 slew-rate = <1>; 207 bias-disable; 208}; 209 210&lpass_tx_swr_clk_sleep { 211 bias-pull-down; 212}; 213 214&lpass_tx_swr_data { 215 drive-strength = <2>; 216 slew-rate = <1>; 217 bias-bus-hold; 218}; 219 220&pm8350c_gpios { 221 gpio-line-names = "FLASH_STROBE_1", /* 1 */ 222 "AP_SUSPEND", 223 "PM8008_1_RST_N", 224 "", 225 "", 226 "EDP_BL_REG_EN", 227 "PMIC_EDP_BL_EN", 228 "PMIC_EDP_BL_PWM", 229 ""; 230 231 edp_bl_reg_en: edp-bl-reg-en { 232 pins = "gpio6"; 233 function = "normal"; 234 bias-disable; 235 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 236 }; 237}; 238 239&tlmm { 240 gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ 241 "AP_TP_I2C_SCL", 242 "PCIE1_RESET_N", 243 "PCIE1_WAKE_N", 244 "APPS_I2C_SDA", 245 "APPS_I2C_SCL", 246 "", 247 "TPAD_INT_N", 248 "", 249 "", 250 251 "GNSS_L1_EN", /* 10 */ 252 "GNSS_L5_EN", 253 "QSPI_DATA_0", 254 "QSPI_DATA_1", 255 "QSPI_CLK", 256 "QSPI_CS_N_1", 257 /* 258 * AP_FLASH_WP is crossystem ABI. Schematics call it 259 * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the 260 * signal is active high). 261 */ 262 "AP_FLASH_WP", 263 "", 264 "AP_EC_INT_N", 265 "", 266 267 "CAM0_RST_N", /* 20 */ 268 "CAM1_RST_N", 269 "SM_DBG_UART_TX", 270 "SM_DBG_UART_RX", 271 "", 272 "PM8008_IRQ_1", 273 "HOST2WLAN_SOL", 274 "WLAN2HOST_SOL", 275 "MOS_BT_UART_CTS", 276 "MOS_BT_UART_RFR", 277 278 "MOS_BT_UART_TX", /* 30 */ 279 "MOS_BT_UART_RX", 280 "", 281 "HUB_RST", 282 "", 283 "", 284 "", 285 "", 286 "", 287 "", 288 289 "EC_SPI_MISO_GPIO40", /* 40 */ 290 "EC_SPI_MOSI_GPIO41", 291 "EC_SPI_CLK_GPIO42", 292 "EC_SPI_CS_GPIO43", 293 "", 294 "EARLY_EUD_EN", 295 "", 296 "DP_HOT_PLUG_DETECT", 297 "AP_BRD_ID_0", 298 "AP_BRD_ID_1", 299 300 "AP_BRD_ID_2", /* 50 */ 301 "NVME_PWR_REG_EN", 302 "TS_I2C_SDA_CONN", 303 "TS_I2C_CLK_CONN", 304 "TS_RST_CONN", 305 "TS_INT_CONN", 306 "AP_I2C_TPM_SDA", 307 "AP_I2C_TPM_SCL", 308 "", 309 "", 310 311 "EDP_HOT_PLUG_DET_N", /* 60 */ 312 "", 313 "", 314 "AMP_EN", 315 "CAM0_MCLK_GPIO_64", 316 "CAM1_MCLK_GPIO_65", 317 "", 318 "", 319 "", 320 "CCI_I2C_SDA0", 321 322 "CCI_I2C_SCL0", /* 70 */ 323 "", 324 "", 325 "", 326 "", 327 "", 328 "", 329 "", 330 "", 331 "PCIE1_CLK_REQ_N", 332 333 "EN_PP3300_DX_EDP", /* 80 */ 334 "US_EURO_HS_SEL", 335 "FORCED_USB_BOOT", 336 "WCD_RESET_N", 337 "MOS_WLAN_EN", 338 "MOS_BT_EN", 339 "MOS_SW_CTRL", 340 "MOS_PCIE0_RST", 341 "MOS_PCIE0_CLKREQ_N", 342 "MOS_PCIE0_WAKE_N", 343 344 "MOS_LAA_AS_EN", /* 90 */ 345 "SD_CARD_DET_CONN", 346 "", 347 "", 348 "MOS_BT_WLAN_SLIMBUS_CLK", 349 "MOS_BT_WLAN_SLIMBUS_DAT0", 350 "", 351 "", 352 "", 353 "", 354 355 "", /* 100 */ 356 "", 357 "", 358 "", 359 "H1_AP_INT_N", 360 "", 361 "AMP_BCLK", 362 "AMP_DIN", 363 "AMP_LRCLK", 364 "UIM1_DATA_GPIO_109", 365 366 "UIM1_CLK_GPIO_110", /* 110 */ 367 "UIM1_RESET_GPIO_111", 368 "", 369 "UIM1_DATA", 370 "UIM1_CLK", 371 "UIM1_RESET", 372 "UIM1_PRESENT", 373 "SDM_RFFE0_CLK", 374 "SDM_RFFE0_DATA", 375 "", 376 377 "SDM_RFFE1_DATA", /* 120 */ 378 "SC_GPIO_121", 379 "FASTBOOT_SEL_1", 380 "SC_GPIO_123", 381 "FASTBOOT_SEL_2", 382 "SM_RFFE4_CLK_GRFC_8", 383 "SM_RFFE4_DATA_GRFC_9", 384 "WLAN_COEX_UART1_RX", 385 "WLAN_COEX_UART1_TX", 386 "", 387 388 "", /* 130 */ 389 "", 390 "", 391 "SDR_QLINK_REQ", 392 "SDR_QLINK_EN", 393 "QLINK0_WMSS_RESET_N", 394 "SMR526_QLINK1_REQ", 395 "SMR526_QLINK1_EN", 396 "SMR526_QLINK1_WMSS_RESET_N", 397 "", 398 399 "SAR1_INT_N", /* 140 */ 400 "SAR0_INT_N", 401 "", 402 "", 403 "WCD_SWR_TX_CLK", 404 "WCD_SWR_TX_DATA0", 405 "WCD_SWR_TX_DATA1", 406 "WCD_SWR_RX_CLK", 407 "WCD_SWR_RX_DATA0", 408 "WCD_SWR_RX_DATA1", 409 410 "DMIC01_CLK", /* 150 */ 411 "DMIC01_DATA", 412 "DMIC23_CLK", 413 "DMIC23_DATA", 414 "", 415 "", 416 "EC_IN_RW_N", 417 "EN_PP3300_HUB", 418 "WCD_SWR_TX_DATA2", 419 "", 420 421 "", /* 160 */ 422 "", 423 "", 424 "", 425 "", 426 "", 427 "", 428 "", 429 "", 430 "", 431 432 "", /* 170 */ 433 "MOS_BLE_UART_TX", 434 "MOS_BLE_UART_RX", 435 "", 436 "", 437 ""; 438}; 439