1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 *
4 * This file defines the common audio settings for the child boards
5 * using rt5682 codec.
6 *
7 * Copyright 2022 Google LLC.
8 */
9
10/ {
11	/* BOARD-SPECIFIC TOP LEVEL NODES */
12	sound: sound {
13		compatible = "google,sc7280-herobrine";
14		model = "sc7280-rt5682-max98360a-1mic";
15
16		audio-routing = "Headphone Jack", "HPOL",
17				"Headphone Jack", "HPOR";
18
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		dai-link@0 {
23			link-name = "MAX98360";
24			reg = <0>;
25
26			cpu {
27				sound-dai = <&lpass_cpu MI2S_SECONDARY>;
28			};
29
30			codec {
31				sound-dai = <&max98360a>;
32			};
33		};
34
35		dai-link@1 {
36			link-name = "ALC5682";
37			reg = <1>;
38
39			cpu {
40				sound-dai = <&lpass_cpu MI2S_PRIMARY>;
41			};
42
43			codec {
44				sound-dai = <&alc5682 0 /* aif1 */>;
45			};
46		};
47	};
48};
49
50hp_i2c: &i2c2 {
51	clock-frequency = <400000>;
52	status = "okay";
53
54	alc5682: codec@1a {
55		compatible = "realtek,rt5682s";
56		reg = <0x1a>;
57		pinctrl-names = "default";
58		pinctrl-0 = <&hp_irq>;
59
60		#sound-dai-cells = <1>;
61
62		interrupt-parent = <&tlmm>;
63		interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
64
65		AVDD-supply = <&pp1800_alc5682>;
66		MICVDD-supply = <&pp3300_codec>;
67
68		realtek,dmic1-data-pin = <1>;
69		realtek,dmic1-clk-pin = <2>;
70		realtek,jd-src = <1>;
71		realtek,dmic-clk-rate-hz = <2048000>;
72	};
73};
74
75&lpass_cpu {
76	pinctrl-names = "default";
77	pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
78			<&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
79
80	#address-cells = <1>;
81	#size-cells = <0>;
82
83	status = "okay";
84
85	dai-link@0 {
86		reg = <MI2S_PRIMARY>;
87		qcom,playback-sd-lines = <1>;
88		qcom,capture-sd-lines = <0>;
89	};
90
91	dai-link@1 {
92		reg = <MI2S_SECONDARY>;
93		qcom,playback-sd-lines = <0>;
94	};
95};
96
97/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
98
99&mi2s0_data0 {
100	drive-strength = <6>;
101	bias-disable;
102};
103
104&mi2s0_data1 {
105	drive-strength = <6>;
106	bias-disable;
107};
108
109&mi2s0_mclk {
110	drive-strength = <6>;
111	bias-disable;
112};
113
114&mi2s0_sclk {
115	drive-strength = <6>;
116	bias-disable;
117};
118
119&mi2s0_ws {
120	drive-strength = <6>;
121	bias-disable;
122};
123