1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 *
4 * This file defines the common audio settings for the child boards
5 * using rt5682 codec and having 3 dmics connected to sc7280.
6 *
7 * Copyright 2022 Google LLC.
8 */
9
10/ {
11	/* BOARD-SPECIFIC TOP LEVEL NODES */
12	sound: sound {
13		compatible = "google,sc7280-herobrine";
14		model = "sc7280-rt5682-max98360a-3mic";
15
16		audio-routing =	"VA DMIC0", "vdd-micb",
17				"VA DMIC1", "vdd-micb",
18				"VA DMIC2", "vdd-micb",
19				"VA DMIC3", "vdd-micb",
20
21				"Headphone Jack", "HPOL",
22				"Headphone Jack", "HPOR";
23
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		dai-link@0 {
28			link-name = "MAX98360";
29			reg = <0>;
30
31			cpu {
32				sound-dai = <&lpass_cpu MI2S_SECONDARY>;
33			};
34
35			codec {
36				sound-dai = <&max98360a>;
37			};
38		};
39
40		dai-link@1 {
41			link-name = "DisplayPort";
42			reg = <1>;
43
44			cpu {
45				sound-dai = <&lpass_cpu LPASS_DP_RX>;
46			};
47
48			codec {
49				sound-dai = <&mdss_dp>;
50			};
51		};
52
53		dai-link@2 {
54			link-name = "ALC5682";
55			reg = <2>;
56
57			cpu {
58				sound-dai = <&lpass_cpu MI2S_PRIMARY>;
59			};
60
61			codec {
62				sound-dai = <&alc5682 0 /* aif1 */>;
63			};
64		};
65
66		dai-link@4 {
67			link-name = "DMIC";
68			reg = <4>;
69
70			cpu {
71				sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
72			};
73
74			codec {
75				sound-dai = <&lpass_va_macro 0>;
76			};
77		};
78	};
79};
80
81hp_i2c: &i2c2 {
82	clock-frequency = <400000>;
83	status = "okay";
84
85	alc5682: codec@1a {
86		compatible = "realtek,rt5682s";
87		reg = <0x1a>;
88		pinctrl-names = "default";
89		pinctrl-0 = <&hp_irq>;
90
91		#sound-dai-cells = <1>;
92
93		interrupt-parent = <&tlmm>;
94		interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
95
96		AVDD-supply = <&pp1800_alc5682>;
97		MICVDD-supply = <&pp3300_codec>;
98
99		realtek,dmic1-data-pin = <1>;
100		realtek,dmic1-clk-pin = <2>;
101		realtek,jd-src = <1>;
102		realtek,dmic-clk-rate-hz = <2048000>;
103	};
104};
105
106&lpass_cpu {
107	pinctrl-names = "default";
108	pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
109			<&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
110
111	#address-cells = <1>;
112	#size-cells = <0>;
113
114	status = "okay";
115
116	dai-link@0 {
117		reg = <MI2S_PRIMARY>;
118		qcom,playback-sd-lines = <1>;
119		qcom,capture-sd-lines = <0>;
120	};
121
122	dai-link@1 {
123		reg = <MI2S_SECONDARY>;
124		qcom,playback-sd-lines = <0>;
125	};
126
127	dai-link@5 {
128		reg = <LPASS_DP_RX>;
129	};
130
131	dai-link@25 {
132		reg = <LPASS_CDC_DMA_VA_TX0>;
133	};
134};
135
136&lpass_va_macro {
137	vdd-micb-supply = <&pp1800_l2c>;
138	pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, <&lpass_dmic23_clk>,
139			<&lpass_dmic23_data>;
140
141	status = "okay";
142};
143
144/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
145
146&lpass_dmic01_clk {
147	drive-strength = <8>;
148	bias-disable;
149};
150
151&lpass_dmic01_data {
152	bias-pull-down;
153};
154
155&lpass_dmic23_clk {
156	drive-strength = <8>;
157	bias-disable;
158};
159
160&lpass_dmic23_data {
161	bias-pull-down;
162};
163
164&mi2s0_data0 {
165	drive-strength = <6>;
166	bias-disable;
167};
168
169&mi2s0_data1 {
170	drive-strength = <6>;
171	bias-disable;
172};
173
174&mi2s0_mclk {
175	drive-strength = <6>;
176	bias-disable;
177};
178
179&mi2s0_sclk {
180	drive-strength = <6>;
181	bias-disable;
182};
183
184&mi2s0_ws {
185	drive-strength = <6>;
186	bias-disable;
187};
188