1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 mmc1 = &sdhc_1; 32 mmc2 = &sdhc_2; 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi3 = &spi3; 48 spi5 = &spi5; 49 spi6 = &spi6; 50 spi8 = &spi8; 51 spi10 = &spi10; 52 spi11 = &spi11; 53 }; 54 55 chosen { }; 56 57 clocks { 58 xo_board: xo-board { 59 compatible = "fixed-clock"; 60 clock-frequency = <38400000>; 61 #clock-cells = <0>; 62 }; 63 64 sleep_clk: sleep-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <32764>; 67 #clock-cells = <0>; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <2>; 73 #size-cells = <0>; 74 75 CPU0: cpu@0 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo468"; 78 reg = <0x0 0x0>; 79 clocks = <&cpufreq_hw 0>; 80 enable-method = "psci"; 81 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 82 &LITTLE_CPU_SLEEP_1 83 &CLUSTER_SLEEP_0>; 84 capacity-dmips-mhz = <415>; 85 dynamic-power-coefficient = <137>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 89 next-level-cache = <&L2_0>; 90 #cooling-cells = <2>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 L2_0: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&L3_0>; 97 L3_0: l3-cache { 98 compatible = "cache"; 99 cache-level = <3>; 100 cache-unified; 101 }; 102 }; 103 }; 104 105 CPU1: cpu@100 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo468"; 108 reg = <0x0 0x100>; 109 clocks = <&cpufreq_hw 0>; 110 enable-method = "psci"; 111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 112 &LITTLE_CPU_SLEEP_1 113 &CLUSTER_SLEEP_0>; 114 capacity-dmips-mhz = <415>; 115 dynamic-power-coefficient = <137>; 116 next-level-cache = <&L2_100>; 117 operating-points-v2 = <&cpu0_opp_table>; 118 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 120 #cooling-cells = <2>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 L2_100: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 CPU2: cpu@200 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo468"; 133 reg = <0x0 0x200>; 134 clocks = <&cpufreq_hw 0>; 135 enable-method = "psci"; 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 137 &LITTLE_CPU_SLEEP_1 138 &CLUSTER_SLEEP_0>; 139 capacity-dmips-mhz = <415>; 140 dynamic-power-coefficient = <137>; 141 next-level-cache = <&L2_200>; 142 operating-points-v2 = <&cpu0_opp_table>; 143 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 145 #cooling-cells = <2>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 L2_200: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 cache-unified; 151 next-level-cache = <&L3_0>; 152 }; 153 }; 154 155 CPU3: cpu@300 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo468"; 158 reg = <0x0 0x300>; 159 clocks = <&cpufreq_hw 0>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 capacity-dmips-mhz = <415>; 165 dynamic-power-coefficient = <137>; 166 next-level-cache = <&L2_300>; 167 operating-points-v2 = <&cpu0_opp_table>; 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 #cooling-cells = <2>; 171 qcom,freq-domain = <&cpufreq_hw 0>; 172 L2_300: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU4: cpu@400 { 181 device_type = "cpu"; 182 compatible = "qcom,kryo468"; 183 reg = <0x0 0x400>; 184 clocks = <&cpufreq_hw 0>; 185 enable-method = "psci"; 186 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 187 &LITTLE_CPU_SLEEP_1 188 &CLUSTER_SLEEP_0>; 189 capacity-dmips-mhz = <415>; 190 dynamic-power-coefficient = <137>; 191 next-level-cache = <&L2_400>; 192 operating-points-v2 = <&cpu0_opp_table>; 193 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195 #cooling-cells = <2>; 196 qcom,freq-domain = <&cpufreq_hw 0>; 197 L2_400: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU5: cpu@500 { 206 device_type = "cpu"; 207 compatible = "qcom,kryo468"; 208 reg = <0x0 0x500>; 209 clocks = <&cpufreq_hw 0>; 210 enable-method = "psci"; 211 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 212 &LITTLE_CPU_SLEEP_1 213 &CLUSTER_SLEEP_0>; 214 capacity-dmips-mhz = <415>; 215 dynamic-power-coefficient = <137>; 216 next-level-cache = <&L2_500>; 217 operating-points-v2 = <&cpu0_opp_table>; 218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 #cooling-cells = <2>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 L2_500: l2-cache { 223 compatible = "cache"; 224 cache-level = <2>; 225 cache-unified; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU6: cpu@600 { 231 device_type = "cpu"; 232 compatible = "qcom,kryo468"; 233 reg = <0x0 0x600>; 234 clocks = <&cpufreq_hw 1>; 235 enable-method = "psci"; 236 cpu-idle-states = <&BIG_CPU_SLEEP_0 237 &BIG_CPU_SLEEP_1 238 &CLUSTER_SLEEP_0>; 239 capacity-dmips-mhz = <1024>; 240 dynamic-power-coefficient = <480>; 241 next-level-cache = <&L2_600>; 242 operating-points-v2 = <&cpu6_opp_table>; 243 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 244 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 245 #cooling-cells = <2>; 246 qcom,freq-domain = <&cpufreq_hw 1>; 247 L2_600: l2-cache { 248 compatible = "cache"; 249 cache-level = <2>; 250 cache-unified; 251 next-level-cache = <&L3_0>; 252 }; 253 }; 254 255 CPU7: cpu@700 { 256 device_type = "cpu"; 257 compatible = "qcom,kryo468"; 258 reg = <0x0 0x700>; 259 clocks = <&cpufreq_hw 1>; 260 enable-method = "psci"; 261 cpu-idle-states = <&BIG_CPU_SLEEP_0 262 &BIG_CPU_SLEEP_1 263 &CLUSTER_SLEEP_0>; 264 capacity-dmips-mhz = <1024>; 265 dynamic-power-coefficient = <480>; 266 next-level-cache = <&L2_700>; 267 operating-points-v2 = <&cpu6_opp_table>; 268 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 269 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 270 #cooling-cells = <2>; 271 qcom,freq-domain = <&cpufreq_hw 1>; 272 L2_700: l2-cache { 273 compatible = "cache"; 274 cache-level = <2>; 275 cache-unified; 276 next-level-cache = <&L3_0>; 277 }; 278 }; 279 280 cpu-map { 281 cluster0 { 282 core0 { 283 cpu = <&CPU0>; 284 }; 285 286 core1 { 287 cpu = <&CPU1>; 288 }; 289 290 core2 { 291 cpu = <&CPU2>; 292 }; 293 294 core3 { 295 cpu = <&CPU3>; 296 }; 297 298 core4 { 299 cpu = <&CPU4>; 300 }; 301 302 core5 { 303 cpu = <&CPU5>; 304 }; 305 306 core6 { 307 cpu = <&CPU6>; 308 }; 309 310 core7 { 311 cpu = <&CPU7>; 312 }; 313 }; 314 }; 315 316 idle-states { 317 entry-method = "psci"; 318 319 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 320 compatible = "arm,idle-state"; 321 idle-state-name = "little-power-down"; 322 arm,psci-suspend-param = <0x40000003>; 323 entry-latency-us = <549>; 324 exit-latency-us = <901>; 325 min-residency-us = <1774>; 326 local-timer-stop; 327 }; 328 329 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-rail-power-down"; 332 arm,psci-suspend-param = <0x40000004>; 333 entry-latency-us = <702>; 334 exit-latency-us = <915>; 335 min-residency-us = <4001>; 336 local-timer-stop; 337 }; 338 339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "big-power-down"; 342 arm,psci-suspend-param = <0x40000003>; 343 entry-latency-us = <523>; 344 exit-latency-us = <1244>; 345 min-residency-us = <2207>; 346 local-timer-stop; 347 }; 348 349 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "big-rail-power-down"; 352 arm,psci-suspend-param = <0x40000004>; 353 entry-latency-us = <526>; 354 exit-latency-us = <1854>; 355 min-residency-us = <5555>; 356 local-timer-stop; 357 }; 358 359 CLUSTER_SLEEP_0: cluster-sleep-0 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "cluster-power-down"; 362 arm,psci-suspend-param = <0x40003444>; 363 entry-latency-us = <3263>; 364 exit-latency-us = <6562>; 365 min-residency-us = <9926>; 366 local-timer-stop; 367 }; 368 }; 369 }; 370 371 firmware { 372 scm: scm { 373 compatible = "qcom,scm-sc7180", "qcom,scm"; 374 }; 375 }; 376 377 memory@80000000 { 378 device_type = "memory"; 379 /* We expect the bootloader to fill in the size */ 380 reg = <0 0x80000000 0 0>; 381 }; 382 383 cpu0_opp_table: opp-table-cpu0 { 384 compatible = "operating-points-v2"; 385 opp-shared; 386 387 cpu0_opp1: opp-300000000 { 388 opp-hz = /bits/ 64 <300000000>; 389 opp-peak-kBps = <1200000 4800000>; 390 }; 391 392 cpu0_opp2: opp-576000000 { 393 opp-hz = /bits/ 64 <576000000>; 394 opp-peak-kBps = <1200000 4800000>; 395 }; 396 397 cpu0_opp3: opp-768000000 { 398 opp-hz = /bits/ 64 <768000000>; 399 opp-peak-kBps = <1200000 4800000>; 400 }; 401 402 cpu0_opp4: opp-1017600000 { 403 opp-hz = /bits/ 64 <1017600000>; 404 opp-peak-kBps = <1804000 8908800>; 405 }; 406 407 cpu0_opp5: opp-1248000000 { 408 opp-hz = /bits/ 64 <1248000000>; 409 opp-peak-kBps = <2188000 12902400>; 410 }; 411 412 cpu0_opp6: opp-1324800000 { 413 opp-hz = /bits/ 64 <1324800000>; 414 opp-peak-kBps = <2188000 12902400>; 415 }; 416 417 cpu0_opp7: opp-1516800000 { 418 opp-hz = /bits/ 64 <1516800000>; 419 opp-peak-kBps = <3072000 15052800>; 420 }; 421 422 cpu0_opp8: opp-1612800000 { 423 opp-hz = /bits/ 64 <1612800000>; 424 opp-peak-kBps = <3072000 15052800>; 425 }; 426 427 cpu0_opp9: opp-1708800000 { 428 opp-hz = /bits/ 64 <1708800000>; 429 opp-peak-kBps = <3072000 15052800>; 430 }; 431 432 cpu0_opp10: opp-1804800000 { 433 opp-hz = /bits/ 64 <1804800000>; 434 opp-peak-kBps = <4068000 22425600>; 435 }; 436 }; 437 438 cpu6_opp_table: opp-table-cpu6 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 cpu6_opp1: opp-300000000 { 443 opp-hz = /bits/ 64 <300000000>; 444 opp-peak-kBps = <2188000 8908800>; 445 }; 446 447 cpu6_opp2: opp-652800000 { 448 opp-hz = /bits/ 64 <652800000>; 449 opp-peak-kBps = <2188000 8908800>; 450 }; 451 452 cpu6_opp3: opp-825600000 { 453 opp-hz = /bits/ 64 <825600000>; 454 opp-peak-kBps = <2188000 8908800>; 455 }; 456 457 cpu6_opp4: opp-979200000 { 458 opp-hz = /bits/ 64 <979200000>; 459 opp-peak-kBps = <2188000 8908800>; 460 }; 461 462 cpu6_opp5: opp-1113600000 { 463 opp-hz = /bits/ 64 <1113600000>; 464 opp-peak-kBps = <2188000 8908800>; 465 }; 466 467 cpu6_opp6: opp-1267200000 { 468 opp-hz = /bits/ 64 <1267200000>; 469 opp-peak-kBps = <4068000 12902400>; 470 }; 471 472 cpu6_opp7: opp-1555200000 { 473 opp-hz = /bits/ 64 <1555200000>; 474 opp-peak-kBps = <4068000 15052800>; 475 }; 476 477 cpu6_opp8: opp-1708800000 { 478 opp-hz = /bits/ 64 <1708800000>; 479 opp-peak-kBps = <6220000 19353600>; 480 }; 481 482 cpu6_opp9: opp-1843200000 { 483 opp-hz = /bits/ 64 <1843200000>; 484 opp-peak-kBps = <6220000 19353600>; 485 }; 486 487 cpu6_opp10: opp-1900800000 { 488 opp-hz = /bits/ 64 <1900800000>; 489 opp-peak-kBps = <6220000 22425600>; 490 }; 491 492 cpu6_opp11: opp-1996800000 { 493 opp-hz = /bits/ 64 <1996800000>; 494 opp-peak-kBps = <6220000 22425600>; 495 }; 496 497 cpu6_opp12: opp-2112000000 { 498 opp-hz = /bits/ 64 <2112000000>; 499 opp-peak-kBps = <6220000 22425600>; 500 }; 501 502 cpu6_opp13: opp-2208000000 { 503 opp-hz = /bits/ 64 <2208000000>; 504 opp-peak-kBps = <7216000 22425600>; 505 }; 506 507 cpu6_opp14: opp-2323200000 { 508 opp-hz = /bits/ 64 <2323200000>; 509 opp-peak-kBps = <7216000 22425600>; 510 }; 511 512 cpu6_opp15: opp-2400000000 { 513 opp-hz = /bits/ 64 <2400000000>; 514 opp-peak-kBps = <8532000 23347200>; 515 }; 516 517 cpu6_opp16: opp-2553600000 { 518 opp-hz = /bits/ 64 <2553600000>; 519 opp-peak-kBps = <8532000 23347200>; 520 }; 521 }; 522 523 qspi_opp_table: opp-table-qspi { 524 compatible = "operating-points-v2"; 525 526 opp-75000000 { 527 opp-hz = /bits/ 64 <75000000>; 528 required-opps = <&rpmhpd_opp_low_svs>; 529 }; 530 531 opp-150000000 { 532 opp-hz = /bits/ 64 <150000000>; 533 required-opps = <&rpmhpd_opp_svs>; 534 }; 535 536 opp-300000000 { 537 opp-hz = /bits/ 64 <300000000>; 538 required-opps = <&rpmhpd_opp_nom>; 539 }; 540 }; 541 542 qup_opp_table: opp-table-qup { 543 compatible = "operating-points-v2"; 544 545 opp-75000000 { 546 opp-hz = /bits/ 64 <75000000>; 547 required-opps = <&rpmhpd_opp_low_svs>; 548 }; 549 550 opp-100000000 { 551 opp-hz = /bits/ 64 <100000000>; 552 required-opps = <&rpmhpd_opp_svs>; 553 }; 554 555 opp-128000000 { 556 opp-hz = /bits/ 64 <128000000>; 557 required-opps = <&rpmhpd_opp_nom>; 558 }; 559 }; 560 561 pmu { 562 compatible = "arm,armv8-pmuv3"; 563 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 564 }; 565 566 psci { 567 compatible = "arm,psci-1.0"; 568 method = "smc"; 569 }; 570 571 reserved_memory: reserved-memory { 572 #address-cells = <2>; 573 #size-cells = <2>; 574 ranges; 575 576 hyp_mem: memory@80000000 { 577 reg = <0x0 0x80000000 0x0 0x600000>; 578 no-map; 579 }; 580 581 xbl_mem: memory@80600000 { 582 reg = <0x0 0x80600000 0x0 0x200000>; 583 no-map; 584 }; 585 586 aop_mem: memory@80800000 { 587 reg = <0x0 0x80800000 0x0 0x20000>; 588 no-map; 589 }; 590 591 aop_cmd_db_mem: memory@80820000 { 592 reg = <0x0 0x80820000 0x0 0x20000>; 593 compatible = "qcom,cmd-db"; 594 no-map; 595 }; 596 597 sec_apps_mem: memory@808ff000 { 598 reg = <0x0 0x808ff000 0x0 0x1000>; 599 no-map; 600 }; 601 602 smem_mem: memory@80900000 { 603 reg = <0x0 0x80900000 0x0 0x200000>; 604 no-map; 605 }; 606 607 tz_mem: memory@80b00000 { 608 reg = <0x0 0x80b00000 0x0 0x3900000>; 609 no-map; 610 }; 611 612 ipa_fw_mem: memory@8b700000 { 613 reg = <0 0x8b700000 0 0x10000>; 614 no-map; 615 }; 616 617 rmtfs_mem: memory@94600000 { 618 compatible = "qcom,rmtfs-mem"; 619 reg = <0x0 0x94600000 0x0 0x200000>; 620 no-map; 621 622 qcom,client-id = <1>; 623 qcom,vmid = <15>; 624 }; 625 }; 626 627 smem { 628 compatible = "qcom,smem"; 629 memory-region = <&smem_mem>; 630 hwlocks = <&tcsr_mutex 3>; 631 }; 632 633 smp2p-cdsp { 634 compatible = "qcom,smp2p"; 635 qcom,smem = <94>, <432>; 636 637 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 638 639 mboxes = <&apss_shared 6>; 640 641 qcom,local-pid = <0>; 642 qcom,remote-pid = <5>; 643 644 cdsp_smp2p_out: master-kernel { 645 qcom,entry-name = "master-kernel"; 646 #qcom,smem-state-cells = <1>; 647 }; 648 649 cdsp_smp2p_in: slave-kernel { 650 qcom,entry-name = "slave-kernel"; 651 652 interrupt-controller; 653 #interrupt-cells = <2>; 654 }; 655 }; 656 657 smp2p-lpass { 658 compatible = "qcom,smp2p"; 659 qcom,smem = <443>, <429>; 660 661 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 662 663 mboxes = <&apss_shared 10>; 664 665 qcom,local-pid = <0>; 666 qcom,remote-pid = <2>; 667 668 adsp_smp2p_out: master-kernel { 669 qcom,entry-name = "master-kernel"; 670 #qcom,smem-state-cells = <1>; 671 }; 672 673 adsp_smp2p_in: slave-kernel { 674 qcom,entry-name = "slave-kernel"; 675 676 interrupt-controller; 677 #interrupt-cells = <2>; 678 }; 679 }; 680 681 smp2p-mpss { 682 compatible = "qcom,smp2p"; 683 qcom,smem = <435>, <428>; 684 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 685 mboxes = <&apss_shared 14>; 686 qcom,local-pid = <0>; 687 qcom,remote-pid = <1>; 688 689 modem_smp2p_out: master-kernel { 690 qcom,entry-name = "master-kernel"; 691 #qcom,smem-state-cells = <1>; 692 }; 693 694 modem_smp2p_in: slave-kernel { 695 qcom,entry-name = "slave-kernel"; 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 }; 699 700 ipa_smp2p_out: ipa-ap-to-modem { 701 qcom,entry-name = "ipa"; 702 #qcom,smem-state-cells = <1>; 703 }; 704 705 ipa_smp2p_in: ipa-modem-to-ap { 706 qcom,entry-name = "ipa"; 707 interrupt-controller; 708 #interrupt-cells = <2>; 709 }; 710 }; 711 712 soc: soc@0 { 713 #address-cells = <2>; 714 #size-cells = <2>; 715 ranges = <0 0 0 0 0x10 0>; 716 dma-ranges = <0 0 0 0 0x10 0>; 717 compatible = "simple-bus"; 718 719 gcc: clock-controller@100000 { 720 compatible = "qcom,gcc-sc7180"; 721 reg = <0 0x00100000 0 0x1f0000>; 722 clocks = <&rpmhcc RPMH_CXO_CLK>, 723 <&rpmhcc RPMH_CXO_CLK_A>, 724 <&sleep_clk>; 725 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 726 #clock-cells = <1>; 727 #reset-cells = <1>; 728 #power-domain-cells = <1>; 729 power-domains = <&rpmhpd SC7180_CX>; 730 }; 731 732 qfprom: efuse@784000 { 733 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 734 reg = <0 0x00784000 0 0x7a0>, 735 <0 0x00780000 0 0x7a0>, 736 <0 0x00782000 0 0x100>, 737 <0 0x00786000 0 0x1fff>; 738 739 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 740 clock-names = "core"; 741 #address-cells = <1>; 742 #size-cells = <1>; 743 744 qusb2p_hstx_trim: hstx-trim-primary@25b { 745 reg = <0x25b 0x1>; 746 bits = <1 3>; 747 }; 748 749 gpu_speed_bin: gpu_speed_bin@1d2 { 750 reg = <0x1d2 0x2>; 751 bits = <5 8>; 752 }; 753 }; 754 755 sdhc_1: mmc@7c4000 { 756 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 757 reg = <0 0x007c4000 0 0x1000>, 758 <0 0x007c5000 0 0x1000>; 759 reg-names = "hc", "cqhci"; 760 761 iommus = <&apps_smmu 0x60 0x0>; 762 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 764 interrupt-names = "hc_irq", "pwr_irq"; 765 766 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 767 <&gcc GCC_SDCC1_APPS_CLK>, 768 <&rpmhcc RPMH_CXO_CLK>; 769 clock-names = "iface", "core", "xo"; 770 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 771 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 772 interconnect-names = "sdhc-ddr","cpu-sdhc"; 773 power-domains = <&rpmhpd SC7180_CX>; 774 operating-points-v2 = <&sdhc1_opp_table>; 775 776 bus-width = <8>; 777 non-removable; 778 supports-cqe; 779 780 mmc-ddr-1_8v; 781 mmc-hs200-1_8v; 782 mmc-hs400-1_8v; 783 mmc-hs400-enhanced-strobe; 784 785 status = "disabled"; 786 787 sdhc1_opp_table: opp-table { 788 compatible = "operating-points-v2"; 789 790 opp-100000000 { 791 opp-hz = /bits/ 64 <100000000>; 792 required-opps = <&rpmhpd_opp_low_svs>; 793 opp-peak-kBps = <1800000 600000>; 794 opp-avg-kBps = <100000 0>; 795 }; 796 797 opp-384000000 { 798 opp-hz = /bits/ 64 <384000000>; 799 required-opps = <&rpmhpd_opp_nom>; 800 opp-peak-kBps = <5400000 1600000>; 801 opp-avg-kBps = <390000 0>; 802 }; 803 }; 804 }; 805 806 qupv3_id_0: geniqup@8c0000 { 807 compatible = "qcom,geni-se-qup"; 808 reg = <0 0x008c0000 0 0x6000>; 809 clock-names = "m-ahb", "s-ahb"; 810 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 811 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 812 #address-cells = <2>; 813 #size-cells = <2>; 814 ranges; 815 iommus = <&apps_smmu 0x43 0x0>; 816 status = "disabled"; 817 818 i2c0: i2c@880000 { 819 compatible = "qcom,geni-i2c"; 820 reg = <0 0x00880000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&qup_i2c0_default>; 825 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 829 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 830 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 831 interconnect-names = "qup-core", "qup-config", 832 "qup-memory"; 833 power-domains = <&rpmhpd SC7180_CX>; 834 required-opps = <&rpmhpd_opp_low_svs>; 835 status = "disabled"; 836 }; 837 838 spi0: spi@880000 { 839 compatible = "qcom,geni-spi"; 840 reg = <0 0x00880000 0 0x4000>; 841 clock-names = "se"; 842 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 845 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 power-domains = <&rpmhpd SC7180_CX>; 849 operating-points-v2 = <&qup_opp_table>; 850 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 851 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 852 interconnect-names = "qup-core", "qup-config"; 853 status = "disabled"; 854 }; 855 856 uart0: serial@880000 { 857 compatible = "qcom,geni-uart"; 858 reg = <0 0x00880000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_uart0_default>; 863 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 864 power-domains = <&rpmhpd SC7180_CX>; 865 operating-points-v2 = <&qup_opp_table>; 866 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 867 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 868 interconnect-names = "qup-core", "qup-config"; 869 status = "disabled"; 870 }; 871 872 i2c1: i2c@884000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0 0x00884000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&qup_i2c1_default>; 879 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 883 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 884 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 885 interconnect-names = "qup-core", "qup-config", 886 "qup-memory"; 887 power-domains = <&rpmhpd SC7180_CX>; 888 required-opps = <&rpmhpd_opp_low_svs>; 889 status = "disabled"; 890 }; 891 892 spi1: spi@884000 { 893 compatible = "qcom,geni-spi"; 894 reg = <0 0x00884000 0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 897 pinctrl-names = "default"; 898 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 899 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 power-domains = <&rpmhpd SC7180_CX>; 903 operating-points-v2 = <&qup_opp_table>; 904 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 905 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 906 interconnect-names = "qup-core", "qup-config"; 907 status = "disabled"; 908 }; 909 910 uart1: serial@884000 { 911 compatible = "qcom,geni-uart"; 912 reg = <0 0x00884000 0 0x4000>; 913 clock-names = "se"; 914 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 915 pinctrl-names = "default"; 916 pinctrl-0 = <&qup_uart1_default>; 917 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 918 power-domains = <&rpmhpd SC7180_CX>; 919 operating-points-v2 = <&qup_opp_table>; 920 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 922 interconnect-names = "qup-core", "qup-config"; 923 status = "disabled"; 924 }; 925 926 i2c2: i2c@888000 { 927 compatible = "qcom,geni-i2c"; 928 reg = <0 0x00888000 0 0x4000>; 929 clock-names = "se"; 930 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&qup_i2c2_default>; 933 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 937 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 938 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 939 interconnect-names = "qup-core", "qup-config", 940 "qup-memory"; 941 power-domains = <&rpmhpd SC7180_CX>; 942 required-opps = <&rpmhpd_opp_low_svs>; 943 status = "disabled"; 944 }; 945 946 uart2: serial@888000 { 947 compatible = "qcom,geni-uart"; 948 reg = <0 0x00888000 0 0x4000>; 949 clock-names = "se"; 950 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_uart2_default>; 953 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 954 power-domains = <&rpmhpd SC7180_CX>; 955 operating-points-v2 = <&qup_opp_table>; 956 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 957 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 958 interconnect-names = "qup-core", "qup-config"; 959 status = "disabled"; 960 }; 961 962 i2c3: i2c@88c000 { 963 compatible = "qcom,geni-i2c"; 964 reg = <0 0x0088c000 0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 967 pinctrl-names = "default"; 968 pinctrl-0 = <&qup_i2c3_default>; 969 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 974 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 975 interconnect-names = "qup-core", "qup-config", 976 "qup-memory"; 977 power-domains = <&rpmhpd SC7180_CX>; 978 required-opps = <&rpmhpd_opp_low_svs>; 979 status = "disabled"; 980 }; 981 982 spi3: spi@88c000 { 983 compatible = "qcom,geni-spi"; 984 reg = <0 0x0088c000 0 0x4000>; 985 clock-names = "se"; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 989 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 power-domains = <&rpmhpd SC7180_CX>; 993 operating-points-v2 = <&qup_opp_table>; 994 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 995 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 996 interconnect-names = "qup-core", "qup-config"; 997 status = "disabled"; 998 }; 999 1000 uart3: serial@88c000 { 1001 compatible = "qcom,geni-uart"; 1002 reg = <0 0x0088c000 0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_uart3_default>; 1007 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1008 power-domains = <&rpmhpd SC7180_CX>; 1009 operating-points-v2 = <&qup_opp_table>; 1010 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1011 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1012 interconnect-names = "qup-core", "qup-config"; 1013 status = "disabled"; 1014 }; 1015 1016 i2c4: i2c@890000 { 1017 compatible = "qcom,geni-i2c"; 1018 reg = <0 0x00890000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_i2c4_default>; 1023 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1027 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1028 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1029 interconnect-names = "qup-core", "qup-config", 1030 "qup-memory"; 1031 power-domains = <&rpmhpd SC7180_CX>; 1032 required-opps = <&rpmhpd_opp_low_svs>; 1033 status = "disabled"; 1034 }; 1035 1036 uart4: serial@890000 { 1037 compatible = "qcom,geni-uart"; 1038 reg = <0 0x00890000 0 0x4000>; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_uart4_default>; 1043 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SC7180_CX>; 1045 operating-points-v2 = <&qup_opp_table>; 1046 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1048 interconnect-names = "qup-core", "qup-config"; 1049 status = "disabled"; 1050 }; 1051 1052 i2c5: i2c@894000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0 0x00894000 0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&qup_i2c5_default>; 1059 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1064 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1065 interconnect-names = "qup-core", "qup-config", 1066 "qup-memory"; 1067 power-domains = <&rpmhpd SC7180_CX>; 1068 required-opps = <&rpmhpd_opp_low_svs>; 1069 status = "disabled"; 1070 }; 1071 1072 spi5: spi@894000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00894000 0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1079 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 power-domains = <&rpmhpd SC7180_CX>; 1083 operating-points-v2 = <&qup_opp_table>; 1084 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1086 interconnect-names = "qup-core", "qup-config"; 1087 status = "disabled"; 1088 }; 1089 1090 uart5: serial@894000 { 1091 compatible = "qcom,geni-uart"; 1092 reg = <0 0x00894000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_uart5_default>; 1097 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1098 power-domains = <&rpmhpd SC7180_CX>; 1099 operating-points-v2 = <&qup_opp_table>; 1100 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1101 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1102 interconnect-names = "qup-core", "qup-config"; 1103 status = "disabled"; 1104 }; 1105 }; 1106 1107 qupv3_id_1: geniqup@ac0000 { 1108 compatible = "qcom,geni-se-qup"; 1109 reg = <0 0x00ac0000 0 0x6000>; 1110 clock-names = "m-ahb", "s-ahb"; 1111 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1112 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1113 #address-cells = <2>; 1114 #size-cells = <2>; 1115 ranges; 1116 iommus = <&apps_smmu 0x4c3 0x0>; 1117 status = "disabled"; 1118 1119 i2c6: i2c@a80000 { 1120 compatible = "qcom,geni-i2c"; 1121 reg = <0 0x00a80000 0 0x4000>; 1122 clock-names = "se"; 1123 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&qup_i2c6_default>; 1126 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1131 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1132 interconnect-names = "qup-core", "qup-config", 1133 "qup-memory"; 1134 power-domains = <&rpmhpd SC7180_CX>; 1135 required-opps = <&rpmhpd_opp_low_svs>; 1136 status = "disabled"; 1137 }; 1138 1139 spi6: spi@a80000 { 1140 compatible = "qcom,geni-spi"; 1141 reg = <0 0x00a80000 0 0x4000>; 1142 clock-names = "se"; 1143 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1144 pinctrl-names = "default"; 1145 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1146 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 power-domains = <&rpmhpd SC7180_CX>; 1150 operating-points-v2 = <&qup_opp_table>; 1151 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1153 interconnect-names = "qup-core", "qup-config"; 1154 status = "disabled"; 1155 }; 1156 1157 uart6: serial@a80000 { 1158 compatible = "qcom,geni-uart"; 1159 reg = <0 0x00a80000 0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_uart6_default>; 1164 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1165 power-domains = <&rpmhpd SC7180_CX>; 1166 operating-points-v2 = <&qup_opp_table>; 1167 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1168 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1169 interconnect-names = "qup-core", "qup-config"; 1170 status = "disabled"; 1171 }; 1172 1173 i2c7: i2c@a84000 { 1174 compatible = "qcom,geni-i2c"; 1175 reg = <0 0x00a84000 0 0x4000>; 1176 clock-names = "se"; 1177 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&qup_i2c7_default>; 1180 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1184 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1185 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1186 interconnect-names = "qup-core", "qup-config", 1187 "qup-memory"; 1188 power-domains = <&rpmhpd SC7180_CX>; 1189 required-opps = <&rpmhpd_opp_low_svs>; 1190 status = "disabled"; 1191 }; 1192 1193 uart7: serial@a84000 { 1194 compatible = "qcom,geni-uart"; 1195 reg = <0 0x00a84000 0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_uart7_default>; 1200 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1201 power-domains = <&rpmhpd SC7180_CX>; 1202 operating-points-v2 = <&qup_opp_table>; 1203 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1205 interconnect-names = "qup-core", "qup-config"; 1206 status = "disabled"; 1207 }; 1208 1209 i2c8: i2c@a88000 { 1210 compatible = "qcom,geni-i2c"; 1211 reg = <0 0x00a88000 0 0x4000>; 1212 clock-names = "se"; 1213 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&qup_i2c8_default>; 1216 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1221 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1222 interconnect-names = "qup-core", "qup-config", 1223 "qup-memory"; 1224 power-domains = <&rpmhpd SC7180_CX>; 1225 required-opps = <&rpmhpd_opp_low_svs>; 1226 status = "disabled"; 1227 }; 1228 1229 spi8: spi@a88000 { 1230 compatible = "qcom,geni-spi"; 1231 reg = <0 0x00a88000 0 0x4000>; 1232 clock-names = "se"; 1233 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1236 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 power-domains = <&rpmhpd SC7180_CX>; 1240 operating-points-v2 = <&qup_opp_table>; 1241 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1242 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1243 interconnect-names = "qup-core", "qup-config"; 1244 status = "disabled"; 1245 }; 1246 1247 uart8: serial@a88000 { 1248 compatible = "qcom,geni-debug-uart"; 1249 reg = <0 0x00a88000 0 0x4000>; 1250 clock-names = "se"; 1251 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1252 pinctrl-names = "default"; 1253 pinctrl-0 = <&qup_uart8_default>; 1254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1255 power-domains = <&rpmhpd SC7180_CX>; 1256 operating-points-v2 = <&qup_opp_table>; 1257 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1258 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1259 interconnect-names = "qup-core", "qup-config"; 1260 status = "disabled"; 1261 }; 1262 1263 i2c9: i2c@a8c000 { 1264 compatible = "qcom,geni-i2c"; 1265 reg = <0 0x00a8c000 0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1268 pinctrl-names = "default"; 1269 pinctrl-0 = <&qup_i2c9_default>; 1270 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1274 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1275 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1276 interconnect-names = "qup-core", "qup-config", 1277 "qup-memory"; 1278 power-domains = <&rpmhpd SC7180_CX>; 1279 required-opps = <&rpmhpd_opp_low_svs>; 1280 status = "disabled"; 1281 }; 1282 1283 uart9: serial@a8c000 { 1284 compatible = "qcom,geni-uart"; 1285 reg = <0 0x00a8c000 0 0x4000>; 1286 clock-names = "se"; 1287 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&qup_uart9_default>; 1290 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1291 power-domains = <&rpmhpd SC7180_CX>; 1292 operating-points-v2 = <&qup_opp_table>; 1293 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1294 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1295 interconnect-names = "qup-core", "qup-config"; 1296 status = "disabled"; 1297 }; 1298 1299 i2c10: i2c@a90000 { 1300 compatible = "qcom,geni-i2c"; 1301 reg = <0 0x00a90000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_i2c10_default>; 1306 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1311 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1312 interconnect-names = "qup-core", "qup-config", 1313 "qup-memory"; 1314 power-domains = <&rpmhpd SC7180_CX>; 1315 required-opps = <&rpmhpd_opp_low_svs>; 1316 status = "disabled"; 1317 }; 1318 1319 spi10: spi@a90000 { 1320 compatible = "qcom,geni-spi"; 1321 reg = <0 0x00a90000 0 0x4000>; 1322 clock-names = "se"; 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1326 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 power-domains = <&rpmhpd SC7180_CX>; 1330 operating-points-v2 = <&qup_opp_table>; 1331 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1333 interconnect-names = "qup-core", "qup-config"; 1334 status = "disabled"; 1335 }; 1336 1337 uart10: serial@a90000 { 1338 compatible = "qcom,geni-uart"; 1339 reg = <0 0x00a90000 0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_uart10_default>; 1344 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd SC7180_CX>; 1346 operating-points-v2 = <&qup_opp_table>; 1347 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1348 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1349 interconnect-names = "qup-core", "qup-config"; 1350 status = "disabled"; 1351 }; 1352 1353 i2c11: i2c@a94000 { 1354 compatible = "qcom,geni-i2c"; 1355 reg = <0 0x00a94000 0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_i2c11_default>; 1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1364 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1365 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1366 interconnect-names = "qup-core", "qup-config", 1367 "qup-memory"; 1368 power-domains = <&rpmhpd SC7180_CX>; 1369 required-opps = <&rpmhpd_opp_low_svs>; 1370 status = "disabled"; 1371 }; 1372 1373 spi11: spi@a94000 { 1374 compatible = "qcom,geni-spi"; 1375 reg = <0 0x00a94000 0 0x4000>; 1376 clock-names = "se"; 1377 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1378 pinctrl-names = "default"; 1379 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1380 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 power-domains = <&rpmhpd SC7180_CX>; 1384 operating-points-v2 = <&qup_opp_table>; 1385 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1386 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1387 interconnect-names = "qup-core", "qup-config"; 1388 status = "disabled"; 1389 }; 1390 1391 uart11: serial@a94000 { 1392 compatible = "qcom,geni-uart"; 1393 reg = <0 0x00a94000 0 0x4000>; 1394 clock-names = "se"; 1395 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_uart11_default>; 1398 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1399 power-domains = <&rpmhpd SC7180_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1402 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1403 interconnect-names = "qup-core", "qup-config"; 1404 status = "disabled"; 1405 }; 1406 }; 1407 1408 config_noc: interconnect@1500000 { 1409 compatible = "qcom,sc7180-config-noc"; 1410 reg = <0 0x01500000 0 0x28000>; 1411 #interconnect-cells = <2>; 1412 qcom,bcm-voters = <&apps_bcm_voter>; 1413 }; 1414 1415 system_noc: interconnect@1620000 { 1416 compatible = "qcom,sc7180-system-noc"; 1417 reg = <0 0x01620000 0 0x17080>; 1418 #interconnect-cells = <2>; 1419 qcom,bcm-voters = <&apps_bcm_voter>; 1420 }; 1421 1422 mc_virt: interconnect@1638000 { 1423 compatible = "qcom,sc7180-mc-virt"; 1424 reg = <0 0x01638000 0 0x1000>; 1425 #interconnect-cells = <2>; 1426 qcom,bcm-voters = <&apps_bcm_voter>; 1427 }; 1428 1429 qup_virt: interconnect@1650000 { 1430 compatible = "qcom,sc7180-qup-virt"; 1431 reg = <0 0x01650000 0 0x1000>; 1432 #interconnect-cells = <2>; 1433 qcom,bcm-voters = <&apps_bcm_voter>; 1434 }; 1435 1436 aggre1_noc: interconnect@16e0000 { 1437 compatible = "qcom,sc7180-aggre1-noc"; 1438 reg = <0 0x016e0000 0 0x15080>; 1439 #interconnect-cells = <2>; 1440 qcom,bcm-voters = <&apps_bcm_voter>; 1441 }; 1442 1443 aggre2_noc: interconnect@1705000 { 1444 compatible = "qcom,sc7180-aggre2-noc"; 1445 reg = <0 0x01705000 0 0x9000>; 1446 #interconnect-cells = <2>; 1447 qcom,bcm-voters = <&apps_bcm_voter>; 1448 }; 1449 1450 compute_noc: interconnect@170e000 { 1451 compatible = "qcom,sc7180-compute-noc"; 1452 reg = <0 0x0170e000 0 0x6000>; 1453 #interconnect-cells = <2>; 1454 qcom,bcm-voters = <&apps_bcm_voter>; 1455 }; 1456 1457 mmss_noc: interconnect@1740000 { 1458 compatible = "qcom,sc7180-mmss-noc"; 1459 reg = <0 0x01740000 0 0x1c100>; 1460 #interconnect-cells = <2>; 1461 qcom,bcm-voters = <&apps_bcm_voter>; 1462 }; 1463 1464 ipa: ipa@1e40000 { 1465 compatible = "qcom,sc7180-ipa"; 1466 1467 iommus = <&apps_smmu 0x440 0x0>, 1468 <&apps_smmu 0x442 0x0>; 1469 reg = <0 0x01e40000 0 0x7000>, 1470 <0 0x01e47000 0 0x2000>, 1471 <0 0x01e04000 0 0x2c000>; 1472 reg-names = "ipa-reg", 1473 "ipa-shared", 1474 "gsi"; 1475 1476 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1477 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1478 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1479 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1480 interrupt-names = "ipa", 1481 "gsi", 1482 "ipa-clock-query", 1483 "ipa-setup-ready"; 1484 1485 clocks = <&rpmhcc RPMH_IPA_CLK>; 1486 clock-names = "core"; 1487 1488 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1489 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1491 interconnect-names = "memory", 1492 "imem", 1493 "config"; 1494 1495 qcom,qmp = <&aoss_qmp>; 1496 1497 qcom,smem-states = <&ipa_smp2p_out 0>, 1498 <&ipa_smp2p_out 1>; 1499 qcom,smem-state-names = "ipa-clock-enabled-valid", 1500 "ipa-clock-enabled"; 1501 1502 status = "disabled"; 1503 }; 1504 1505 tcsr_mutex: hwlock@1f40000 { 1506 compatible = "qcom,tcsr-mutex"; 1507 reg = <0 0x01f40000 0 0x20000>; 1508 #hwlock-cells = <1>; 1509 }; 1510 1511 tcsr_regs_1: syscon@1f60000 { 1512 compatible = "qcom,sc7180-tcsr", "syscon"; 1513 reg = <0 0x01f60000 0 0x20000>; 1514 }; 1515 1516 tcsr_regs_2: syscon@1fc0000 { 1517 compatible = "qcom,sc7180-tcsr", "syscon"; 1518 reg = <0 0x01fc0000 0 0x40000>; 1519 }; 1520 1521 tlmm: pinctrl@3500000 { 1522 compatible = "qcom,sc7180-pinctrl"; 1523 reg = <0 0x03500000 0 0x300000>, 1524 <0 0x03900000 0 0x300000>, 1525 <0 0x03d00000 0 0x300000>; 1526 reg-names = "west", "north", "south"; 1527 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1528 gpio-controller; 1529 #gpio-cells = <2>; 1530 interrupt-controller; 1531 #interrupt-cells = <2>; 1532 gpio-ranges = <&tlmm 0 0 120>; 1533 wakeup-parent = <&pdc>; 1534 1535 dp_hot_plug_det: dp-hot-plug-det-state { 1536 pins = "gpio117"; 1537 function = "dp_hot"; 1538 }; 1539 1540 qspi_clk: qspi-clk-state { 1541 pins = "gpio63"; 1542 function = "qspi_clk"; 1543 }; 1544 1545 qspi_cs0: qspi-cs0-state { 1546 pins = "gpio68"; 1547 function = "qspi_cs"; 1548 }; 1549 1550 qspi_cs1: qspi-cs1-state { 1551 pins = "gpio72"; 1552 function = "qspi_cs"; 1553 }; 1554 1555 qspi_data0: qspi-data0-state { 1556 pins = "gpio64"; 1557 function = "qspi_data"; 1558 }; 1559 1560 qspi_data1: qspi-data1-state { 1561 pins = "gpio65"; 1562 function = "qspi_data"; 1563 }; 1564 1565 qspi_data23: qspi-data23-state { 1566 pins = "gpio66", "gpio67"; 1567 function = "qspi_data"; 1568 }; 1569 1570 qup_i2c0_default: qup-i2c0-default-state { 1571 pins = "gpio34", "gpio35"; 1572 function = "qup00"; 1573 }; 1574 1575 qup_i2c1_default: qup-i2c1-default-state { 1576 pins = "gpio0", "gpio1"; 1577 function = "qup01"; 1578 }; 1579 1580 qup_i2c2_default: qup-i2c2-default-state { 1581 pins = "gpio15", "gpio16"; 1582 function = "qup02_i2c"; 1583 }; 1584 1585 qup_i2c3_default: qup-i2c3-default-state { 1586 pins = "gpio38", "gpio39"; 1587 function = "qup03"; 1588 }; 1589 1590 qup_i2c4_default: qup-i2c4-default-state { 1591 pins = "gpio115", "gpio116"; 1592 function = "qup04_i2c"; 1593 }; 1594 1595 qup_i2c5_default: qup-i2c5-default-state { 1596 pins = "gpio25", "gpio26"; 1597 function = "qup05"; 1598 }; 1599 1600 qup_i2c6_default: qup-i2c6-default-state { 1601 pins = "gpio59", "gpio60"; 1602 function = "qup10"; 1603 }; 1604 1605 qup_i2c7_default: qup-i2c7-default-state { 1606 pins = "gpio6", "gpio7"; 1607 function = "qup11_i2c"; 1608 }; 1609 1610 qup_i2c8_default: qup-i2c8-default-state { 1611 pins = "gpio42", "gpio43"; 1612 function = "qup12"; 1613 }; 1614 1615 qup_i2c9_default: qup-i2c9-default-state { 1616 pins = "gpio46", "gpio47"; 1617 function = "qup13_i2c"; 1618 }; 1619 1620 qup_i2c10_default: qup-i2c10-default-state { 1621 pins = "gpio86", "gpio87"; 1622 function = "qup14"; 1623 }; 1624 1625 qup_i2c11_default: qup-i2c11-default-state { 1626 pins = "gpio53", "gpio54"; 1627 function = "qup15"; 1628 }; 1629 1630 qup_spi0_spi: qup-spi0-spi-state { 1631 pins = "gpio34", "gpio35", "gpio36"; 1632 function = "qup00"; 1633 }; 1634 1635 qup_spi0_cs: qup-spi0-cs-state { 1636 pins = "gpio37"; 1637 function = "qup00"; 1638 }; 1639 1640 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1641 pins = "gpio37"; 1642 function = "gpio"; 1643 }; 1644 1645 qup_spi1_spi: qup-spi1-spi-state { 1646 pins = "gpio0", "gpio1", "gpio2"; 1647 function = "qup01"; 1648 }; 1649 1650 qup_spi1_cs: qup-spi1-cs-state { 1651 pins = "gpio3"; 1652 function = "qup01"; 1653 }; 1654 1655 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1656 pins = "gpio3"; 1657 function = "gpio"; 1658 }; 1659 1660 qup_spi3_spi: qup-spi3-spi-state { 1661 pins = "gpio38", "gpio39", "gpio40"; 1662 function = "qup03"; 1663 }; 1664 1665 qup_spi3_cs: qup-spi3-cs-state { 1666 pins = "gpio41"; 1667 function = "qup03"; 1668 }; 1669 1670 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1671 pins = "gpio41"; 1672 function = "gpio"; 1673 }; 1674 1675 qup_spi5_spi: qup-spi5-spi-state { 1676 pins = "gpio25", "gpio26", "gpio27"; 1677 function = "qup05"; 1678 }; 1679 1680 qup_spi5_cs: qup-spi5-cs-state { 1681 pins = "gpio28"; 1682 function = "qup05"; 1683 }; 1684 1685 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1686 pins = "gpio28"; 1687 function = "gpio"; 1688 }; 1689 1690 qup_spi6_spi: qup-spi6-spi-state { 1691 pins = "gpio59", "gpio60", "gpio61"; 1692 function = "qup10"; 1693 }; 1694 1695 qup_spi6_cs: qup-spi6-cs-state { 1696 pins = "gpio62"; 1697 function = "qup10"; 1698 }; 1699 1700 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1701 pins = "gpio62"; 1702 function = "gpio"; 1703 }; 1704 1705 qup_spi8_spi: qup-spi8-spi-state { 1706 pins = "gpio42", "gpio43", "gpio44"; 1707 function = "qup12"; 1708 }; 1709 1710 qup_spi8_cs: qup-spi8-cs-state { 1711 pins = "gpio45"; 1712 function = "qup12"; 1713 }; 1714 1715 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1716 pins = "gpio45"; 1717 function = "gpio"; 1718 }; 1719 1720 qup_spi10_spi: qup-spi10-spi-state { 1721 pins = "gpio86", "gpio87", "gpio88"; 1722 function = "qup14"; 1723 }; 1724 1725 qup_spi10_cs: qup-spi10-cs-state { 1726 pins = "gpio89"; 1727 function = "qup14"; 1728 }; 1729 1730 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1731 pins = "gpio89"; 1732 function = "gpio"; 1733 }; 1734 1735 qup_spi11_spi: qup-spi11-spi-state { 1736 pins = "gpio53", "gpio54", "gpio55"; 1737 function = "qup15"; 1738 }; 1739 1740 qup_spi11_cs: qup-spi11-cs-state { 1741 pins = "gpio56"; 1742 function = "qup15"; 1743 }; 1744 1745 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1746 pins = "gpio56"; 1747 function = "gpio"; 1748 }; 1749 1750 qup_uart0_default: qup-uart0-default-state { 1751 qup_uart0_cts: cts-pins { 1752 pins = "gpio34"; 1753 function = "qup00"; 1754 }; 1755 1756 qup_uart0_rts: rts-pins { 1757 pins = "gpio35"; 1758 function = "qup00"; 1759 }; 1760 1761 qup_uart0_tx: tx-pins { 1762 pins = "gpio36"; 1763 function = "qup00"; 1764 }; 1765 1766 qup_uart0_rx: rx-pins { 1767 pins = "gpio37"; 1768 function = "qup00"; 1769 }; 1770 }; 1771 1772 qup_uart1_default: qup-uart1-default-state { 1773 qup_uart1_cts: cts-pins { 1774 pins = "gpio0"; 1775 function = "qup01"; 1776 }; 1777 1778 qup_uart1_rts: rts-pins { 1779 pins = "gpio1"; 1780 function = "qup01"; 1781 }; 1782 1783 qup_uart1_tx: tx-pins { 1784 pins = "gpio2"; 1785 function = "qup01"; 1786 }; 1787 1788 qup_uart1_rx: rx-pins { 1789 pins = "gpio3"; 1790 function = "qup01"; 1791 }; 1792 }; 1793 1794 qup_uart2_default: qup-uart2-default-state { 1795 qup_uart2_tx: tx-pins { 1796 pins = "gpio15"; 1797 function = "qup02_uart"; 1798 }; 1799 1800 qup_uart2_rx: rx-pins { 1801 pins = "gpio16"; 1802 function = "qup02_uart"; 1803 }; 1804 }; 1805 1806 qup_uart3_default: qup-uart3-default-state { 1807 qup_uart3_cts: cts-pins { 1808 pins = "gpio38"; 1809 function = "qup03"; 1810 }; 1811 1812 qup_uart3_rts: rts-pins { 1813 pins = "gpio39"; 1814 function = "qup03"; 1815 }; 1816 1817 qup_uart3_tx: tx-pins { 1818 pins = "gpio40"; 1819 function = "qup03"; 1820 }; 1821 1822 qup_uart3_rx: rx-pins { 1823 pins = "gpio41"; 1824 function = "qup03"; 1825 }; 1826 }; 1827 1828 qup_uart4_default: qup-uart4-default-state { 1829 qup_uart4_tx: tx-pins { 1830 pins = "gpio115"; 1831 function = "qup04_uart"; 1832 }; 1833 1834 qup_uart4_rx: rx-pins { 1835 pins = "gpio116"; 1836 function = "qup04_uart"; 1837 }; 1838 }; 1839 1840 qup_uart5_default: qup-uart5-default-state { 1841 qup_uart5_cts: cts-pins { 1842 pins = "gpio25"; 1843 function = "qup05"; 1844 }; 1845 1846 qup_uart5_rts: rts-pins { 1847 pins = "gpio26"; 1848 function = "qup05"; 1849 }; 1850 1851 qup_uart5_tx: tx-pins { 1852 pins = "gpio27"; 1853 function = "qup05"; 1854 }; 1855 1856 qup_uart5_rx: rx-pins { 1857 pins = "gpio28"; 1858 function = "qup05"; 1859 }; 1860 }; 1861 1862 qup_uart6_default: qup-uart6-default-state { 1863 qup_uart6_cts: cts-pins { 1864 pins = "gpio59"; 1865 function = "qup10"; 1866 }; 1867 1868 qup_uart6_rts: rts-pins { 1869 pins = "gpio60"; 1870 function = "qup10"; 1871 }; 1872 1873 qup_uart6_tx: tx-pins { 1874 pins = "gpio61"; 1875 function = "qup10"; 1876 }; 1877 1878 qup_uart6_rx: rx-pins { 1879 pins = "gpio62"; 1880 function = "qup10"; 1881 }; 1882 }; 1883 1884 qup_uart7_default: qup-uart7-default-state { 1885 qup_uart7_tx: tx-pins { 1886 pins = "gpio6"; 1887 function = "qup11_uart"; 1888 }; 1889 1890 qup_uart7_rx: rx-pins { 1891 pins = "gpio7"; 1892 function = "qup11_uart"; 1893 }; 1894 }; 1895 1896 qup_uart8_default: qup-uart8-default-state { 1897 qup_uart8_tx: tx-pins { 1898 pins = "gpio44"; 1899 function = "qup12"; 1900 }; 1901 1902 qup_uart8_rx: rx-pins { 1903 pins = "gpio45"; 1904 function = "qup12"; 1905 }; 1906 }; 1907 1908 qup_uart9_default: qup-uart9-default-state { 1909 qup_uart9_tx: tx-pins { 1910 pins = "gpio46"; 1911 function = "qup13_uart"; 1912 }; 1913 1914 qup_uart9_rx: rx-pins { 1915 pins = "gpio47"; 1916 function = "qup13_uart"; 1917 }; 1918 }; 1919 1920 qup_uart10_default: qup-uart10-default-state { 1921 qup_uart10_cts: cts-pins { 1922 pins = "gpio86"; 1923 function = "qup14"; 1924 }; 1925 1926 qup_uart10_rts: rts-pins { 1927 pins = "gpio87"; 1928 function = "qup14"; 1929 }; 1930 1931 qup_uart10_tx: tx-pins { 1932 pins = "gpio88"; 1933 function = "qup14"; 1934 }; 1935 1936 qup_uart10_rx: rx-pins { 1937 pins = "gpio89"; 1938 function = "qup14"; 1939 }; 1940 }; 1941 1942 qup_uart11_default: qup-uart11-default-state { 1943 qup_uart11_cts: cts-pins { 1944 pins = "gpio53"; 1945 function = "qup15"; 1946 }; 1947 1948 qup_uart11_rts: rts-pins { 1949 pins = "gpio54"; 1950 function = "qup15"; 1951 }; 1952 1953 qup_uart11_tx: tx-pins { 1954 pins = "gpio55"; 1955 function = "qup15"; 1956 }; 1957 1958 qup_uart11_rx: rx-pins { 1959 pins = "gpio56"; 1960 function = "qup15"; 1961 }; 1962 }; 1963 1964 sec_mi2s_active: sec-mi2s-active-state { 1965 pins = "gpio49", "gpio50", "gpio51"; 1966 function = "mi2s_1"; 1967 }; 1968 1969 pri_mi2s_active: pri-mi2s-active-state { 1970 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1971 function = "mi2s_0"; 1972 }; 1973 1974 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 1975 pins = "gpio57"; 1976 function = "lpass_ext"; 1977 }; 1978 }; 1979 1980 remoteproc_mpss: remoteproc@4080000 { 1981 compatible = "qcom,sc7180-mpss-pas"; 1982 reg = <0 0x04080000 0 0x4040>; 1983 1984 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1985 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1986 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1987 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1988 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1989 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1990 interrupt-names = "wdog", "fatal", "ready", "handover", 1991 "stop-ack", "shutdown-ack"; 1992 1993 clocks = <&rpmhcc RPMH_CXO_CLK>; 1994 clock-names = "xo"; 1995 1996 power-domains = <&rpmhpd SC7180_CX>, 1997 <&rpmhpd SC7180_MX>, 1998 <&rpmhpd SC7180_MSS>; 1999 power-domain-names = "cx", "mx", "mss"; 2000 2001 memory-region = <&mpss_mem>; 2002 2003 qcom,qmp = <&aoss_qmp>; 2004 2005 qcom,smem-states = <&modem_smp2p_out 0>; 2006 qcom,smem-state-names = "stop"; 2007 2008 status = "disabled"; 2009 2010 glink-edge { 2011 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2012 label = "modem"; 2013 qcom,remote-pid = <1>; 2014 mboxes = <&apss_shared 12>; 2015 }; 2016 }; 2017 2018 gpu: gpu@5000000 { 2019 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2020 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2021 <0 0x05061000 0 0x800>; 2022 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2023 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2024 iommus = <&adreno_smmu 0>; 2025 operating-points-v2 = <&gpu_opp_table>; 2026 qcom,gmu = <&gmu>; 2027 2028 #cooling-cells = <2>; 2029 2030 nvmem-cells = <&gpu_speed_bin>; 2031 nvmem-cell-names = "speed_bin"; 2032 2033 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2034 interconnect-names = "gfx-mem"; 2035 2036 gpu_opp_table: opp-table { 2037 compatible = "operating-points-v2"; 2038 2039 opp-825000000 { 2040 opp-hz = /bits/ 64 <825000000>; 2041 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2042 opp-peak-kBps = <8532000>; 2043 opp-supported-hw = <0x04>; 2044 }; 2045 2046 opp-800000000 { 2047 opp-hz = /bits/ 64 <800000000>; 2048 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2049 opp-peak-kBps = <8532000>; 2050 opp-supported-hw = <0x07>; 2051 }; 2052 2053 opp-650000000 { 2054 opp-hz = /bits/ 64 <650000000>; 2055 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2056 opp-peak-kBps = <7216000>; 2057 opp-supported-hw = <0x07>; 2058 }; 2059 2060 opp-565000000 { 2061 opp-hz = /bits/ 64 <565000000>; 2062 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2063 opp-peak-kBps = <5412000>; 2064 opp-supported-hw = <0x07>; 2065 }; 2066 2067 opp-430000000 { 2068 opp-hz = /bits/ 64 <430000000>; 2069 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2070 opp-peak-kBps = <5412000>; 2071 opp-supported-hw = <0x07>; 2072 }; 2073 2074 opp-355000000 { 2075 opp-hz = /bits/ 64 <355000000>; 2076 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2077 opp-peak-kBps = <3072000>; 2078 opp-supported-hw = <0x07>; 2079 }; 2080 2081 opp-267000000 { 2082 opp-hz = /bits/ 64 <267000000>; 2083 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2084 opp-peak-kBps = <3072000>; 2085 opp-supported-hw = <0x07>; 2086 }; 2087 2088 opp-180000000 { 2089 opp-hz = /bits/ 64 <180000000>; 2090 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2091 opp-peak-kBps = <1804000>; 2092 opp-supported-hw = <0x07>; 2093 }; 2094 }; 2095 }; 2096 2097 adreno_smmu: iommu@5040000 { 2098 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2099 reg = <0 0x05040000 0 0x10000>; 2100 #iommu-cells = <1>; 2101 #global-interrupts = <2>; 2102 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2105 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2106 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2107 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2108 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2109 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2110 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2111 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2112 2113 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2114 <&gcc GCC_GPU_CFG_AHB_CLK>; 2115 clock-names = "bus", "iface"; 2116 2117 power-domains = <&gpucc CX_GDSC>; 2118 }; 2119 2120 gmu: gmu@506a000 { 2121 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2122 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2123 <0 0x0b490000 0 0x10000>; 2124 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2125 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2127 interrupt-names = "hfi", "gmu"; 2128 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2129 <&gpucc GPU_CC_CXO_CLK>, 2130 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2131 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2132 clock-names = "gmu", "cxo", "axi", "memnoc"; 2133 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2134 power-domain-names = "cx", "gx"; 2135 iommus = <&adreno_smmu 5>; 2136 operating-points-v2 = <&gmu_opp_table>; 2137 2138 gmu_opp_table: opp-table { 2139 compatible = "operating-points-v2"; 2140 2141 opp-200000000 { 2142 opp-hz = /bits/ 64 <200000000>; 2143 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2144 }; 2145 }; 2146 }; 2147 2148 gpucc: clock-controller@5090000 { 2149 compatible = "qcom,sc7180-gpucc"; 2150 reg = <0 0x05090000 0 0x9000>; 2151 clocks = <&rpmhcc RPMH_CXO_CLK>, 2152 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2153 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2154 clock-names = "bi_tcxo", 2155 "gcc_gpu_gpll0_clk_src", 2156 "gcc_gpu_gpll0_div_clk_src"; 2157 #clock-cells = <1>; 2158 #reset-cells = <1>; 2159 #power-domain-cells = <1>; 2160 }; 2161 2162 dma@10a2000 { 2163 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2164 reg = <0x0 0x010a2000 0x0 0x1000>, 2165 <0x0 0x010ae000 0x0 0x2000>; 2166 }; 2167 2168 stm@6002000 { 2169 compatible = "arm,coresight-stm", "arm,primecell"; 2170 reg = <0 0x06002000 0 0x1000>, 2171 <0 0x16280000 0 0x180000>; 2172 reg-names = "stm-base", "stm-stimulus-base"; 2173 2174 clocks = <&aoss_qmp>; 2175 clock-names = "apb_pclk"; 2176 2177 out-ports { 2178 port { 2179 stm_out: endpoint { 2180 remote-endpoint = <&funnel0_in7>; 2181 }; 2182 }; 2183 }; 2184 }; 2185 2186 funnel@6041000 { 2187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2188 reg = <0 0x06041000 0 0x1000>; 2189 2190 clocks = <&aoss_qmp>; 2191 clock-names = "apb_pclk"; 2192 2193 out-ports { 2194 port { 2195 funnel0_out: endpoint { 2196 remote-endpoint = <&merge_funnel_in0>; 2197 }; 2198 }; 2199 }; 2200 2201 in-ports { 2202 #address-cells = <1>; 2203 #size-cells = <0>; 2204 2205 port@7 { 2206 reg = <7>; 2207 funnel0_in7: endpoint { 2208 remote-endpoint = <&stm_out>; 2209 }; 2210 }; 2211 }; 2212 }; 2213 2214 funnel@6042000 { 2215 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2216 reg = <0 0x06042000 0 0x1000>; 2217 2218 clocks = <&aoss_qmp>; 2219 clock-names = "apb_pclk"; 2220 2221 out-ports { 2222 port { 2223 funnel1_out: endpoint { 2224 remote-endpoint = <&merge_funnel_in1>; 2225 }; 2226 }; 2227 }; 2228 2229 in-ports { 2230 #address-cells = <1>; 2231 #size-cells = <0>; 2232 2233 port@4 { 2234 reg = <4>; 2235 funnel1_in4: endpoint { 2236 remote-endpoint = <&apss_merge_funnel_out>; 2237 }; 2238 }; 2239 }; 2240 }; 2241 2242 funnel@6045000 { 2243 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2244 reg = <0 0x06045000 0 0x1000>; 2245 2246 clocks = <&aoss_qmp>; 2247 clock-names = "apb_pclk"; 2248 2249 out-ports { 2250 port { 2251 merge_funnel_out: endpoint { 2252 remote-endpoint = <&swao_funnel_in>; 2253 }; 2254 }; 2255 }; 2256 2257 in-ports { 2258 #address-cells = <1>; 2259 #size-cells = <0>; 2260 2261 port@0 { 2262 reg = <0>; 2263 merge_funnel_in0: endpoint { 2264 remote-endpoint = <&funnel0_out>; 2265 }; 2266 }; 2267 2268 port@1 { 2269 reg = <1>; 2270 merge_funnel_in1: endpoint { 2271 remote-endpoint = <&funnel1_out>; 2272 }; 2273 }; 2274 }; 2275 }; 2276 2277 replicator@6046000 { 2278 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2279 reg = <0 0x06046000 0 0x1000>; 2280 2281 clocks = <&aoss_qmp>; 2282 clock-names = "apb_pclk"; 2283 2284 out-ports { 2285 port { 2286 replicator_out: endpoint { 2287 remote-endpoint = <&etr_in>; 2288 }; 2289 }; 2290 }; 2291 2292 in-ports { 2293 port { 2294 replicator_in: endpoint { 2295 remote-endpoint = <&swao_replicator_out>; 2296 }; 2297 }; 2298 }; 2299 }; 2300 2301 etr@6048000 { 2302 compatible = "arm,coresight-tmc", "arm,primecell"; 2303 reg = <0 0x06048000 0 0x1000>; 2304 iommus = <&apps_smmu 0x04a0 0x20>; 2305 2306 clocks = <&aoss_qmp>; 2307 clock-names = "apb_pclk"; 2308 arm,scatter-gather; 2309 2310 in-ports { 2311 port { 2312 etr_in: endpoint { 2313 remote-endpoint = <&replicator_out>; 2314 }; 2315 }; 2316 }; 2317 }; 2318 2319 funnel@6b04000 { 2320 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2321 reg = <0 0x06b04000 0 0x1000>; 2322 2323 clocks = <&aoss_qmp>; 2324 clock-names = "apb_pclk"; 2325 2326 out-ports { 2327 port { 2328 swao_funnel_out: endpoint { 2329 remote-endpoint = <&etf_in>; 2330 }; 2331 }; 2332 }; 2333 2334 in-ports { 2335 #address-cells = <1>; 2336 #size-cells = <0>; 2337 2338 port@7 { 2339 reg = <7>; 2340 swao_funnel_in: endpoint { 2341 remote-endpoint = <&merge_funnel_out>; 2342 }; 2343 }; 2344 }; 2345 }; 2346 2347 etf@6b05000 { 2348 compatible = "arm,coresight-tmc", "arm,primecell"; 2349 reg = <0 0x06b05000 0 0x1000>; 2350 2351 clocks = <&aoss_qmp>; 2352 clock-names = "apb_pclk"; 2353 2354 out-ports { 2355 port { 2356 etf_out: endpoint { 2357 remote-endpoint = <&swao_replicator_in>; 2358 }; 2359 }; 2360 }; 2361 2362 in-ports { 2363 port { 2364 etf_in: endpoint { 2365 remote-endpoint = <&swao_funnel_out>; 2366 }; 2367 }; 2368 }; 2369 }; 2370 2371 replicator@6b06000 { 2372 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2373 reg = <0 0x06b06000 0 0x1000>; 2374 2375 clocks = <&aoss_qmp>; 2376 clock-names = "apb_pclk"; 2377 qcom,replicator-loses-context; 2378 2379 out-ports { 2380 port { 2381 swao_replicator_out: endpoint { 2382 remote-endpoint = <&replicator_in>; 2383 }; 2384 }; 2385 }; 2386 2387 in-ports { 2388 port { 2389 swao_replicator_in: endpoint { 2390 remote-endpoint = <&etf_out>; 2391 }; 2392 }; 2393 }; 2394 }; 2395 2396 etm@7040000 { 2397 compatible = "arm,coresight-etm4x", "arm,primecell"; 2398 reg = <0 0x07040000 0 0x1000>; 2399 2400 cpu = <&CPU0>; 2401 2402 clocks = <&aoss_qmp>; 2403 clock-names = "apb_pclk"; 2404 arm,coresight-loses-context-with-cpu; 2405 qcom,skip-power-up; 2406 2407 out-ports { 2408 port { 2409 etm0_out: endpoint { 2410 remote-endpoint = <&apss_funnel_in0>; 2411 }; 2412 }; 2413 }; 2414 }; 2415 2416 etm@7140000 { 2417 compatible = "arm,coresight-etm4x", "arm,primecell"; 2418 reg = <0 0x07140000 0 0x1000>; 2419 2420 cpu = <&CPU1>; 2421 2422 clocks = <&aoss_qmp>; 2423 clock-names = "apb_pclk"; 2424 arm,coresight-loses-context-with-cpu; 2425 qcom,skip-power-up; 2426 2427 out-ports { 2428 port { 2429 etm1_out: endpoint { 2430 remote-endpoint = <&apss_funnel_in1>; 2431 }; 2432 }; 2433 }; 2434 }; 2435 2436 etm@7240000 { 2437 compatible = "arm,coresight-etm4x", "arm,primecell"; 2438 reg = <0 0x07240000 0 0x1000>; 2439 2440 cpu = <&CPU2>; 2441 2442 clocks = <&aoss_qmp>; 2443 clock-names = "apb_pclk"; 2444 arm,coresight-loses-context-with-cpu; 2445 qcom,skip-power-up; 2446 2447 out-ports { 2448 port { 2449 etm2_out: endpoint { 2450 remote-endpoint = <&apss_funnel_in2>; 2451 }; 2452 }; 2453 }; 2454 }; 2455 2456 etm@7340000 { 2457 compatible = "arm,coresight-etm4x", "arm,primecell"; 2458 reg = <0 0x07340000 0 0x1000>; 2459 2460 cpu = <&CPU3>; 2461 2462 clocks = <&aoss_qmp>; 2463 clock-names = "apb_pclk"; 2464 arm,coresight-loses-context-with-cpu; 2465 qcom,skip-power-up; 2466 2467 out-ports { 2468 port { 2469 etm3_out: endpoint { 2470 remote-endpoint = <&apss_funnel_in3>; 2471 }; 2472 }; 2473 }; 2474 }; 2475 2476 etm@7440000 { 2477 compatible = "arm,coresight-etm4x", "arm,primecell"; 2478 reg = <0 0x07440000 0 0x1000>; 2479 2480 cpu = <&CPU4>; 2481 2482 clocks = <&aoss_qmp>; 2483 clock-names = "apb_pclk"; 2484 arm,coresight-loses-context-with-cpu; 2485 qcom,skip-power-up; 2486 2487 out-ports { 2488 port { 2489 etm4_out: endpoint { 2490 remote-endpoint = <&apss_funnel_in4>; 2491 }; 2492 }; 2493 }; 2494 }; 2495 2496 etm@7540000 { 2497 compatible = "arm,coresight-etm4x", "arm,primecell"; 2498 reg = <0 0x07540000 0 0x1000>; 2499 2500 cpu = <&CPU5>; 2501 2502 clocks = <&aoss_qmp>; 2503 clock-names = "apb_pclk"; 2504 arm,coresight-loses-context-with-cpu; 2505 qcom,skip-power-up; 2506 2507 out-ports { 2508 port { 2509 etm5_out: endpoint { 2510 remote-endpoint = <&apss_funnel_in5>; 2511 }; 2512 }; 2513 }; 2514 }; 2515 2516 etm@7640000 { 2517 compatible = "arm,coresight-etm4x", "arm,primecell"; 2518 reg = <0 0x07640000 0 0x1000>; 2519 2520 cpu = <&CPU6>; 2521 2522 clocks = <&aoss_qmp>; 2523 clock-names = "apb_pclk"; 2524 arm,coresight-loses-context-with-cpu; 2525 qcom,skip-power-up; 2526 2527 out-ports { 2528 port { 2529 etm6_out: endpoint { 2530 remote-endpoint = <&apss_funnel_in6>; 2531 }; 2532 }; 2533 }; 2534 }; 2535 2536 etm@7740000 { 2537 compatible = "arm,coresight-etm4x", "arm,primecell"; 2538 reg = <0 0x07740000 0 0x1000>; 2539 2540 cpu = <&CPU7>; 2541 2542 clocks = <&aoss_qmp>; 2543 clock-names = "apb_pclk"; 2544 arm,coresight-loses-context-with-cpu; 2545 qcom,skip-power-up; 2546 2547 out-ports { 2548 port { 2549 etm7_out: endpoint { 2550 remote-endpoint = <&apss_funnel_in7>; 2551 }; 2552 }; 2553 }; 2554 }; 2555 2556 funnel@7800000 { /* APSS Funnel */ 2557 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2558 reg = <0 0x07800000 0 0x1000>; 2559 2560 clocks = <&aoss_qmp>; 2561 clock-names = "apb_pclk"; 2562 2563 out-ports { 2564 port { 2565 apss_funnel_out: endpoint { 2566 remote-endpoint = <&apss_merge_funnel_in>; 2567 }; 2568 }; 2569 }; 2570 2571 in-ports { 2572 #address-cells = <1>; 2573 #size-cells = <0>; 2574 2575 port@0 { 2576 reg = <0>; 2577 apss_funnel_in0: endpoint { 2578 remote-endpoint = <&etm0_out>; 2579 }; 2580 }; 2581 2582 port@1 { 2583 reg = <1>; 2584 apss_funnel_in1: endpoint { 2585 remote-endpoint = <&etm1_out>; 2586 }; 2587 }; 2588 2589 port@2 { 2590 reg = <2>; 2591 apss_funnel_in2: endpoint { 2592 remote-endpoint = <&etm2_out>; 2593 }; 2594 }; 2595 2596 port@3 { 2597 reg = <3>; 2598 apss_funnel_in3: endpoint { 2599 remote-endpoint = <&etm3_out>; 2600 }; 2601 }; 2602 2603 port@4 { 2604 reg = <4>; 2605 apss_funnel_in4: endpoint { 2606 remote-endpoint = <&etm4_out>; 2607 }; 2608 }; 2609 2610 port@5 { 2611 reg = <5>; 2612 apss_funnel_in5: endpoint { 2613 remote-endpoint = <&etm5_out>; 2614 }; 2615 }; 2616 2617 port@6 { 2618 reg = <6>; 2619 apss_funnel_in6: endpoint { 2620 remote-endpoint = <&etm6_out>; 2621 }; 2622 }; 2623 2624 port@7 { 2625 reg = <7>; 2626 apss_funnel_in7: endpoint { 2627 remote-endpoint = <&etm7_out>; 2628 }; 2629 }; 2630 }; 2631 }; 2632 2633 funnel@7810000 { 2634 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2635 reg = <0 0x07810000 0 0x1000>; 2636 2637 clocks = <&aoss_qmp>; 2638 clock-names = "apb_pclk"; 2639 2640 out-ports { 2641 port { 2642 apss_merge_funnel_out: endpoint { 2643 remote-endpoint = <&funnel1_in4>; 2644 }; 2645 }; 2646 }; 2647 2648 in-ports { 2649 port { 2650 apss_merge_funnel_in: endpoint { 2651 remote-endpoint = <&apss_funnel_out>; 2652 }; 2653 }; 2654 }; 2655 }; 2656 2657 sdhc_2: mmc@8804000 { 2658 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2659 reg = <0 0x08804000 0 0x1000>; 2660 2661 iommus = <&apps_smmu 0x80 0>; 2662 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2663 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2664 interrupt-names = "hc_irq", "pwr_irq"; 2665 2666 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2667 <&gcc GCC_SDCC2_APPS_CLK>, 2668 <&rpmhcc RPMH_CXO_CLK>; 2669 clock-names = "iface", "core", "xo"; 2670 2671 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2672 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2673 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2674 power-domains = <&rpmhpd SC7180_CX>; 2675 operating-points-v2 = <&sdhc2_opp_table>; 2676 2677 bus-width = <4>; 2678 2679 status = "disabled"; 2680 2681 sdhc2_opp_table: opp-table { 2682 compatible = "operating-points-v2"; 2683 2684 opp-100000000 { 2685 opp-hz = /bits/ 64 <100000000>; 2686 required-opps = <&rpmhpd_opp_low_svs>; 2687 opp-peak-kBps = <1800000 600000>; 2688 opp-avg-kBps = <100000 0>; 2689 }; 2690 2691 opp-202000000 { 2692 opp-hz = /bits/ 64 <202000000>; 2693 required-opps = <&rpmhpd_opp_nom>; 2694 opp-peak-kBps = <5400000 1600000>; 2695 opp-avg-kBps = <200000 0>; 2696 }; 2697 }; 2698 }; 2699 2700 qspi: spi@88dc000 { 2701 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2702 reg = <0 0x088dc000 0 0x600>; 2703 iommus = <&apps_smmu 0x20 0x0>; 2704 #address-cells = <1>; 2705 #size-cells = <0>; 2706 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2707 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2708 <&gcc GCC_QSPI_CORE_CLK>; 2709 clock-names = "iface", "core"; 2710 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2711 &config_noc SLAVE_QSPI_0 0>; 2712 interconnect-names = "qspi-config"; 2713 power-domains = <&rpmhpd SC7180_CX>; 2714 operating-points-v2 = <&qspi_opp_table>; 2715 status = "disabled"; 2716 }; 2717 2718 usb_1_hsphy: phy@88e3000 { 2719 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2720 reg = <0 0x088e3000 0 0x400>; 2721 status = "disabled"; 2722 #phy-cells = <0>; 2723 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2724 <&rpmhcc RPMH_CXO_CLK>; 2725 clock-names = "cfg_ahb", "ref"; 2726 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2727 2728 nvmem-cells = <&qusb2p_hstx_trim>; 2729 }; 2730 2731 usb_1_qmpphy: phy-wrapper@88e9000 { 2732 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2733 reg = <0 0x088e9000 0 0x18c>, 2734 <0 0x088e8000 0 0x3c>, 2735 <0 0x088ea000 0 0x18c>; 2736 status = "disabled"; 2737 #address-cells = <2>; 2738 #size-cells = <2>; 2739 ranges; 2740 2741 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2742 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2743 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2744 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2745 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2746 2747 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2748 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2749 reset-names = "phy", "common"; 2750 2751 usb_1_ssphy: usb3-phy@88e9200 { 2752 reg = <0 0x088e9200 0 0x128>, 2753 <0 0x088e9400 0 0x200>, 2754 <0 0x088e9c00 0 0x218>, 2755 <0 0x088e9600 0 0x128>, 2756 <0 0x088e9800 0 0x200>, 2757 <0 0x088e9a00 0 0x18>; 2758 #clock-cells = <0>; 2759 #phy-cells = <0>; 2760 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2761 clock-names = "pipe0"; 2762 clock-output-names = "usb3_phy_pipe_clk_src"; 2763 }; 2764 2765 dp_phy: dp-phy@88ea200 { 2766 reg = <0 0x088ea200 0 0x200>, 2767 <0 0x088ea400 0 0x200>, 2768 <0 0x088eaa00 0 0x200>, 2769 <0 0x088ea600 0 0x200>, 2770 <0 0x088ea800 0 0x200>; 2771 #clock-cells = <1>; 2772 #phy-cells = <0>; 2773 }; 2774 }; 2775 2776 dc_noc: interconnect@9160000 { 2777 compatible = "qcom,sc7180-dc-noc"; 2778 reg = <0 0x09160000 0 0x03200>; 2779 #interconnect-cells = <2>; 2780 qcom,bcm-voters = <&apps_bcm_voter>; 2781 }; 2782 2783 system-cache-controller@9200000 { 2784 compatible = "qcom,sc7180-llcc"; 2785 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2786 reg-names = "llcc0_base", "llcc_broadcast_base"; 2787 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2788 }; 2789 2790 gem_noc: interconnect@9680000 { 2791 compatible = "qcom,sc7180-gem-noc"; 2792 reg = <0 0x09680000 0 0x3e200>; 2793 #interconnect-cells = <2>; 2794 qcom,bcm-voters = <&apps_bcm_voter>; 2795 }; 2796 2797 npu_noc: interconnect@9990000 { 2798 compatible = "qcom,sc7180-npu-noc"; 2799 reg = <0 0x09990000 0 0x1600>; 2800 #interconnect-cells = <2>; 2801 qcom,bcm-voters = <&apps_bcm_voter>; 2802 }; 2803 2804 usb_1: usb@a6f8800 { 2805 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2806 reg = <0 0x0a6f8800 0 0x400>; 2807 status = "disabled"; 2808 #address-cells = <2>; 2809 #size-cells = <2>; 2810 ranges; 2811 dma-ranges; 2812 2813 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2814 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2815 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2816 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2817 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2818 clock-names = "cfg_noc", 2819 "core", 2820 "iface", 2821 "sleep", 2822 "mock_utmi"; 2823 2824 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2825 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2826 assigned-clock-rates = <19200000>, <150000000>; 2827 2828 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2829 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2830 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2831 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2832 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2833 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2834 2835 power-domains = <&gcc USB30_PRIM_GDSC>; 2836 required-opps = <&rpmhpd_opp_nom>; 2837 2838 resets = <&gcc GCC_USB30_PRIM_BCR>; 2839 2840 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2842 interconnect-names = "usb-ddr", "apps-usb"; 2843 2844 wakeup-source; 2845 2846 usb_1_dwc3: usb@a600000 { 2847 compatible = "snps,dwc3"; 2848 reg = <0 0x0a600000 0 0xe000>; 2849 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2850 iommus = <&apps_smmu 0x540 0>; 2851 snps,dis_u2_susphy_quirk; 2852 snps,dis_enblslpm_quirk; 2853 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2854 phy-names = "usb2-phy", "usb3-phy"; 2855 maximum-speed = "super-speed"; 2856 }; 2857 }; 2858 2859 venus: video-codec@aa00000 { 2860 compatible = "qcom,sc7180-venus"; 2861 reg = <0 0x0aa00000 0 0xff000>; 2862 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2863 power-domains = <&videocc VENUS_GDSC>, 2864 <&videocc VCODEC0_GDSC>, 2865 <&rpmhpd SC7180_CX>; 2866 power-domain-names = "venus", "vcodec0", "cx"; 2867 operating-points-v2 = <&venus_opp_table>; 2868 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2869 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2870 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2871 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2872 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2873 clock-names = "core", "iface", "bus", 2874 "vcodec0_core", "vcodec0_bus"; 2875 iommus = <&apps_smmu 0x0c00 0x60>; 2876 memory-region = <&venus_mem>; 2877 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2879 interconnect-names = "video-mem", "cpu-cfg"; 2880 2881 video-decoder { 2882 compatible = "venus-decoder"; 2883 }; 2884 2885 video-encoder { 2886 compatible = "venus-encoder"; 2887 }; 2888 2889 venus_opp_table: opp-table { 2890 compatible = "operating-points-v2"; 2891 2892 opp-150000000 { 2893 opp-hz = /bits/ 64 <150000000>; 2894 required-opps = <&rpmhpd_opp_low_svs>; 2895 }; 2896 2897 opp-270000000 { 2898 opp-hz = /bits/ 64 <270000000>; 2899 required-opps = <&rpmhpd_opp_svs>; 2900 }; 2901 2902 opp-340000000 { 2903 opp-hz = /bits/ 64 <340000000>; 2904 required-opps = <&rpmhpd_opp_svs_l1>; 2905 }; 2906 2907 opp-434000000 { 2908 opp-hz = /bits/ 64 <434000000>; 2909 required-opps = <&rpmhpd_opp_nom>; 2910 }; 2911 2912 opp-500000097 { 2913 opp-hz = /bits/ 64 <500000097>; 2914 required-opps = <&rpmhpd_opp_turbo>; 2915 }; 2916 }; 2917 }; 2918 2919 videocc: clock-controller@ab00000 { 2920 compatible = "qcom,sc7180-videocc"; 2921 reg = <0 0x0ab00000 0 0x10000>; 2922 clocks = <&rpmhcc RPMH_CXO_CLK>; 2923 clock-names = "bi_tcxo"; 2924 #clock-cells = <1>; 2925 #reset-cells = <1>; 2926 #power-domain-cells = <1>; 2927 }; 2928 2929 camnoc_virt: interconnect@ac00000 { 2930 compatible = "qcom,sc7180-camnoc-virt"; 2931 reg = <0 0x0ac00000 0 0x1000>; 2932 #interconnect-cells = <2>; 2933 qcom,bcm-voters = <&apps_bcm_voter>; 2934 }; 2935 2936 camcc: clock-controller@ad00000 { 2937 compatible = "qcom,sc7180-camcc"; 2938 reg = <0 0x0ad00000 0 0x10000>; 2939 clocks = <&rpmhcc RPMH_CXO_CLK>, 2940 <&gcc GCC_CAMERA_AHB_CLK>, 2941 <&gcc GCC_CAMERA_XO_CLK>; 2942 clock-names = "bi_tcxo", "iface", "xo"; 2943 #clock-cells = <1>; 2944 #reset-cells = <1>; 2945 #power-domain-cells = <1>; 2946 }; 2947 2948 mdss: display-subsystem@ae00000 { 2949 compatible = "qcom,sc7180-mdss"; 2950 reg = <0 0x0ae00000 0 0x1000>; 2951 reg-names = "mdss"; 2952 2953 power-domains = <&dispcc MDSS_GDSC>; 2954 2955 clocks = <&gcc GCC_DISP_AHB_CLK>, 2956 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2957 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2958 clock-names = "iface", "ahb", "core"; 2959 2960 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2961 interrupt-controller; 2962 #interrupt-cells = <1>; 2963 2964 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2965 interconnect-names = "mdp0-mem"; 2966 2967 iommus = <&apps_smmu 0x800 0x2>; 2968 2969 #address-cells = <2>; 2970 #size-cells = <2>; 2971 ranges; 2972 2973 status = "disabled"; 2974 2975 mdp: display-controller@ae01000 { 2976 compatible = "qcom,sc7180-dpu"; 2977 reg = <0 0x0ae01000 0 0x8f000>, 2978 <0 0x0aeb0000 0 0x2008>; 2979 reg-names = "mdp", "vbif"; 2980 2981 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2982 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2983 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2984 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2985 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2986 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2987 clock-names = "bus", "iface", "rot", "lut", "core", 2988 "vsync"; 2989 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2990 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2991 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2992 assigned-clock-rates = <19200000>, 2993 <19200000>, 2994 <19200000>; 2995 operating-points-v2 = <&mdp_opp_table>; 2996 power-domains = <&rpmhpd SC7180_CX>; 2997 2998 interrupt-parent = <&mdss>; 2999 interrupts = <0>; 3000 3001 ports { 3002 #address-cells = <1>; 3003 #size-cells = <0>; 3004 3005 port@0 { 3006 reg = <0>; 3007 dpu_intf1_out: endpoint { 3008 remote-endpoint = <&mdss_dsi0_in>; 3009 }; 3010 }; 3011 3012 port@2 { 3013 reg = <2>; 3014 dpu_intf0_out: endpoint { 3015 remote-endpoint = <&dp_in>; 3016 }; 3017 }; 3018 }; 3019 3020 mdp_opp_table: opp-table { 3021 compatible = "operating-points-v2"; 3022 3023 opp-200000000 { 3024 opp-hz = /bits/ 64 <200000000>; 3025 required-opps = <&rpmhpd_opp_low_svs>; 3026 }; 3027 3028 opp-300000000 { 3029 opp-hz = /bits/ 64 <300000000>; 3030 required-opps = <&rpmhpd_opp_svs>; 3031 }; 3032 3033 opp-345000000 { 3034 opp-hz = /bits/ 64 <345000000>; 3035 required-opps = <&rpmhpd_opp_svs_l1>; 3036 }; 3037 3038 opp-460000000 { 3039 opp-hz = /bits/ 64 <460000000>; 3040 required-opps = <&rpmhpd_opp_nom>; 3041 }; 3042 }; 3043 }; 3044 3045 mdss_dsi0: dsi@ae94000 { 3046 compatible = "qcom,sc7180-dsi-ctrl", 3047 "qcom,mdss-dsi-ctrl"; 3048 reg = <0 0x0ae94000 0 0x400>; 3049 reg-names = "dsi_ctrl"; 3050 3051 interrupt-parent = <&mdss>; 3052 interrupts = <4>; 3053 3054 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3055 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3056 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3057 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3058 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3059 <&gcc GCC_DISP_HF_AXI_CLK>; 3060 clock-names = "byte", 3061 "byte_intf", 3062 "pixel", 3063 "core", 3064 "iface", 3065 "bus"; 3066 3067 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3068 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3069 3070 operating-points-v2 = <&dsi_opp_table>; 3071 power-domains = <&rpmhpd SC7180_CX>; 3072 3073 phys = <&mdss_dsi0_phy>; 3074 3075 #address-cells = <1>; 3076 #size-cells = <0>; 3077 3078 status = "disabled"; 3079 3080 ports { 3081 #address-cells = <1>; 3082 #size-cells = <0>; 3083 3084 port@0 { 3085 reg = <0>; 3086 mdss_dsi0_in: endpoint { 3087 remote-endpoint = <&dpu_intf1_out>; 3088 }; 3089 }; 3090 3091 port@1 { 3092 reg = <1>; 3093 mdss_dsi0_out: endpoint { 3094 }; 3095 }; 3096 }; 3097 3098 dsi_opp_table: opp-table { 3099 compatible = "operating-points-v2"; 3100 3101 opp-187500000 { 3102 opp-hz = /bits/ 64 <187500000>; 3103 required-opps = <&rpmhpd_opp_low_svs>; 3104 }; 3105 3106 opp-300000000 { 3107 opp-hz = /bits/ 64 <300000000>; 3108 required-opps = <&rpmhpd_opp_svs>; 3109 }; 3110 3111 opp-358000000 { 3112 opp-hz = /bits/ 64 <358000000>; 3113 required-opps = <&rpmhpd_opp_svs_l1>; 3114 }; 3115 }; 3116 }; 3117 3118 mdss_dsi0_phy: phy@ae94400 { 3119 compatible = "qcom,dsi-phy-10nm"; 3120 reg = <0 0x0ae94400 0 0x200>, 3121 <0 0x0ae94600 0 0x280>, 3122 <0 0x0ae94a00 0 0x1e0>; 3123 reg-names = "dsi0_phy", 3124 "dsi0_phy_lane", 3125 "dsi_pll"; 3126 3127 #clock-cells = <1>; 3128 #phy-cells = <0>; 3129 3130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3131 <&rpmhcc RPMH_CXO_CLK>; 3132 clock-names = "iface", "ref"; 3133 3134 status = "disabled"; 3135 }; 3136 3137 mdss_dp: displayport-controller@ae90000 { 3138 compatible = "qcom,sc7180-dp"; 3139 status = "disabled"; 3140 3141 reg = <0 0x0ae90000 0 0x200>, 3142 <0 0x0ae90200 0 0x200>, 3143 <0 0x0ae90400 0 0xc00>, 3144 <0 0x0ae91000 0 0x400>, 3145 <0 0x0ae91400 0 0x400>; 3146 3147 interrupt-parent = <&mdss>; 3148 interrupts = <12>; 3149 3150 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3151 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3152 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3153 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3154 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3155 clock-names = "core_iface", "core_aux", "ctrl_link", 3156 "ctrl_link_iface", "stream_pixel"; 3157 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3158 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3159 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3160 phys = <&dp_phy>; 3161 phy-names = "dp"; 3162 3163 operating-points-v2 = <&dp_opp_table>; 3164 power-domains = <&rpmhpd SC7180_CX>; 3165 3166 #sound-dai-cells = <0>; 3167 3168 ports { 3169 #address-cells = <1>; 3170 #size-cells = <0>; 3171 port@0 { 3172 reg = <0>; 3173 dp_in: endpoint { 3174 remote-endpoint = <&dpu_intf0_out>; 3175 }; 3176 }; 3177 3178 port@1 { 3179 reg = <1>; 3180 mdss_dp_out: endpoint { }; 3181 }; 3182 }; 3183 3184 dp_opp_table: opp-table { 3185 compatible = "operating-points-v2"; 3186 3187 opp-160000000 { 3188 opp-hz = /bits/ 64 <160000000>; 3189 required-opps = <&rpmhpd_opp_low_svs>; 3190 }; 3191 3192 opp-270000000 { 3193 opp-hz = /bits/ 64 <270000000>; 3194 required-opps = <&rpmhpd_opp_svs>; 3195 }; 3196 3197 opp-540000000 { 3198 opp-hz = /bits/ 64 <540000000>; 3199 required-opps = <&rpmhpd_opp_svs_l1>; 3200 }; 3201 3202 opp-810000000 { 3203 opp-hz = /bits/ 64 <810000000>; 3204 required-opps = <&rpmhpd_opp_nom>; 3205 }; 3206 }; 3207 }; 3208 }; 3209 3210 dispcc: clock-controller@af00000 { 3211 compatible = "qcom,sc7180-dispcc"; 3212 reg = <0 0x0af00000 0 0x200000>; 3213 clocks = <&rpmhcc RPMH_CXO_CLK>, 3214 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3215 <&mdss_dsi0_phy 0>, 3216 <&mdss_dsi0_phy 1>, 3217 <&dp_phy 0>, 3218 <&dp_phy 1>; 3219 clock-names = "bi_tcxo", 3220 "gcc_disp_gpll0_clk_src", 3221 "dsi0_phy_pll_out_byteclk", 3222 "dsi0_phy_pll_out_dsiclk", 3223 "dp_phy_pll_link_clk", 3224 "dp_phy_pll_vco_div_clk"; 3225 #clock-cells = <1>; 3226 #reset-cells = <1>; 3227 #power-domain-cells = <1>; 3228 }; 3229 3230 pdc: interrupt-controller@b220000 { 3231 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3232 reg = <0 0x0b220000 0 0x30000>; 3233 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3234 #interrupt-cells = <2>; 3235 interrupt-parent = <&intc>; 3236 interrupt-controller; 3237 }; 3238 3239 pdc_reset: reset-controller@b2e0000 { 3240 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3241 reg = <0 0x0b2e0000 0 0x20000>; 3242 #reset-cells = <1>; 3243 }; 3244 3245 tsens0: thermal-sensor@c263000 { 3246 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3247 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3248 <0 0x0c222000 0 0x1ff>; /* SROT */ 3249 #qcom,sensors = <15>; 3250 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3252 interrupt-names = "uplow","critical"; 3253 #thermal-sensor-cells = <1>; 3254 }; 3255 3256 tsens1: thermal-sensor@c265000 { 3257 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3258 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3259 <0 0x0c223000 0 0x1ff>; /* SROT */ 3260 #qcom,sensors = <10>; 3261 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3263 interrupt-names = "uplow","critical"; 3264 #thermal-sensor-cells = <1>; 3265 }; 3266 3267 aoss_reset: reset-controller@c2a0000 { 3268 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3269 reg = <0 0x0c2a0000 0 0x31000>; 3270 #reset-cells = <1>; 3271 }; 3272 3273 aoss_qmp: power-management@c300000 { 3274 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3275 reg = <0 0x0c300000 0 0x400>; 3276 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3277 mboxes = <&apss_shared 0>; 3278 3279 #clock-cells = <0>; 3280 }; 3281 3282 sram@c3f0000 { 3283 compatible = "qcom,rpmh-stats"; 3284 reg = <0 0x0c3f0000 0 0x400>; 3285 }; 3286 3287 spmi_bus: spmi@c440000 { 3288 compatible = "qcom,spmi-pmic-arb"; 3289 reg = <0 0x0c440000 0 0x1100>, 3290 <0 0x0c600000 0 0x2000000>, 3291 <0 0x0e600000 0 0x100000>, 3292 <0 0x0e700000 0 0xa0000>, 3293 <0 0x0c40a000 0 0x26000>; 3294 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3295 interrupt-names = "periph_irq"; 3296 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3297 qcom,ee = <0>; 3298 qcom,channel = <0>; 3299 #address-cells = <2>; 3300 #size-cells = <0>; 3301 interrupt-controller; 3302 #interrupt-cells = <4>; 3303 }; 3304 3305 sram@146aa000 { 3306 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3307 reg = <0 0x146aa000 0 0x2000>; 3308 3309 #address-cells = <1>; 3310 #size-cells = <1>; 3311 3312 ranges = <0 0 0x146aa000 0x2000>; 3313 3314 pil-reloc@94c { 3315 compatible = "qcom,pil-reloc-info"; 3316 reg = <0x94c 0xc8>; 3317 }; 3318 }; 3319 3320 apps_smmu: iommu@15000000 { 3321 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3322 reg = <0 0x15000000 0 0x100000>; 3323 #iommu-cells = <2>; 3324 #global-interrupts = <1>; 3325 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3406 }; 3407 3408 intc: interrupt-controller@17a00000 { 3409 compatible = "arm,gic-v3"; 3410 #address-cells = <2>; 3411 #size-cells = <2>; 3412 ranges; 3413 #interrupt-cells = <3>; 3414 interrupt-controller; 3415 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3416 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3417 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3418 3419 msi-controller@17a40000 { 3420 compatible = "arm,gic-v3-its"; 3421 msi-controller; 3422 #msi-cells = <1>; 3423 reg = <0 0x17a40000 0 0x20000>; 3424 status = "disabled"; 3425 }; 3426 }; 3427 3428 apss_shared: mailbox@17c00000 { 3429 compatible = "qcom,sc7180-apss-shared", 3430 "qcom,sdm845-apss-shared"; 3431 reg = <0 0x17c00000 0 0x10000>; 3432 #mbox-cells = <1>; 3433 }; 3434 3435 watchdog@17c10000 { 3436 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3437 reg = <0 0x17c10000 0 0x1000>; 3438 clocks = <&sleep_clk>; 3439 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3440 }; 3441 3442 timer@17c20000 { 3443 #address-cells = <1>; 3444 #size-cells = <1>; 3445 ranges = <0 0 0 0x20000000>; 3446 compatible = "arm,armv7-timer-mem"; 3447 reg = <0 0x17c20000 0 0x1000>; 3448 3449 frame@17c21000 { 3450 frame-number = <0>; 3451 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3453 reg = <0x17c21000 0x1000>, 3454 <0x17c22000 0x1000>; 3455 }; 3456 3457 frame@17c23000 { 3458 frame-number = <1>; 3459 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3460 reg = <0x17c23000 0x1000>; 3461 status = "disabled"; 3462 }; 3463 3464 frame@17c25000 { 3465 frame-number = <2>; 3466 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3467 reg = <0x17c25000 0x1000>; 3468 status = "disabled"; 3469 }; 3470 3471 frame@17c27000 { 3472 frame-number = <3>; 3473 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3474 reg = <0x17c27000 0x1000>; 3475 status = "disabled"; 3476 }; 3477 3478 frame@17c29000 { 3479 frame-number = <4>; 3480 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3481 reg = <0x17c29000 0x1000>; 3482 status = "disabled"; 3483 }; 3484 3485 frame@17c2b000 { 3486 frame-number = <5>; 3487 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3488 reg = <0x17c2b000 0x1000>; 3489 status = "disabled"; 3490 }; 3491 3492 frame@17c2d000 { 3493 frame-number = <6>; 3494 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3495 reg = <0x17c2d000 0x1000>; 3496 status = "disabled"; 3497 }; 3498 }; 3499 3500 apps_rsc: rsc@18200000 { 3501 compatible = "qcom,rpmh-rsc"; 3502 reg = <0 0x18200000 0 0x10000>, 3503 <0 0x18210000 0 0x10000>, 3504 <0 0x18220000 0 0x10000>; 3505 reg-names = "drv-0", "drv-1", "drv-2"; 3506 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3509 qcom,tcs-offset = <0xd00>; 3510 qcom,drv-id = <2>; 3511 qcom,tcs-config = <ACTIVE_TCS 2>, 3512 <SLEEP_TCS 3>, 3513 <WAKE_TCS 3>, 3514 <CONTROL_TCS 1>; 3515 3516 rpmhcc: clock-controller { 3517 compatible = "qcom,sc7180-rpmh-clk"; 3518 clocks = <&xo_board>; 3519 clock-names = "xo"; 3520 #clock-cells = <1>; 3521 }; 3522 3523 rpmhpd: power-controller { 3524 compatible = "qcom,sc7180-rpmhpd"; 3525 #power-domain-cells = <1>; 3526 operating-points-v2 = <&rpmhpd_opp_table>; 3527 3528 rpmhpd_opp_table: opp-table { 3529 compatible = "operating-points-v2"; 3530 3531 rpmhpd_opp_ret: opp1 { 3532 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3533 }; 3534 3535 rpmhpd_opp_min_svs: opp2 { 3536 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3537 }; 3538 3539 rpmhpd_opp_low_svs: opp3 { 3540 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3541 }; 3542 3543 rpmhpd_opp_svs: opp4 { 3544 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3545 }; 3546 3547 rpmhpd_opp_svs_l1: opp5 { 3548 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3549 }; 3550 3551 rpmhpd_opp_svs_l2: opp6 { 3552 opp-level = <224>; 3553 }; 3554 3555 rpmhpd_opp_nom: opp7 { 3556 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3557 }; 3558 3559 rpmhpd_opp_nom_l1: opp8 { 3560 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3561 }; 3562 3563 rpmhpd_opp_nom_l2: opp9 { 3564 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3565 }; 3566 3567 rpmhpd_opp_turbo: opp10 { 3568 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3569 }; 3570 3571 rpmhpd_opp_turbo_l1: opp11 { 3572 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3573 }; 3574 }; 3575 }; 3576 3577 apps_bcm_voter: bcm-voter { 3578 compatible = "qcom,bcm-voter"; 3579 }; 3580 }; 3581 3582 osm_l3: interconnect@18321000 { 3583 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3584 reg = <0 0x18321000 0 0x1400>; 3585 3586 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3587 clock-names = "xo", "alternate"; 3588 3589 #interconnect-cells = <1>; 3590 }; 3591 3592 cpufreq_hw: cpufreq@18323000 { 3593 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; 3594 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3595 reg-names = "freq-domain0", "freq-domain1"; 3596 3597 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3598 clock-names = "xo", "alternate"; 3599 3600 #freq-domain-cells = <1>; 3601 #clock-cells = <1>; 3602 }; 3603 3604 wifi: wifi@18800000 { 3605 compatible = "qcom,wcn3990-wifi"; 3606 reg = <0 0x18800000 0 0x800000>; 3607 reg-names = "membase"; 3608 iommus = <&apps_smmu 0xc0 0x1>; 3609 interrupts = 3610 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3611 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3612 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3613 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3614 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3615 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3616 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3617 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3618 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3619 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3620 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3621 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3622 memory-region = <&wlan_mem>; 3623 qcom,msa-fixed-perm; 3624 status = "disabled"; 3625 }; 3626 3627 lpasscc: clock-controller@62d00000 { 3628 compatible = "qcom,sc7180-lpasscorecc"; 3629 reg = <0 0x62d00000 0 0x50000>, 3630 <0 0x62780000 0 0x30000>; 3631 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3632 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3633 <&rpmhcc RPMH_CXO_CLK>; 3634 clock-names = "iface", "bi_tcxo"; 3635 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3636 #clock-cells = <1>; 3637 #power-domain-cells = <1>; 3638 3639 status = "reserved"; /* Controlled by ADSP */ 3640 }; 3641 3642 lpass_cpu: lpass@62d87000 { 3643 compatible = "qcom,sc7180-lpass-cpu"; 3644 3645 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3646 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3647 3648 iommus = <&apps_smmu 0x1020 0>, 3649 <&apps_smmu 0x1021 0>, 3650 <&apps_smmu 0x1032 0>; 3651 3652 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3653 required-opps = <&rpmhpd_opp_nom>; 3654 3655 status = "disabled"; 3656 3657 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3658 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3659 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3660 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3661 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3662 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3663 3664 clock-names = "pcnoc-sway-clk", "audio-core", 3665 "mclk0", "pcnoc-mport-clk", 3666 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3667 3668 3669 #sound-dai-cells = <1>; 3670 #address-cells = <1>; 3671 #size-cells = <0>; 3672 3673 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3675 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3676 }; 3677 3678 lpass_hm: clock-controller@63000000 { 3679 compatible = "qcom,sc7180-lpasshm"; 3680 reg = <0 0x63000000 0 0x28>; 3681 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3682 <&rpmhcc RPMH_CXO_CLK>; 3683 clock-names = "iface", "bi_tcxo"; 3684 power-domains = <&rpmhpd SC7180_CX>; 3685 3686 #clock-cells = <1>; 3687 #power-domain-cells = <1>; 3688 3689 status = "reserved"; /* Controlled by ADSP */ 3690 }; 3691 }; 3692 3693 thermal-zones { 3694 cpu0_thermal: cpu0-thermal { 3695 polling-delay-passive = <250>; 3696 polling-delay = <0>; 3697 3698 thermal-sensors = <&tsens0 1>; 3699 sustainable-power = <1052>; 3700 3701 trips { 3702 cpu0_alert0: trip-point0 { 3703 temperature = <90000>; 3704 hysteresis = <2000>; 3705 type = "passive"; 3706 }; 3707 3708 cpu0_alert1: trip-point1 { 3709 temperature = <95000>; 3710 hysteresis = <2000>; 3711 type = "passive"; 3712 }; 3713 3714 cpu0_crit: cpu-crit { 3715 temperature = <110000>; 3716 hysteresis = <1000>; 3717 type = "critical"; 3718 }; 3719 }; 3720 3721 cooling-maps { 3722 map0 { 3723 trip = <&cpu0_alert0>; 3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3728 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3730 }; 3731 map1 { 3732 trip = <&cpu0_alert1>; 3733 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3734 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3735 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3736 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3739 }; 3740 }; 3741 }; 3742 3743 cpu1_thermal: cpu1-thermal { 3744 polling-delay-passive = <250>; 3745 polling-delay = <0>; 3746 3747 thermal-sensors = <&tsens0 2>; 3748 sustainable-power = <1052>; 3749 3750 trips { 3751 cpu1_alert0: trip-point0 { 3752 temperature = <90000>; 3753 hysteresis = <2000>; 3754 type = "passive"; 3755 }; 3756 3757 cpu1_alert1: trip-point1 { 3758 temperature = <95000>; 3759 hysteresis = <2000>; 3760 type = "passive"; 3761 }; 3762 3763 cpu1_crit: cpu-crit { 3764 temperature = <110000>; 3765 hysteresis = <1000>; 3766 type = "critical"; 3767 }; 3768 }; 3769 3770 cooling-maps { 3771 map0 { 3772 trip = <&cpu1_alert0>; 3773 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3774 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3776 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3777 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3778 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3779 }; 3780 map1 { 3781 trip = <&cpu1_alert1>; 3782 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3783 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3785 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3787 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3788 }; 3789 }; 3790 }; 3791 3792 cpu2_thermal: cpu2-thermal { 3793 polling-delay-passive = <250>; 3794 polling-delay = <0>; 3795 3796 thermal-sensors = <&tsens0 3>; 3797 sustainable-power = <1052>; 3798 3799 trips { 3800 cpu2_alert0: trip-point0 { 3801 temperature = <90000>; 3802 hysteresis = <2000>; 3803 type = "passive"; 3804 }; 3805 3806 cpu2_alert1: trip-point1 { 3807 temperature = <95000>; 3808 hysteresis = <2000>; 3809 type = "passive"; 3810 }; 3811 3812 cpu2_crit: cpu-crit { 3813 temperature = <110000>; 3814 hysteresis = <1000>; 3815 type = "critical"; 3816 }; 3817 }; 3818 3819 cooling-maps { 3820 map0 { 3821 trip = <&cpu2_alert0>; 3822 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3826 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3827 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3828 }; 3829 map1 { 3830 trip = <&cpu2_alert1>; 3831 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3832 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3833 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3834 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3837 }; 3838 }; 3839 }; 3840 3841 cpu3_thermal: cpu3-thermal { 3842 polling-delay-passive = <250>; 3843 polling-delay = <0>; 3844 3845 thermal-sensors = <&tsens0 4>; 3846 sustainable-power = <1052>; 3847 3848 trips { 3849 cpu3_alert0: trip-point0 { 3850 temperature = <90000>; 3851 hysteresis = <2000>; 3852 type = "passive"; 3853 }; 3854 3855 cpu3_alert1: trip-point1 { 3856 temperature = <95000>; 3857 hysteresis = <2000>; 3858 type = "passive"; 3859 }; 3860 3861 cpu3_crit: cpu-crit { 3862 temperature = <110000>; 3863 hysteresis = <1000>; 3864 type = "critical"; 3865 }; 3866 }; 3867 3868 cooling-maps { 3869 map0 { 3870 trip = <&cpu3_alert0>; 3871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3875 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3876 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3877 }; 3878 map1 { 3879 trip = <&cpu3_alert1>; 3880 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3882 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3883 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3884 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3886 }; 3887 }; 3888 }; 3889 3890 cpu4_thermal: cpu4-thermal { 3891 polling-delay-passive = <250>; 3892 polling-delay = <0>; 3893 3894 thermal-sensors = <&tsens0 5>; 3895 sustainable-power = <1052>; 3896 3897 trips { 3898 cpu4_alert0: trip-point0 { 3899 temperature = <90000>; 3900 hysteresis = <2000>; 3901 type = "passive"; 3902 }; 3903 3904 cpu4_alert1: trip-point1 { 3905 temperature = <95000>; 3906 hysteresis = <2000>; 3907 type = "passive"; 3908 }; 3909 3910 cpu4_crit: cpu-crit { 3911 temperature = <110000>; 3912 hysteresis = <1000>; 3913 type = "critical"; 3914 }; 3915 }; 3916 3917 cooling-maps { 3918 map0 { 3919 trip = <&cpu4_alert0>; 3920 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3923 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3926 }; 3927 map1 { 3928 trip = <&cpu4_alert1>; 3929 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3933 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3934 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3935 }; 3936 }; 3937 }; 3938 3939 cpu5_thermal: cpu5-thermal { 3940 polling-delay-passive = <250>; 3941 polling-delay = <0>; 3942 3943 thermal-sensors = <&tsens0 6>; 3944 sustainable-power = <1052>; 3945 3946 trips { 3947 cpu5_alert0: trip-point0 { 3948 temperature = <90000>; 3949 hysteresis = <2000>; 3950 type = "passive"; 3951 }; 3952 3953 cpu5_alert1: trip-point1 { 3954 temperature = <95000>; 3955 hysteresis = <2000>; 3956 type = "passive"; 3957 }; 3958 3959 cpu5_crit: cpu-crit { 3960 temperature = <110000>; 3961 hysteresis = <1000>; 3962 type = "critical"; 3963 }; 3964 }; 3965 3966 cooling-maps { 3967 map0 { 3968 trip = <&cpu5_alert0>; 3969 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3970 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3971 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3972 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3973 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3975 }; 3976 map1 { 3977 trip = <&cpu5_alert1>; 3978 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3979 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3980 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3984 }; 3985 }; 3986 }; 3987 3988 cpu6_thermal: cpu6-thermal { 3989 polling-delay-passive = <250>; 3990 polling-delay = <0>; 3991 3992 thermal-sensors = <&tsens0 9>; 3993 sustainable-power = <1425>; 3994 3995 trips { 3996 cpu6_alert0: trip-point0 { 3997 temperature = <90000>; 3998 hysteresis = <2000>; 3999 type = "passive"; 4000 }; 4001 4002 cpu6_alert1: trip-point1 { 4003 temperature = <95000>; 4004 hysteresis = <2000>; 4005 type = "passive"; 4006 }; 4007 4008 cpu6_crit: cpu-crit { 4009 temperature = <110000>; 4010 hysteresis = <1000>; 4011 type = "critical"; 4012 }; 4013 }; 4014 4015 cooling-maps { 4016 map0 { 4017 trip = <&cpu6_alert0>; 4018 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4019 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4020 }; 4021 map1 { 4022 trip = <&cpu6_alert1>; 4023 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4024 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4025 }; 4026 }; 4027 }; 4028 4029 cpu7_thermal: cpu7-thermal { 4030 polling-delay-passive = <250>; 4031 polling-delay = <0>; 4032 4033 thermal-sensors = <&tsens0 10>; 4034 sustainable-power = <1425>; 4035 4036 trips { 4037 cpu7_alert0: trip-point0 { 4038 temperature = <90000>; 4039 hysteresis = <2000>; 4040 type = "passive"; 4041 }; 4042 4043 cpu7_alert1: trip-point1 { 4044 temperature = <95000>; 4045 hysteresis = <2000>; 4046 type = "passive"; 4047 }; 4048 4049 cpu7_crit: cpu-crit { 4050 temperature = <110000>; 4051 hysteresis = <1000>; 4052 type = "critical"; 4053 }; 4054 }; 4055 4056 cooling-maps { 4057 map0 { 4058 trip = <&cpu7_alert0>; 4059 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4060 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4061 }; 4062 map1 { 4063 trip = <&cpu7_alert1>; 4064 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4065 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4066 }; 4067 }; 4068 }; 4069 4070 cpu8_thermal: cpu8-thermal { 4071 polling-delay-passive = <250>; 4072 polling-delay = <0>; 4073 4074 thermal-sensors = <&tsens0 11>; 4075 sustainable-power = <1425>; 4076 4077 trips { 4078 cpu8_alert0: trip-point0 { 4079 temperature = <90000>; 4080 hysteresis = <2000>; 4081 type = "passive"; 4082 }; 4083 4084 cpu8_alert1: trip-point1 { 4085 temperature = <95000>; 4086 hysteresis = <2000>; 4087 type = "passive"; 4088 }; 4089 4090 cpu8_crit: cpu-crit { 4091 temperature = <110000>; 4092 hysteresis = <1000>; 4093 type = "critical"; 4094 }; 4095 }; 4096 4097 cooling-maps { 4098 map0 { 4099 trip = <&cpu8_alert0>; 4100 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4101 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4102 }; 4103 map1 { 4104 trip = <&cpu8_alert1>; 4105 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4106 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4107 }; 4108 }; 4109 }; 4110 4111 cpu9_thermal: cpu9-thermal { 4112 polling-delay-passive = <250>; 4113 polling-delay = <0>; 4114 4115 thermal-sensors = <&tsens0 12>; 4116 sustainable-power = <1425>; 4117 4118 trips { 4119 cpu9_alert0: trip-point0 { 4120 temperature = <90000>; 4121 hysteresis = <2000>; 4122 type = "passive"; 4123 }; 4124 4125 cpu9_alert1: trip-point1 { 4126 temperature = <95000>; 4127 hysteresis = <2000>; 4128 type = "passive"; 4129 }; 4130 4131 cpu9_crit: cpu-crit { 4132 temperature = <110000>; 4133 hysteresis = <1000>; 4134 type = "critical"; 4135 }; 4136 }; 4137 4138 cooling-maps { 4139 map0 { 4140 trip = <&cpu9_alert0>; 4141 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4142 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4143 }; 4144 map1 { 4145 trip = <&cpu9_alert1>; 4146 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4147 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4148 }; 4149 }; 4150 }; 4151 4152 aoss0-thermal { 4153 polling-delay-passive = <250>; 4154 polling-delay = <0>; 4155 4156 thermal-sensors = <&tsens0 0>; 4157 4158 trips { 4159 aoss0_alert0: trip-point0 { 4160 temperature = <90000>; 4161 hysteresis = <2000>; 4162 type = "hot"; 4163 }; 4164 4165 aoss0_crit: aoss0-crit { 4166 temperature = <110000>; 4167 hysteresis = <2000>; 4168 type = "critical"; 4169 }; 4170 }; 4171 }; 4172 4173 cpuss0-thermal { 4174 polling-delay-passive = <250>; 4175 polling-delay = <0>; 4176 4177 thermal-sensors = <&tsens0 7>; 4178 4179 trips { 4180 cpuss0_alert0: trip-point0 { 4181 temperature = <90000>; 4182 hysteresis = <2000>; 4183 type = "hot"; 4184 }; 4185 cpuss0_crit: cluster0-crit { 4186 temperature = <110000>; 4187 hysteresis = <2000>; 4188 type = "critical"; 4189 }; 4190 }; 4191 }; 4192 4193 cpuss1-thermal { 4194 polling-delay-passive = <250>; 4195 polling-delay = <0>; 4196 4197 thermal-sensors = <&tsens0 8>; 4198 4199 trips { 4200 cpuss1_alert0: trip-point0 { 4201 temperature = <90000>; 4202 hysteresis = <2000>; 4203 type = "hot"; 4204 }; 4205 cpuss1_crit: cluster0-crit { 4206 temperature = <110000>; 4207 hysteresis = <2000>; 4208 type = "critical"; 4209 }; 4210 }; 4211 }; 4212 4213 gpuss0-thermal { 4214 polling-delay-passive = <250>; 4215 polling-delay = <0>; 4216 4217 thermal-sensors = <&tsens0 13>; 4218 4219 trips { 4220 gpuss0_alert0: trip-point0 { 4221 temperature = <95000>; 4222 hysteresis = <2000>; 4223 type = "passive"; 4224 }; 4225 4226 gpuss0_crit: gpuss0-crit { 4227 temperature = <110000>; 4228 hysteresis = <2000>; 4229 type = "critical"; 4230 }; 4231 }; 4232 4233 cooling-maps { 4234 map0 { 4235 trip = <&gpuss0_alert0>; 4236 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4237 }; 4238 }; 4239 }; 4240 4241 gpuss1-thermal { 4242 polling-delay-passive = <250>; 4243 polling-delay = <0>; 4244 4245 thermal-sensors = <&tsens0 14>; 4246 4247 trips { 4248 gpuss1_alert0: trip-point0 { 4249 temperature = <95000>; 4250 hysteresis = <2000>; 4251 type = "passive"; 4252 }; 4253 4254 gpuss1_crit: gpuss1-crit { 4255 temperature = <110000>; 4256 hysteresis = <2000>; 4257 type = "critical"; 4258 }; 4259 }; 4260 4261 cooling-maps { 4262 map0 { 4263 trip = <&gpuss1_alert0>; 4264 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4265 }; 4266 }; 4267 }; 4268 4269 aoss1-thermal { 4270 polling-delay-passive = <250>; 4271 polling-delay = <0>; 4272 4273 thermal-sensors = <&tsens1 0>; 4274 4275 trips { 4276 aoss1_alert0: trip-point0 { 4277 temperature = <90000>; 4278 hysteresis = <2000>; 4279 type = "hot"; 4280 }; 4281 4282 aoss1_crit: aoss1-crit { 4283 temperature = <110000>; 4284 hysteresis = <2000>; 4285 type = "critical"; 4286 }; 4287 }; 4288 }; 4289 4290 cwlan-thermal { 4291 polling-delay-passive = <250>; 4292 polling-delay = <0>; 4293 4294 thermal-sensors = <&tsens1 1>; 4295 4296 trips { 4297 cwlan_alert0: trip-point0 { 4298 temperature = <90000>; 4299 hysteresis = <2000>; 4300 type = "hot"; 4301 }; 4302 4303 cwlan_crit: cwlan-crit { 4304 temperature = <110000>; 4305 hysteresis = <2000>; 4306 type = "critical"; 4307 }; 4308 }; 4309 }; 4310 4311 audio-thermal { 4312 polling-delay-passive = <250>; 4313 polling-delay = <0>; 4314 4315 thermal-sensors = <&tsens1 2>; 4316 4317 trips { 4318 audio_alert0: trip-point0 { 4319 temperature = <90000>; 4320 hysteresis = <2000>; 4321 type = "hot"; 4322 }; 4323 4324 audio_crit: audio-crit { 4325 temperature = <110000>; 4326 hysteresis = <2000>; 4327 type = "critical"; 4328 }; 4329 }; 4330 }; 4331 4332 ddr-thermal { 4333 polling-delay-passive = <250>; 4334 polling-delay = <0>; 4335 4336 thermal-sensors = <&tsens1 3>; 4337 4338 trips { 4339 ddr_alert0: trip-point0 { 4340 temperature = <90000>; 4341 hysteresis = <2000>; 4342 type = "hot"; 4343 }; 4344 4345 ddr_crit: ddr-crit { 4346 temperature = <110000>; 4347 hysteresis = <2000>; 4348 type = "critical"; 4349 }; 4350 }; 4351 }; 4352 4353 q6-hvx-thermal { 4354 polling-delay-passive = <250>; 4355 polling-delay = <0>; 4356 4357 thermal-sensors = <&tsens1 4>; 4358 4359 trips { 4360 q6_hvx_alert0: trip-point0 { 4361 temperature = <90000>; 4362 hysteresis = <2000>; 4363 type = "hot"; 4364 }; 4365 4366 q6_hvx_crit: q6-hvx-crit { 4367 temperature = <110000>; 4368 hysteresis = <2000>; 4369 type = "critical"; 4370 }; 4371 }; 4372 }; 4373 4374 camera-thermal { 4375 polling-delay-passive = <250>; 4376 polling-delay = <0>; 4377 4378 thermal-sensors = <&tsens1 5>; 4379 4380 trips { 4381 camera_alert0: trip-point0 { 4382 temperature = <90000>; 4383 hysteresis = <2000>; 4384 type = "hot"; 4385 }; 4386 4387 camera_crit: camera-crit { 4388 temperature = <110000>; 4389 hysteresis = <2000>; 4390 type = "critical"; 4391 }; 4392 }; 4393 }; 4394 4395 mdm-core-thermal { 4396 polling-delay-passive = <250>; 4397 polling-delay = <0>; 4398 4399 thermal-sensors = <&tsens1 6>; 4400 4401 trips { 4402 mdm_alert0: trip-point0 { 4403 temperature = <90000>; 4404 hysteresis = <2000>; 4405 type = "hot"; 4406 }; 4407 4408 mdm_crit: mdm-crit { 4409 temperature = <110000>; 4410 hysteresis = <2000>; 4411 type = "critical"; 4412 }; 4413 }; 4414 }; 4415 4416 mdm-dsp-thermal { 4417 polling-delay-passive = <250>; 4418 polling-delay = <0>; 4419 4420 thermal-sensors = <&tsens1 7>; 4421 4422 trips { 4423 mdm_dsp_alert0: trip-point0 { 4424 temperature = <90000>; 4425 hysteresis = <2000>; 4426 type = "hot"; 4427 }; 4428 4429 mdm_dsp_crit: mdm-dsp-crit { 4430 temperature = <110000>; 4431 hysteresis = <2000>; 4432 type = "critical"; 4433 }; 4434 }; 4435 }; 4436 4437 npu-thermal { 4438 polling-delay-passive = <250>; 4439 polling-delay = <0>; 4440 4441 thermal-sensors = <&tsens1 8>; 4442 4443 trips { 4444 npu_alert0: trip-point0 { 4445 temperature = <90000>; 4446 hysteresis = <2000>; 4447 type = "hot"; 4448 }; 4449 4450 npu_crit: npu-crit { 4451 temperature = <110000>; 4452 hysteresis = <2000>; 4453 type = "critical"; 4454 }; 4455 }; 4456 }; 4457 4458 video-thermal { 4459 polling-delay-passive = <250>; 4460 polling-delay = <0>; 4461 4462 thermal-sensors = <&tsens1 9>; 4463 4464 trips { 4465 video_alert0: trip-point0 { 4466 temperature = <90000>; 4467 hysteresis = <2000>; 4468 type = "hot"; 4469 }; 4470 4471 video_crit: video-crit { 4472 temperature = <110000>; 4473 hysteresis = <2000>; 4474 type = "critical"; 4475 }; 4476 }; 4477 }; 4478 }; 4479 4480 timer { 4481 compatible = "arm,armv8-timer"; 4482 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4483 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4484 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4485 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4486 }; 4487}; 4488