1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 aliases { 33 mmc1 = &sdhc_1; 34 mmc2 = &sdhc_2; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi3 = &spi3; 50 spi5 = &spi5; 51 spi6 = &spi6; 52 spi8 = &spi8; 53 spi10 = &spi10; 54 spi11 = &spi11; 55 }; 56 57 clocks { 58 xo_board: xo-board { 59 compatible = "fixed-clock"; 60 clock-frequency = <38400000>; 61 #clock-cells = <0>; 62 }; 63 64 sleep_clk: sleep-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <32764>; 67 #clock-cells = <0>; 68 }; 69 }; 70 71 reserved_memory: reserved-memory { 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 hyp_mem: memory@80000000 { 77 reg = <0x0 0x80000000 0x0 0x600000>; 78 no-map; 79 }; 80 81 xbl_mem: memory@80600000 { 82 reg = <0x0 0x80600000 0x0 0x200000>; 83 no-map; 84 }; 85 86 aop_mem: memory@80800000 { 87 reg = <0x0 0x80800000 0x0 0x20000>; 88 no-map; 89 }; 90 91 aop_cmd_db_mem: memory@80820000 { 92 reg = <0x0 0x80820000 0x0 0x20000>; 93 compatible = "qcom,cmd-db"; 94 no-map; 95 }; 96 97 sec_apps_mem: memory@808ff000 { 98 reg = <0x0 0x808ff000 0x0 0x1000>; 99 no-map; 100 }; 101 102 smem_mem: memory@80900000 { 103 reg = <0x0 0x80900000 0x0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@80b00000 { 108 reg = <0x0 0x80b00000 0x0 0x3900000>; 109 no-map; 110 }; 111 112 ipa_fw_mem: memory@8b700000 { 113 reg = <0 0x8b700000 0 0x10000>; 114 no-map; 115 }; 116 117 rmtfs_mem: memory@94600000 { 118 compatible = "qcom,rmtfs-mem"; 119 reg = <0x0 0x94600000 0x0 0x200000>; 120 no-map; 121 122 qcom,client-id = <1>; 123 qcom,vmid = <15>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <2>; 129 #size-cells = <0>; 130 131 CPU0: cpu@0 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo468"; 134 reg = <0x0 0x0>; 135 enable-method = "psci"; 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 137 &LITTLE_CPU_SLEEP_1 138 &CLUSTER_SLEEP_0>; 139 capacity-dmips-mhz = <415>; 140 dynamic-power-coefficient = <137>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 144 next-level-cache = <&L2_0>; 145 #cooling-cells = <2>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 L2_0: l2-cache { 148 compatible = "cache"; 149 next-level-cache = <&L3_0>; 150 L3_0: l3-cache { 151 compatible = "cache"; 152 }; 153 }; 154 }; 155 156 CPU1: cpu@100 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo468"; 159 reg = <0x0 0x100>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 capacity-dmips-mhz = <415>; 165 dynamic-power-coefficient = <137>; 166 next-level-cache = <&L2_100>; 167 operating-points-v2 = <&cpu0_opp_table>; 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 #cooling-cells = <2>; 171 qcom,freq-domain = <&cpufreq_hw 0>; 172 L2_100: l2-cache { 173 compatible = "cache"; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU2: cpu@200 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo468"; 181 reg = <0x0 0x200>; 182 enable-method = "psci"; 183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 184 &LITTLE_CPU_SLEEP_1 185 &CLUSTER_SLEEP_0>; 186 capacity-dmips-mhz = <415>; 187 dynamic-power-coefficient = <137>; 188 next-level-cache = <&L2_200>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 192 #cooling-cells = <2>; 193 qcom,freq-domain = <&cpufreq_hw 0>; 194 L2_200: l2-cache { 195 compatible = "cache"; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU3: cpu@300 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo468"; 203 reg = <0x0 0x300>; 204 enable-method = "psci"; 205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 206 &LITTLE_CPU_SLEEP_1 207 &CLUSTER_SLEEP_0>; 208 capacity-dmips-mhz = <415>; 209 dynamic-power-coefficient = <137>; 210 next-level-cache = <&L2_300>; 211 operating-points-v2 = <&cpu0_opp_table>; 212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 #cooling-cells = <2>; 215 qcom,freq-domain = <&cpufreq_hw 0>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo468"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 228 &LITTLE_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 capacity-dmips-mhz = <415>; 231 dynamic-power-coefficient = <137>; 232 next-level-cache = <&L2_400>; 233 operating-points-v2 = <&cpu0_opp_table>; 234 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 236 #cooling-cells = <2>; 237 qcom,freq-domain = <&cpufreq_hw 0>; 238 L2_400: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU5: cpu@500 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo468"; 247 reg = <0x0 0x500>; 248 enable-method = "psci"; 249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 250 &LITTLE_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252 capacity-dmips-mhz = <415>; 253 dynamic-power-coefficient = <137>; 254 next-level-cache = <&L2_500>; 255 operating-points-v2 = <&cpu0_opp_table>; 256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 257 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 258 #cooling-cells = <2>; 259 qcom,freq-domain = <&cpufreq_hw 0>; 260 L2_500: l2-cache { 261 compatible = "cache"; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU6: cpu@600 { 267 device_type = "cpu"; 268 compatible = "qcom,kryo468"; 269 reg = <0x0 0x600>; 270 enable-method = "psci"; 271 cpu-idle-states = <&BIG_CPU_SLEEP_0 272 &BIG_CPU_SLEEP_1 273 &CLUSTER_SLEEP_0>; 274 capacity-dmips-mhz = <1024>; 275 dynamic-power-coefficient = <480>; 276 next-level-cache = <&L2_600>; 277 operating-points-v2 = <&cpu6_opp_table>; 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 280 #cooling-cells = <2>; 281 qcom,freq-domain = <&cpufreq_hw 1>; 282 L2_600: l2-cache { 283 compatible = "cache"; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU7: cpu@700 { 289 device_type = "cpu"; 290 compatible = "qcom,kryo468"; 291 reg = <0x0 0x700>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 capacity-dmips-mhz = <1024>; 297 dynamic-power-coefficient = <480>; 298 next-level-cache = <&L2_700>; 299 operating-points-v2 = <&cpu6_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 302 #cooling-cells = <2>; 303 qcom,freq-domain = <&cpufreq_hw 1>; 304 L2_700: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 cpu-map { 311 cluster0 { 312 core0 { 313 cpu = <&CPU0>; 314 }; 315 316 core1 { 317 cpu = <&CPU1>; 318 }; 319 320 core2 { 321 cpu = <&CPU2>; 322 }; 323 324 core3 { 325 cpu = <&CPU3>; 326 }; 327 328 core4 { 329 cpu = <&CPU4>; 330 }; 331 332 core5 { 333 cpu = <&CPU5>; 334 }; 335 336 core6 { 337 cpu = <&CPU6>; 338 }; 339 340 core7 { 341 cpu = <&CPU7>; 342 }; 343 }; 344 }; 345 346 idle-states { 347 entry-method = "psci"; 348 349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "little-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <549>; 354 exit-latency-us = <901>; 355 min-residency-us = <1774>; 356 local-timer-stop; 357 }; 358 359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "little-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <702>; 364 exit-latency-us = <915>; 365 min-residency-us = <4001>; 366 local-timer-stop; 367 }; 368 369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "big-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <523>; 374 exit-latency-us = <1244>; 375 min-residency-us = <2207>; 376 local-timer-stop; 377 }; 378 379 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "big-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <526>; 384 exit-latency-us = <1854>; 385 min-residency-us = <5555>; 386 local-timer-stop; 387 }; 388 389 CLUSTER_SLEEP_0: cluster-sleep-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "cluster-power-down"; 392 arm,psci-suspend-param = <0x40003444>; 393 entry-latency-us = <3263>; 394 exit-latency-us = <6562>; 395 min-residency-us = <9926>; 396 local-timer-stop; 397 }; 398 }; 399 }; 400 401 cpu0_opp_table: cpu0_opp_table { 402 compatible = "operating-points-v2"; 403 opp-shared; 404 405 cpu0_opp1: opp-300000000 { 406 opp-hz = /bits/ 64 <300000000>; 407 opp-peak-kBps = <1200000 4800000>; 408 }; 409 410 cpu0_opp2: opp-576000000 { 411 opp-hz = /bits/ 64 <576000000>; 412 opp-peak-kBps = <1200000 4800000>; 413 }; 414 415 cpu0_opp3: opp-768000000 { 416 opp-hz = /bits/ 64 <768000000>; 417 opp-peak-kBps = <1200000 4800000>; 418 }; 419 420 cpu0_opp4: opp-1017600000 { 421 opp-hz = /bits/ 64 <1017600000>; 422 opp-peak-kBps = <1804000 8908800>; 423 }; 424 425 cpu0_opp5: opp-1248000000 { 426 opp-hz = /bits/ 64 <1248000000>; 427 opp-peak-kBps = <2188000 12902400>; 428 }; 429 430 cpu0_opp6: opp-1324800000 { 431 opp-hz = /bits/ 64 <1324800000>; 432 opp-peak-kBps = <2188000 12902400>; 433 }; 434 435 cpu0_opp7: opp-1516800000 { 436 opp-hz = /bits/ 64 <1516800000>; 437 opp-peak-kBps = <3072000 15052800>; 438 }; 439 440 cpu0_opp8: opp-1612800000 { 441 opp-hz = /bits/ 64 <1612800000>; 442 opp-peak-kBps = <3072000 15052800>; 443 }; 444 445 cpu0_opp9: opp-1708800000 { 446 opp-hz = /bits/ 64 <1708800000>; 447 opp-peak-kBps = <3072000 15052800>; 448 }; 449 450 cpu0_opp10: opp-1804800000 { 451 opp-hz = /bits/ 64 <1804800000>; 452 opp-peak-kBps = <4068000 22425600>; 453 }; 454 }; 455 456 cpu6_opp_table: cpu6_opp_table { 457 compatible = "operating-points-v2"; 458 opp-shared; 459 460 cpu6_opp1: opp-300000000 { 461 opp-hz = /bits/ 64 <300000000>; 462 opp-peak-kBps = <2188000 8908800>; 463 }; 464 465 cpu6_opp2: opp-652800000 { 466 opp-hz = /bits/ 64 <652800000>; 467 opp-peak-kBps = <2188000 8908800>; 468 }; 469 470 cpu6_opp3: opp-825600000 { 471 opp-hz = /bits/ 64 <825600000>; 472 opp-peak-kBps = <2188000 8908800>; 473 }; 474 475 cpu6_opp4: opp-979200000 { 476 opp-hz = /bits/ 64 <979200000>; 477 opp-peak-kBps = <2188000 8908800>; 478 }; 479 480 cpu6_opp5: opp-1113600000 { 481 opp-hz = /bits/ 64 <1113600000>; 482 opp-peak-kBps = <2188000 8908800>; 483 }; 484 485 cpu6_opp6: opp-1267200000 { 486 opp-hz = /bits/ 64 <1267200000>; 487 opp-peak-kBps = <4068000 12902400>; 488 }; 489 490 cpu6_opp7: opp-1555200000 { 491 opp-hz = /bits/ 64 <1555200000>; 492 opp-peak-kBps = <4068000 15052800>; 493 }; 494 495 cpu6_opp8: opp-1708800000 { 496 opp-hz = /bits/ 64 <1708800000>; 497 opp-peak-kBps = <6220000 19353600>; 498 }; 499 500 cpu6_opp9: opp-1843200000 { 501 opp-hz = /bits/ 64 <1843200000>; 502 opp-peak-kBps = <6220000 19353600>; 503 }; 504 505 cpu6_opp10: opp-1900800000 { 506 opp-hz = /bits/ 64 <1900800000>; 507 opp-peak-kBps = <6220000 22425600>; 508 }; 509 510 cpu6_opp11: opp-1996800000 { 511 opp-hz = /bits/ 64 <1996800000>; 512 opp-peak-kBps = <6220000 22425600>; 513 }; 514 515 cpu6_opp12: opp-2112000000 { 516 opp-hz = /bits/ 64 <2112000000>; 517 opp-peak-kBps = <6220000 22425600>; 518 }; 519 520 cpu6_opp13: opp-2208000000 { 521 opp-hz = /bits/ 64 <2208000000>; 522 opp-peak-kBps = <7216000 22425600>; 523 }; 524 525 cpu6_opp14: opp-2323200000 { 526 opp-hz = /bits/ 64 <2323200000>; 527 opp-peak-kBps = <7216000 22425600>; 528 }; 529 530 cpu6_opp15: opp-2400000000 { 531 opp-hz = /bits/ 64 <2400000000>; 532 opp-peak-kBps = <8532000 23347200>; 533 }; 534 535 cpu6_opp16: opp-2553600000 { 536 opp-hz = /bits/ 64 <2553600000>; 537 opp-peak-kBps = <8532000 23347200>; 538 }; 539 }; 540 541 memory@80000000 { 542 device_type = "memory"; 543 /* We expect the bootloader to fill in the size */ 544 reg = <0 0x80000000 0 0>; 545 }; 546 547 pmu { 548 compatible = "arm,armv8-pmuv3"; 549 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 550 }; 551 552 firmware { 553 scm { 554 compatible = "qcom,scm-sc7180", "qcom,scm"; 555 }; 556 }; 557 558 tcsr_mutex: hwlock { 559 compatible = "qcom,tcsr-mutex"; 560 syscon = <&tcsr_mutex_regs 0 0x1000>; 561 #hwlock-cells = <1>; 562 }; 563 564 smem { 565 compatible = "qcom,smem"; 566 memory-region = <&smem_mem>; 567 hwlocks = <&tcsr_mutex 3>; 568 }; 569 570 smp2p-cdsp { 571 compatible = "qcom,smp2p"; 572 qcom,smem = <94>, <432>; 573 574 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 575 576 mboxes = <&apss_shared 6>; 577 578 qcom,local-pid = <0>; 579 qcom,remote-pid = <5>; 580 581 cdsp_smp2p_out: master-kernel { 582 qcom,entry-name = "master-kernel"; 583 #qcom,smem-state-cells = <1>; 584 }; 585 586 cdsp_smp2p_in: slave-kernel { 587 qcom,entry-name = "slave-kernel"; 588 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 }; 592 }; 593 594 smp2p-lpass { 595 compatible = "qcom,smp2p"; 596 qcom,smem = <443>, <429>; 597 598 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 599 600 mboxes = <&apss_shared 10>; 601 602 qcom,local-pid = <0>; 603 qcom,remote-pid = <2>; 604 605 adsp_smp2p_out: master-kernel { 606 qcom,entry-name = "master-kernel"; 607 #qcom,smem-state-cells = <1>; 608 }; 609 610 adsp_smp2p_in: slave-kernel { 611 qcom,entry-name = "slave-kernel"; 612 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 }; 616 }; 617 618 smp2p-mpss { 619 compatible = "qcom,smp2p"; 620 qcom,smem = <435>, <428>; 621 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 622 mboxes = <&apss_shared 14>; 623 qcom,local-pid = <0>; 624 qcom,remote-pid = <1>; 625 626 modem_smp2p_out: master-kernel { 627 qcom,entry-name = "master-kernel"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 modem_smp2p_in: slave-kernel { 632 qcom,entry-name = "slave-kernel"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 637 ipa_smp2p_out: ipa-ap-to-modem { 638 qcom,entry-name = "ipa"; 639 #qcom,smem-state-cells = <1>; 640 }; 641 642 ipa_smp2p_in: ipa-modem-to-ap { 643 qcom,entry-name = "ipa"; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 }; 648 649 psci { 650 compatible = "arm,psci-1.0"; 651 method = "smc"; 652 }; 653 654 soc: soc@0 { 655 #address-cells = <2>; 656 #size-cells = <2>; 657 ranges = <0 0 0 0 0x10 0>; 658 dma-ranges = <0 0 0 0 0x10 0>; 659 compatible = "simple-bus"; 660 661 gcc: clock-controller@100000 { 662 compatible = "qcom,gcc-sc7180"; 663 reg = <0 0x00100000 0 0x1f0000>; 664 clocks = <&rpmhcc RPMH_CXO_CLK>, 665 <&rpmhcc RPMH_CXO_CLK_A>, 666 <&sleep_clk>; 667 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 668 #clock-cells = <1>; 669 #reset-cells = <1>; 670 #power-domain-cells = <1>; 671 }; 672 673 qfprom: efuse@784000 { 674 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 675 reg = <0 0x00784000 0 0x7a0>, 676 <0 0x00780000 0 0x7a0>, 677 <0 0x00782000 0 0x100>, 678 <0 0x00786000 0 0x1fff>; 679 680 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 681 clock-names = "core"; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 685 qusb2p_hstx_trim: hstx-trim-primary@25b { 686 reg = <0x25b 0x1>; 687 bits = <1 3>; 688 }; 689 690 gpu_speed_bin: gpu_speed_bin@1d2 { 691 reg = <0x1d2 0x2>; 692 bits = <5 8>; 693 }; 694 }; 695 696 sdhc_1: sdhci@7c4000 { 697 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 698 reg = <0 0x7c4000 0 0x1000>, 699 <0 0x07c5000 0 0x1000>; 700 reg-names = "hc", "cqhci"; 701 702 iommus = <&apps_smmu 0x60 0x0>; 703 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-names = "hc_irq", "pwr_irq"; 706 707 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 708 <&gcc GCC_SDCC1_AHB_CLK>, 709 <&rpmhcc RPMH_CXO_CLK>; 710 clock-names = "core", "iface", "xo"; 711 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 712 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 713 interconnect-names = "sdhc-ddr","cpu-sdhc"; 714 power-domains = <&rpmhpd SC7180_CX>; 715 operating-points-v2 = <&sdhc1_opp_table>; 716 717 bus-width = <8>; 718 non-removable; 719 supports-cqe; 720 721 mmc-ddr-1_8v; 722 mmc-hs200-1_8v; 723 mmc-hs400-1_8v; 724 mmc-hs400-enhanced-strobe; 725 726 status = "disabled"; 727 728 sdhc1_opp_table: sdhc1-opp-table { 729 compatible = "operating-points-v2"; 730 731 opp-100000000 { 732 opp-hz = /bits/ 64 <100000000>; 733 required-opps = <&rpmhpd_opp_low_svs>; 734 opp-peak-kBps = <1800000 600000>; 735 opp-avg-kBps = <100000 0>; 736 }; 737 738 opp-384000000 { 739 opp-hz = /bits/ 64 <384000000>; 740 required-opps = <&rpmhpd_opp_nom>; 741 opp-peak-kBps = <5400000 1600000>; 742 opp-avg-kBps = <390000 0>; 743 }; 744 }; 745 }; 746 747 qup_opp_table: qup-opp-table { 748 compatible = "operating-points-v2"; 749 750 opp-75000000 { 751 opp-hz = /bits/ 64 <75000000>; 752 required-opps = <&rpmhpd_opp_low_svs>; 753 }; 754 755 opp-100000000 { 756 opp-hz = /bits/ 64 <100000000>; 757 required-opps = <&rpmhpd_opp_svs>; 758 }; 759 760 opp-128000000 { 761 opp-hz = /bits/ 64 <128000000>; 762 required-opps = <&rpmhpd_opp_nom>; 763 }; 764 }; 765 766 qupv3_id_0: geniqup@8c0000 { 767 compatible = "qcom,geni-se-qup"; 768 reg = <0 0x008c0000 0 0x6000>; 769 clock-names = "m-ahb", "s-ahb"; 770 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 771 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 772 #address-cells = <2>; 773 #size-cells = <2>; 774 ranges; 775 iommus = <&apps_smmu 0x43 0x0>; 776 status = "disabled"; 777 778 i2c0: i2c@880000 { 779 compatible = "qcom,geni-i2c"; 780 reg = <0 0x00880000 0 0x4000>; 781 clock-names = "se"; 782 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&qup_i2c0_default>; 785 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 789 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 790 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 791 interconnect-names = "qup-core", "qup-config", 792 "qup-memory"; 793 power-domains = <&rpmhpd SC7180_CX>; 794 required-opps = <&rpmhpd_opp_low_svs>; 795 status = "disabled"; 796 }; 797 798 spi0: spi@880000 { 799 compatible = "qcom,geni-spi"; 800 reg = <0 0x00880000 0 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_spi0_default>; 805 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 power-domains = <&rpmhpd SC7180_CX>; 809 operating-points-v2 = <&qup_opp_table>; 810 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 811 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 812 interconnect-names = "qup-core", "qup-config"; 813 status = "disabled"; 814 }; 815 816 uart0: serial@880000 { 817 compatible = "qcom,geni-uart"; 818 reg = <0 0x00880000 0 0x4000>; 819 clock-names = "se"; 820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&qup_uart0_default>; 823 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 824 power-domains = <&rpmhpd SC7180_CX>; 825 operating-points-v2 = <&qup_opp_table>; 826 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 827 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 828 interconnect-names = "qup-core", "qup-config"; 829 status = "disabled"; 830 }; 831 832 i2c1: i2c@884000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0 0x00884000 0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c1_default>; 839 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 843 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 844 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 845 interconnect-names = "qup-core", "qup-config", 846 "qup-memory"; 847 power-domains = <&rpmhpd SC7180_CX>; 848 required-opps = <&rpmhpd_opp_low_svs>; 849 status = "disabled"; 850 }; 851 852 spi1: spi@884000 { 853 compatible = "qcom,geni-spi"; 854 reg = <0 0x00884000 0 0x4000>; 855 clock-names = "se"; 856 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 857 pinctrl-names = "default"; 858 pinctrl-0 = <&qup_spi1_default>; 859 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 power-domains = <&rpmhpd SC7180_CX>; 863 operating-points-v2 = <&qup_opp_table>; 864 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 865 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 866 interconnect-names = "qup-core", "qup-config"; 867 status = "disabled"; 868 }; 869 870 uart1: serial@884000 { 871 compatible = "qcom,geni-uart"; 872 reg = <0 0x00884000 0 0x4000>; 873 clock-names = "se"; 874 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&qup_uart1_default>; 877 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 878 power-domains = <&rpmhpd SC7180_CX>; 879 operating-points-v2 = <&qup_opp_table>; 880 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 881 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 882 interconnect-names = "qup-core", "qup-config"; 883 status = "disabled"; 884 }; 885 886 i2c2: i2c@888000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0 0x00888000 0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c2_default>; 893 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", 900 "qup-memory"; 901 power-domains = <&rpmhpd SC7180_CX>; 902 required-opps = <&rpmhpd_opp_low_svs>; 903 status = "disabled"; 904 }; 905 906 uart2: serial@888000 { 907 compatible = "qcom,geni-uart"; 908 reg = <0 0x00888000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_uart2_default>; 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 914 power-domains = <&rpmhpd SC7180_CX>; 915 operating-points-v2 = <&qup_opp_table>; 916 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 917 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 918 interconnect-names = "qup-core", "qup-config"; 919 status = "disabled"; 920 }; 921 922 i2c3: i2c@88c000 { 923 compatible = "qcom,geni-i2c"; 924 reg = <0 0x0088c000 0 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_i2c3_default>; 929 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 934 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", 936 "qup-memory"; 937 power-domains = <&rpmhpd SC7180_CX>; 938 required-opps = <&rpmhpd_opp_low_svs>; 939 status = "disabled"; 940 }; 941 942 spi3: spi@88c000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x0088c000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_spi3_default>; 949 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 power-domains = <&rpmhpd SC7180_CX>; 953 operating-points-v2 = <&qup_opp_table>; 954 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 956 interconnect-names = "qup-core", "qup-config"; 957 status = "disabled"; 958 }; 959 960 uart3: serial@88c000 { 961 compatible = "qcom,geni-uart"; 962 reg = <0 0x0088c000 0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_uart3_default>; 967 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 968 power-domains = <&rpmhpd SC7180_CX>; 969 operating-points-v2 = <&qup_opp_table>; 970 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 972 interconnect-names = "qup-core", "qup-config"; 973 status = "disabled"; 974 }; 975 976 i2c4: i2c@890000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0 0x00890000 0 0x4000>; 979 clock-names = "se"; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_i2c4_default>; 983 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 988 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 989 interconnect-names = "qup-core", "qup-config", 990 "qup-memory"; 991 power-domains = <&rpmhpd SC7180_CX>; 992 required-opps = <&rpmhpd_opp_low_svs>; 993 status = "disabled"; 994 }; 995 996 uart4: serial@890000 { 997 compatible = "qcom,geni-uart"; 998 reg = <0 0x00890000 0 0x4000>; 999 clock-names = "se"; 1000 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&qup_uart4_default>; 1003 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1004 power-domains = <&rpmhpd SC7180_CX>; 1005 operating-points-v2 = <&qup_opp_table>; 1006 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1007 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1008 interconnect-names = "qup-core", "qup-config"; 1009 status = "disabled"; 1010 }; 1011 1012 i2c5: i2c@894000 { 1013 compatible = "qcom,geni-i2c"; 1014 reg = <0 0x00894000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_i2c5_default>; 1019 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1023 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1024 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1025 interconnect-names = "qup-core", "qup-config", 1026 "qup-memory"; 1027 power-domains = <&rpmhpd SC7180_CX>; 1028 required-opps = <&rpmhpd_opp_low_svs>; 1029 status = "disabled"; 1030 }; 1031 1032 spi5: spi@894000 { 1033 compatible = "qcom,geni-spi"; 1034 reg = <0 0x00894000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_spi5_default>; 1039 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 power-domains = <&rpmhpd SC7180_CX>; 1043 operating-points-v2 = <&qup_opp_table>; 1044 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1046 interconnect-names = "qup-core", "qup-config"; 1047 status = "disabled"; 1048 }; 1049 1050 uart5: serial@894000 { 1051 compatible = "qcom,geni-uart"; 1052 reg = <0 0x00894000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&qup_uart5_default>; 1057 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1058 power-domains = <&rpmhpd SC7180_CX>; 1059 operating-points-v2 = <&qup_opp_table>; 1060 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1062 interconnect-names = "qup-core", "qup-config"; 1063 status = "disabled"; 1064 }; 1065 }; 1066 1067 qupv3_id_1: geniqup@ac0000 { 1068 compatible = "qcom,geni-se-qup"; 1069 reg = <0 0x00ac0000 0 0x6000>; 1070 clock-names = "m-ahb", "s-ahb"; 1071 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1072 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1073 #address-cells = <2>; 1074 #size-cells = <2>; 1075 ranges; 1076 iommus = <&apps_smmu 0x4c3 0x0>; 1077 status = "disabled"; 1078 1079 i2c6: i2c@a80000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x00a80000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_i2c6_default>; 1086 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1090 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1091 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1092 interconnect-names = "qup-core", "qup-config", 1093 "qup-memory"; 1094 power-domains = <&rpmhpd SC7180_CX>; 1095 required-opps = <&rpmhpd_opp_low_svs>; 1096 status = "disabled"; 1097 }; 1098 1099 spi6: spi@a80000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0 0x00a80000 0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_spi6_default>; 1106 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 power-domains = <&rpmhpd SC7180_CX>; 1110 operating-points-v2 = <&qup_opp_table>; 1111 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1112 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1113 interconnect-names = "qup-core", "qup-config"; 1114 status = "disabled"; 1115 }; 1116 1117 uart6: serial@a80000 { 1118 compatible = "qcom,geni-uart"; 1119 reg = <0 0x00a80000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_uart6_default>; 1124 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1125 power-domains = <&rpmhpd SC7180_CX>; 1126 operating-points-v2 = <&qup_opp_table>; 1127 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1128 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1129 interconnect-names = "qup-core", "qup-config"; 1130 status = "disabled"; 1131 }; 1132 1133 i2c7: i2c@a84000 { 1134 compatible = "qcom,geni-i2c"; 1135 reg = <0 0x00a84000 0 0x4000>; 1136 clock-names = "se"; 1137 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_i2c7_default>; 1140 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1145 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1146 interconnect-names = "qup-core", "qup-config", 1147 "qup-memory"; 1148 power-domains = <&rpmhpd SC7180_CX>; 1149 required-opps = <&rpmhpd_opp_low_svs>; 1150 status = "disabled"; 1151 }; 1152 1153 uart7: serial@a84000 { 1154 compatible = "qcom,geni-uart"; 1155 reg = <0 0x00a84000 0 0x4000>; 1156 clock-names = "se"; 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_uart7_default>; 1160 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1161 power-domains = <&rpmhpd SC7180_CX>; 1162 operating-points-v2 = <&qup_opp_table>; 1163 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1165 interconnect-names = "qup-core", "qup-config"; 1166 status = "disabled"; 1167 }; 1168 1169 i2c8: i2c@a88000 { 1170 compatible = "qcom,geni-i2c"; 1171 reg = <0 0x00a88000 0 0x4000>; 1172 clock-names = "se"; 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_i2c8_default>; 1176 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1180 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1181 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1182 interconnect-names = "qup-core", "qup-config", 1183 "qup-memory"; 1184 power-domains = <&rpmhpd SC7180_CX>; 1185 required-opps = <&rpmhpd_opp_low_svs>; 1186 status = "disabled"; 1187 }; 1188 1189 spi8: spi@a88000 { 1190 compatible = "qcom,geni-spi"; 1191 reg = <0 0x00a88000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_spi8_default>; 1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 power-domains = <&rpmhpd SC7180_CX>; 1200 operating-points-v2 = <&qup_opp_table>; 1201 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1202 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1203 interconnect-names = "qup-core", "qup-config"; 1204 status = "disabled"; 1205 }; 1206 1207 uart8: serial@a88000 { 1208 compatible = "qcom,geni-debug-uart"; 1209 reg = <0 0x00a88000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_uart8_default>; 1214 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd SC7180_CX>; 1216 operating-points-v2 = <&qup_opp_table>; 1217 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1218 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1219 interconnect-names = "qup-core", "qup-config"; 1220 status = "disabled"; 1221 }; 1222 1223 i2c9: i2c@a8c000 { 1224 compatible = "qcom,geni-i2c"; 1225 reg = <0 0x00a8c000 0 0x4000>; 1226 clock-names = "se"; 1227 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&qup_i2c9_default>; 1230 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1234 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1235 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1236 interconnect-names = "qup-core", "qup-config", 1237 "qup-memory"; 1238 power-domains = <&rpmhpd SC7180_CX>; 1239 required-opps = <&rpmhpd_opp_low_svs>; 1240 status = "disabled"; 1241 }; 1242 1243 uart9: serial@a8c000 { 1244 compatible = "qcom,geni-uart"; 1245 reg = <0 0x00a8c000 0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_uart9_default>; 1250 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1251 power-domains = <&rpmhpd SC7180_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1255 interconnect-names = "qup-core", "qup-config"; 1256 status = "disabled"; 1257 }; 1258 1259 i2c10: i2c@a90000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0 0x00a90000 0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_i2c10_default>; 1266 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1270 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1271 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1272 interconnect-names = "qup-core", "qup-config", 1273 "qup-memory"; 1274 power-domains = <&rpmhpd SC7180_CX>; 1275 required-opps = <&rpmhpd_opp_low_svs>; 1276 status = "disabled"; 1277 }; 1278 1279 spi10: spi@a90000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0 0x00a90000 0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi10_default>; 1286 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 power-domains = <&rpmhpd SC7180_CX>; 1290 operating-points-v2 = <&qup_opp_table>; 1291 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1292 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1293 interconnect-names = "qup-core", "qup-config"; 1294 status = "disabled"; 1295 }; 1296 1297 uart10: serial@a90000 { 1298 compatible = "qcom,geni-uart"; 1299 reg = <0 0x00a90000 0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_uart10_default>; 1304 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1305 power-domains = <&rpmhpd SC7180_CX>; 1306 operating-points-v2 = <&qup_opp_table>; 1307 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1308 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 status = "disabled"; 1311 }; 1312 1313 i2c11: i2c@a94000 { 1314 compatible = "qcom,geni-i2c"; 1315 reg = <0 0x00a94000 0 0x4000>; 1316 clock-names = "se"; 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_i2c11_default>; 1320 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1324 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1325 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1326 interconnect-names = "qup-core", "qup-config", 1327 "qup-memory"; 1328 power-domains = <&rpmhpd SC7180_CX>; 1329 required-opps = <&rpmhpd_opp_low_svs>; 1330 status = "disabled"; 1331 }; 1332 1333 spi11: spi@a94000 { 1334 compatible = "qcom,geni-spi"; 1335 reg = <0 0x00a94000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_spi11_default>; 1340 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 power-domains = <&rpmhpd SC7180_CX>; 1344 operating-points-v2 = <&qup_opp_table>; 1345 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1346 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1347 interconnect-names = "qup-core", "qup-config"; 1348 status = "disabled"; 1349 }; 1350 1351 uart11: serial@a94000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0 0x00a94000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&qup_uart11_default>; 1358 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1359 power-domains = <&rpmhpd SC7180_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 status = "disabled"; 1365 }; 1366 }; 1367 1368 config_noc: interconnect@1500000 { 1369 compatible = "qcom,sc7180-config-noc"; 1370 reg = <0 0x01500000 0 0x28000>; 1371 #interconnect-cells = <2>; 1372 qcom,bcm-voters = <&apps_bcm_voter>; 1373 }; 1374 1375 system_noc: interconnect@1620000 { 1376 compatible = "qcom,sc7180-system-noc"; 1377 reg = <0 0x01620000 0 0x17080>; 1378 #interconnect-cells = <2>; 1379 qcom,bcm-voters = <&apps_bcm_voter>; 1380 }; 1381 1382 mc_virt: interconnect@1638000 { 1383 compatible = "qcom,sc7180-mc-virt"; 1384 reg = <0 0x01638000 0 0x1000>; 1385 #interconnect-cells = <2>; 1386 qcom,bcm-voters = <&apps_bcm_voter>; 1387 }; 1388 1389 qup_virt: interconnect@1650000 { 1390 compatible = "qcom,sc7180-qup-virt"; 1391 reg = <0 0x01650000 0 0x1000>; 1392 #interconnect-cells = <2>; 1393 qcom,bcm-voters = <&apps_bcm_voter>; 1394 }; 1395 1396 aggre1_noc: interconnect@16e0000 { 1397 compatible = "qcom,sc7180-aggre1-noc"; 1398 reg = <0 0x016e0000 0 0x15080>; 1399 #interconnect-cells = <2>; 1400 qcom,bcm-voters = <&apps_bcm_voter>; 1401 }; 1402 1403 aggre2_noc: interconnect@1705000 { 1404 compatible = "qcom,sc7180-aggre2-noc"; 1405 reg = <0 0x01705000 0 0x9000>; 1406 #interconnect-cells = <2>; 1407 qcom,bcm-voters = <&apps_bcm_voter>; 1408 }; 1409 1410 compute_noc: interconnect@170e000 { 1411 compatible = "qcom,sc7180-compute-noc"; 1412 reg = <0 0x0170e000 0 0x6000>; 1413 #interconnect-cells = <2>; 1414 qcom,bcm-voters = <&apps_bcm_voter>; 1415 }; 1416 1417 mmss_noc: interconnect@1740000 { 1418 compatible = "qcom,sc7180-mmss-noc"; 1419 reg = <0 0x01740000 0 0x1c100>; 1420 #interconnect-cells = <2>; 1421 qcom,bcm-voters = <&apps_bcm_voter>; 1422 }; 1423 1424 ipa_virt: interconnect@1e00000 { 1425 compatible = "qcom,sc7180-ipa-virt"; 1426 reg = <0 0x01e00000 0 0x1000>; 1427 #interconnect-cells = <2>; 1428 qcom,bcm-voters = <&apps_bcm_voter>; 1429 }; 1430 1431 ipa: ipa@1e40000 { 1432 compatible = "qcom,sc7180-ipa"; 1433 1434 iommus = <&apps_smmu 0x440 0x0>, 1435 <&apps_smmu 0x442 0x0>; 1436 reg = <0 0x1e40000 0 0x7000>, 1437 <0 0x1e47000 0 0x2000>, 1438 <0 0x1e04000 0 0x2c000>; 1439 reg-names = "ipa-reg", 1440 "ipa-shared", 1441 "gsi"; 1442 1443 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1444 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1445 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1446 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1447 interrupt-names = "ipa", 1448 "gsi", 1449 "ipa-clock-query", 1450 "ipa-setup-ready"; 1451 1452 clocks = <&rpmhcc RPMH_IPA_CLK>; 1453 clock-names = "core"; 1454 1455 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1456 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1457 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1458 interconnect-names = "memory", 1459 "imem", 1460 "config"; 1461 1462 qcom,qmp = <&aoss_qmp>; 1463 1464 qcom,smem-states = <&ipa_smp2p_out 0>, 1465 <&ipa_smp2p_out 1>; 1466 qcom,smem-state-names = "ipa-clock-enabled-valid", 1467 "ipa-clock-enabled"; 1468 1469 status = "disabled"; 1470 }; 1471 1472 tcsr_mutex_regs: syscon@1f40000 { 1473 compatible = "syscon"; 1474 reg = <0 0x01f40000 0 0x40000>; 1475 }; 1476 1477 tcsr_regs: syscon@1fc0000 { 1478 compatible = "syscon"; 1479 reg = <0 0x01fc0000 0 0x40000>; 1480 }; 1481 1482 tlmm: pinctrl@3500000 { 1483 compatible = "qcom,sc7180-pinctrl"; 1484 reg = <0 0x03500000 0 0x300000>, 1485 <0 0x03900000 0 0x300000>, 1486 <0 0x03d00000 0 0x300000>; 1487 reg-names = "west", "north", "south"; 1488 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1489 gpio-controller; 1490 #gpio-cells = <2>; 1491 interrupt-controller; 1492 #interrupt-cells = <2>; 1493 gpio-ranges = <&tlmm 0 0 120>; 1494 wakeup-parent = <&pdc>; 1495 1496 dp_hot_plug_det: dp-hot-plug-det { 1497 pinmux { 1498 pins = "gpio117"; 1499 function = "dp_hot"; 1500 }; 1501 }; 1502 1503 qspi_clk: qspi-clk { 1504 pinmux { 1505 pins = "gpio63"; 1506 function = "qspi_clk"; 1507 }; 1508 }; 1509 1510 qspi_cs0: qspi-cs0 { 1511 pinmux { 1512 pins = "gpio68"; 1513 function = "qspi_cs"; 1514 }; 1515 }; 1516 1517 qspi_cs1: qspi-cs1 { 1518 pinmux { 1519 pins = "gpio72"; 1520 function = "qspi_cs"; 1521 }; 1522 }; 1523 1524 qspi_data01: qspi-data01 { 1525 pinmux-data { 1526 pins = "gpio64", "gpio65"; 1527 function = "qspi_data"; 1528 }; 1529 }; 1530 1531 qspi_data12: qspi-data12 { 1532 pinmux-data { 1533 pins = "gpio66", "gpio67"; 1534 function = "qspi_data"; 1535 }; 1536 }; 1537 1538 qup_i2c0_default: qup-i2c0-default { 1539 pinmux { 1540 pins = "gpio34", "gpio35"; 1541 function = "qup00"; 1542 }; 1543 }; 1544 1545 qup_i2c1_default: qup-i2c1-default { 1546 pinmux { 1547 pins = "gpio0", "gpio1"; 1548 function = "qup01"; 1549 }; 1550 }; 1551 1552 qup_i2c2_default: qup-i2c2-default { 1553 pinmux { 1554 pins = "gpio15", "gpio16"; 1555 function = "qup02_i2c"; 1556 }; 1557 }; 1558 1559 qup_i2c3_default: qup-i2c3-default { 1560 pinmux { 1561 pins = "gpio38", "gpio39"; 1562 function = "qup03"; 1563 }; 1564 }; 1565 1566 qup_i2c4_default: qup-i2c4-default { 1567 pinmux { 1568 pins = "gpio115", "gpio116"; 1569 function = "qup04_i2c"; 1570 }; 1571 }; 1572 1573 qup_i2c5_default: qup-i2c5-default { 1574 pinmux { 1575 pins = "gpio25", "gpio26"; 1576 function = "qup05"; 1577 }; 1578 }; 1579 1580 qup_i2c6_default: qup-i2c6-default { 1581 pinmux { 1582 pins = "gpio59", "gpio60"; 1583 function = "qup10"; 1584 }; 1585 }; 1586 1587 qup_i2c7_default: qup-i2c7-default { 1588 pinmux { 1589 pins = "gpio6", "gpio7"; 1590 function = "qup11_i2c"; 1591 }; 1592 }; 1593 1594 qup_i2c8_default: qup-i2c8-default { 1595 pinmux { 1596 pins = "gpio42", "gpio43"; 1597 function = "qup12"; 1598 }; 1599 }; 1600 1601 qup_i2c9_default: qup-i2c9-default { 1602 pinmux { 1603 pins = "gpio46", "gpio47"; 1604 function = "qup13_i2c"; 1605 }; 1606 }; 1607 1608 qup_i2c10_default: qup-i2c10-default { 1609 pinmux { 1610 pins = "gpio86", "gpio87"; 1611 function = "qup14"; 1612 }; 1613 }; 1614 1615 qup_i2c11_default: qup-i2c11-default { 1616 pinmux { 1617 pins = "gpio53", "gpio54"; 1618 function = "qup15"; 1619 }; 1620 }; 1621 1622 qup_spi0_default: qup-spi0-default { 1623 pinmux { 1624 pins = "gpio34", "gpio35", 1625 "gpio36", "gpio37"; 1626 function = "qup00"; 1627 }; 1628 }; 1629 1630 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 1631 pinmux { 1632 pins = "gpio34", "gpio35", 1633 "gpio36"; 1634 function = "qup00"; 1635 }; 1636 1637 pinmux-cs { 1638 pins = "gpio37"; 1639 function = "gpio"; 1640 }; 1641 }; 1642 1643 qup_spi1_default: qup-spi1-default { 1644 pinmux { 1645 pins = "gpio0", "gpio1", 1646 "gpio2", "gpio3"; 1647 function = "qup01"; 1648 }; 1649 }; 1650 1651 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 1652 pinmux { 1653 pins = "gpio0", "gpio1", 1654 "gpio2"; 1655 function = "qup01"; 1656 }; 1657 1658 pinmux-cs { 1659 pins = "gpio3"; 1660 function = "gpio"; 1661 }; 1662 }; 1663 1664 qup_spi3_default: qup-spi3-default { 1665 pinmux { 1666 pins = "gpio38", "gpio39", 1667 "gpio40", "gpio41"; 1668 function = "qup03"; 1669 }; 1670 }; 1671 1672 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 1673 pinmux { 1674 pins = "gpio38", "gpio39", 1675 "gpio40"; 1676 function = "qup03"; 1677 }; 1678 1679 pinmux-cs { 1680 pins = "gpio41"; 1681 function = "gpio"; 1682 }; 1683 }; 1684 1685 qup_spi5_default: qup-spi5-default { 1686 pinmux { 1687 pins = "gpio25", "gpio26", 1688 "gpio27", "gpio28"; 1689 function = "qup05"; 1690 }; 1691 }; 1692 1693 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 1694 pinmux { 1695 pins = "gpio25", "gpio26", 1696 "gpio27"; 1697 function = "qup05"; 1698 }; 1699 1700 pinmux-cs { 1701 pins = "gpio28"; 1702 function = "gpio"; 1703 }; 1704 }; 1705 1706 qup_spi6_default: qup-spi6-default { 1707 pinmux { 1708 pins = "gpio59", "gpio60", 1709 "gpio61", "gpio62"; 1710 function = "qup10"; 1711 }; 1712 }; 1713 1714 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 1715 pinmux { 1716 pins = "gpio59", "gpio60", 1717 "gpio61"; 1718 function = "qup10"; 1719 }; 1720 1721 pinmux-cs { 1722 pins = "gpio62"; 1723 function = "gpio"; 1724 }; 1725 }; 1726 1727 qup_spi8_default: qup-spi8-default { 1728 pinmux { 1729 pins = "gpio42", "gpio43", 1730 "gpio44", "gpio45"; 1731 function = "qup12"; 1732 }; 1733 }; 1734 1735 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 1736 pinmux { 1737 pins = "gpio42", "gpio43", 1738 "gpio44"; 1739 function = "qup12"; 1740 }; 1741 1742 pinmux-cs { 1743 pins = "gpio45"; 1744 function = "gpio"; 1745 }; 1746 }; 1747 1748 qup_spi10_default: qup-spi10-default { 1749 pinmux { 1750 pins = "gpio86", "gpio87", 1751 "gpio88", "gpio89"; 1752 function = "qup14"; 1753 }; 1754 }; 1755 1756 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 1757 pinmux { 1758 pins = "gpio86", "gpio87", 1759 "gpio88"; 1760 function = "qup14"; 1761 }; 1762 1763 pinmux-cs { 1764 pins = "gpio89"; 1765 function = "gpio"; 1766 }; 1767 }; 1768 1769 qup_spi11_default: qup-spi11-default { 1770 pinmux { 1771 pins = "gpio53", "gpio54", 1772 "gpio55", "gpio56"; 1773 function = "qup15"; 1774 }; 1775 }; 1776 1777 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 1778 pinmux { 1779 pins = "gpio53", "gpio54", 1780 "gpio55"; 1781 function = "qup15"; 1782 }; 1783 1784 pinmux-cs { 1785 pins = "gpio56"; 1786 function = "gpio"; 1787 }; 1788 }; 1789 1790 qup_uart0_default: qup-uart0-default { 1791 pinmux { 1792 pins = "gpio34", "gpio35", 1793 "gpio36", "gpio37"; 1794 function = "qup00"; 1795 }; 1796 }; 1797 1798 qup_uart1_default: qup-uart1-default { 1799 pinmux { 1800 pins = "gpio0", "gpio1", 1801 "gpio2", "gpio3"; 1802 function = "qup01"; 1803 }; 1804 }; 1805 1806 qup_uart2_default: qup-uart2-default { 1807 pinmux { 1808 pins = "gpio15", "gpio16"; 1809 function = "qup02_uart"; 1810 }; 1811 }; 1812 1813 qup_uart3_default: qup-uart3-default { 1814 pinmux { 1815 pins = "gpio38", "gpio39", 1816 "gpio40", "gpio41"; 1817 function = "qup03"; 1818 }; 1819 }; 1820 1821 qup_uart4_default: qup-uart4-default { 1822 pinmux { 1823 pins = "gpio115", "gpio116"; 1824 function = "qup04_uart"; 1825 }; 1826 }; 1827 1828 qup_uart5_default: qup-uart5-default { 1829 pinmux { 1830 pins = "gpio25", "gpio26", 1831 "gpio27", "gpio28"; 1832 function = "qup05"; 1833 }; 1834 }; 1835 1836 qup_uart6_default: qup-uart6-default { 1837 pinmux { 1838 pins = "gpio59", "gpio60", 1839 "gpio61", "gpio62"; 1840 function = "qup10"; 1841 }; 1842 }; 1843 1844 qup_uart7_default: qup-uart7-default { 1845 pinmux { 1846 pins = "gpio6", "gpio7"; 1847 function = "qup11_uart"; 1848 }; 1849 }; 1850 1851 qup_uart8_default: qup-uart8-default { 1852 pinmux { 1853 pins = "gpio44", "gpio45"; 1854 function = "qup12"; 1855 }; 1856 }; 1857 1858 qup_uart9_default: qup-uart9-default { 1859 pinmux { 1860 pins = "gpio46", "gpio47"; 1861 function = "qup13_uart"; 1862 }; 1863 }; 1864 1865 qup_uart10_default: qup-uart10-default { 1866 pinmux { 1867 pins = "gpio86", "gpio87", 1868 "gpio88", "gpio89"; 1869 function = "qup14"; 1870 }; 1871 }; 1872 1873 qup_uart11_default: qup-uart11-default { 1874 pinmux { 1875 pins = "gpio53", "gpio54", 1876 "gpio55", "gpio56"; 1877 function = "qup15"; 1878 }; 1879 }; 1880 1881 sec_mi2s_active: sec-mi2s-active { 1882 pinmux { 1883 pins = "gpio49", "gpio50", "gpio51"; 1884 function = "mi2s_1"; 1885 }; 1886 }; 1887 1888 pri_mi2s_active: pri-mi2s-active { 1889 pinmux { 1890 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1891 function = "mi2s_0"; 1892 }; 1893 }; 1894 1895 pri_mi2s_mclk_active: pri-mi2s-mclk-active { 1896 pinmux { 1897 pins = "gpio57"; 1898 function = "lpass_ext"; 1899 }; 1900 }; 1901 }; 1902 1903 remoteproc_mpss: remoteproc@4080000 { 1904 compatible = "qcom,sc7180-mpss-pas"; 1905 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1906 reg-names = "qdsp6", "rmb"; 1907 1908 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1909 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1910 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1911 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1912 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1913 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1914 interrupt-names = "wdog", "fatal", "ready", "handover", 1915 "stop-ack", "shutdown-ack"; 1916 1917 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1918 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1919 <&gcc GCC_MSS_NAV_AXI_CLK>, 1920 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1921 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1922 <&rpmhcc RPMH_CXO_CLK>; 1923 clock-names = "iface", "bus", "nav", "snoc_axi", 1924 "mnoc_axi", "xo"; 1925 1926 power-domains = <&rpmhpd SC7180_CX>, 1927 <&rpmhpd SC7180_MX>, 1928 <&rpmhpd SC7180_MSS>; 1929 power-domain-names = "cx", "mx", "mss"; 1930 1931 memory-region = <&mpss_mem>; 1932 1933 qcom,qmp = <&aoss_qmp>; 1934 1935 qcom,smem-states = <&modem_smp2p_out 0>; 1936 qcom,smem-state-names = "stop"; 1937 1938 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1939 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1940 reset-names = "mss_restart", "pdc_reset"; 1941 1942 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1943 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 1944 1945 status = "disabled"; 1946 1947 glink-edge { 1948 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1949 label = "modem"; 1950 qcom,remote-pid = <1>; 1951 mboxes = <&apss_shared 12>; 1952 }; 1953 }; 1954 1955 gpu: gpu@5000000 { 1956 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1957 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1958 <0 0x05061000 0 0x800>; 1959 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1960 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1961 iommus = <&adreno_smmu 0>; 1962 operating-points-v2 = <&gpu_opp_table>; 1963 qcom,gmu = <&gmu>; 1964 1965 #cooling-cells = <2>; 1966 1967 nvmem-cells = <&gpu_speed_bin>; 1968 nvmem-cell-names = "speed_bin"; 1969 1970 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1971 interconnect-names = "gfx-mem"; 1972 1973 gpu_opp_table: opp-table { 1974 compatible = "operating-points-v2"; 1975 1976 opp-825000000 { 1977 opp-hz = /bits/ 64 <825000000>; 1978 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1979 opp-peak-kBps = <8532000>; 1980 opp-supported-hw = <0x04>; 1981 }; 1982 1983 opp-800000000 { 1984 opp-hz = /bits/ 64 <800000000>; 1985 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1986 opp-peak-kBps = <8532000>; 1987 opp-supported-hw = <0x07>; 1988 }; 1989 1990 opp-650000000 { 1991 opp-hz = /bits/ 64 <650000000>; 1992 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1993 opp-peak-kBps = <7216000>; 1994 opp-supported-hw = <0x07>; 1995 }; 1996 1997 opp-565000000 { 1998 opp-hz = /bits/ 64 <565000000>; 1999 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2000 opp-peak-kBps = <5412000>; 2001 opp-supported-hw = <0x07>; 2002 }; 2003 2004 opp-430000000 { 2005 opp-hz = /bits/ 64 <430000000>; 2006 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2007 opp-peak-kBps = <5412000>; 2008 opp-supported-hw = <0x07>; 2009 }; 2010 2011 opp-355000000 { 2012 opp-hz = /bits/ 64 <355000000>; 2013 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2014 opp-peak-kBps = <3072000>; 2015 opp-supported-hw = <0x07>; 2016 }; 2017 2018 opp-267000000 { 2019 opp-hz = /bits/ 64 <267000000>; 2020 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2021 opp-peak-kBps = <3072000>; 2022 opp-supported-hw = <0x07>; 2023 }; 2024 2025 opp-180000000 { 2026 opp-hz = /bits/ 64 <180000000>; 2027 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2028 opp-peak-kBps = <1804000>; 2029 opp-supported-hw = <0x07>; 2030 }; 2031 }; 2032 }; 2033 2034 adreno_smmu: iommu@5040000 { 2035 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2036 reg = <0 0x05040000 0 0x10000>; 2037 #iommu-cells = <1>; 2038 #global-interrupts = <2>; 2039 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2049 2050 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2051 <&gcc GCC_GPU_CFG_AHB_CLK>; 2052 clock-names = "bus", "iface"; 2053 2054 power-domains = <&gpucc CX_GDSC>; 2055 }; 2056 2057 gmu: gmu@506a000 { 2058 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2059 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2060 <0 0x0b490000 0 0x10000>; 2061 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2062 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2064 interrupt-names = "hfi", "gmu"; 2065 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2066 <&gpucc GPU_CC_CXO_CLK>, 2067 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2068 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2069 clock-names = "gmu", "cxo", "axi", "memnoc"; 2070 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2071 power-domain-names = "cx", "gx"; 2072 iommus = <&adreno_smmu 5>; 2073 operating-points-v2 = <&gmu_opp_table>; 2074 2075 gmu_opp_table: opp-table { 2076 compatible = "operating-points-v2"; 2077 2078 opp-200000000 { 2079 opp-hz = /bits/ 64 <200000000>; 2080 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2081 }; 2082 }; 2083 }; 2084 2085 gpucc: clock-controller@5090000 { 2086 compatible = "qcom,sc7180-gpucc"; 2087 reg = <0 0x05090000 0 0x9000>; 2088 clocks = <&rpmhcc RPMH_CXO_CLK>, 2089 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2090 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2091 clock-names = "bi_tcxo", 2092 "gcc_gpu_gpll0_clk_src", 2093 "gcc_gpu_gpll0_div_clk_src"; 2094 #clock-cells = <1>; 2095 #reset-cells = <1>; 2096 #power-domain-cells = <1>; 2097 }; 2098 2099 stm@6002000 { 2100 compatible = "arm,coresight-stm", "arm,primecell"; 2101 reg = <0 0x06002000 0 0x1000>, 2102 <0 0x16280000 0 0x180000>; 2103 reg-names = "stm-base", "stm-stimulus-base"; 2104 2105 clocks = <&aoss_qmp>; 2106 clock-names = "apb_pclk"; 2107 2108 out-ports { 2109 port { 2110 stm_out: endpoint { 2111 remote-endpoint = <&funnel0_in7>; 2112 }; 2113 }; 2114 }; 2115 }; 2116 2117 funnel@6041000 { 2118 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2119 reg = <0 0x06041000 0 0x1000>; 2120 2121 clocks = <&aoss_qmp>; 2122 clock-names = "apb_pclk"; 2123 2124 out-ports { 2125 port { 2126 funnel0_out: endpoint { 2127 remote-endpoint = <&merge_funnel_in0>; 2128 }; 2129 }; 2130 }; 2131 2132 in-ports { 2133 #address-cells = <1>; 2134 #size-cells = <0>; 2135 2136 port@7 { 2137 reg = <7>; 2138 funnel0_in7: endpoint { 2139 remote-endpoint = <&stm_out>; 2140 }; 2141 }; 2142 }; 2143 }; 2144 2145 funnel@6042000 { 2146 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2147 reg = <0 0x06042000 0 0x1000>; 2148 2149 clocks = <&aoss_qmp>; 2150 clock-names = "apb_pclk"; 2151 2152 out-ports { 2153 port { 2154 funnel1_out: endpoint { 2155 remote-endpoint = <&merge_funnel_in1>; 2156 }; 2157 }; 2158 }; 2159 2160 in-ports { 2161 #address-cells = <1>; 2162 #size-cells = <0>; 2163 2164 port@4 { 2165 reg = <4>; 2166 funnel1_in4: endpoint { 2167 remote-endpoint = <&apss_merge_funnel_out>; 2168 }; 2169 }; 2170 }; 2171 }; 2172 2173 funnel@6045000 { 2174 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2175 reg = <0 0x06045000 0 0x1000>; 2176 2177 clocks = <&aoss_qmp>; 2178 clock-names = "apb_pclk"; 2179 2180 out-ports { 2181 port { 2182 merge_funnel_out: endpoint { 2183 remote-endpoint = <&swao_funnel_in>; 2184 }; 2185 }; 2186 }; 2187 2188 in-ports { 2189 #address-cells = <1>; 2190 #size-cells = <0>; 2191 2192 port@0 { 2193 reg = <0>; 2194 merge_funnel_in0: endpoint { 2195 remote-endpoint = <&funnel0_out>; 2196 }; 2197 }; 2198 2199 port@1 { 2200 reg = <1>; 2201 merge_funnel_in1: endpoint { 2202 remote-endpoint = <&funnel1_out>; 2203 }; 2204 }; 2205 }; 2206 }; 2207 2208 replicator@6046000 { 2209 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2210 reg = <0 0x06046000 0 0x1000>; 2211 2212 clocks = <&aoss_qmp>; 2213 clock-names = "apb_pclk"; 2214 2215 out-ports { 2216 port { 2217 replicator_out: endpoint { 2218 remote-endpoint = <&etr_in>; 2219 }; 2220 }; 2221 }; 2222 2223 in-ports { 2224 port { 2225 replicator_in: endpoint { 2226 remote-endpoint = <&swao_replicator_out>; 2227 }; 2228 }; 2229 }; 2230 }; 2231 2232 etr@6048000 { 2233 compatible = "arm,coresight-tmc", "arm,primecell"; 2234 reg = <0 0x06048000 0 0x1000>; 2235 iommus = <&apps_smmu 0x04a0 0x20>; 2236 2237 clocks = <&aoss_qmp>; 2238 clock-names = "apb_pclk"; 2239 arm,scatter-gather; 2240 2241 in-ports { 2242 port { 2243 etr_in: endpoint { 2244 remote-endpoint = <&replicator_out>; 2245 }; 2246 }; 2247 }; 2248 }; 2249 2250 funnel@6b04000 { 2251 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2252 reg = <0 0x06b04000 0 0x1000>; 2253 2254 clocks = <&aoss_qmp>; 2255 clock-names = "apb_pclk"; 2256 2257 out-ports { 2258 port { 2259 swao_funnel_out: endpoint { 2260 remote-endpoint = <&etf_in>; 2261 }; 2262 }; 2263 }; 2264 2265 in-ports { 2266 #address-cells = <1>; 2267 #size-cells = <0>; 2268 2269 port@7 { 2270 reg = <7>; 2271 swao_funnel_in: endpoint { 2272 remote-endpoint = <&merge_funnel_out>; 2273 }; 2274 }; 2275 }; 2276 }; 2277 2278 etf@6b05000 { 2279 compatible = "arm,coresight-tmc", "arm,primecell"; 2280 reg = <0 0x06b05000 0 0x1000>; 2281 2282 clocks = <&aoss_qmp>; 2283 clock-names = "apb_pclk"; 2284 2285 out-ports { 2286 port { 2287 etf_out: endpoint { 2288 remote-endpoint = <&swao_replicator_in>; 2289 }; 2290 }; 2291 }; 2292 2293 in-ports { 2294 port { 2295 etf_in: endpoint { 2296 remote-endpoint = <&swao_funnel_out>; 2297 }; 2298 }; 2299 }; 2300 }; 2301 2302 replicator@6b06000 { 2303 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2304 reg = <0 0x06b06000 0 0x1000>; 2305 2306 clocks = <&aoss_qmp>; 2307 clock-names = "apb_pclk"; 2308 qcom,replicator-loses-context; 2309 2310 out-ports { 2311 port { 2312 swao_replicator_out: endpoint { 2313 remote-endpoint = <&replicator_in>; 2314 }; 2315 }; 2316 }; 2317 2318 in-ports { 2319 port { 2320 swao_replicator_in: endpoint { 2321 remote-endpoint = <&etf_out>; 2322 }; 2323 }; 2324 }; 2325 }; 2326 2327 etm@7040000 { 2328 compatible = "arm,coresight-etm4x", "arm,primecell"; 2329 reg = <0 0x07040000 0 0x1000>; 2330 2331 cpu = <&CPU0>; 2332 2333 clocks = <&aoss_qmp>; 2334 clock-names = "apb_pclk"; 2335 arm,coresight-loses-context-with-cpu; 2336 qcom,skip-power-up; 2337 2338 out-ports { 2339 port { 2340 etm0_out: endpoint { 2341 remote-endpoint = <&apss_funnel_in0>; 2342 }; 2343 }; 2344 }; 2345 }; 2346 2347 etm@7140000 { 2348 compatible = "arm,coresight-etm4x", "arm,primecell"; 2349 reg = <0 0x07140000 0 0x1000>; 2350 2351 cpu = <&CPU1>; 2352 2353 clocks = <&aoss_qmp>; 2354 clock-names = "apb_pclk"; 2355 arm,coresight-loses-context-with-cpu; 2356 qcom,skip-power-up; 2357 2358 out-ports { 2359 port { 2360 etm1_out: endpoint { 2361 remote-endpoint = <&apss_funnel_in1>; 2362 }; 2363 }; 2364 }; 2365 }; 2366 2367 etm@7240000 { 2368 compatible = "arm,coresight-etm4x", "arm,primecell"; 2369 reg = <0 0x07240000 0 0x1000>; 2370 2371 cpu = <&CPU2>; 2372 2373 clocks = <&aoss_qmp>; 2374 clock-names = "apb_pclk"; 2375 arm,coresight-loses-context-with-cpu; 2376 qcom,skip-power-up; 2377 2378 out-ports { 2379 port { 2380 etm2_out: endpoint { 2381 remote-endpoint = <&apss_funnel_in2>; 2382 }; 2383 }; 2384 }; 2385 }; 2386 2387 etm@7340000 { 2388 compatible = "arm,coresight-etm4x", "arm,primecell"; 2389 reg = <0 0x07340000 0 0x1000>; 2390 2391 cpu = <&CPU3>; 2392 2393 clocks = <&aoss_qmp>; 2394 clock-names = "apb_pclk"; 2395 arm,coresight-loses-context-with-cpu; 2396 qcom,skip-power-up; 2397 2398 out-ports { 2399 port { 2400 etm3_out: endpoint { 2401 remote-endpoint = <&apss_funnel_in3>; 2402 }; 2403 }; 2404 }; 2405 }; 2406 2407 etm@7440000 { 2408 compatible = "arm,coresight-etm4x", "arm,primecell"; 2409 reg = <0 0x07440000 0 0x1000>; 2410 2411 cpu = <&CPU4>; 2412 2413 clocks = <&aoss_qmp>; 2414 clock-names = "apb_pclk"; 2415 arm,coresight-loses-context-with-cpu; 2416 qcom,skip-power-up; 2417 2418 out-ports { 2419 port { 2420 etm4_out: endpoint { 2421 remote-endpoint = <&apss_funnel_in4>; 2422 }; 2423 }; 2424 }; 2425 }; 2426 2427 etm@7540000 { 2428 compatible = "arm,coresight-etm4x", "arm,primecell"; 2429 reg = <0 0x07540000 0 0x1000>; 2430 2431 cpu = <&CPU5>; 2432 2433 clocks = <&aoss_qmp>; 2434 clock-names = "apb_pclk"; 2435 arm,coresight-loses-context-with-cpu; 2436 qcom,skip-power-up; 2437 2438 out-ports { 2439 port { 2440 etm5_out: endpoint { 2441 remote-endpoint = <&apss_funnel_in5>; 2442 }; 2443 }; 2444 }; 2445 }; 2446 2447 etm@7640000 { 2448 compatible = "arm,coresight-etm4x", "arm,primecell"; 2449 reg = <0 0x07640000 0 0x1000>; 2450 2451 cpu = <&CPU6>; 2452 2453 clocks = <&aoss_qmp>; 2454 clock-names = "apb_pclk"; 2455 arm,coresight-loses-context-with-cpu; 2456 qcom,skip-power-up; 2457 2458 out-ports { 2459 port { 2460 etm6_out: endpoint { 2461 remote-endpoint = <&apss_funnel_in6>; 2462 }; 2463 }; 2464 }; 2465 }; 2466 2467 etm@7740000 { 2468 compatible = "arm,coresight-etm4x", "arm,primecell"; 2469 reg = <0 0x07740000 0 0x1000>; 2470 2471 cpu = <&CPU7>; 2472 2473 clocks = <&aoss_qmp>; 2474 clock-names = "apb_pclk"; 2475 arm,coresight-loses-context-with-cpu; 2476 qcom,skip-power-up; 2477 2478 out-ports { 2479 port { 2480 etm7_out: endpoint { 2481 remote-endpoint = <&apss_funnel_in7>; 2482 }; 2483 }; 2484 }; 2485 }; 2486 2487 funnel@7800000 { /* APSS Funnel */ 2488 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2489 reg = <0 0x07800000 0 0x1000>; 2490 2491 clocks = <&aoss_qmp>; 2492 clock-names = "apb_pclk"; 2493 2494 out-ports { 2495 port { 2496 apss_funnel_out: endpoint { 2497 remote-endpoint = <&apss_merge_funnel_in>; 2498 }; 2499 }; 2500 }; 2501 2502 in-ports { 2503 #address-cells = <1>; 2504 #size-cells = <0>; 2505 2506 port@0 { 2507 reg = <0>; 2508 apss_funnel_in0: endpoint { 2509 remote-endpoint = <&etm0_out>; 2510 }; 2511 }; 2512 2513 port@1 { 2514 reg = <1>; 2515 apss_funnel_in1: endpoint { 2516 remote-endpoint = <&etm1_out>; 2517 }; 2518 }; 2519 2520 port@2 { 2521 reg = <2>; 2522 apss_funnel_in2: endpoint { 2523 remote-endpoint = <&etm2_out>; 2524 }; 2525 }; 2526 2527 port@3 { 2528 reg = <3>; 2529 apss_funnel_in3: endpoint { 2530 remote-endpoint = <&etm3_out>; 2531 }; 2532 }; 2533 2534 port@4 { 2535 reg = <4>; 2536 apss_funnel_in4: endpoint { 2537 remote-endpoint = <&etm4_out>; 2538 }; 2539 }; 2540 2541 port@5 { 2542 reg = <5>; 2543 apss_funnel_in5: endpoint { 2544 remote-endpoint = <&etm5_out>; 2545 }; 2546 }; 2547 2548 port@6 { 2549 reg = <6>; 2550 apss_funnel_in6: endpoint { 2551 remote-endpoint = <&etm6_out>; 2552 }; 2553 }; 2554 2555 port@7 { 2556 reg = <7>; 2557 apss_funnel_in7: endpoint { 2558 remote-endpoint = <&etm7_out>; 2559 }; 2560 }; 2561 }; 2562 }; 2563 2564 funnel@7810000 { 2565 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2566 reg = <0 0x07810000 0 0x1000>; 2567 2568 clocks = <&aoss_qmp>; 2569 clock-names = "apb_pclk"; 2570 2571 out-ports { 2572 port { 2573 apss_merge_funnel_out: endpoint { 2574 remote-endpoint = <&funnel1_in4>; 2575 }; 2576 }; 2577 }; 2578 2579 in-ports { 2580 port { 2581 apss_merge_funnel_in: endpoint { 2582 remote-endpoint = <&apss_funnel_out>; 2583 }; 2584 }; 2585 }; 2586 }; 2587 2588 sdhc_2: sdhci@8804000 { 2589 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2590 reg = <0 0x08804000 0 0x1000>; 2591 2592 iommus = <&apps_smmu 0x80 0>; 2593 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2595 interrupt-names = "hc_irq", "pwr_irq"; 2596 2597 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2598 <&gcc GCC_SDCC2_AHB_CLK>, 2599 <&rpmhcc RPMH_CXO_CLK>; 2600 clock-names = "core", "iface", "xo"; 2601 2602 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2603 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2604 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2605 power-domains = <&rpmhpd SC7180_CX>; 2606 operating-points-v2 = <&sdhc2_opp_table>; 2607 2608 bus-width = <4>; 2609 2610 status = "disabled"; 2611 2612 sdhc2_opp_table: sdhc2-opp-table { 2613 compatible = "operating-points-v2"; 2614 2615 opp-100000000 { 2616 opp-hz = /bits/ 64 <100000000>; 2617 required-opps = <&rpmhpd_opp_low_svs>; 2618 opp-peak-kBps = <1800000 600000>; 2619 opp-avg-kBps = <100000 0>; 2620 }; 2621 2622 opp-202000000 { 2623 opp-hz = /bits/ 64 <202000000>; 2624 required-opps = <&rpmhpd_opp_nom>; 2625 opp-peak-kBps = <5400000 1600000>; 2626 opp-avg-kBps = <200000 0>; 2627 }; 2628 }; 2629 }; 2630 2631 qspi_opp_table: qspi-opp-table { 2632 compatible = "operating-points-v2"; 2633 2634 opp-75000000 { 2635 opp-hz = /bits/ 64 <75000000>; 2636 required-opps = <&rpmhpd_opp_low_svs>; 2637 }; 2638 2639 opp-150000000 { 2640 opp-hz = /bits/ 64 <150000000>; 2641 required-opps = <&rpmhpd_opp_svs>; 2642 }; 2643 2644 opp-300000000 { 2645 opp-hz = /bits/ 64 <300000000>; 2646 required-opps = <&rpmhpd_opp_nom>; 2647 }; 2648 }; 2649 2650 qspi: spi@88dc000 { 2651 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2652 reg = <0 0x088dc000 0 0x600>; 2653 #address-cells = <1>; 2654 #size-cells = <0>; 2655 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2656 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2657 <&gcc GCC_QSPI_CORE_CLK>; 2658 clock-names = "iface", "core"; 2659 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2660 &config_noc SLAVE_QSPI_0 0>; 2661 interconnect-names = "qspi-config"; 2662 power-domains = <&rpmhpd SC7180_CX>; 2663 operating-points-v2 = <&qspi_opp_table>; 2664 status = "disabled"; 2665 }; 2666 2667 usb_1_hsphy: phy@88e3000 { 2668 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2669 reg = <0 0x088e3000 0 0x400>; 2670 status = "disabled"; 2671 #phy-cells = <0>; 2672 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2673 <&rpmhcc RPMH_CXO_CLK>; 2674 clock-names = "cfg_ahb", "ref"; 2675 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2676 2677 nvmem-cells = <&qusb2p_hstx_trim>; 2678 }; 2679 2680 usb_1_qmpphy: phy-wrapper@88e9000 { 2681 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2682 reg = <0 0x088e9000 0 0x18c>, 2683 <0 0x088e8000 0 0x3c>, 2684 <0 0x088ea000 0 0x18c>; 2685 status = "disabled"; 2686 #address-cells = <2>; 2687 #size-cells = <2>; 2688 ranges; 2689 2690 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2691 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2692 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2693 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2694 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2695 2696 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2697 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2698 reset-names = "phy", "common"; 2699 2700 usb_1_ssphy: usb3-phy@88e9200 { 2701 reg = <0 0x088e9200 0 0x128>, 2702 <0 0x088e9400 0 0x200>, 2703 <0 0x088e9c00 0 0x218>, 2704 <0 0x088e9600 0 0x128>, 2705 <0 0x088e9800 0 0x200>, 2706 <0 0x088e9a00 0 0x18>; 2707 #clock-cells = <0>; 2708 #phy-cells = <0>; 2709 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2710 clock-names = "pipe0"; 2711 clock-output-names = "usb3_phy_pipe_clk_src"; 2712 }; 2713 2714 dp_phy: dp-phy@88ea200 { 2715 reg = <0 0x088ea200 0 0x200>, 2716 <0 0x088ea400 0 0x200>, 2717 <0 0x088eaa00 0 0x200>, 2718 <0 0x088ea600 0 0x200>, 2719 <0 0x088ea800 0 0x200>; 2720 #clock-cells = <1>; 2721 #phy-cells = <0>; 2722 }; 2723 }; 2724 2725 dc_noc: interconnect@9160000 { 2726 compatible = "qcom,sc7180-dc-noc"; 2727 reg = <0 0x09160000 0 0x03200>; 2728 #interconnect-cells = <2>; 2729 qcom,bcm-voters = <&apps_bcm_voter>; 2730 }; 2731 2732 system-cache-controller@9200000 { 2733 compatible = "qcom,sc7180-llcc"; 2734 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2735 reg-names = "llcc_base", "llcc_broadcast_base"; 2736 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2737 }; 2738 2739 gem_noc: interconnect@9680000 { 2740 compatible = "qcom,sc7180-gem-noc"; 2741 reg = <0 0x09680000 0 0x3e200>; 2742 #interconnect-cells = <2>; 2743 qcom,bcm-voters = <&apps_bcm_voter>; 2744 }; 2745 2746 npu_noc: interconnect@9990000 { 2747 compatible = "qcom,sc7180-npu-noc"; 2748 reg = <0 0x09990000 0 0x1600>; 2749 #interconnect-cells = <2>; 2750 qcom,bcm-voters = <&apps_bcm_voter>; 2751 }; 2752 2753 usb_1: usb@a6f8800 { 2754 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2755 reg = <0 0x0a6f8800 0 0x400>; 2756 status = "disabled"; 2757 #address-cells = <2>; 2758 #size-cells = <2>; 2759 ranges; 2760 dma-ranges; 2761 2762 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2763 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2764 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2765 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2766 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2767 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2768 "sleep"; 2769 2770 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2771 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2772 assigned-clock-rates = <19200000>, <150000000>; 2773 2774 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2775 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2776 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2777 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2778 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2779 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2780 2781 power-domains = <&gcc USB30_PRIM_GDSC>; 2782 2783 resets = <&gcc GCC_USB30_PRIM_BCR>; 2784 2785 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2786 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2787 interconnect-names = "usb-ddr", "apps-usb"; 2788 2789 usb_1_dwc3: dwc3@a600000 { 2790 compatible = "snps,dwc3"; 2791 reg = <0 0x0a600000 0 0xe000>; 2792 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2793 iommus = <&apps_smmu 0x540 0>; 2794 snps,dis_u2_susphy_quirk; 2795 snps,dis_enblslpm_quirk; 2796 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2797 phy-names = "usb2-phy", "usb3-phy"; 2798 maximum-speed = "super-speed"; 2799 }; 2800 }; 2801 2802 venus: video-codec@aa00000 { 2803 compatible = "qcom,sc7180-venus"; 2804 reg = <0 0x0aa00000 0 0xff000>; 2805 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2806 power-domains = <&videocc VENUS_GDSC>, 2807 <&videocc VCODEC0_GDSC>, 2808 <&rpmhpd SC7180_CX>; 2809 power-domain-names = "venus", "vcodec0", "cx"; 2810 operating-points-v2 = <&venus_opp_table>; 2811 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2812 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2813 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2814 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2815 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2816 clock-names = "core", "iface", "bus", 2817 "vcodec0_core", "vcodec0_bus"; 2818 iommus = <&apps_smmu 0x0c00 0x60>; 2819 memory-region = <&venus_mem>; 2820 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2821 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2822 interconnect-names = "video-mem", "cpu-cfg"; 2823 2824 video-decoder { 2825 compatible = "venus-decoder"; 2826 }; 2827 2828 video-encoder { 2829 compatible = "venus-encoder"; 2830 }; 2831 2832 venus_opp_table: venus-opp-table { 2833 compatible = "operating-points-v2"; 2834 2835 opp-150000000 { 2836 opp-hz = /bits/ 64 <150000000>; 2837 required-opps = <&rpmhpd_opp_low_svs>; 2838 }; 2839 2840 opp-270000000 { 2841 opp-hz = /bits/ 64 <270000000>; 2842 required-opps = <&rpmhpd_opp_svs>; 2843 }; 2844 2845 opp-340000000 { 2846 opp-hz = /bits/ 64 <340000000>; 2847 required-opps = <&rpmhpd_opp_svs_l1>; 2848 }; 2849 2850 opp-434000000 { 2851 opp-hz = /bits/ 64 <434000000>; 2852 required-opps = <&rpmhpd_opp_nom>; 2853 }; 2854 2855 opp-500000097 { 2856 opp-hz = /bits/ 64 <500000097>; 2857 required-opps = <&rpmhpd_opp_turbo>; 2858 }; 2859 }; 2860 }; 2861 2862 videocc: clock-controller@ab00000 { 2863 compatible = "qcom,sc7180-videocc"; 2864 reg = <0 0x0ab00000 0 0x10000>; 2865 clocks = <&rpmhcc RPMH_CXO_CLK>; 2866 clock-names = "bi_tcxo"; 2867 #clock-cells = <1>; 2868 #reset-cells = <1>; 2869 #power-domain-cells = <1>; 2870 }; 2871 2872 camnoc_virt: interconnect@ac00000 { 2873 compatible = "qcom,sc7180-camnoc-virt"; 2874 reg = <0 0x0ac00000 0 0x1000>; 2875 #interconnect-cells = <2>; 2876 qcom,bcm-voters = <&apps_bcm_voter>; 2877 }; 2878 2879 camcc: clock-controller@ad00000 { 2880 compatible = "qcom,sc7180-camcc"; 2881 reg = <0 0x0ad00000 0 0x10000>; 2882 clocks = <&rpmhcc RPMH_CXO_CLK>, 2883 <&gcc GCC_CAMERA_AHB_CLK>, 2884 <&gcc GCC_CAMERA_XO_CLK>; 2885 clock-names = "bi_tcxo", "iface", "xo"; 2886 #clock-cells = <1>; 2887 #reset-cells = <1>; 2888 #power-domain-cells = <1>; 2889 }; 2890 2891 mdss: mdss@ae00000 { 2892 compatible = "qcom,sc7180-mdss"; 2893 reg = <0 0x0ae00000 0 0x1000>; 2894 reg-names = "mdss"; 2895 2896 power-domains = <&dispcc MDSS_GDSC>; 2897 2898 clocks = <&gcc GCC_DISP_AHB_CLK>, 2899 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2900 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2901 clock-names = "iface", "ahb", "core"; 2902 2903 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2904 assigned-clock-rates = <300000000>; 2905 2906 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2907 interrupt-controller; 2908 #interrupt-cells = <1>; 2909 2910 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2911 interconnect-names = "mdp0-mem"; 2912 2913 iommus = <&apps_smmu 0x800 0x2>; 2914 2915 #address-cells = <2>; 2916 #size-cells = <2>; 2917 ranges; 2918 2919 status = "disabled"; 2920 2921 mdp: mdp@ae01000 { 2922 compatible = "qcom,sc7180-dpu"; 2923 reg = <0 0x0ae01000 0 0x8f000>, 2924 <0 0x0aeb0000 0 0x2008>; 2925 reg-names = "mdp", "vbif"; 2926 2927 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2928 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2929 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2930 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2931 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2932 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2933 clock-names = "bus", "iface", "rot", "lut", "core", 2934 "vsync"; 2935 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2936 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2937 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2938 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2939 assigned-clock-rates = <300000000>, 2940 <19200000>, 2941 <19200000>, 2942 <19200000>; 2943 operating-points-v2 = <&mdp_opp_table>; 2944 power-domains = <&rpmhpd SC7180_CX>; 2945 2946 interrupt-parent = <&mdss>; 2947 interrupts = <0>; 2948 2949 status = "disabled"; 2950 2951 ports { 2952 #address-cells = <1>; 2953 #size-cells = <0>; 2954 2955 port@0 { 2956 reg = <0>; 2957 dpu_intf1_out: endpoint { 2958 remote-endpoint = <&dsi0_in>; 2959 }; 2960 }; 2961 2962 port@2 { 2963 reg = <2>; 2964 dpu_intf0_out: endpoint { 2965 remote-endpoint = <&dp_in>; 2966 }; 2967 }; 2968 }; 2969 2970 mdp_opp_table: mdp-opp-table { 2971 compatible = "operating-points-v2"; 2972 2973 opp-200000000 { 2974 opp-hz = /bits/ 64 <200000000>; 2975 required-opps = <&rpmhpd_opp_low_svs>; 2976 }; 2977 2978 opp-300000000 { 2979 opp-hz = /bits/ 64 <300000000>; 2980 required-opps = <&rpmhpd_opp_svs>; 2981 }; 2982 2983 opp-345000000 { 2984 opp-hz = /bits/ 64 <345000000>; 2985 required-opps = <&rpmhpd_opp_svs_l1>; 2986 }; 2987 2988 opp-460000000 { 2989 opp-hz = /bits/ 64 <460000000>; 2990 required-opps = <&rpmhpd_opp_nom>; 2991 }; 2992 }; 2993 2994 }; 2995 2996 dsi0: dsi@ae94000 { 2997 compatible = "qcom,mdss-dsi-ctrl"; 2998 reg = <0 0x0ae94000 0 0x400>; 2999 reg-names = "dsi_ctrl"; 3000 3001 interrupt-parent = <&mdss>; 3002 interrupts = <4>; 3003 3004 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3005 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3006 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3007 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3008 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3009 <&gcc GCC_DISP_HF_AXI_CLK>; 3010 clock-names = "byte", 3011 "byte_intf", 3012 "pixel", 3013 "core", 3014 "iface", 3015 "bus"; 3016 3017 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3018 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 3019 3020 operating-points-v2 = <&dsi_opp_table>; 3021 power-domains = <&rpmhpd SC7180_CX>; 3022 3023 phys = <&dsi_phy>; 3024 phy-names = "dsi"; 3025 3026 #address-cells = <1>; 3027 #size-cells = <0>; 3028 3029 status = "disabled"; 3030 3031 ports { 3032 #address-cells = <1>; 3033 #size-cells = <0>; 3034 3035 port@0 { 3036 reg = <0>; 3037 dsi0_in: endpoint { 3038 remote-endpoint = <&dpu_intf1_out>; 3039 }; 3040 }; 3041 3042 port@1 { 3043 reg = <1>; 3044 dsi0_out: endpoint { 3045 }; 3046 }; 3047 }; 3048 3049 dsi_opp_table: dsi-opp-table { 3050 compatible = "operating-points-v2"; 3051 3052 opp-187500000 { 3053 opp-hz = /bits/ 64 <187500000>; 3054 required-opps = <&rpmhpd_opp_low_svs>; 3055 }; 3056 3057 opp-300000000 { 3058 opp-hz = /bits/ 64 <300000000>; 3059 required-opps = <&rpmhpd_opp_svs>; 3060 }; 3061 3062 opp-358000000 { 3063 opp-hz = /bits/ 64 <358000000>; 3064 required-opps = <&rpmhpd_opp_svs_l1>; 3065 }; 3066 }; 3067 }; 3068 3069 dsi_phy: dsi-phy@ae94400 { 3070 compatible = "qcom,dsi-phy-10nm"; 3071 reg = <0 0x0ae94400 0 0x200>, 3072 <0 0x0ae94600 0 0x280>, 3073 <0 0x0ae94a00 0 0x1e0>; 3074 reg-names = "dsi_phy", 3075 "dsi_phy_lane", 3076 "dsi_pll"; 3077 3078 #clock-cells = <1>; 3079 #phy-cells = <0>; 3080 3081 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3082 <&rpmhcc RPMH_CXO_CLK>; 3083 clock-names = "iface", "ref"; 3084 3085 status = "disabled"; 3086 }; 3087 3088 mdss_dp: displayport-controller@ae90000 { 3089 compatible = "qcom,sc7180-dp"; 3090 status = "disabled"; 3091 3092 reg = <0 0x0ae90000 0 0x1400>; 3093 3094 interrupt-parent = <&mdss>; 3095 interrupts = <12>; 3096 3097 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3098 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3099 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3100 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3101 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3102 clock-names = "core_iface", "core_aux", "ctrl_link", 3103 "ctrl_link_iface", "stream_pixel"; 3104 #clock-cells = <1>; 3105 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3106 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3107 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3108 phys = <&dp_phy>; 3109 phy-names = "dp"; 3110 3111 operating-points-v2 = <&dp_opp_table>; 3112 power-domains = <&rpmhpd SC7180_CX>; 3113 3114 #sound-dai-cells = <0>; 3115 3116 ports { 3117 #address-cells = <1>; 3118 #size-cells = <0>; 3119 port@0 { 3120 reg = <0>; 3121 dp_in: endpoint { 3122 remote-endpoint = <&dpu_intf0_out>; 3123 }; 3124 }; 3125 3126 port@1 { 3127 reg = <1>; 3128 dp_out: endpoint { }; 3129 }; 3130 }; 3131 3132 dp_opp_table: opp-table { 3133 compatible = "operating-points-v2"; 3134 3135 opp-160000000 { 3136 opp-hz = /bits/ 64 <160000000>; 3137 required-opps = <&rpmhpd_opp_low_svs>; 3138 }; 3139 3140 opp-270000000 { 3141 opp-hz = /bits/ 64 <270000000>; 3142 required-opps = <&rpmhpd_opp_svs>; 3143 }; 3144 3145 opp-540000000 { 3146 opp-hz = /bits/ 64 <540000000>; 3147 required-opps = <&rpmhpd_opp_svs_l1>; 3148 }; 3149 3150 opp-810000000 { 3151 opp-hz = /bits/ 64 <810000000>; 3152 required-opps = <&rpmhpd_opp_nom>; 3153 }; 3154 }; 3155 }; 3156 }; 3157 3158 dispcc: clock-controller@af00000 { 3159 compatible = "qcom,sc7180-dispcc"; 3160 reg = <0 0x0af00000 0 0x200000>; 3161 clocks = <&rpmhcc RPMH_CXO_CLK>, 3162 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3163 <&dsi_phy 0>, 3164 <&dsi_phy 1>, 3165 <&dp_phy 0>, 3166 <&dp_phy 1>; 3167 clock-names = "bi_tcxo", 3168 "gcc_disp_gpll0_clk_src", 3169 "dsi0_phy_pll_out_byteclk", 3170 "dsi0_phy_pll_out_dsiclk", 3171 "dp_phy_pll_link_clk", 3172 "dp_phy_pll_vco_div_clk"; 3173 #clock-cells = <1>; 3174 #reset-cells = <1>; 3175 #power-domain-cells = <1>; 3176 }; 3177 3178 pdc: interrupt-controller@b220000 { 3179 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3180 reg = <0 0x0b220000 0 0x30000>; 3181 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3182 #interrupt-cells = <2>; 3183 interrupt-parent = <&intc>; 3184 interrupt-controller; 3185 }; 3186 3187 pdc_reset: reset-controller@b2e0000 { 3188 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3189 reg = <0 0x0b2e0000 0 0x20000>; 3190 #reset-cells = <1>; 3191 }; 3192 3193 tsens0: thermal-sensor@c263000 { 3194 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3195 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3196 <0 0x0c222000 0 0x1ff>; /* SROT */ 3197 #qcom,sensors = <15>; 3198 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3200 interrupt-names = "uplow","critical"; 3201 #thermal-sensor-cells = <1>; 3202 }; 3203 3204 tsens1: thermal-sensor@c265000 { 3205 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3206 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3207 <0 0x0c223000 0 0x1ff>; /* SROT */ 3208 #qcom,sensors = <10>; 3209 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3211 interrupt-names = "uplow","critical"; 3212 #thermal-sensor-cells = <1>; 3213 }; 3214 3215 aoss_reset: reset-controller@c2a0000 { 3216 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3217 reg = <0 0x0c2a0000 0 0x31000>; 3218 #reset-cells = <1>; 3219 }; 3220 3221 aoss_qmp: power-controller@c300000 { 3222 compatible = "qcom,sc7180-aoss-qmp"; 3223 reg = <0 0x0c300000 0 0x400>; 3224 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3225 mboxes = <&apss_shared 0>; 3226 3227 #clock-cells = <0>; 3228 }; 3229 3230 sram@c3f0000 { 3231 compatible = "qcom,rpmh-stats"; 3232 reg = <0 0x0c3f0000 0 0x400>; 3233 }; 3234 3235 spmi_bus: spmi@c440000 { 3236 compatible = "qcom,spmi-pmic-arb"; 3237 reg = <0 0x0c440000 0 0x1100>, 3238 <0 0x0c600000 0 0x2000000>, 3239 <0 0x0e600000 0 0x100000>, 3240 <0 0x0e700000 0 0xa0000>, 3241 <0 0x0c40a000 0 0x26000>; 3242 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3243 interrupt-names = "periph_irq"; 3244 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3245 qcom,ee = <0>; 3246 qcom,channel = <0>; 3247 #address-cells = <1>; 3248 #size-cells = <1>; 3249 interrupt-controller; 3250 #interrupt-cells = <4>; 3251 cell-index = <0>; 3252 }; 3253 3254 imem@146aa000 { 3255 compatible = "simple-mfd"; 3256 reg = <0 0x146aa000 0 0x2000>; 3257 3258 #address-cells = <1>; 3259 #size-cells = <1>; 3260 3261 ranges = <0 0 0x146aa000 0x2000>; 3262 3263 pil-reloc@94c { 3264 compatible = "qcom,pil-reloc-info"; 3265 reg = <0x94c 0xc8>; 3266 }; 3267 }; 3268 3269 apps_smmu: iommu@15000000 { 3270 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3271 reg = <0 0x15000000 0 0x100000>; 3272 #iommu-cells = <2>; 3273 #global-interrupts = <1>; 3274 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3355 }; 3356 3357 intc: interrupt-controller@17a00000 { 3358 compatible = "arm,gic-v3"; 3359 #address-cells = <2>; 3360 #size-cells = <2>; 3361 ranges; 3362 #interrupt-cells = <3>; 3363 interrupt-controller; 3364 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3365 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3366 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3367 3368 msi-controller@17a40000 { 3369 compatible = "arm,gic-v3-its"; 3370 msi-controller; 3371 #msi-cells = <1>; 3372 reg = <0 0x17a40000 0 0x20000>; 3373 status = "disabled"; 3374 }; 3375 }; 3376 3377 apss_shared: mailbox@17c00000 { 3378 compatible = "qcom,sc7180-apss-shared"; 3379 reg = <0 0x17c00000 0 0x10000>; 3380 #mbox-cells = <1>; 3381 }; 3382 3383 watchdog@17c10000 { 3384 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3385 reg = <0 0x17c10000 0 0x1000>; 3386 clocks = <&sleep_clk>; 3387 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3388 }; 3389 3390 timer@17c20000{ 3391 #address-cells = <2>; 3392 #size-cells = <2>; 3393 ranges; 3394 compatible = "arm,armv7-timer-mem"; 3395 reg = <0 0x17c20000 0 0x1000>; 3396 3397 frame@17c21000 { 3398 frame-number = <0>; 3399 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3401 reg = <0 0x17c21000 0 0x1000>, 3402 <0 0x17c22000 0 0x1000>; 3403 }; 3404 3405 frame@17c23000 { 3406 frame-number = <1>; 3407 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3408 reg = <0 0x17c23000 0 0x1000>; 3409 status = "disabled"; 3410 }; 3411 3412 frame@17c25000 { 3413 frame-number = <2>; 3414 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3415 reg = <0 0x17c25000 0 0x1000>; 3416 status = "disabled"; 3417 }; 3418 3419 frame@17c27000 { 3420 frame-number = <3>; 3421 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3422 reg = <0 0x17c27000 0 0x1000>; 3423 status = "disabled"; 3424 }; 3425 3426 frame@17c29000 { 3427 frame-number = <4>; 3428 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3429 reg = <0 0x17c29000 0 0x1000>; 3430 status = "disabled"; 3431 }; 3432 3433 frame@17c2b000 { 3434 frame-number = <5>; 3435 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3436 reg = <0 0x17c2b000 0 0x1000>; 3437 status = "disabled"; 3438 }; 3439 3440 frame@17c2d000 { 3441 frame-number = <6>; 3442 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3443 reg = <0 0x17c2d000 0 0x1000>; 3444 status = "disabled"; 3445 }; 3446 }; 3447 3448 apps_rsc: rsc@18200000 { 3449 compatible = "qcom,rpmh-rsc"; 3450 reg = <0 0x18200000 0 0x10000>, 3451 <0 0x18210000 0 0x10000>, 3452 <0 0x18220000 0 0x10000>; 3453 reg-names = "drv-0", "drv-1", "drv-2"; 3454 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3457 qcom,tcs-offset = <0xd00>; 3458 qcom,drv-id = <2>; 3459 qcom,tcs-config = <ACTIVE_TCS 2>, 3460 <SLEEP_TCS 3>, 3461 <WAKE_TCS 3>, 3462 <CONTROL_TCS 1>; 3463 3464 rpmhcc: clock-controller { 3465 compatible = "qcom,sc7180-rpmh-clk"; 3466 clocks = <&xo_board>; 3467 clock-names = "xo"; 3468 #clock-cells = <1>; 3469 }; 3470 3471 rpmhpd: power-controller { 3472 compatible = "qcom,sc7180-rpmhpd"; 3473 #power-domain-cells = <1>; 3474 operating-points-v2 = <&rpmhpd_opp_table>; 3475 3476 rpmhpd_opp_table: opp-table { 3477 compatible = "operating-points-v2"; 3478 3479 rpmhpd_opp_ret: opp1 { 3480 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3481 }; 3482 3483 rpmhpd_opp_min_svs: opp2 { 3484 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3485 }; 3486 3487 rpmhpd_opp_low_svs: opp3 { 3488 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3489 }; 3490 3491 rpmhpd_opp_svs: opp4 { 3492 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3493 }; 3494 3495 rpmhpd_opp_svs_l1: opp5 { 3496 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3497 }; 3498 3499 rpmhpd_opp_svs_l2: opp6 { 3500 opp-level = <224>; 3501 }; 3502 3503 rpmhpd_opp_nom: opp7 { 3504 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3505 }; 3506 3507 rpmhpd_opp_nom_l1: opp8 { 3508 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3509 }; 3510 3511 rpmhpd_opp_nom_l2: opp9 { 3512 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3513 }; 3514 3515 rpmhpd_opp_turbo: opp10 { 3516 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3517 }; 3518 3519 rpmhpd_opp_turbo_l1: opp11 { 3520 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3521 }; 3522 }; 3523 }; 3524 3525 apps_bcm_voter: bcm_voter { 3526 compatible = "qcom,bcm-voter"; 3527 }; 3528 }; 3529 3530 osm_l3: interconnect@18321000 { 3531 compatible = "qcom,sc7180-osm-l3"; 3532 reg = <0 0x18321000 0 0x1400>; 3533 3534 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3535 clock-names = "xo", "alternate"; 3536 3537 #interconnect-cells = <1>; 3538 }; 3539 3540 cpufreq_hw: cpufreq@18323000 { 3541 compatible = "qcom,cpufreq-hw"; 3542 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3543 reg-names = "freq-domain0", "freq-domain1"; 3544 3545 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3546 clock-names = "xo", "alternate"; 3547 3548 #freq-domain-cells = <1>; 3549 }; 3550 3551 wifi: wifi@18800000 { 3552 compatible = "qcom,wcn3990-wifi"; 3553 reg = <0 0x18800000 0 0x800000>; 3554 reg-names = "membase"; 3555 iommus = <&apps_smmu 0xc0 0x1>; 3556 interrupts = 3557 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3558 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3559 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3560 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3561 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3562 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3563 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3564 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3565 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3566 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3567 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3568 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3569 memory-region = <&wlan_mem>; 3570 qcom,msa-fixed-perm; 3571 status = "disabled"; 3572 }; 3573 3574 lpasscc: clock-controller@62d00000 { 3575 compatible = "qcom,sc7180-lpasscorecc"; 3576 reg = <0 0x62d00000 0 0x50000>, 3577 <0 0x62780000 0 0x30000>; 3578 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3579 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3580 <&rpmhcc RPMH_CXO_CLK>; 3581 clock-names = "iface", "bi_tcxo"; 3582 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3583 #clock-cells = <1>; 3584 #power-domain-cells = <1>; 3585 }; 3586 3587 lpass_cpu: lpass@62d87000 { 3588 compatible = "qcom,sc7180-lpass-cpu"; 3589 3590 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3591 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3592 3593 iommus = <&apps_smmu 0x1020 0>, 3594 <&apps_smmu 0x1021 0>, 3595 <&apps_smmu 0x1032 0>; 3596 3597 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3598 3599 status = "disabled"; 3600 3601 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3602 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3603 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3604 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3605 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3606 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3607 3608 clock-names = "pcnoc-sway-clk", "audio-core", 3609 "mclk0", "pcnoc-mport-clk", 3610 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3611 3612 3613 #sound-dai-cells = <1>; 3614 #address-cells = <1>; 3615 #size-cells = <0>; 3616 3617 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3619 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3620 }; 3621 3622 lpass_hm: clock-controller@63000000 { 3623 compatible = "qcom,sc7180-lpasshm"; 3624 reg = <0 0x63000000 0 0x28>; 3625 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3626 <&rpmhcc RPMH_CXO_CLK>; 3627 clock-names = "iface", "bi_tcxo"; 3628 #clock-cells = <1>; 3629 #power-domain-cells = <1>; 3630 }; 3631 }; 3632 3633 thermal-zones { 3634 cpu0_thermal: cpu0-thermal { 3635 polling-delay-passive = <250>; 3636 polling-delay = <0>; 3637 3638 thermal-sensors = <&tsens0 1>; 3639 sustainable-power = <1052>; 3640 3641 trips { 3642 cpu0_alert0: trip-point0 { 3643 temperature = <90000>; 3644 hysteresis = <2000>; 3645 type = "passive"; 3646 }; 3647 3648 cpu0_alert1: trip-point1 { 3649 temperature = <95000>; 3650 hysteresis = <2000>; 3651 type = "passive"; 3652 }; 3653 3654 cpu0_crit: cpu_crit { 3655 temperature = <110000>; 3656 hysteresis = <1000>; 3657 type = "critical"; 3658 }; 3659 }; 3660 3661 cooling-maps { 3662 map0 { 3663 trip = <&cpu0_alert0>; 3664 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3665 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3666 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3667 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3668 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3669 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3670 }; 3671 map1 { 3672 trip = <&cpu0_alert1>; 3673 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3674 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3675 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3676 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3677 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3678 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3679 }; 3680 }; 3681 }; 3682 3683 cpu1_thermal: cpu1-thermal { 3684 polling-delay-passive = <250>; 3685 polling-delay = <0>; 3686 3687 thermal-sensors = <&tsens0 2>; 3688 sustainable-power = <1052>; 3689 3690 trips { 3691 cpu1_alert0: trip-point0 { 3692 temperature = <90000>; 3693 hysteresis = <2000>; 3694 type = "passive"; 3695 }; 3696 3697 cpu1_alert1: trip-point1 { 3698 temperature = <95000>; 3699 hysteresis = <2000>; 3700 type = "passive"; 3701 }; 3702 3703 cpu1_crit: cpu_crit { 3704 temperature = <110000>; 3705 hysteresis = <1000>; 3706 type = "critical"; 3707 }; 3708 }; 3709 3710 cooling-maps { 3711 map0 { 3712 trip = <&cpu1_alert0>; 3713 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3714 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3715 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3716 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3719 }; 3720 map1 { 3721 trip = <&cpu1_alert1>; 3722 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3723 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3724 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3728 }; 3729 }; 3730 }; 3731 3732 cpu2_thermal: cpu2-thermal { 3733 polling-delay-passive = <250>; 3734 polling-delay = <0>; 3735 3736 thermal-sensors = <&tsens0 3>; 3737 sustainable-power = <1052>; 3738 3739 trips { 3740 cpu2_alert0: trip-point0 { 3741 temperature = <90000>; 3742 hysteresis = <2000>; 3743 type = "passive"; 3744 }; 3745 3746 cpu2_alert1: trip-point1 { 3747 temperature = <95000>; 3748 hysteresis = <2000>; 3749 type = "passive"; 3750 }; 3751 3752 cpu2_crit: cpu_crit { 3753 temperature = <110000>; 3754 hysteresis = <1000>; 3755 type = "critical"; 3756 }; 3757 }; 3758 3759 cooling-maps { 3760 map0 { 3761 trip = <&cpu2_alert0>; 3762 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3764 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3765 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3767 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3768 }; 3769 map1 { 3770 trip = <&cpu2_alert1>; 3771 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3772 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3773 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3774 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3776 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3777 }; 3778 }; 3779 }; 3780 3781 cpu3_thermal: cpu3-thermal { 3782 polling-delay-passive = <250>; 3783 polling-delay = <0>; 3784 3785 thermal-sensors = <&tsens0 4>; 3786 sustainable-power = <1052>; 3787 3788 trips { 3789 cpu3_alert0: trip-point0 { 3790 temperature = <90000>; 3791 hysteresis = <2000>; 3792 type = "passive"; 3793 }; 3794 3795 cpu3_alert1: trip-point1 { 3796 temperature = <95000>; 3797 hysteresis = <2000>; 3798 type = "passive"; 3799 }; 3800 3801 cpu3_crit: cpu_crit { 3802 temperature = <110000>; 3803 hysteresis = <1000>; 3804 type = "critical"; 3805 }; 3806 }; 3807 3808 cooling-maps { 3809 map0 { 3810 trip = <&cpu3_alert0>; 3811 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3812 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3816 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3817 }; 3818 map1 { 3819 trip = <&cpu3_alert1>; 3820 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3821 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3822 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3826 }; 3827 }; 3828 }; 3829 3830 cpu4_thermal: cpu4-thermal { 3831 polling-delay-passive = <250>; 3832 polling-delay = <0>; 3833 3834 thermal-sensors = <&tsens0 5>; 3835 sustainable-power = <1052>; 3836 3837 trips { 3838 cpu4_alert0: trip-point0 { 3839 temperature = <90000>; 3840 hysteresis = <2000>; 3841 type = "passive"; 3842 }; 3843 3844 cpu4_alert1: trip-point1 { 3845 temperature = <95000>; 3846 hysteresis = <2000>; 3847 type = "passive"; 3848 }; 3849 3850 cpu4_crit: cpu_crit { 3851 temperature = <110000>; 3852 hysteresis = <1000>; 3853 type = "critical"; 3854 }; 3855 }; 3856 3857 cooling-maps { 3858 map0 { 3859 trip = <&cpu4_alert0>; 3860 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3862 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3863 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3864 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3865 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3866 }; 3867 map1 { 3868 trip = <&cpu4_alert1>; 3869 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3870 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3875 }; 3876 }; 3877 }; 3878 3879 cpu5_thermal: cpu5-thermal { 3880 polling-delay-passive = <250>; 3881 polling-delay = <0>; 3882 3883 thermal-sensors = <&tsens0 6>; 3884 sustainable-power = <1052>; 3885 3886 trips { 3887 cpu5_alert0: trip-point0 { 3888 temperature = <90000>; 3889 hysteresis = <2000>; 3890 type = "passive"; 3891 }; 3892 3893 cpu5_alert1: trip-point1 { 3894 temperature = <95000>; 3895 hysteresis = <2000>; 3896 type = "passive"; 3897 }; 3898 3899 cpu5_crit: cpu_crit { 3900 temperature = <110000>; 3901 hysteresis = <1000>; 3902 type = "critical"; 3903 }; 3904 }; 3905 3906 cooling-maps { 3907 map0 { 3908 trip = <&cpu5_alert0>; 3909 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3914 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3915 }; 3916 map1 { 3917 trip = <&cpu5_alert1>; 3918 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3919 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3923 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3924 }; 3925 }; 3926 }; 3927 3928 cpu6_thermal: cpu6-thermal { 3929 polling-delay-passive = <250>; 3930 polling-delay = <0>; 3931 3932 thermal-sensors = <&tsens0 9>; 3933 sustainable-power = <1425>; 3934 3935 trips { 3936 cpu6_alert0: trip-point0 { 3937 temperature = <90000>; 3938 hysteresis = <2000>; 3939 type = "passive"; 3940 }; 3941 3942 cpu6_alert1: trip-point1 { 3943 temperature = <95000>; 3944 hysteresis = <2000>; 3945 type = "passive"; 3946 }; 3947 3948 cpu6_crit: cpu_crit { 3949 temperature = <110000>; 3950 hysteresis = <1000>; 3951 type = "critical"; 3952 }; 3953 }; 3954 3955 cooling-maps { 3956 map0 { 3957 trip = <&cpu6_alert0>; 3958 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3959 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3960 }; 3961 map1 { 3962 trip = <&cpu6_alert1>; 3963 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3964 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3965 }; 3966 }; 3967 }; 3968 3969 cpu7_thermal: cpu7-thermal { 3970 polling-delay-passive = <250>; 3971 polling-delay = <0>; 3972 3973 thermal-sensors = <&tsens0 10>; 3974 sustainable-power = <1425>; 3975 3976 trips { 3977 cpu7_alert0: trip-point0 { 3978 temperature = <90000>; 3979 hysteresis = <2000>; 3980 type = "passive"; 3981 }; 3982 3983 cpu7_alert1: trip-point1 { 3984 temperature = <95000>; 3985 hysteresis = <2000>; 3986 type = "passive"; 3987 }; 3988 3989 cpu7_crit: cpu_crit { 3990 temperature = <110000>; 3991 hysteresis = <1000>; 3992 type = "critical"; 3993 }; 3994 }; 3995 3996 cooling-maps { 3997 map0 { 3998 trip = <&cpu7_alert0>; 3999 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4000 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4001 }; 4002 map1 { 4003 trip = <&cpu7_alert1>; 4004 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4005 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4006 }; 4007 }; 4008 }; 4009 4010 cpu8_thermal: cpu8-thermal { 4011 polling-delay-passive = <250>; 4012 polling-delay = <0>; 4013 4014 thermal-sensors = <&tsens0 11>; 4015 sustainable-power = <1425>; 4016 4017 trips { 4018 cpu8_alert0: trip-point0 { 4019 temperature = <90000>; 4020 hysteresis = <2000>; 4021 type = "passive"; 4022 }; 4023 4024 cpu8_alert1: trip-point1 { 4025 temperature = <95000>; 4026 hysteresis = <2000>; 4027 type = "passive"; 4028 }; 4029 4030 cpu8_crit: cpu_crit { 4031 temperature = <110000>; 4032 hysteresis = <1000>; 4033 type = "critical"; 4034 }; 4035 }; 4036 4037 cooling-maps { 4038 map0 { 4039 trip = <&cpu8_alert0>; 4040 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4041 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4042 }; 4043 map1 { 4044 trip = <&cpu8_alert1>; 4045 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4046 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4047 }; 4048 }; 4049 }; 4050 4051 cpu9_thermal: cpu9-thermal { 4052 polling-delay-passive = <250>; 4053 polling-delay = <0>; 4054 4055 thermal-sensors = <&tsens0 12>; 4056 sustainable-power = <1425>; 4057 4058 trips { 4059 cpu9_alert0: trip-point0 { 4060 temperature = <90000>; 4061 hysteresis = <2000>; 4062 type = "passive"; 4063 }; 4064 4065 cpu9_alert1: trip-point1 { 4066 temperature = <95000>; 4067 hysteresis = <2000>; 4068 type = "passive"; 4069 }; 4070 4071 cpu9_crit: cpu_crit { 4072 temperature = <110000>; 4073 hysteresis = <1000>; 4074 type = "critical"; 4075 }; 4076 }; 4077 4078 cooling-maps { 4079 map0 { 4080 trip = <&cpu9_alert0>; 4081 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4082 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4083 }; 4084 map1 { 4085 trip = <&cpu9_alert1>; 4086 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4087 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4088 }; 4089 }; 4090 }; 4091 4092 aoss0-thermal { 4093 polling-delay-passive = <250>; 4094 polling-delay = <0>; 4095 4096 thermal-sensors = <&tsens0 0>; 4097 4098 trips { 4099 aoss0_alert0: trip-point0 { 4100 temperature = <90000>; 4101 hysteresis = <2000>; 4102 type = "hot"; 4103 }; 4104 4105 aoss0_crit: aoss0_crit { 4106 temperature = <110000>; 4107 hysteresis = <2000>; 4108 type = "critical"; 4109 }; 4110 }; 4111 }; 4112 4113 cpuss0-thermal { 4114 polling-delay-passive = <250>; 4115 polling-delay = <0>; 4116 4117 thermal-sensors = <&tsens0 7>; 4118 4119 trips { 4120 cpuss0_alert0: trip-point0 { 4121 temperature = <90000>; 4122 hysteresis = <2000>; 4123 type = "hot"; 4124 }; 4125 cpuss0_crit: cluster0_crit { 4126 temperature = <110000>; 4127 hysteresis = <2000>; 4128 type = "critical"; 4129 }; 4130 }; 4131 }; 4132 4133 cpuss1-thermal { 4134 polling-delay-passive = <250>; 4135 polling-delay = <0>; 4136 4137 thermal-sensors = <&tsens0 8>; 4138 4139 trips { 4140 cpuss1_alert0: trip-point0 { 4141 temperature = <90000>; 4142 hysteresis = <2000>; 4143 type = "hot"; 4144 }; 4145 cpuss1_crit: cluster0_crit { 4146 temperature = <110000>; 4147 hysteresis = <2000>; 4148 type = "critical"; 4149 }; 4150 }; 4151 }; 4152 4153 gpuss0-thermal { 4154 polling-delay-passive = <250>; 4155 polling-delay = <0>; 4156 4157 thermal-sensors = <&tsens0 13>; 4158 4159 trips { 4160 gpuss0_alert0: trip-point0 { 4161 temperature = <95000>; 4162 hysteresis = <2000>; 4163 type = "passive"; 4164 }; 4165 4166 gpuss0_crit: gpuss0_crit { 4167 temperature = <110000>; 4168 hysteresis = <2000>; 4169 type = "critical"; 4170 }; 4171 }; 4172 4173 cooling-maps { 4174 map0 { 4175 trip = <&gpuss0_alert0>; 4176 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4177 }; 4178 }; 4179 }; 4180 4181 gpuss1-thermal { 4182 polling-delay-passive = <250>; 4183 polling-delay = <0>; 4184 4185 thermal-sensors = <&tsens0 14>; 4186 4187 trips { 4188 gpuss1_alert0: trip-point0 { 4189 temperature = <95000>; 4190 hysteresis = <2000>; 4191 type = "passive"; 4192 }; 4193 4194 gpuss1_crit: gpuss1_crit { 4195 temperature = <110000>; 4196 hysteresis = <2000>; 4197 type = "critical"; 4198 }; 4199 }; 4200 4201 cooling-maps { 4202 map0 { 4203 trip = <&gpuss1_alert0>; 4204 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4205 }; 4206 }; 4207 }; 4208 4209 aoss1-thermal { 4210 polling-delay-passive = <250>; 4211 polling-delay = <0>; 4212 4213 thermal-sensors = <&tsens1 0>; 4214 4215 trips { 4216 aoss1_alert0: trip-point0 { 4217 temperature = <90000>; 4218 hysteresis = <2000>; 4219 type = "hot"; 4220 }; 4221 4222 aoss1_crit: aoss1_crit { 4223 temperature = <110000>; 4224 hysteresis = <2000>; 4225 type = "critical"; 4226 }; 4227 }; 4228 }; 4229 4230 cwlan-thermal { 4231 polling-delay-passive = <250>; 4232 polling-delay = <0>; 4233 4234 thermal-sensors = <&tsens1 1>; 4235 4236 trips { 4237 cwlan_alert0: trip-point0 { 4238 temperature = <90000>; 4239 hysteresis = <2000>; 4240 type = "hot"; 4241 }; 4242 4243 cwlan_crit: cwlan_crit { 4244 temperature = <110000>; 4245 hysteresis = <2000>; 4246 type = "critical"; 4247 }; 4248 }; 4249 }; 4250 4251 audio-thermal { 4252 polling-delay-passive = <250>; 4253 polling-delay = <0>; 4254 4255 thermal-sensors = <&tsens1 2>; 4256 4257 trips { 4258 audio_alert0: trip-point0 { 4259 temperature = <90000>; 4260 hysteresis = <2000>; 4261 type = "hot"; 4262 }; 4263 4264 audio_crit: audio_crit { 4265 temperature = <110000>; 4266 hysteresis = <2000>; 4267 type = "critical"; 4268 }; 4269 }; 4270 }; 4271 4272 ddr-thermal { 4273 polling-delay-passive = <250>; 4274 polling-delay = <0>; 4275 4276 thermal-sensors = <&tsens1 3>; 4277 4278 trips { 4279 ddr_alert0: trip-point0 { 4280 temperature = <90000>; 4281 hysteresis = <2000>; 4282 type = "hot"; 4283 }; 4284 4285 ddr_crit: ddr_crit { 4286 temperature = <110000>; 4287 hysteresis = <2000>; 4288 type = "critical"; 4289 }; 4290 }; 4291 }; 4292 4293 q6-hvx-thermal { 4294 polling-delay-passive = <250>; 4295 polling-delay = <0>; 4296 4297 thermal-sensors = <&tsens1 4>; 4298 4299 trips { 4300 q6_hvx_alert0: trip-point0 { 4301 temperature = <90000>; 4302 hysteresis = <2000>; 4303 type = "hot"; 4304 }; 4305 4306 q6_hvx_crit: q6_hvx_crit { 4307 temperature = <110000>; 4308 hysteresis = <2000>; 4309 type = "critical"; 4310 }; 4311 }; 4312 }; 4313 4314 camera-thermal { 4315 polling-delay-passive = <250>; 4316 polling-delay = <0>; 4317 4318 thermal-sensors = <&tsens1 5>; 4319 4320 trips { 4321 camera_alert0: trip-point0 { 4322 temperature = <90000>; 4323 hysteresis = <2000>; 4324 type = "hot"; 4325 }; 4326 4327 camera_crit: camera_crit { 4328 temperature = <110000>; 4329 hysteresis = <2000>; 4330 type = "critical"; 4331 }; 4332 }; 4333 }; 4334 4335 mdm-core-thermal { 4336 polling-delay-passive = <250>; 4337 polling-delay = <0>; 4338 4339 thermal-sensors = <&tsens1 6>; 4340 4341 trips { 4342 mdm_alert0: trip-point0 { 4343 temperature = <90000>; 4344 hysteresis = <2000>; 4345 type = "hot"; 4346 }; 4347 4348 mdm_crit: mdm_crit { 4349 temperature = <110000>; 4350 hysteresis = <2000>; 4351 type = "critical"; 4352 }; 4353 }; 4354 }; 4355 4356 mdm-dsp-thermal { 4357 polling-delay-passive = <250>; 4358 polling-delay = <0>; 4359 4360 thermal-sensors = <&tsens1 7>; 4361 4362 trips { 4363 mdm_dsp_alert0: trip-point0 { 4364 temperature = <90000>; 4365 hysteresis = <2000>; 4366 type = "hot"; 4367 }; 4368 4369 mdm_dsp_crit: mdm_dsp_crit { 4370 temperature = <110000>; 4371 hysteresis = <2000>; 4372 type = "critical"; 4373 }; 4374 }; 4375 }; 4376 4377 npu-thermal { 4378 polling-delay-passive = <250>; 4379 polling-delay = <0>; 4380 4381 thermal-sensors = <&tsens1 8>; 4382 4383 trips { 4384 npu_alert0: trip-point0 { 4385 temperature = <90000>; 4386 hysteresis = <2000>; 4387 type = "hot"; 4388 }; 4389 4390 npu_crit: npu_crit { 4391 temperature = <110000>; 4392 hysteresis = <2000>; 4393 type = "critical"; 4394 }; 4395 }; 4396 }; 4397 4398 video-thermal { 4399 polling-delay-passive = <250>; 4400 polling-delay = <0>; 4401 4402 thermal-sensors = <&tsens1 9>; 4403 4404 trips { 4405 video_alert0: trip-point0 { 4406 temperature = <90000>; 4407 hysteresis = <2000>; 4408 type = "hot"; 4409 }; 4410 4411 video_crit: video_crit { 4412 temperature = <110000>; 4413 hysteresis = <2000>; 4414 type = "critical"; 4415 }; 4416 }; 4417 }; 4418 }; 4419 4420 timer { 4421 compatible = "arm,armv8-timer"; 4422 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4423 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4424 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4425 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4426 }; 4427}; 4428