1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-aoss-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi3 = &spi3; 49 spi5 = &spi5; 50 spi6 = &spi6; 51 spi8 = &spi8; 52 spi10 = &spi10; 53 spi11 = &spi11; 54 }; 55 56 clocks { 57 xo_board: xo-board { 58 compatible = "fixed-clock"; 59 clock-frequency = <38400000>; 60 #clock-cells = <0>; 61 }; 62 63 sleep_clk: sleep-clk { 64 compatible = "fixed-clock"; 65 clock-frequency = <32764>; 66 #clock-cells = <0>; 67 }; 68 }; 69 70 reserved_memory: reserved-memory { 71 #address-cells = <2>; 72 #size-cells = <2>; 73 ranges; 74 75 hyp_mem: memory@80000000 { 76 reg = <0x0 0x80000000 0x0 0x600000>; 77 no-map; 78 }; 79 80 xbl_mem: memory@80600000 { 81 reg = <0x0 0x80600000 0x0 0x200000>; 82 no-map; 83 }; 84 85 aop_mem: memory@80800000 { 86 reg = <0x0 0x80800000 0x0 0x20000>; 87 no-map; 88 }; 89 90 aop_cmd_db_mem: memory@80820000 { 91 reg = <0x0 0x80820000 0x0 0x20000>; 92 compatible = "qcom,cmd-db"; 93 no-map; 94 }; 95 96 sec_apps_mem: memory@808ff000 { 97 reg = <0x0 0x808ff000 0x0 0x1000>; 98 no-map; 99 }; 100 101 smem_mem: memory@80900000 { 102 reg = <0x0 0x80900000 0x0 0x200000>; 103 no-map; 104 }; 105 106 tz_mem: memory@80b00000 { 107 reg = <0x0 0x80b00000 0x0 0x3900000>; 108 no-map; 109 }; 110 111 rmtfs_mem: memory@84400000 { 112 compatible = "qcom,rmtfs-mem"; 113 reg = <0x0 0x84400000 0x0 0x200000>; 114 no-map; 115 116 qcom,client-id = <1>; 117 qcom,vmid = <15>; 118 }; 119 }; 120 121 cpus { 122 #address-cells = <2>; 123 #size-cells = <0>; 124 125 CPU0: cpu@0 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo468"; 128 reg = <0x0 0x0>; 129 enable-method = "psci"; 130 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 131 &LITTLE_CPU_SLEEP_1 132 &CLUSTER_SLEEP_0>; 133 capacity-dmips-mhz = <1024>; 134 dynamic-power-coefficient = <100>; 135 operating-points-v2 = <&cpu0_opp_table>; 136 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 137 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 138 next-level-cache = <&L2_0>; 139 #cooling-cells = <2>; 140 qcom,freq-domain = <&cpufreq_hw 0>; 141 L2_0: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_0>; 144 L3_0: l3-cache { 145 compatible = "cache"; 146 }; 147 }; 148 }; 149 150 CPU1: cpu@100 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo468"; 153 reg = <0x0 0x100>; 154 enable-method = "psci"; 155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 156 &LITTLE_CPU_SLEEP_1 157 &CLUSTER_SLEEP_0>; 158 capacity-dmips-mhz = <1024>; 159 dynamic-power-coefficient = <100>; 160 next-level-cache = <&L2_100>; 161 operating-points-v2 = <&cpu0_opp_table>; 162 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 163 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 164 #cooling-cells = <2>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 L2_100: l2-cache { 167 compatible = "cache"; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU2: cpu@200 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo468"; 175 reg = <0x0 0x200>; 176 enable-method = "psci"; 177 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 178 &LITTLE_CPU_SLEEP_1 179 &CLUSTER_SLEEP_0>; 180 capacity-dmips-mhz = <1024>; 181 dynamic-power-coefficient = <100>; 182 next-level-cache = <&L2_200>; 183 operating-points-v2 = <&cpu0_opp_table>; 184 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 185 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 186 #cooling-cells = <2>; 187 qcom,freq-domain = <&cpufreq_hw 0>; 188 L2_200: l2-cache { 189 compatible = "cache"; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU3: cpu@300 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo468"; 197 reg = <0x0 0x300>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <100>; 204 next-level-cache = <&L2_300>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 #cooling-cells = <2>; 209 qcom,freq-domain = <&cpufreq_hw 0>; 210 L2_300: l2-cache { 211 compatible = "cache"; 212 next-level-cache = <&L3_0>; 213 }; 214 }; 215 216 CPU4: cpu@400 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo468"; 219 reg = <0x0 0x400>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 capacity-dmips-mhz = <1024>; 225 dynamic-power-coefficient = <100>; 226 next-level-cache = <&L2_400>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 #cooling-cells = <2>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 L2_400: l2-cache { 233 compatible = "cache"; 234 next-level-cache = <&L3_0>; 235 }; 236 }; 237 238 CPU5: cpu@500 { 239 device_type = "cpu"; 240 compatible = "qcom,kryo468"; 241 reg = <0x0 0x500>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 capacity-dmips-mhz = <1024>; 247 dynamic-power-coefficient = <100>; 248 next-level-cache = <&L2_500>; 249 operating-points-v2 = <&cpu0_opp_table>; 250 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 252 #cooling-cells = <2>; 253 qcom,freq-domain = <&cpufreq_hw 0>; 254 L2_500: l2-cache { 255 compatible = "cache"; 256 next-level-cache = <&L3_0>; 257 }; 258 }; 259 260 CPU6: cpu@600 { 261 device_type = "cpu"; 262 compatible = "qcom,kryo468"; 263 reg = <0x0 0x600>; 264 enable-method = "psci"; 265 cpu-idle-states = <&BIG_CPU_SLEEP_0 266 &BIG_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 capacity-dmips-mhz = <1740>; 269 dynamic-power-coefficient = <405>; 270 next-level-cache = <&L2_600>; 271 operating-points-v2 = <&cpu6_opp_table>; 272 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 274 #cooling-cells = <2>; 275 qcom,freq-domain = <&cpufreq_hw 1>; 276 L2_600: l2-cache { 277 compatible = "cache"; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 CPU7: cpu@700 { 283 device_type = "cpu"; 284 compatible = "qcom,kryo468"; 285 reg = <0x0 0x700>; 286 enable-method = "psci"; 287 cpu-idle-states = <&BIG_CPU_SLEEP_0 288 &BIG_CPU_SLEEP_1 289 &CLUSTER_SLEEP_0>; 290 capacity-dmips-mhz = <1740>; 291 dynamic-power-coefficient = <405>; 292 next-level-cache = <&L2_700>; 293 operating-points-v2 = <&cpu6_opp_table>; 294 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 296 #cooling-cells = <2>; 297 qcom,freq-domain = <&cpufreq_hw 1>; 298 L2_700: l2-cache { 299 compatible = "cache"; 300 next-level-cache = <&L3_0>; 301 }; 302 }; 303 304 cpu-map { 305 cluster0 { 306 core0 { 307 cpu = <&CPU0>; 308 }; 309 310 core1 { 311 cpu = <&CPU1>; 312 }; 313 314 core2 { 315 cpu = <&CPU2>; 316 }; 317 318 core3 { 319 cpu = <&CPU3>; 320 }; 321 322 core4 { 323 cpu = <&CPU4>; 324 }; 325 326 core5 { 327 cpu = <&CPU5>; 328 }; 329 330 core6 { 331 cpu = <&CPU6>; 332 }; 333 334 core7 { 335 cpu = <&CPU7>; 336 }; 337 }; 338 }; 339 340 idle-states { 341 entry-method = "psci"; 342 343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 344 compatible = "arm,idle-state"; 345 idle-state-name = "little-power-down"; 346 arm,psci-suspend-param = <0x40000003>; 347 entry-latency-us = <549>; 348 exit-latency-us = <901>; 349 min-residency-us = <1774>; 350 local-timer-stop; 351 }; 352 353 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 354 compatible = "arm,idle-state"; 355 idle-state-name = "little-rail-power-down"; 356 arm,psci-suspend-param = <0x40000004>; 357 entry-latency-us = <702>; 358 exit-latency-us = <915>; 359 min-residency-us = <4001>; 360 local-timer-stop; 361 }; 362 363 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 364 compatible = "arm,idle-state"; 365 idle-state-name = "big-power-down"; 366 arm,psci-suspend-param = <0x40000003>; 367 entry-latency-us = <523>; 368 exit-latency-us = <1244>; 369 min-residency-us = <2207>; 370 local-timer-stop; 371 }; 372 373 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 374 compatible = "arm,idle-state"; 375 idle-state-name = "big-rail-power-down"; 376 arm,psci-suspend-param = <0x40000004>; 377 entry-latency-us = <526>; 378 exit-latency-us = <1854>; 379 min-residency-us = <5555>; 380 local-timer-stop; 381 }; 382 383 CLUSTER_SLEEP_0: cluster-sleep-0 { 384 compatible = "arm,idle-state"; 385 idle-state-name = "cluster-power-down"; 386 arm,psci-suspend-param = <0x40003444>; 387 entry-latency-us = <3263>; 388 exit-latency-us = <6562>; 389 min-residency-us = <9926>; 390 local-timer-stop; 391 }; 392 }; 393 }; 394 395 cpu0_opp_table: cpu0_opp_table { 396 compatible = "operating-points-v2"; 397 opp-shared; 398 399 cpu0_opp1: opp-300000000 { 400 opp-hz = /bits/ 64 <300000000>; 401 opp-peak-kBps = <1200000 4800000>; 402 }; 403 404 cpu0_opp2: opp-576000000 { 405 opp-hz = /bits/ 64 <576000000>; 406 opp-peak-kBps = <1200000 4800000>; 407 }; 408 409 cpu0_opp3: opp-768000000 { 410 opp-hz = /bits/ 64 <768000000>; 411 opp-peak-kBps = <1200000 4800000>; 412 }; 413 414 cpu0_opp4: opp-1017600000 { 415 opp-hz = /bits/ 64 <1017600000>; 416 opp-peak-kBps = <1804000 8908800>; 417 }; 418 419 cpu0_opp5: opp-1248000000 { 420 opp-hz = /bits/ 64 <1248000000>; 421 opp-peak-kBps = <2188000 12902400>; 422 }; 423 424 cpu0_opp6: opp-1324800000 { 425 opp-hz = /bits/ 64 <1324800000>; 426 opp-peak-kBps = <2188000 12902400>; 427 }; 428 429 cpu0_opp7: opp-1516800000 { 430 opp-hz = /bits/ 64 <1516800000>; 431 opp-peak-kBps = <3072000 15052800>; 432 }; 433 434 cpu0_opp8: opp-1612800000 { 435 opp-hz = /bits/ 64 <1612800000>; 436 opp-peak-kBps = <3072000 15052800>; 437 }; 438 439 cpu0_opp9: opp-1708800000 { 440 opp-hz = /bits/ 64 <1708800000>; 441 opp-peak-kBps = <3072000 15052800>; 442 }; 443 444 cpu0_opp10: opp-1804800000 { 445 opp-hz = /bits/ 64 <1804800000>; 446 opp-peak-kBps = <4068000 22425600>; 447 }; 448 }; 449 450 cpu6_opp_table: cpu6_opp_table { 451 compatible = "operating-points-v2"; 452 opp-shared; 453 454 cpu6_opp1: opp-300000000 { 455 opp-hz = /bits/ 64 <300000000>; 456 opp-peak-kBps = <2188000 8908800>; 457 }; 458 459 cpu6_opp2: opp-652800000 { 460 opp-hz = /bits/ 64 <652800000>; 461 opp-peak-kBps = <2188000 8908800>; 462 }; 463 464 cpu6_opp3: opp-825600000 { 465 opp-hz = /bits/ 64 <825600000>; 466 opp-peak-kBps = <2188000 8908800>; 467 }; 468 469 cpu6_opp4: opp-979200000 { 470 opp-hz = /bits/ 64 <979200000>; 471 opp-peak-kBps = <2188000 8908800>; 472 }; 473 474 cpu6_opp5: opp-1113600000 { 475 opp-hz = /bits/ 64 <1113600000>; 476 opp-peak-kBps = <2188000 8908800>; 477 }; 478 479 cpu6_opp6: opp-1267200000 { 480 opp-hz = /bits/ 64 <1267200000>; 481 opp-peak-kBps = <4068000 12902400>; 482 }; 483 484 cpu6_opp7: opp-1555200000 { 485 opp-hz = /bits/ 64 <1555200000>; 486 opp-peak-kBps = <4068000 15052800>; 487 }; 488 489 cpu6_opp8: opp-1708800000 { 490 opp-hz = /bits/ 64 <1708800000>; 491 opp-peak-kBps = <6220000 19353600>; 492 }; 493 494 cpu6_opp9: opp-1843200000 { 495 opp-hz = /bits/ 64 <1843200000>; 496 opp-peak-kBps = <6220000 19353600>; 497 }; 498 499 cpu6_opp10: opp-1900800000 { 500 opp-hz = /bits/ 64 <1900800000>; 501 opp-peak-kBps = <6220000 22425600>; 502 }; 503 504 cpu6_opp11: opp-1996800000 { 505 opp-hz = /bits/ 64 <1996800000>; 506 opp-peak-kBps = <6220000 22425600>; 507 }; 508 509 cpu6_opp12: opp-2112000000 { 510 opp-hz = /bits/ 64 <2112000000>; 511 opp-peak-kBps = <6220000 22425600>; 512 }; 513 514 cpu6_opp13: opp-2208000000 { 515 opp-hz = /bits/ 64 <2208000000>; 516 opp-peak-kBps = <7216000 22425600>; 517 }; 518 519 cpu6_opp14: opp-2323200000 { 520 opp-hz = /bits/ 64 <2323200000>; 521 opp-peak-kBps = <7216000 22425600>; 522 }; 523 524 cpu6_opp15: opp-2400000000 { 525 opp-hz = /bits/ 64 <2400000000>; 526 opp-peak-kBps = <8532000 23347200>; 527 }; 528 }; 529 530 memory@80000000 { 531 device_type = "memory"; 532 /* We expect the bootloader to fill in the size */ 533 reg = <0 0x80000000 0 0>; 534 }; 535 536 pmu { 537 compatible = "arm,armv8-pmuv3"; 538 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 539 }; 540 541 firmware { 542 scm { 543 compatible = "qcom,scm-sc7180", "qcom,scm"; 544 }; 545 }; 546 547 tcsr_mutex: hwlock { 548 compatible = "qcom,tcsr-mutex"; 549 syscon = <&tcsr_mutex_regs 0 0x1000>; 550 #hwlock-cells = <1>; 551 }; 552 553 smem { 554 compatible = "qcom,smem"; 555 memory-region = <&smem_mem>; 556 hwlocks = <&tcsr_mutex 3>; 557 }; 558 559 smp2p-cdsp { 560 compatible = "qcom,smp2p"; 561 qcom,smem = <94>, <432>; 562 563 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 564 565 mboxes = <&apss_shared 6>; 566 567 qcom,local-pid = <0>; 568 qcom,remote-pid = <5>; 569 570 cdsp_smp2p_out: master-kernel { 571 qcom,entry-name = "master-kernel"; 572 #qcom,smem-state-cells = <1>; 573 }; 574 575 cdsp_smp2p_in: slave-kernel { 576 qcom,entry-name = "slave-kernel"; 577 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 }; 581 }; 582 583 smp2p-lpass { 584 compatible = "qcom,smp2p"; 585 qcom,smem = <443>, <429>; 586 587 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 588 589 mboxes = <&apss_shared 10>; 590 591 qcom,local-pid = <0>; 592 qcom,remote-pid = <2>; 593 594 adsp_smp2p_out: master-kernel { 595 qcom,entry-name = "master-kernel"; 596 #qcom,smem-state-cells = <1>; 597 }; 598 599 adsp_smp2p_in: slave-kernel { 600 qcom,entry-name = "slave-kernel"; 601 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 }; 606 607 smp2p-mpss { 608 compatible = "qcom,smp2p"; 609 qcom,smem = <435>, <428>; 610 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 611 mboxes = <&apss_shared 14>; 612 qcom,local-pid = <0>; 613 qcom,remote-pid = <1>; 614 615 modem_smp2p_out: master-kernel { 616 qcom,entry-name = "master-kernel"; 617 #qcom,smem-state-cells = <1>; 618 }; 619 620 modem_smp2p_in: slave-kernel { 621 qcom,entry-name = "slave-kernel"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 626 ipa_smp2p_out: ipa-ap-to-modem { 627 qcom,entry-name = "ipa"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 ipa_smp2p_in: ipa-modem-to-ap { 632 qcom,entry-name = "ipa"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 }; 637 638 psci { 639 compatible = "arm,psci-1.0"; 640 method = "smc"; 641 }; 642 643 soc: soc@0 { 644 #address-cells = <2>; 645 #size-cells = <2>; 646 ranges = <0 0 0 0 0x10 0>; 647 dma-ranges = <0 0 0 0 0x10 0>; 648 compatible = "simple-bus"; 649 650 gcc: clock-controller@100000 { 651 compatible = "qcom,gcc-sc7180"; 652 reg = <0 0x00100000 0 0x1f0000>; 653 clocks = <&rpmhcc RPMH_CXO_CLK>, 654 <&rpmhcc RPMH_CXO_CLK_A>, 655 <&sleep_clk>; 656 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 657 #clock-cells = <1>; 658 #reset-cells = <1>; 659 #power-domain-cells = <1>; 660 }; 661 662 qfprom: efuse@784000 { 663 compatible = "qcom,qfprom"; 664 reg = <0 0x00784000 0 0x8ff>, 665 <0 0x00780000 0 0x7a0>, 666 <0 0x00782000 0 0x100>, 667 <0 0x00786000 0 0x1fff>; 668 669 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 670 clock-names = "core"; 671 #address-cells = <1>; 672 #size-cells = <1>; 673 674 qusb2p_hstx_trim: hstx-trim-primary@25b { 675 reg = <0x25b 0x1>; 676 bits = <1 3>; 677 }; 678 }; 679 680 sdhc_1: sdhci@7c4000 { 681 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 682 reg = <0 0x7c4000 0 0x1000>, 683 <0 0x07c5000 0 0x1000>; 684 reg-names = "hc", "cqhci"; 685 686 iommus = <&apps_smmu 0x60 0x0>; 687 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 689 interrupt-names = "hc_irq", "pwr_irq"; 690 691 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 692 <&gcc GCC_SDCC1_AHB_CLK>; 693 clock-names = "core", "iface"; 694 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 695 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 696 interconnect-names = "sdhc-ddr","cpu-sdhc"; 697 power-domains = <&rpmhpd SC7180_CX>; 698 operating-points-v2 = <&sdhc1_opp_table>; 699 700 bus-width = <8>; 701 non-removable; 702 supports-cqe; 703 704 mmc-ddr-1_8v; 705 mmc-hs200-1_8v; 706 mmc-hs400-1_8v; 707 mmc-hs400-enhanced-strobe; 708 709 status = "disabled"; 710 711 sdhc1_opp_table: sdhc1-opp-table { 712 compatible = "operating-points-v2"; 713 714 opp-100000000 { 715 opp-hz = /bits/ 64 <100000000>; 716 required-opps = <&rpmhpd_opp_low_svs>; 717 opp-peak-kBps = <100000 100000>; 718 opp-avg-kBps = <100000 50000>; 719 }; 720 721 opp-384000000 { 722 opp-hz = /bits/ 64 <384000000>; 723 required-opps = <&rpmhpd_opp_svs_l1>; 724 opp-peak-kBps = <600000 900000>; 725 opp-avg-kBps = <261438 300000>; 726 }; 727 }; 728 }; 729 730 qup_opp_table: qup-opp-table { 731 compatible = "operating-points-v2"; 732 733 opp-75000000 { 734 opp-hz = /bits/ 64 <75000000>; 735 required-opps = <&rpmhpd_opp_low_svs>; 736 }; 737 738 opp-100000000 { 739 opp-hz = /bits/ 64 <100000000>; 740 required-opps = <&rpmhpd_opp_svs>; 741 }; 742 743 opp-128000000 { 744 opp-hz = /bits/ 64 <128000000>; 745 required-opps = <&rpmhpd_opp_nom>; 746 }; 747 }; 748 749 qupv3_id_0: geniqup@8c0000 { 750 compatible = "qcom,geni-se-qup"; 751 reg = <0 0x008c0000 0 0x6000>; 752 clock-names = "m-ahb", "s-ahb"; 753 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 754 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 755 #address-cells = <2>; 756 #size-cells = <2>; 757 ranges; 758 iommus = <&apps_smmu 0x43 0x0>; 759 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; 760 interconnect-names = "qup-core"; 761 status = "disabled"; 762 763 i2c0: i2c@880000 { 764 compatible = "qcom,geni-i2c"; 765 reg = <0 0x00880000 0 0x4000>; 766 clock-names = "se"; 767 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&qup_i2c0_default>; 770 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 774 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 775 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 776 interconnect-names = "qup-core", "qup-config", 777 "qup-memory"; 778 status = "disabled"; 779 }; 780 781 spi0: spi@880000 { 782 compatible = "qcom,geni-spi"; 783 reg = <0 0x00880000 0 0x4000>; 784 clock-names = "se"; 785 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&qup_spi0_default>; 788 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 power-domains = <&rpmhpd SC7180_CX>; 792 operating-points-v2 = <&qup_opp_table>; 793 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 794 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 795 interconnect-names = "qup-core", "qup-config"; 796 status = "disabled"; 797 }; 798 799 uart0: serial@880000 { 800 compatible = "qcom,geni-uart"; 801 reg = <0 0x00880000 0 0x4000>; 802 clock-names = "se"; 803 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&qup_uart0_default>; 806 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 807 power-domains = <&rpmhpd SC7180_CX>; 808 operating-points-v2 = <&qup_opp_table>; 809 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 810 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 811 interconnect-names = "qup-core", "qup-config"; 812 status = "disabled"; 813 }; 814 815 i2c1: i2c@884000 { 816 compatible = "qcom,geni-i2c"; 817 reg = <0 0x00884000 0 0x4000>; 818 clock-names = "se"; 819 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&qup_i2c1_default>; 822 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 826 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 827 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 828 interconnect-names = "qup-core", "qup-config", 829 "qup-memory"; 830 status = "disabled"; 831 }; 832 833 spi1: spi@884000 { 834 compatible = "qcom,geni-spi"; 835 reg = <0 0x00884000 0 0x4000>; 836 clock-names = "se"; 837 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&qup_spi1_default>; 840 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 power-domains = <&rpmhpd SC7180_CX>; 844 operating-points-v2 = <&qup_opp_table>; 845 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 846 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 847 interconnect-names = "qup-core", "qup-config"; 848 status = "disabled"; 849 }; 850 851 uart1: serial@884000 { 852 compatible = "qcom,geni-uart"; 853 reg = <0 0x00884000 0 0x4000>; 854 clock-names = "se"; 855 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&qup_uart1_default>; 858 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 859 power-domains = <&rpmhpd SC7180_CX>; 860 operating-points-v2 = <&qup_opp_table>; 861 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 862 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 863 interconnect-names = "qup-core", "qup-config"; 864 status = "disabled"; 865 }; 866 867 i2c2: i2c@888000 { 868 compatible = "qcom,geni-i2c"; 869 reg = <0 0x00888000 0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&qup_i2c2_default>; 874 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 879 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 880 interconnect-names = "qup-core", "qup-config", 881 "qup-memory"; 882 status = "disabled"; 883 }; 884 885 uart2: serial@888000 { 886 compatible = "qcom,geni-uart"; 887 reg = <0 0x00888000 0 0x4000>; 888 clock-names = "se"; 889 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&qup_uart2_default>; 892 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 893 power-domains = <&rpmhpd SC7180_CX>; 894 operating-points-v2 = <&qup_opp_table>; 895 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 897 interconnect-names = "qup-core", "qup-config"; 898 status = "disabled"; 899 }; 900 901 i2c3: i2c@88c000 { 902 compatible = "qcom,geni-i2c"; 903 reg = <0 0x0088c000 0 0x4000>; 904 clock-names = "se"; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_i2c3_default>; 908 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 913 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 914 interconnect-names = "qup-core", "qup-config", 915 "qup-memory"; 916 status = "disabled"; 917 }; 918 919 spi3: spi@88c000 { 920 compatible = "qcom,geni-spi"; 921 reg = <0 0x0088c000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&qup_spi3_default>; 926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 power-domains = <&rpmhpd SC7180_CX>; 930 operating-points-v2 = <&qup_opp_table>; 931 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 932 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 933 interconnect-names = "qup-core", "qup-config"; 934 status = "disabled"; 935 }; 936 937 uart3: serial@88c000 { 938 compatible = "qcom,geni-uart"; 939 reg = <0 0x0088c000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_uart3_default>; 944 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 945 power-domains = <&rpmhpd SC7180_CX>; 946 operating-points-v2 = <&qup_opp_table>; 947 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 948 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 949 interconnect-names = "qup-core", "qup-config"; 950 status = "disabled"; 951 }; 952 953 i2c4: i2c@890000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0 0x00890000 0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_i2c4_default>; 960 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 964 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 965 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", 967 "qup-memory"; 968 status = "disabled"; 969 }; 970 971 uart4: serial@890000 { 972 compatible = "qcom,geni-uart"; 973 reg = <0 0x00890000 0 0x4000>; 974 clock-names = "se"; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_uart4_default>; 978 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 979 power-domains = <&rpmhpd SC7180_CX>; 980 operating-points-v2 = <&qup_opp_table>; 981 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 983 interconnect-names = "qup-core", "qup-config"; 984 status = "disabled"; 985 }; 986 987 i2c5: i2c@894000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00894000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c5_default>; 994 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 999 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1000 interconnect-names = "qup-core", "qup-config", 1001 "qup-memory"; 1002 status = "disabled"; 1003 }; 1004 1005 spi5: spi@894000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x00894000 0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_spi5_default>; 1012 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 power-domains = <&rpmhpd SC7180_CX>; 1016 operating-points-v2 = <&qup_opp_table>; 1017 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1018 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1019 interconnect-names = "qup-core", "qup-config"; 1020 status = "disabled"; 1021 }; 1022 1023 uart5: serial@894000 { 1024 compatible = "qcom,geni-uart"; 1025 reg = <0 0x00894000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_uart5_default>; 1030 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1031 power-domains = <&rpmhpd SC7180_CX>; 1032 operating-points-v2 = <&qup_opp_table>; 1033 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1034 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1035 interconnect-names = "qup-core", "qup-config"; 1036 status = "disabled"; 1037 }; 1038 }; 1039 1040 qupv3_id_1: geniqup@ac0000 { 1041 compatible = "qcom,geni-se-qup"; 1042 reg = <0 0x00ac0000 0 0x6000>; 1043 clock-names = "m-ahb", "s-ahb"; 1044 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1045 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1046 #address-cells = <2>; 1047 #size-cells = <2>; 1048 ranges; 1049 iommus = <&apps_smmu 0x4c3 0x0>; 1050 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; 1051 interconnect-names = "qup-core"; 1052 status = "disabled"; 1053 1054 i2c6: i2c@a80000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00a80000 0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_i2c6_default>; 1061 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1065 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1066 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1067 interconnect-names = "qup-core", "qup-config", 1068 "qup-memory"; 1069 status = "disabled"; 1070 }; 1071 1072 spi6: spi@a80000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00a80000 0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_spi6_default>; 1079 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 power-domains = <&rpmhpd SC7180_CX>; 1083 operating-points-v2 = <&qup_opp_table>; 1084 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1086 interconnect-names = "qup-core", "qup-config"; 1087 status = "disabled"; 1088 }; 1089 1090 uart6: serial@a80000 { 1091 compatible = "qcom,geni-uart"; 1092 reg = <0 0x00a80000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_uart6_default>; 1097 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1098 power-domains = <&rpmhpd SC7180_CX>; 1099 operating-points-v2 = <&qup_opp_table>; 1100 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1101 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1102 interconnect-names = "qup-core", "qup-config"; 1103 status = "disabled"; 1104 }; 1105 1106 i2c7: i2c@a84000 { 1107 compatible = "qcom,geni-i2c"; 1108 reg = <0 0x00a84000 0 0x4000>; 1109 clock-names = "se"; 1110 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&qup_i2c7_default>; 1113 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1117 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1118 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1119 interconnect-names = "qup-core", "qup-config", 1120 "qup-memory"; 1121 status = "disabled"; 1122 }; 1123 1124 uart7: serial@a84000 { 1125 compatible = "qcom,geni-uart"; 1126 reg = <0 0x00a84000 0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_uart7_default>; 1131 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1132 power-domains = <&rpmhpd SC7180_CX>; 1133 operating-points-v2 = <&qup_opp_table>; 1134 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1136 interconnect-names = "qup-core", "qup-config"; 1137 status = "disabled"; 1138 }; 1139 1140 i2c8: i2c@a88000 { 1141 compatible = "qcom,geni-i2c"; 1142 reg = <0 0x00a88000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_i2c8_default>; 1147 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1151 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1152 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1153 interconnect-names = "qup-core", "qup-config", 1154 "qup-memory"; 1155 status = "disabled"; 1156 }; 1157 1158 spi8: spi@a88000 { 1159 compatible = "qcom,geni-spi"; 1160 reg = <0 0x00a88000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_spi8_default>; 1165 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 power-domains = <&rpmhpd SC7180_CX>; 1169 operating-points-v2 = <&qup_opp_table>; 1170 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1171 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1172 interconnect-names = "qup-core", "qup-config"; 1173 status = "disabled"; 1174 }; 1175 1176 uart8: serial@a88000 { 1177 compatible = "qcom,geni-debug-uart"; 1178 reg = <0 0x00a88000 0 0x4000>; 1179 clock-names = "se"; 1180 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&qup_uart8_default>; 1183 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1184 power-domains = <&rpmhpd SC7180_CX>; 1185 operating-points-v2 = <&qup_opp_table>; 1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1188 interconnect-names = "qup-core", "qup-config"; 1189 status = "disabled"; 1190 }; 1191 1192 i2c9: i2c@a8c000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x00a8c000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_i2c9_default>; 1199 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1204 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1205 interconnect-names = "qup-core", "qup-config", 1206 "qup-memory"; 1207 status = "disabled"; 1208 }; 1209 1210 uart9: serial@a8c000 { 1211 compatible = "qcom,geni-uart"; 1212 reg = <0 0x00a8c000 0 0x4000>; 1213 clock-names = "se"; 1214 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_uart9_default>; 1217 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1218 power-domains = <&rpmhpd SC7180_CX>; 1219 operating-points-v2 = <&qup_opp_table>; 1220 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 i2c10: i2c@a90000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0 0x00a90000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_i2c10_default>; 1233 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1238 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1239 interconnect-names = "qup-core", "qup-config", 1240 "qup-memory"; 1241 status = "disabled"; 1242 }; 1243 1244 spi10: spi@a90000 { 1245 compatible = "qcom,geni-spi"; 1246 reg = <0 0x00a90000 0 0x4000>; 1247 clock-names = "se"; 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_spi10_default>; 1251 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 power-domains = <&rpmhpd SC7180_CX>; 1255 operating-points-v2 = <&qup_opp_table>; 1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1257 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1258 interconnect-names = "qup-core", "qup-config"; 1259 status = "disabled"; 1260 }; 1261 1262 uart10: serial@a90000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0 0x00a90000 0 0x4000>; 1265 clock-names = "se"; 1266 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_uart10_default>; 1269 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1270 power-domains = <&rpmhpd SC7180_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 i2c11: i2c@a94000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0 0x00a94000 0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c11_default>; 1285 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1290 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", 1292 "qup-memory"; 1293 status = "disabled"; 1294 }; 1295 1296 spi11: spi@a94000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0 0x00a94000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_spi11_default>; 1303 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 power-domains = <&rpmhpd SC7180_CX>; 1307 operating-points-v2 = <&qup_opp_table>; 1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1309 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1310 interconnect-names = "qup-core", "qup-config"; 1311 status = "disabled"; 1312 }; 1313 1314 uart11: serial@a94000 { 1315 compatible = "qcom,geni-uart"; 1316 reg = <0 0x00a94000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_uart11_default>; 1321 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1322 power-domains = <&rpmhpd SC7180_CX>; 1323 operating-points-v2 = <&qup_opp_table>; 1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1326 interconnect-names = "qup-core", "qup-config"; 1327 status = "disabled"; 1328 }; 1329 }; 1330 1331 config_noc: interconnect@1500000 { 1332 compatible = "qcom,sc7180-config-noc"; 1333 reg = <0 0x01500000 0 0x28000>; 1334 #interconnect-cells = <2>; 1335 qcom,bcm-voters = <&apps_bcm_voter>; 1336 }; 1337 1338 system_noc: interconnect@1620000 { 1339 compatible = "qcom,sc7180-system-noc"; 1340 reg = <0 0x01620000 0 0x17080>; 1341 #interconnect-cells = <2>; 1342 qcom,bcm-voters = <&apps_bcm_voter>; 1343 }; 1344 1345 mc_virt: interconnect@1638000 { 1346 compatible = "qcom,sc7180-mc-virt"; 1347 reg = <0 0x01638000 0 0x1000>; 1348 #interconnect-cells = <2>; 1349 qcom,bcm-voters = <&apps_bcm_voter>; 1350 }; 1351 1352 qup_virt: interconnect@1650000 { 1353 compatible = "qcom,sc7180-qup-virt"; 1354 reg = <0 0x01650000 0 0x1000>; 1355 #interconnect-cells = <2>; 1356 qcom,bcm-voters = <&apps_bcm_voter>; 1357 }; 1358 1359 aggre1_noc: interconnect@16e0000 { 1360 compatible = "qcom,sc7180-aggre1-noc"; 1361 reg = <0 0x016e0000 0 0x15080>; 1362 #interconnect-cells = <2>; 1363 qcom,bcm-voters = <&apps_bcm_voter>; 1364 }; 1365 1366 aggre2_noc: interconnect@1705000 { 1367 compatible = "qcom,sc7180-aggre2-noc"; 1368 reg = <0 0x01705000 0 0x9000>; 1369 #interconnect-cells = <2>; 1370 qcom,bcm-voters = <&apps_bcm_voter>; 1371 }; 1372 1373 compute_noc: interconnect@170e000 { 1374 compatible = "qcom,sc7180-compute-noc"; 1375 reg = <0 0x0170e000 0 0x6000>; 1376 #interconnect-cells = <2>; 1377 qcom,bcm-voters = <&apps_bcm_voter>; 1378 }; 1379 1380 mmss_noc: interconnect@1740000 { 1381 compatible = "qcom,sc7180-mmss-noc"; 1382 reg = <0 0x01740000 0 0x1c100>; 1383 #interconnect-cells = <2>; 1384 qcom,bcm-voters = <&apps_bcm_voter>; 1385 }; 1386 1387 ipa_virt: interconnect@1e00000 { 1388 compatible = "qcom,sc7180-ipa-virt"; 1389 reg = <0 0x01e00000 0 0x1000>; 1390 #interconnect-cells = <2>; 1391 qcom,bcm-voters = <&apps_bcm_voter>; 1392 }; 1393 1394 ipa: ipa@1e40000 { 1395 compatible = "qcom,sc7180-ipa"; 1396 1397 iommus = <&apps_smmu 0x440 0x3>; 1398 reg = <0 0x1e40000 0 0x7000>, 1399 <0 0x1e47000 0 0x2000>, 1400 <0 0x1e04000 0 0x2c000>; 1401 reg-names = "ipa-reg", 1402 "ipa-shared", 1403 "gsi"; 1404 1405 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 1406 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 1407 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1408 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1409 interrupt-names = "ipa", 1410 "gsi", 1411 "ipa-clock-query", 1412 "ipa-setup-ready"; 1413 1414 clocks = <&rpmhcc RPMH_IPA_CLK>; 1415 clock-names = "core"; 1416 1417 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1418 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1419 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1420 interconnect-names = "memory", 1421 "imem", 1422 "config"; 1423 1424 qcom,smem-states = <&ipa_smp2p_out 0>, 1425 <&ipa_smp2p_out 1>; 1426 qcom,smem-state-names = "ipa-clock-enabled-valid", 1427 "ipa-clock-enabled"; 1428 1429 modem-remoteproc = <&remoteproc_mpss>; 1430 1431 status = "disabled"; 1432 }; 1433 1434 tcsr_mutex_regs: syscon@1f40000 { 1435 compatible = "syscon"; 1436 reg = <0 0x01f40000 0 0x40000>; 1437 }; 1438 1439 tcsr_regs: syscon@1fc0000 { 1440 compatible = "syscon"; 1441 reg = <0 0x01fc0000 0 0x40000>; 1442 }; 1443 1444 tlmm: pinctrl@3500000 { 1445 compatible = "qcom,sc7180-pinctrl"; 1446 reg = <0 0x03500000 0 0x300000>, 1447 <0 0x03900000 0 0x300000>, 1448 <0 0x03d00000 0 0x300000>; 1449 reg-names = "west", "north", "south"; 1450 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1451 gpio-controller; 1452 #gpio-cells = <2>; 1453 interrupt-controller; 1454 #interrupt-cells = <2>; 1455 gpio-ranges = <&tlmm 0 0 120>; 1456 wakeup-parent = <&pdc>; 1457 1458 dp_hot_plug_det: dp-hot-plug-det { 1459 pinmux { 1460 pins = "gpio117"; 1461 function = "dp_hot"; 1462 }; 1463 1464 pinconf { 1465 pins = "gpio117"; 1466 bias-disable; 1467 input-enable; 1468 }; 1469 }; 1470 1471 qspi_clk: qspi-clk { 1472 pinmux { 1473 pins = "gpio63"; 1474 function = "qspi_clk"; 1475 }; 1476 }; 1477 1478 qspi_cs0: qspi-cs0 { 1479 pinmux { 1480 pins = "gpio68"; 1481 function = "qspi_cs"; 1482 }; 1483 }; 1484 1485 qspi_cs1: qspi-cs1 { 1486 pinmux { 1487 pins = "gpio72"; 1488 function = "qspi_cs"; 1489 }; 1490 }; 1491 1492 qspi_data01: qspi-data01 { 1493 pinmux-data { 1494 pins = "gpio64", "gpio65"; 1495 function = "qspi_data"; 1496 }; 1497 }; 1498 1499 qspi_data12: qspi-data12 { 1500 pinmux-data { 1501 pins = "gpio66", "gpio67"; 1502 function = "qspi_data"; 1503 }; 1504 }; 1505 1506 qup_i2c0_default: qup-i2c0-default { 1507 pinmux { 1508 pins = "gpio34", "gpio35"; 1509 function = "qup00"; 1510 }; 1511 }; 1512 1513 qup_i2c1_default: qup-i2c1-default { 1514 pinmux { 1515 pins = "gpio0", "gpio1"; 1516 function = "qup01"; 1517 }; 1518 }; 1519 1520 qup_i2c2_default: qup-i2c2-default { 1521 pinmux { 1522 pins = "gpio15", "gpio16"; 1523 function = "qup02_i2c"; 1524 }; 1525 }; 1526 1527 qup_i2c3_default: qup-i2c3-default { 1528 pinmux { 1529 pins = "gpio38", "gpio39"; 1530 function = "qup03"; 1531 }; 1532 }; 1533 1534 qup_i2c4_default: qup-i2c4-default { 1535 pinmux { 1536 pins = "gpio115", "gpio116"; 1537 function = "qup04_i2c"; 1538 }; 1539 }; 1540 1541 qup_i2c5_default: qup-i2c5-default { 1542 pinmux { 1543 pins = "gpio25", "gpio26"; 1544 function = "qup05"; 1545 }; 1546 }; 1547 1548 qup_i2c6_default: qup-i2c6-default { 1549 pinmux { 1550 pins = "gpio59", "gpio60"; 1551 function = "qup10"; 1552 }; 1553 }; 1554 1555 qup_i2c7_default: qup-i2c7-default { 1556 pinmux { 1557 pins = "gpio6", "gpio7"; 1558 function = "qup11_i2c"; 1559 }; 1560 }; 1561 1562 qup_i2c8_default: qup-i2c8-default { 1563 pinmux { 1564 pins = "gpio42", "gpio43"; 1565 function = "qup12"; 1566 }; 1567 }; 1568 1569 qup_i2c9_default: qup-i2c9-default { 1570 pinmux { 1571 pins = "gpio46", "gpio47"; 1572 function = "qup13_i2c"; 1573 }; 1574 }; 1575 1576 qup_i2c10_default: qup-i2c10-default { 1577 pinmux { 1578 pins = "gpio86", "gpio87"; 1579 function = "qup14"; 1580 }; 1581 }; 1582 1583 qup_i2c11_default: qup-i2c11-default { 1584 pinmux { 1585 pins = "gpio53", "gpio54"; 1586 function = "qup15"; 1587 }; 1588 }; 1589 1590 qup_spi0_default: qup-spi0-default { 1591 pinmux { 1592 pins = "gpio34", "gpio35", 1593 "gpio36", "gpio37"; 1594 function = "qup00"; 1595 }; 1596 }; 1597 1598 qup_spi1_default: qup-spi1-default { 1599 pinmux { 1600 pins = "gpio0", "gpio1", 1601 "gpio2", "gpio3"; 1602 function = "qup01"; 1603 }; 1604 }; 1605 1606 qup_spi3_default: qup-spi3-default { 1607 pinmux { 1608 pins = "gpio38", "gpio39", 1609 "gpio40", "gpio41"; 1610 function = "qup03"; 1611 }; 1612 }; 1613 1614 qup_spi5_default: qup-spi5-default { 1615 pinmux { 1616 pins = "gpio25", "gpio26", 1617 "gpio27", "gpio28"; 1618 function = "qup05"; 1619 }; 1620 }; 1621 1622 qup_spi6_default: qup-spi6-default { 1623 pinmux { 1624 pins = "gpio59", "gpio60", 1625 "gpio61", "gpio62"; 1626 function = "qup10"; 1627 }; 1628 }; 1629 1630 qup_spi8_default: qup-spi8-default { 1631 pinmux { 1632 pins = "gpio42", "gpio43", 1633 "gpio44", "gpio45"; 1634 function = "qup12"; 1635 }; 1636 }; 1637 1638 qup_spi10_default: qup-spi10-default { 1639 pinmux { 1640 pins = "gpio86", "gpio87", 1641 "gpio88", "gpio89"; 1642 function = "qup14"; 1643 }; 1644 }; 1645 1646 qup_spi11_default: qup-spi11-default { 1647 pinmux { 1648 pins = "gpio53", "gpio54", 1649 "gpio55", "gpio56"; 1650 function = "qup15"; 1651 }; 1652 }; 1653 1654 qup_uart0_default: qup-uart0-default { 1655 pinmux { 1656 pins = "gpio34", "gpio35", 1657 "gpio36", "gpio37"; 1658 function = "qup00"; 1659 }; 1660 }; 1661 1662 qup_uart1_default: qup-uart1-default { 1663 pinmux { 1664 pins = "gpio0", "gpio1", 1665 "gpio2", "gpio3"; 1666 function = "qup01"; 1667 }; 1668 }; 1669 1670 qup_uart2_default: qup-uart2-default { 1671 pinmux { 1672 pins = "gpio15", "gpio16"; 1673 function = "qup02_uart"; 1674 }; 1675 }; 1676 1677 qup_uart3_default: qup-uart3-default { 1678 pinmux { 1679 pins = "gpio38", "gpio39", 1680 "gpio40", "gpio41"; 1681 function = "qup03"; 1682 }; 1683 }; 1684 1685 qup_uart4_default: qup-uart4-default { 1686 pinmux { 1687 pins = "gpio115", "gpio116"; 1688 function = "qup04_uart"; 1689 }; 1690 }; 1691 1692 qup_uart5_default: qup-uart5-default { 1693 pinmux { 1694 pins = "gpio25", "gpio26", 1695 "gpio27", "gpio28"; 1696 function = "qup05"; 1697 }; 1698 }; 1699 1700 qup_uart6_default: qup-uart6-default { 1701 pinmux { 1702 pins = "gpio59", "gpio60", 1703 "gpio61", "gpio62"; 1704 function = "qup10"; 1705 }; 1706 }; 1707 1708 qup_uart7_default: qup-uart7-default { 1709 pinmux { 1710 pins = "gpio6", "gpio7"; 1711 function = "qup11_uart"; 1712 }; 1713 }; 1714 1715 qup_uart8_default: qup-uart8-default { 1716 pinmux { 1717 pins = "gpio44", "gpio45"; 1718 function = "qup12"; 1719 }; 1720 }; 1721 1722 qup_uart9_default: qup-uart9-default { 1723 pinmux { 1724 pins = "gpio46", "gpio47"; 1725 function = "qup13_uart"; 1726 }; 1727 }; 1728 1729 qup_uart10_default: qup-uart10-default { 1730 pinmux { 1731 pins = "gpio86", "gpio87", 1732 "gpio88", "gpio89"; 1733 function = "qup14"; 1734 }; 1735 }; 1736 1737 qup_uart11_default: qup-uart11-default { 1738 pinmux { 1739 pins = "gpio53", "gpio54", 1740 "gpio55", "gpio56"; 1741 function = "qup15"; 1742 }; 1743 }; 1744 1745 sdc1_on: sdc1-on { 1746 pinconf-clk { 1747 pins = "sdc1_clk"; 1748 bias-disable; 1749 drive-strength = <16>; 1750 }; 1751 1752 pinconf-cmd { 1753 pins = "sdc1_cmd"; 1754 bias-pull-up; 1755 drive-strength = <10>; 1756 }; 1757 1758 pinconf-data { 1759 pins = "sdc1_data"; 1760 bias-pull-up; 1761 drive-strength = <10>; 1762 }; 1763 1764 pinconf-rclk { 1765 pins = "sdc1_rclk"; 1766 bias-pull-down; 1767 }; 1768 }; 1769 1770 sdc1_off: sdc1-off { 1771 pinconf-clk { 1772 pins = "sdc1_clk"; 1773 bias-disable; 1774 drive-strength = <2>; 1775 }; 1776 1777 pinconf-cmd { 1778 pins = "sdc1_cmd"; 1779 bias-pull-up; 1780 drive-strength = <2>; 1781 }; 1782 1783 pinconf-data { 1784 pins = "sdc1_data"; 1785 bias-pull-up; 1786 drive-strength = <2>; 1787 }; 1788 1789 pinconf-rclk { 1790 pins = "sdc1_rclk"; 1791 bias-pull-down; 1792 }; 1793 }; 1794 1795 sdc2_on: sdc2-on { 1796 pinconf-clk { 1797 pins = "sdc2_clk"; 1798 bias-disable; 1799 drive-strength = <16>; 1800 }; 1801 1802 pinconf-cmd { 1803 pins = "sdc2_cmd"; 1804 bias-pull-up; 1805 drive-strength = <10>; 1806 }; 1807 1808 pinconf-data { 1809 pins = "sdc2_data"; 1810 bias-pull-up; 1811 drive-strength = <10>; 1812 }; 1813 1814 pinconf-sd-cd { 1815 pins = "gpio69"; 1816 bias-pull-up; 1817 drive-strength = <2>; 1818 }; 1819 }; 1820 1821 sdc2_off: sdc2-off { 1822 pinconf-clk { 1823 pins = "sdc2_clk"; 1824 bias-disable; 1825 drive-strength = <2>; 1826 }; 1827 1828 pinconf-cmd { 1829 pins = "sdc2_cmd"; 1830 bias-pull-up; 1831 drive-strength = <2>; 1832 }; 1833 1834 pinconf-data { 1835 pins = "sdc2_data"; 1836 bias-pull-up; 1837 drive-strength = <2>; 1838 }; 1839 1840 pinconf-sd-cd { 1841 pins = "gpio69"; 1842 bias-disable; 1843 drive-strength = <2>; 1844 }; 1845 }; 1846 }; 1847 1848 remoteproc_mpss: remoteproc@4080000 { 1849 compatible = "qcom,sc7180-mpss-pas"; 1850 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1851 reg-names = "qdsp6", "rmb"; 1852 1853 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1854 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1855 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1856 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1857 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1858 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1859 interrupt-names = "wdog", "fatal", "ready", "handover", 1860 "stop-ack", "shutdown-ack"; 1861 1862 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1863 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1864 <&gcc GCC_MSS_NAV_AXI_CLK>, 1865 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1866 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1867 <&rpmhcc RPMH_CXO_CLK>; 1868 clock-names = "iface", "bus", "nav", "snoc_axi", 1869 "mnoc_axi", "xo"; 1870 1871 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 1872 <&rpmhpd SC7180_CX>, 1873 <&rpmhpd SC7180_MX>, 1874 <&rpmhpd SC7180_MSS>; 1875 power-domain-names = "load_state", "cx", "mx", "mss"; 1876 1877 memory-region = <&mpss_mem>; 1878 1879 qcom,smem-states = <&modem_smp2p_out 0>; 1880 qcom,smem-state-names = "stop"; 1881 1882 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1883 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1884 reset-names = "mss_restart", "pdc_reset"; 1885 1886 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1887 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 1888 1889 status = "disabled"; 1890 1891 glink-edge { 1892 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1893 label = "modem"; 1894 qcom,remote-pid = <1>; 1895 mboxes = <&apss_shared 12>; 1896 }; 1897 }; 1898 1899 gpu: gpu@5000000 { 1900 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1901 #stream-id-cells = <16>; 1902 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1903 <0 0x05061000 0 0x800>; 1904 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1905 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1906 iommus = <&adreno_smmu 0>; 1907 operating-points-v2 = <&gpu_opp_table>; 1908 qcom,gmu = <&gmu>; 1909 1910 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1911 interconnect-names = "gfx-mem"; 1912 1913 gpu_opp_table: opp-table { 1914 compatible = "operating-points-v2"; 1915 1916 opp-800000000 { 1917 opp-hz = /bits/ 64 <800000000>; 1918 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1919 opp-peak-kBps = <8532000>; 1920 }; 1921 1922 opp-650000000 { 1923 opp-hz = /bits/ 64 <650000000>; 1924 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1925 opp-peak-kBps = <7216000>; 1926 }; 1927 1928 opp-565000000 { 1929 opp-hz = /bits/ 64 <565000000>; 1930 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1931 opp-peak-kBps = <5412000>; 1932 }; 1933 1934 opp-430000000 { 1935 opp-hz = /bits/ 64 <430000000>; 1936 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1937 opp-peak-kBps = <5412000>; 1938 }; 1939 1940 opp-355000000 { 1941 opp-hz = /bits/ 64 <355000000>; 1942 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1943 opp-peak-kBps = <3072000>; 1944 }; 1945 1946 opp-267000000 { 1947 opp-hz = /bits/ 64 <267000000>; 1948 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1949 opp-peak-kBps = <3072000>; 1950 }; 1951 1952 opp-180000000 { 1953 opp-hz = /bits/ 64 <180000000>; 1954 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1955 opp-peak-kBps = <1804000>; 1956 }; 1957 }; 1958 }; 1959 1960 adreno_smmu: iommu@5040000 { 1961 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; 1962 reg = <0 0x05040000 0 0x10000>; 1963 #iommu-cells = <1>; 1964 #global-interrupts = <2>; 1965 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 1968 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 1969 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 1970 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 1971 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 1972 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 1975 1976 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1977 <&gcc GCC_GPU_CFG_AHB_CLK>; 1978 clock-names = "bus", "iface"; 1979 1980 power-domains = <&gpucc CX_GDSC>; 1981 }; 1982 1983 gmu: gmu@506a000 { 1984 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 1985 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 1986 <0 0x0b490000 0 0x10000>; 1987 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1988 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1990 interrupt-names = "hfi", "gmu"; 1991 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1992 <&gpucc GPU_CC_CXO_CLK>, 1993 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1994 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1995 clock-names = "gmu", "cxo", "axi", "memnoc"; 1996 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 1997 power-domain-names = "cx", "gx"; 1998 iommus = <&adreno_smmu 5>; 1999 operating-points-v2 = <&gmu_opp_table>; 2000 2001 gmu_opp_table: opp-table { 2002 compatible = "operating-points-v2"; 2003 2004 opp-200000000 { 2005 opp-hz = /bits/ 64 <200000000>; 2006 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2007 }; 2008 }; 2009 }; 2010 2011 gpucc: clock-controller@5090000 { 2012 compatible = "qcom,sc7180-gpucc"; 2013 reg = <0 0x05090000 0 0x9000>; 2014 clocks = <&rpmhcc RPMH_CXO_CLK>, 2015 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2016 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2017 clock-names = "bi_tcxo", 2018 "gcc_gpu_gpll0_clk_src", 2019 "gcc_gpu_gpll0_div_clk_src"; 2020 #clock-cells = <1>; 2021 #reset-cells = <1>; 2022 #power-domain-cells = <1>; 2023 }; 2024 2025 stm@6002000 { 2026 compatible = "arm,coresight-stm", "arm,primecell"; 2027 reg = <0 0x06002000 0 0x1000>, 2028 <0 0x16280000 0 0x180000>; 2029 reg-names = "stm-base", "stm-stimulus-base"; 2030 2031 clocks = <&aoss_qmp>; 2032 clock-names = "apb_pclk"; 2033 2034 out-ports { 2035 port { 2036 stm_out: endpoint { 2037 remote-endpoint = <&funnel0_in7>; 2038 }; 2039 }; 2040 }; 2041 }; 2042 2043 funnel@6041000 { 2044 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2045 reg = <0 0x06041000 0 0x1000>; 2046 2047 clocks = <&aoss_qmp>; 2048 clock-names = "apb_pclk"; 2049 2050 out-ports { 2051 port { 2052 funnel0_out: endpoint { 2053 remote-endpoint = <&merge_funnel_in0>; 2054 }; 2055 }; 2056 }; 2057 2058 in-ports { 2059 #address-cells = <1>; 2060 #size-cells = <0>; 2061 2062 port@7 { 2063 reg = <7>; 2064 funnel0_in7: endpoint { 2065 remote-endpoint = <&stm_out>; 2066 }; 2067 }; 2068 }; 2069 }; 2070 2071 funnel@6042000 { 2072 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2073 reg = <0 0x06042000 0 0x1000>; 2074 2075 clocks = <&aoss_qmp>; 2076 clock-names = "apb_pclk"; 2077 2078 out-ports { 2079 port { 2080 funnel1_out: endpoint { 2081 remote-endpoint = <&merge_funnel_in1>; 2082 }; 2083 }; 2084 }; 2085 2086 in-ports { 2087 #address-cells = <1>; 2088 #size-cells = <0>; 2089 2090 port@4 { 2091 reg = <4>; 2092 funnel1_in4: endpoint { 2093 remote-endpoint = <&apss_merge_funnel_out>; 2094 }; 2095 }; 2096 }; 2097 }; 2098 2099 funnel@6045000 { 2100 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2101 reg = <0 0x06045000 0 0x1000>; 2102 2103 clocks = <&aoss_qmp>; 2104 clock-names = "apb_pclk"; 2105 2106 out-ports { 2107 port { 2108 merge_funnel_out: endpoint { 2109 remote-endpoint = <&swao_funnel_in>; 2110 }; 2111 }; 2112 }; 2113 2114 in-ports { 2115 #address-cells = <1>; 2116 #size-cells = <0>; 2117 2118 port@0 { 2119 reg = <0>; 2120 merge_funnel_in0: endpoint { 2121 remote-endpoint = <&funnel0_out>; 2122 }; 2123 }; 2124 2125 port@1 { 2126 reg = <1>; 2127 merge_funnel_in1: endpoint { 2128 remote-endpoint = <&funnel1_out>; 2129 }; 2130 }; 2131 }; 2132 }; 2133 2134 replicator@6046000 { 2135 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2136 reg = <0 0x06046000 0 0x1000>; 2137 2138 clocks = <&aoss_qmp>; 2139 clock-names = "apb_pclk"; 2140 2141 out-ports { 2142 port { 2143 replicator_out: endpoint { 2144 remote-endpoint = <&etr_in>; 2145 }; 2146 }; 2147 }; 2148 2149 in-ports { 2150 port { 2151 replicator_in: endpoint { 2152 remote-endpoint = <&swao_replicator_out>; 2153 }; 2154 }; 2155 }; 2156 }; 2157 2158 etr@6048000 { 2159 compatible = "arm,coresight-tmc", "arm,primecell"; 2160 reg = <0 0x06048000 0 0x1000>; 2161 iommus = <&apps_smmu 0x04a0 0x20>; 2162 2163 clocks = <&aoss_qmp>; 2164 clock-names = "apb_pclk"; 2165 arm,scatter-gather; 2166 2167 in-ports { 2168 port { 2169 etr_in: endpoint { 2170 remote-endpoint = <&replicator_out>; 2171 }; 2172 }; 2173 }; 2174 }; 2175 2176 funnel@6b04000 { 2177 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2178 reg = <0 0x06b04000 0 0x1000>; 2179 2180 clocks = <&aoss_qmp>; 2181 clock-names = "apb_pclk"; 2182 2183 out-ports { 2184 port { 2185 swao_funnel_out: endpoint { 2186 remote-endpoint = <&etf_in>; 2187 }; 2188 }; 2189 }; 2190 2191 in-ports { 2192 #address-cells = <1>; 2193 #size-cells = <0>; 2194 2195 port@7 { 2196 reg = <7>; 2197 swao_funnel_in: endpoint { 2198 remote-endpoint = <&merge_funnel_out>; 2199 }; 2200 }; 2201 }; 2202 }; 2203 2204 etf@6b05000 { 2205 compatible = "arm,coresight-tmc", "arm,primecell"; 2206 reg = <0 0x06b05000 0 0x1000>; 2207 2208 clocks = <&aoss_qmp>; 2209 clock-names = "apb_pclk"; 2210 2211 out-ports { 2212 port { 2213 etf_out: endpoint { 2214 remote-endpoint = <&swao_replicator_in>; 2215 }; 2216 }; 2217 }; 2218 2219 in-ports { 2220 port { 2221 etf_in: endpoint { 2222 remote-endpoint = <&swao_funnel_out>; 2223 }; 2224 }; 2225 }; 2226 }; 2227 2228 replicator@6b06000 { 2229 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2230 reg = <0 0x06b06000 0 0x1000>; 2231 2232 clocks = <&aoss_qmp>; 2233 clock-names = "apb_pclk"; 2234 qcom,replicator-loses-context; 2235 2236 out-ports { 2237 port { 2238 swao_replicator_out: endpoint { 2239 remote-endpoint = <&replicator_in>; 2240 }; 2241 }; 2242 }; 2243 2244 in-ports { 2245 port { 2246 swao_replicator_in: endpoint { 2247 remote-endpoint = <&etf_out>; 2248 }; 2249 }; 2250 }; 2251 }; 2252 2253 etm@7040000 { 2254 compatible = "arm,coresight-etm4x", "arm,primecell"; 2255 reg = <0 0x07040000 0 0x1000>; 2256 2257 cpu = <&CPU0>; 2258 2259 clocks = <&aoss_qmp>; 2260 clock-names = "apb_pclk"; 2261 arm,coresight-loses-context-with-cpu; 2262 qcom,skip-power-up; 2263 2264 out-ports { 2265 port { 2266 etm0_out: endpoint { 2267 remote-endpoint = <&apss_funnel_in0>; 2268 }; 2269 }; 2270 }; 2271 }; 2272 2273 etm@7140000 { 2274 compatible = "arm,coresight-etm4x", "arm,primecell"; 2275 reg = <0 0x07140000 0 0x1000>; 2276 2277 cpu = <&CPU1>; 2278 2279 clocks = <&aoss_qmp>; 2280 clock-names = "apb_pclk"; 2281 arm,coresight-loses-context-with-cpu; 2282 qcom,skip-power-up; 2283 2284 out-ports { 2285 port { 2286 etm1_out: endpoint { 2287 remote-endpoint = <&apss_funnel_in1>; 2288 }; 2289 }; 2290 }; 2291 }; 2292 2293 etm@7240000 { 2294 compatible = "arm,coresight-etm4x", "arm,primecell"; 2295 reg = <0 0x07240000 0 0x1000>; 2296 2297 cpu = <&CPU2>; 2298 2299 clocks = <&aoss_qmp>; 2300 clock-names = "apb_pclk"; 2301 arm,coresight-loses-context-with-cpu; 2302 qcom,skip-power-up; 2303 2304 out-ports { 2305 port { 2306 etm2_out: endpoint { 2307 remote-endpoint = <&apss_funnel_in2>; 2308 }; 2309 }; 2310 }; 2311 }; 2312 2313 etm@7340000 { 2314 compatible = "arm,coresight-etm4x", "arm,primecell"; 2315 reg = <0 0x07340000 0 0x1000>; 2316 2317 cpu = <&CPU3>; 2318 2319 clocks = <&aoss_qmp>; 2320 clock-names = "apb_pclk"; 2321 arm,coresight-loses-context-with-cpu; 2322 qcom,skip-power-up; 2323 2324 out-ports { 2325 port { 2326 etm3_out: endpoint { 2327 remote-endpoint = <&apss_funnel_in3>; 2328 }; 2329 }; 2330 }; 2331 }; 2332 2333 etm@7440000 { 2334 compatible = "arm,coresight-etm4x", "arm,primecell"; 2335 reg = <0 0x07440000 0 0x1000>; 2336 2337 cpu = <&CPU4>; 2338 2339 clocks = <&aoss_qmp>; 2340 clock-names = "apb_pclk"; 2341 arm,coresight-loses-context-with-cpu; 2342 qcom,skip-power-up; 2343 2344 out-ports { 2345 port { 2346 etm4_out: endpoint { 2347 remote-endpoint = <&apss_funnel_in4>; 2348 }; 2349 }; 2350 }; 2351 }; 2352 2353 etm@7540000 { 2354 compatible = "arm,coresight-etm4x", "arm,primecell"; 2355 reg = <0 0x07540000 0 0x1000>; 2356 2357 cpu = <&CPU5>; 2358 2359 clocks = <&aoss_qmp>; 2360 clock-names = "apb_pclk"; 2361 arm,coresight-loses-context-with-cpu; 2362 qcom,skip-power-up; 2363 2364 out-ports { 2365 port { 2366 etm5_out: endpoint { 2367 remote-endpoint = <&apss_funnel_in5>; 2368 }; 2369 }; 2370 }; 2371 }; 2372 2373 etm@7640000 { 2374 compatible = "arm,coresight-etm4x", "arm,primecell"; 2375 reg = <0 0x07640000 0 0x1000>; 2376 2377 cpu = <&CPU6>; 2378 2379 clocks = <&aoss_qmp>; 2380 clock-names = "apb_pclk"; 2381 arm,coresight-loses-context-with-cpu; 2382 qcom,skip-power-up; 2383 2384 out-ports { 2385 port { 2386 etm6_out: endpoint { 2387 remote-endpoint = <&apss_funnel_in6>; 2388 }; 2389 }; 2390 }; 2391 }; 2392 2393 etm@7740000 { 2394 compatible = "arm,coresight-etm4x", "arm,primecell"; 2395 reg = <0 0x07740000 0 0x1000>; 2396 2397 cpu = <&CPU7>; 2398 2399 clocks = <&aoss_qmp>; 2400 clock-names = "apb_pclk"; 2401 arm,coresight-loses-context-with-cpu; 2402 qcom,skip-power-up; 2403 2404 out-ports { 2405 port { 2406 etm7_out: endpoint { 2407 remote-endpoint = <&apss_funnel_in7>; 2408 }; 2409 }; 2410 }; 2411 }; 2412 2413 funnel@7800000 { /* APSS Funnel */ 2414 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2415 reg = <0 0x07800000 0 0x1000>; 2416 2417 clocks = <&aoss_qmp>; 2418 clock-names = "apb_pclk"; 2419 2420 out-ports { 2421 port { 2422 apss_funnel_out: endpoint { 2423 remote-endpoint = <&apss_merge_funnel_in>; 2424 }; 2425 }; 2426 }; 2427 2428 in-ports { 2429 #address-cells = <1>; 2430 #size-cells = <0>; 2431 2432 port@0 { 2433 reg = <0>; 2434 apss_funnel_in0: endpoint { 2435 remote-endpoint = <&etm0_out>; 2436 }; 2437 }; 2438 2439 port@1 { 2440 reg = <1>; 2441 apss_funnel_in1: endpoint { 2442 remote-endpoint = <&etm1_out>; 2443 }; 2444 }; 2445 2446 port@2 { 2447 reg = <2>; 2448 apss_funnel_in2: endpoint { 2449 remote-endpoint = <&etm2_out>; 2450 }; 2451 }; 2452 2453 port@3 { 2454 reg = <3>; 2455 apss_funnel_in3: endpoint { 2456 remote-endpoint = <&etm3_out>; 2457 }; 2458 }; 2459 2460 port@4 { 2461 reg = <4>; 2462 apss_funnel_in4: endpoint { 2463 remote-endpoint = <&etm4_out>; 2464 }; 2465 }; 2466 2467 port@5 { 2468 reg = <5>; 2469 apss_funnel_in5: endpoint { 2470 remote-endpoint = <&etm5_out>; 2471 }; 2472 }; 2473 2474 port@6 { 2475 reg = <6>; 2476 apss_funnel_in6: endpoint { 2477 remote-endpoint = <&etm6_out>; 2478 }; 2479 }; 2480 2481 port@7 { 2482 reg = <7>; 2483 apss_funnel_in7: endpoint { 2484 remote-endpoint = <&etm7_out>; 2485 }; 2486 }; 2487 }; 2488 }; 2489 2490 funnel@7810000 { 2491 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2492 reg = <0 0x07810000 0 0x1000>; 2493 2494 clocks = <&aoss_qmp>; 2495 clock-names = "apb_pclk"; 2496 2497 out-ports { 2498 port { 2499 apss_merge_funnel_out: endpoint { 2500 remote-endpoint = <&funnel1_in4>; 2501 }; 2502 }; 2503 }; 2504 2505 in-ports { 2506 port { 2507 apss_merge_funnel_in: endpoint { 2508 remote-endpoint = <&apss_funnel_out>; 2509 }; 2510 }; 2511 }; 2512 }; 2513 2514 sdhc_2: sdhci@8804000 { 2515 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2516 reg = <0 0x08804000 0 0x1000>; 2517 2518 iommus = <&apps_smmu 0x80 0>; 2519 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2521 interrupt-names = "hc_irq", "pwr_irq"; 2522 2523 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2524 <&gcc GCC_SDCC2_AHB_CLK>; 2525 clock-names = "core", "iface"; 2526 2527 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2529 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2530 power-domains = <&rpmhpd SC7180_CX>; 2531 operating-points-v2 = <&sdhc2_opp_table>; 2532 2533 bus-width = <4>; 2534 2535 status = "disabled"; 2536 2537 sdhc2_opp_table: sdhc2-opp-table { 2538 compatible = "operating-points-v2"; 2539 2540 opp-100000000 { 2541 opp-hz = /bits/ 64 <100000000>; 2542 required-opps = <&rpmhpd_opp_low_svs>; 2543 opp-peak-kBps = <160000 100000>; 2544 opp-avg-kBps = <80000 50000>; 2545 }; 2546 2547 opp-202000000 { 2548 opp-hz = /bits/ 64 <202000000>; 2549 required-opps = <&rpmhpd_opp_svs_l1>; 2550 opp-peak-kBps = <200000 120000>; 2551 opp-avg-kBps = <100000 60000>; 2552 }; 2553 }; 2554 }; 2555 2556 qspi_opp_table: qspi-opp-table { 2557 compatible = "operating-points-v2"; 2558 2559 opp-75000000 { 2560 opp-hz = /bits/ 64 <75000000>; 2561 required-opps = <&rpmhpd_opp_low_svs>; 2562 }; 2563 2564 opp-150000000 { 2565 opp-hz = /bits/ 64 <150000000>; 2566 required-opps = <&rpmhpd_opp_svs>; 2567 }; 2568 2569 opp-300000000 { 2570 opp-hz = /bits/ 64 <300000000>; 2571 required-opps = <&rpmhpd_opp_nom>; 2572 }; 2573 }; 2574 2575 qspi: spi@88dc000 { 2576 compatible = "qcom,qspi-v1"; 2577 reg = <0 0x088dc000 0 0x600>; 2578 #address-cells = <1>; 2579 #size-cells = <0>; 2580 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2581 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2582 <&gcc GCC_QSPI_CORE_CLK>; 2583 clock-names = "iface", "core"; 2584 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2585 &config_noc SLAVE_QSPI_0 0>; 2586 interconnect-names = "qspi-config"; 2587 power-domains = <&rpmhpd SC7180_CX>; 2588 operating-points-v2 = <&qspi_opp_table>; 2589 status = "disabled"; 2590 }; 2591 2592 usb_1_hsphy: phy@88e3000 { 2593 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2594 reg = <0 0x088e3000 0 0x400>; 2595 status = "disabled"; 2596 #phy-cells = <0>; 2597 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2598 <&rpmhcc RPMH_CXO_CLK>; 2599 clock-names = "cfg_ahb", "ref"; 2600 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2601 2602 nvmem-cells = <&qusb2p_hstx_trim>; 2603 }; 2604 2605 usb_1_qmpphy: phy-wrapper@88e9000 { 2606 compatible = "qcom,sc7180-qmp-usb3-phy"; 2607 reg = <0 0x088e9000 0 0x18c>, 2608 <0 0x088e8000 0 0x38>; 2609 reg-names = "reg-base", "dp_com"; 2610 status = "disabled"; 2611 #clock-cells = <1>; 2612 #address-cells = <2>; 2613 #size-cells = <2>; 2614 ranges; 2615 2616 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2617 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2618 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2619 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2620 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2621 2622 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2623 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2624 reset-names = "phy", "common"; 2625 2626 usb_1_ssphy: phy@88e9200 { 2627 reg = <0 0x088e9200 0 0x128>, 2628 <0 0x088e9400 0 0x200>, 2629 <0 0x088e9c00 0 0x218>, 2630 <0 0x088e9600 0 0x128>, 2631 <0 0x088e9800 0 0x200>, 2632 <0 0x088e9a00 0 0x18>; 2633 #clock-cells = <0>; 2634 #phy-cells = <0>; 2635 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2636 clock-names = "pipe0"; 2637 clock-output-names = "usb3_phy_pipe_clk_src"; 2638 }; 2639 }; 2640 2641 dc_noc: interconnect@9160000 { 2642 compatible = "qcom,sc7180-dc-noc"; 2643 reg = <0 0x09160000 0 0x03200>; 2644 #interconnect-cells = <2>; 2645 qcom,bcm-voters = <&apps_bcm_voter>; 2646 }; 2647 2648 system-cache-controller@9200000 { 2649 compatible = "qcom,sc7180-llcc"; 2650 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2651 reg-names = "llcc_base", "llcc_broadcast_base"; 2652 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2653 }; 2654 2655 gem_noc: interconnect@9680000 { 2656 compatible = "qcom,sc7180-gem-noc"; 2657 reg = <0 0x09680000 0 0x3e200>; 2658 #interconnect-cells = <2>; 2659 qcom,bcm-voters = <&apps_bcm_voter>; 2660 }; 2661 2662 npu_noc: interconnect@9990000 { 2663 compatible = "qcom,sc7180-npu-noc"; 2664 reg = <0 0x09990000 0 0x1600>; 2665 #interconnect-cells = <2>; 2666 qcom,bcm-voters = <&apps_bcm_voter>; 2667 }; 2668 2669 usb_1: usb@a6f8800 { 2670 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2671 reg = <0 0x0a6f8800 0 0x400>; 2672 status = "disabled"; 2673 #address-cells = <2>; 2674 #size-cells = <2>; 2675 ranges; 2676 dma-ranges; 2677 2678 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2679 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2680 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2681 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2682 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2683 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2684 "sleep"; 2685 2686 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2687 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2688 assigned-clock-rates = <19200000>, <150000000>; 2689 2690 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2691 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2694 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2695 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2696 2697 power-domains = <&gcc USB30_PRIM_GDSC>; 2698 2699 resets = <&gcc GCC_USB30_PRIM_BCR>; 2700 2701 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2702 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2703 interconnect-names = "usb-ddr", "apps-usb"; 2704 2705 usb_1_dwc3: dwc3@a600000 { 2706 compatible = "snps,dwc3"; 2707 reg = <0 0x0a600000 0 0xe000>; 2708 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2709 iommus = <&apps_smmu 0x540 0>; 2710 snps,dis_u2_susphy_quirk; 2711 snps,dis_enblslpm_quirk; 2712 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2713 phy-names = "usb2-phy", "usb3-phy"; 2714 maximum-speed = "super-speed"; 2715 }; 2716 }; 2717 2718 venus: video-codec@aa00000 { 2719 compatible = "qcom,sc7180-venus"; 2720 reg = <0 0x0aa00000 0 0xff000>; 2721 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2722 power-domains = <&videocc VENUS_GDSC>, 2723 <&videocc VCODEC0_GDSC>, 2724 <&rpmhpd SC7180_CX>; 2725 power-domain-names = "venus", "vcodec0", "cx"; 2726 operating-points-v2 = <&venus_opp_table>; 2727 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2728 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2729 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2730 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2731 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2732 clock-names = "core", "iface", "bus", 2733 "vcodec0_core", "vcodec0_bus"; 2734 iommus = <&apps_smmu 0x0c00 0x60>; 2735 memory-region = <&venus_mem>; 2736 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2737 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2738 interconnect-names = "video-mem", "cpu-cfg"; 2739 2740 video-decoder { 2741 compatible = "venus-decoder"; 2742 }; 2743 2744 video-encoder { 2745 compatible = "venus-encoder"; 2746 }; 2747 2748 venus_opp_table: venus-opp-table { 2749 compatible = "operating-points-v2"; 2750 2751 opp-150000000 { 2752 opp-hz = /bits/ 64 <150000000>; 2753 required-opps = <&rpmhpd_opp_low_svs>; 2754 }; 2755 2756 opp-270000000 { 2757 opp-hz = /bits/ 64 <270000000>; 2758 required-opps = <&rpmhpd_opp_svs>; 2759 }; 2760 2761 opp-340000000 { 2762 opp-hz = /bits/ 64 <340000000>; 2763 required-opps = <&rpmhpd_opp_svs_l1>; 2764 }; 2765 2766 opp-434000000 { 2767 opp-hz = /bits/ 64 <434000000>; 2768 required-opps = <&rpmhpd_opp_nom>; 2769 }; 2770 2771 opp-500000097 { 2772 opp-hz = /bits/ 64 <500000097>; 2773 required-opps = <&rpmhpd_opp_turbo>; 2774 }; 2775 }; 2776 }; 2777 2778 videocc: clock-controller@ab00000 { 2779 compatible = "qcom,sc7180-videocc"; 2780 reg = <0 0x0ab00000 0 0x10000>; 2781 clocks = <&rpmhcc RPMH_CXO_CLK>; 2782 clock-names = "bi_tcxo"; 2783 #clock-cells = <1>; 2784 #reset-cells = <1>; 2785 #power-domain-cells = <1>; 2786 }; 2787 2788 camnoc_virt: interconnect@ac00000 { 2789 compatible = "qcom,sc7180-camnoc-virt"; 2790 reg = <0 0x0ac00000 0 0x1000>; 2791 #interconnect-cells = <2>; 2792 qcom,bcm-voters = <&apps_bcm_voter>; 2793 }; 2794 2795 mdss: mdss@ae00000 { 2796 compatible = "qcom,sc7180-mdss"; 2797 reg = <0 0x0ae00000 0 0x1000>; 2798 reg-names = "mdss"; 2799 2800 power-domains = <&dispcc MDSS_GDSC>; 2801 2802 clocks = <&gcc GCC_DISP_AHB_CLK>, 2803 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2804 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2805 clock-names = "iface", "ahb", "core"; 2806 2807 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2808 assigned-clock-rates = <300000000>; 2809 2810 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2811 interrupt-controller; 2812 #interrupt-cells = <1>; 2813 2814 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; 2815 interconnect-names = "mdp0-mem"; 2816 2817 iommus = <&apps_smmu 0x800 0x2>; 2818 2819 #address-cells = <2>; 2820 #size-cells = <2>; 2821 ranges; 2822 2823 status = "disabled"; 2824 2825 mdp: mdp@ae01000 { 2826 compatible = "qcom,sc7180-dpu"; 2827 reg = <0 0x0ae01000 0 0x8f000>, 2828 <0 0x0aeb0000 0 0x2008>; 2829 reg-names = "mdp", "vbif"; 2830 2831 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2832 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2833 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2834 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2835 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2836 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2837 clock-names = "bus", "iface", "rot", "lut", "core", 2838 "vsync"; 2839 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2840 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2841 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2842 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2843 assigned-clock-rates = <300000000>, 2844 <19200000>, 2845 <19200000>, 2846 <19200000>; 2847 operating-points-v2 = <&mdp_opp_table>; 2848 power-domains = <&rpmhpd SC7180_CX>; 2849 2850 interrupt-parent = <&mdss>; 2851 interrupts = <0>; 2852 2853 status = "disabled"; 2854 2855 ports { 2856 #address-cells = <1>; 2857 #size-cells = <0>; 2858 2859 port@0 { 2860 reg = <0>; 2861 dpu_intf1_out: endpoint { 2862 remote-endpoint = <&dsi0_in>; 2863 }; 2864 }; 2865 }; 2866 2867 mdp_opp_table: mdp-opp-table { 2868 compatible = "operating-points-v2"; 2869 2870 opp-200000000 { 2871 opp-hz = /bits/ 64 <200000000>; 2872 required-opps = <&rpmhpd_opp_low_svs>; 2873 }; 2874 2875 opp-300000000 { 2876 opp-hz = /bits/ 64 <300000000>; 2877 required-opps = <&rpmhpd_opp_svs>; 2878 }; 2879 2880 opp-345000000 { 2881 opp-hz = /bits/ 64 <345000000>; 2882 required-opps = <&rpmhpd_opp_svs_l1>; 2883 }; 2884 2885 opp-460000000 { 2886 opp-hz = /bits/ 64 <460000000>; 2887 required-opps = <&rpmhpd_opp_nom>; 2888 }; 2889 }; 2890 2891 }; 2892 2893 dsi0: dsi@ae94000 { 2894 compatible = "qcom,mdss-dsi-ctrl"; 2895 reg = <0 0x0ae94000 0 0x400>; 2896 reg-names = "dsi_ctrl"; 2897 2898 interrupt-parent = <&mdss>; 2899 interrupts = <4>; 2900 2901 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2902 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2903 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2904 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2905 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2906 <&gcc GCC_DISP_HF_AXI_CLK>; 2907 clock-names = "byte", 2908 "byte_intf", 2909 "pixel", 2910 "core", 2911 "iface", 2912 "bus"; 2913 2914 operating-points-v2 = <&dsi_opp_table>; 2915 power-domains = <&rpmhpd SC7180_CX>; 2916 2917 phys = <&dsi_phy>; 2918 phy-names = "dsi"; 2919 2920 #address-cells = <1>; 2921 #size-cells = <0>; 2922 2923 status = "disabled"; 2924 2925 ports { 2926 #address-cells = <1>; 2927 #size-cells = <0>; 2928 2929 port@0 { 2930 reg = <0>; 2931 dsi0_in: endpoint { 2932 remote-endpoint = <&dpu_intf1_out>; 2933 }; 2934 }; 2935 2936 port@1 { 2937 reg = <1>; 2938 dsi0_out: endpoint { 2939 }; 2940 }; 2941 }; 2942 2943 dsi_opp_table: dsi-opp-table { 2944 compatible = "operating-points-v2"; 2945 2946 opp-187500000 { 2947 opp-hz = /bits/ 64 <187500000>; 2948 required-opps = <&rpmhpd_opp_low_svs>; 2949 }; 2950 2951 opp-300000000 { 2952 opp-hz = /bits/ 64 <300000000>; 2953 required-opps = <&rpmhpd_opp_svs>; 2954 }; 2955 2956 opp-358000000 { 2957 opp-hz = /bits/ 64 <358000000>; 2958 required-opps = <&rpmhpd_opp_svs_l1>; 2959 }; 2960 }; 2961 }; 2962 2963 dsi_phy: dsi-phy@ae94400 { 2964 compatible = "qcom,dsi-phy-10nm"; 2965 reg = <0 0x0ae94400 0 0x200>, 2966 <0 0x0ae94600 0 0x280>, 2967 <0 0x0ae94a00 0 0x1e0>; 2968 reg-names = "dsi_phy", 2969 "dsi_phy_lane", 2970 "dsi_pll"; 2971 2972 #clock-cells = <1>; 2973 #phy-cells = <0>; 2974 2975 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2976 <&rpmhcc RPMH_CXO_CLK>; 2977 clock-names = "iface", "ref"; 2978 2979 status = "disabled"; 2980 }; 2981 }; 2982 2983 dispcc: clock-controller@af00000 { 2984 compatible = "qcom,sc7180-dispcc"; 2985 reg = <0 0x0af00000 0 0x200000>; 2986 clocks = <&rpmhcc RPMH_CXO_CLK>, 2987 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2988 <&dsi_phy 0>, 2989 <&dsi_phy 1>, 2990 <0>, 2991 <0>; 2992 clock-names = "bi_tcxo", 2993 "gcc_disp_gpll0_clk_src", 2994 "dsi0_phy_pll_out_byteclk", 2995 "dsi0_phy_pll_out_dsiclk", 2996 "dp_phy_pll_link_clk", 2997 "dp_phy_pll_vco_div_clk"; 2998 #clock-cells = <1>; 2999 #reset-cells = <1>; 3000 #power-domain-cells = <1>; 3001 }; 3002 3003 pdc: interrupt-controller@b220000 { 3004 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3005 reg = <0 0x0b220000 0 0x30000>; 3006 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3007 #interrupt-cells = <2>; 3008 interrupt-parent = <&intc>; 3009 interrupt-controller; 3010 }; 3011 3012 pdc_reset: reset-controller@b2e0000 { 3013 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3014 reg = <0 0x0b2e0000 0 0x20000>; 3015 #reset-cells = <1>; 3016 }; 3017 3018 tsens0: thermal-sensor@c263000 { 3019 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3020 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3021 <0 0x0c222000 0 0x1ff>; /* SROT */ 3022 #qcom,sensors = <15>; 3023 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3025 interrupt-names = "uplow","critical"; 3026 #thermal-sensor-cells = <1>; 3027 }; 3028 3029 tsens1: thermal-sensor@c265000 { 3030 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3031 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3032 <0 0x0c223000 0 0x1ff>; /* SROT */ 3033 #qcom,sensors = <10>; 3034 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3036 interrupt-names = "uplow","critical"; 3037 #thermal-sensor-cells = <1>; 3038 }; 3039 3040 aoss_reset: reset-controller@c2a0000 { 3041 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3042 reg = <0 0x0c2a0000 0 0x31000>; 3043 #reset-cells = <1>; 3044 }; 3045 3046 aoss_qmp: qmp@c300000 { 3047 compatible = "qcom,sc7180-aoss-qmp"; 3048 reg = <0 0x0c300000 0 0x100000>; 3049 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3050 mboxes = <&apss_shared 0>; 3051 3052 #clock-cells = <0>; 3053 #power-domain-cells = <1>; 3054 }; 3055 3056 spmi_bus: spmi@c440000 { 3057 compatible = "qcom,spmi-pmic-arb"; 3058 reg = <0 0x0c440000 0 0x1100>, 3059 <0 0x0c600000 0 0x2000000>, 3060 <0 0x0e600000 0 0x100000>, 3061 <0 0x0e700000 0 0xa0000>, 3062 <0 0x0c40a000 0 0x26000>; 3063 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3064 interrupt-names = "periph_irq"; 3065 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3066 qcom,ee = <0>; 3067 qcom,channel = <0>; 3068 #address-cells = <1>; 3069 #size-cells = <1>; 3070 interrupt-controller; 3071 #interrupt-cells = <4>; 3072 cell-index = <0>; 3073 }; 3074 3075 apps_smmu: iommu@15000000 { 3076 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3077 reg = <0 0x15000000 0 0x100000>; 3078 #iommu-cells = <2>; 3079 #global-interrupts = <1>; 3080 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3161 }; 3162 3163 intc: interrupt-controller@17a00000 { 3164 compatible = "arm,gic-v3"; 3165 #address-cells = <2>; 3166 #size-cells = <2>; 3167 ranges; 3168 #interrupt-cells = <3>; 3169 interrupt-controller; 3170 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3171 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3172 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3173 3174 msi-controller@17a40000 { 3175 compatible = "arm,gic-v3-its"; 3176 msi-controller; 3177 #msi-cells = <1>; 3178 reg = <0 0x17a40000 0 0x20000>; 3179 status = "disabled"; 3180 }; 3181 }; 3182 3183 apss_shared: mailbox@17c00000 { 3184 compatible = "qcom,sc7180-apss-shared"; 3185 reg = <0 0x17c00000 0 0x10000>; 3186 #mbox-cells = <1>; 3187 }; 3188 3189 watchdog@17c10000 { 3190 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3191 reg = <0 0x17c10000 0 0x1000>; 3192 clocks = <&sleep_clk>; 3193 }; 3194 3195 timer@17c20000{ 3196 #address-cells = <2>; 3197 #size-cells = <2>; 3198 ranges; 3199 compatible = "arm,armv7-timer-mem"; 3200 reg = <0 0x17c20000 0 0x1000>; 3201 3202 frame@17c21000 { 3203 frame-number = <0>; 3204 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3206 reg = <0 0x17c21000 0 0x1000>, 3207 <0 0x17c22000 0 0x1000>; 3208 }; 3209 3210 frame@17c23000 { 3211 frame-number = <1>; 3212 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3213 reg = <0 0x17c23000 0 0x1000>; 3214 status = "disabled"; 3215 }; 3216 3217 frame@17c25000 { 3218 frame-number = <2>; 3219 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3220 reg = <0 0x17c25000 0 0x1000>; 3221 status = "disabled"; 3222 }; 3223 3224 frame@17c27000 { 3225 frame-number = <3>; 3226 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3227 reg = <0 0x17c27000 0 0x1000>; 3228 status = "disabled"; 3229 }; 3230 3231 frame@17c29000 { 3232 frame-number = <4>; 3233 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3234 reg = <0 0x17c29000 0 0x1000>; 3235 status = "disabled"; 3236 }; 3237 3238 frame@17c2b000 { 3239 frame-number = <5>; 3240 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3241 reg = <0 0x17c2b000 0 0x1000>; 3242 status = "disabled"; 3243 }; 3244 3245 frame@17c2d000 { 3246 frame-number = <6>; 3247 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3248 reg = <0 0x17c2d000 0 0x1000>; 3249 status = "disabled"; 3250 }; 3251 }; 3252 3253 apps_rsc: rsc@18200000 { 3254 compatible = "qcom,rpmh-rsc"; 3255 reg = <0 0x18200000 0 0x10000>, 3256 <0 0x18210000 0 0x10000>, 3257 <0 0x18220000 0 0x10000>; 3258 reg-names = "drv-0", "drv-1", "drv-2"; 3259 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3262 qcom,tcs-offset = <0xd00>; 3263 qcom,drv-id = <2>; 3264 qcom,tcs-config = <ACTIVE_TCS 2>, 3265 <SLEEP_TCS 3>, 3266 <WAKE_TCS 3>, 3267 <CONTROL_TCS 1>; 3268 3269 rpmhcc: clock-controller { 3270 compatible = "qcom,sc7180-rpmh-clk"; 3271 clocks = <&xo_board>; 3272 clock-names = "xo"; 3273 #clock-cells = <1>; 3274 }; 3275 3276 rpmhpd: power-controller { 3277 compatible = "qcom,sc7180-rpmhpd"; 3278 #power-domain-cells = <1>; 3279 operating-points-v2 = <&rpmhpd_opp_table>; 3280 3281 rpmhpd_opp_table: opp-table { 3282 compatible = "operating-points-v2"; 3283 3284 rpmhpd_opp_ret: opp1 { 3285 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3286 }; 3287 3288 rpmhpd_opp_min_svs: opp2 { 3289 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3290 }; 3291 3292 rpmhpd_opp_low_svs: opp3 { 3293 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3294 }; 3295 3296 rpmhpd_opp_svs: opp4 { 3297 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3298 }; 3299 3300 rpmhpd_opp_svs_l1: opp5 { 3301 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3302 }; 3303 3304 rpmhpd_opp_svs_l2: opp6 { 3305 opp-level = <224>; 3306 }; 3307 3308 rpmhpd_opp_nom: opp7 { 3309 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3310 }; 3311 3312 rpmhpd_opp_nom_l1: opp8 { 3313 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3314 }; 3315 3316 rpmhpd_opp_nom_l2: opp9 { 3317 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3318 }; 3319 3320 rpmhpd_opp_turbo: opp10 { 3321 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3322 }; 3323 3324 rpmhpd_opp_turbo_l1: opp11 { 3325 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3326 }; 3327 }; 3328 }; 3329 3330 apps_bcm_voter: bcm_voter { 3331 compatible = "qcom,bcm-voter"; 3332 }; 3333 }; 3334 3335 osm_l3: interconnect@18321000 { 3336 compatible = "qcom,sc7180-osm-l3"; 3337 reg = <0 0x18321000 0 0x1400>; 3338 3339 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3340 clock-names = "xo", "alternate"; 3341 3342 #interconnect-cells = <1>; 3343 }; 3344 3345 cpufreq_hw: cpufreq@18323000 { 3346 compatible = "qcom,cpufreq-hw"; 3347 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3348 reg-names = "freq-domain0", "freq-domain1"; 3349 3350 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3351 clock-names = "xo", "alternate"; 3352 3353 #freq-domain-cells = <1>; 3354 }; 3355 3356 wifi: wifi@18800000 { 3357 compatible = "qcom,wcn3990-wifi"; 3358 reg = <0 0x18800000 0 0x800000>; 3359 reg-names = "membase"; 3360 iommus = <&apps_smmu 0xc0 0x1>; 3361 interrupts = 3362 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3363 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3364 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3365 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3366 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3367 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3368 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3369 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3370 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3371 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3372 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3373 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3374 memory-region = <&wlan_mem>; 3375 qcom,msa-fixed-perm; 3376 status = "disabled"; 3377 }; 3378 3379 lpasscc: clock-controller@62d00000 { 3380 compatible = "qcom,sc7180-lpasscorecc"; 3381 reg = <0 0x62d00000 0 0x50000>, 3382 <0 0x62780000 0 0x30000>; 3383 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3384 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3385 <&rpmhcc RPMH_CXO_CLK>; 3386 clock-names = "iface", "bi_tcxo"; 3387 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3388 #clock-cells = <1>; 3389 #power-domain-cells = <1>; 3390 }; 3391 3392 lpass_hm: clock-controller@63000000 { 3393 compatible = "qcom,sc7180-lpasshm"; 3394 reg = <0 0x63000000 0 0x28>; 3395 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3396 <&rpmhcc RPMH_CXO_CLK>; 3397 clock-names = "iface", "bi_tcxo"; 3398 #clock-cells = <1>; 3399 #power-domain-cells = <1>; 3400 }; 3401 }; 3402 3403 thermal-zones { 3404 cpu0-thermal { 3405 polling-delay-passive = <0>; 3406 polling-delay = <0>; 3407 3408 thermal-sensors = <&tsens0 1>; 3409 sustainable-power = <768>; 3410 3411 trips { 3412 cpu0_alert0: trip-point0 { 3413 temperature = <90000>; 3414 hysteresis = <2000>; 3415 type = "passive"; 3416 }; 3417 3418 cpu0_alert1: trip-point1 { 3419 temperature = <95000>; 3420 hysteresis = <2000>; 3421 type = "passive"; 3422 }; 3423 3424 cpu0_crit: cpu_crit { 3425 temperature = <110000>; 3426 hysteresis = <1000>; 3427 type = "critical"; 3428 }; 3429 }; 3430 3431 cooling-maps { 3432 map0 { 3433 trip = <&cpu0_alert0>; 3434 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3435 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3436 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3437 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3438 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3439 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3440 }; 3441 map1 { 3442 trip = <&cpu0_alert1>; 3443 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3444 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3445 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3446 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3447 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3448 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3449 }; 3450 }; 3451 }; 3452 3453 cpu1-thermal { 3454 polling-delay-passive = <0>; 3455 polling-delay = <0>; 3456 3457 thermal-sensors = <&tsens0 2>; 3458 sustainable-power = <768>; 3459 3460 trips { 3461 cpu1_alert0: trip-point0 { 3462 temperature = <90000>; 3463 hysteresis = <2000>; 3464 type = "passive"; 3465 }; 3466 3467 cpu1_alert1: trip-point1 { 3468 temperature = <95000>; 3469 hysteresis = <2000>; 3470 type = "passive"; 3471 }; 3472 3473 cpu1_crit: cpu_crit { 3474 temperature = <110000>; 3475 hysteresis = <1000>; 3476 type = "critical"; 3477 }; 3478 }; 3479 3480 cooling-maps { 3481 map0 { 3482 trip = <&cpu1_alert0>; 3483 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3484 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3485 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3486 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3487 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3488 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3489 }; 3490 map1 { 3491 trip = <&cpu1_alert1>; 3492 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3493 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3494 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3495 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3496 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3497 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3498 }; 3499 }; 3500 }; 3501 3502 cpu2-thermal { 3503 polling-delay-passive = <0>; 3504 polling-delay = <0>; 3505 3506 thermal-sensors = <&tsens0 3>; 3507 sustainable-power = <768>; 3508 3509 trips { 3510 cpu2_alert0: trip-point0 { 3511 temperature = <90000>; 3512 hysteresis = <2000>; 3513 type = "passive"; 3514 }; 3515 3516 cpu2_alert1: trip-point1 { 3517 temperature = <95000>; 3518 hysteresis = <2000>; 3519 type = "passive"; 3520 }; 3521 3522 cpu2_crit: cpu_crit { 3523 temperature = <110000>; 3524 hysteresis = <1000>; 3525 type = "critical"; 3526 }; 3527 }; 3528 3529 cooling-maps { 3530 map0 { 3531 trip = <&cpu2_alert0>; 3532 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3533 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3534 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3535 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3536 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3537 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3538 }; 3539 map1 { 3540 trip = <&cpu2_alert1>; 3541 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3542 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3543 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3544 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3545 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3546 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3547 }; 3548 }; 3549 }; 3550 3551 cpu3-thermal { 3552 polling-delay-passive = <0>; 3553 polling-delay = <0>; 3554 3555 thermal-sensors = <&tsens0 4>; 3556 sustainable-power = <768>; 3557 3558 trips { 3559 cpu3_alert0: trip-point0 { 3560 temperature = <90000>; 3561 hysteresis = <2000>; 3562 type = "passive"; 3563 }; 3564 3565 cpu3_alert1: trip-point1 { 3566 temperature = <95000>; 3567 hysteresis = <2000>; 3568 type = "passive"; 3569 }; 3570 3571 cpu3_crit: cpu_crit { 3572 temperature = <110000>; 3573 hysteresis = <1000>; 3574 type = "critical"; 3575 }; 3576 }; 3577 3578 cooling-maps { 3579 map0 { 3580 trip = <&cpu3_alert0>; 3581 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3582 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3583 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3584 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3585 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3586 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3587 }; 3588 map1 { 3589 trip = <&cpu3_alert1>; 3590 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3591 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3592 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3593 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3594 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3595 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3596 }; 3597 }; 3598 }; 3599 3600 cpu4-thermal { 3601 polling-delay-passive = <0>; 3602 polling-delay = <0>; 3603 3604 thermal-sensors = <&tsens0 5>; 3605 sustainable-power = <768>; 3606 3607 trips { 3608 cpu4_alert0: trip-point0 { 3609 temperature = <90000>; 3610 hysteresis = <2000>; 3611 type = "passive"; 3612 }; 3613 3614 cpu4_alert1: trip-point1 { 3615 temperature = <95000>; 3616 hysteresis = <2000>; 3617 type = "passive"; 3618 }; 3619 3620 cpu4_crit: cpu_crit { 3621 temperature = <110000>; 3622 hysteresis = <1000>; 3623 type = "critical"; 3624 }; 3625 }; 3626 3627 cooling-maps { 3628 map0 { 3629 trip = <&cpu4_alert0>; 3630 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3631 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3632 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3633 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3634 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3635 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3636 }; 3637 map1 { 3638 trip = <&cpu4_alert1>; 3639 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3640 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3641 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3642 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3643 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3644 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3645 }; 3646 }; 3647 }; 3648 3649 cpu5-thermal { 3650 polling-delay-passive = <0>; 3651 polling-delay = <0>; 3652 3653 thermal-sensors = <&tsens0 6>; 3654 sustainable-power = <768>; 3655 3656 trips { 3657 cpu5_alert0: trip-point0 { 3658 temperature = <90000>; 3659 hysteresis = <2000>; 3660 type = "passive"; 3661 }; 3662 3663 cpu5_alert1: trip-point1 { 3664 temperature = <95000>; 3665 hysteresis = <2000>; 3666 type = "passive"; 3667 }; 3668 3669 cpu5_crit: cpu_crit { 3670 temperature = <110000>; 3671 hysteresis = <1000>; 3672 type = "critical"; 3673 }; 3674 }; 3675 3676 cooling-maps { 3677 map0 { 3678 trip = <&cpu5_alert0>; 3679 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3680 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3681 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3682 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3683 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3684 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3685 }; 3686 map1 { 3687 trip = <&cpu5_alert1>; 3688 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3689 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3690 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3691 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3692 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3694 }; 3695 }; 3696 }; 3697 3698 cpu6-thermal { 3699 polling-delay-passive = <0>; 3700 polling-delay = <0>; 3701 3702 thermal-sensors = <&tsens0 9>; 3703 sustainable-power = <1202>; 3704 3705 trips { 3706 cpu6_alert0: trip-point0 { 3707 temperature = <90000>; 3708 hysteresis = <2000>; 3709 type = "passive"; 3710 }; 3711 3712 cpu6_alert1: trip-point1 { 3713 temperature = <95000>; 3714 hysteresis = <2000>; 3715 type = "passive"; 3716 }; 3717 3718 cpu6_crit: cpu_crit { 3719 temperature = <110000>; 3720 hysteresis = <1000>; 3721 type = "critical"; 3722 }; 3723 }; 3724 3725 cooling-maps { 3726 map0 { 3727 trip = <&cpu6_alert0>; 3728 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3729 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3730 }; 3731 map1 { 3732 trip = <&cpu6_alert1>; 3733 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3734 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3735 }; 3736 }; 3737 }; 3738 3739 cpu7-thermal { 3740 polling-delay-passive = <0>; 3741 polling-delay = <0>; 3742 3743 thermal-sensors = <&tsens0 10>; 3744 sustainable-power = <1202>; 3745 3746 trips { 3747 cpu7_alert0: trip-point0 { 3748 temperature = <90000>; 3749 hysteresis = <2000>; 3750 type = "passive"; 3751 }; 3752 3753 cpu7_alert1: trip-point1 { 3754 temperature = <95000>; 3755 hysteresis = <2000>; 3756 type = "passive"; 3757 }; 3758 3759 cpu7_crit: cpu_crit { 3760 temperature = <110000>; 3761 hysteresis = <1000>; 3762 type = "critical"; 3763 }; 3764 }; 3765 3766 cooling-maps { 3767 map0 { 3768 trip = <&cpu7_alert0>; 3769 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3770 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3771 }; 3772 map1 { 3773 trip = <&cpu7_alert1>; 3774 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3776 }; 3777 }; 3778 }; 3779 3780 cpu8-thermal { 3781 polling-delay-passive = <0>; 3782 polling-delay = <0>; 3783 3784 thermal-sensors = <&tsens0 11>; 3785 sustainable-power = <1202>; 3786 3787 trips { 3788 cpu8_alert0: trip-point0 { 3789 temperature = <90000>; 3790 hysteresis = <2000>; 3791 type = "passive"; 3792 }; 3793 3794 cpu8_alert1: trip-point1 { 3795 temperature = <95000>; 3796 hysteresis = <2000>; 3797 type = "passive"; 3798 }; 3799 3800 cpu8_crit: cpu_crit { 3801 temperature = <110000>; 3802 hysteresis = <1000>; 3803 type = "critical"; 3804 }; 3805 }; 3806 3807 cooling-maps { 3808 map0 { 3809 trip = <&cpu8_alert0>; 3810 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3812 }; 3813 map1 { 3814 trip = <&cpu8_alert1>; 3815 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3816 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3817 }; 3818 }; 3819 }; 3820 3821 cpu9-thermal { 3822 polling-delay-passive = <0>; 3823 polling-delay = <0>; 3824 3825 thermal-sensors = <&tsens0 12>; 3826 sustainable-power = <1202>; 3827 3828 trips { 3829 cpu9_alert0: trip-point0 { 3830 temperature = <90000>; 3831 hysteresis = <2000>; 3832 type = "passive"; 3833 }; 3834 3835 cpu9_alert1: trip-point1 { 3836 temperature = <95000>; 3837 hysteresis = <2000>; 3838 type = "passive"; 3839 }; 3840 3841 cpu9_crit: cpu_crit { 3842 temperature = <110000>; 3843 hysteresis = <1000>; 3844 type = "critical"; 3845 }; 3846 }; 3847 3848 cooling-maps { 3849 map0 { 3850 trip = <&cpu9_alert0>; 3851 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3853 }; 3854 map1 { 3855 trip = <&cpu9_alert1>; 3856 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3858 }; 3859 }; 3860 }; 3861 3862 aoss0-thermal { 3863 polling-delay-passive = <0>; 3864 polling-delay = <0>; 3865 3866 thermal-sensors = <&tsens0 0>; 3867 3868 trips { 3869 aoss0_alert0: trip-point0 { 3870 temperature = <90000>; 3871 hysteresis = <2000>; 3872 type = "hot"; 3873 }; 3874 3875 aoss0_crit: aoss0_crit { 3876 temperature = <110000>; 3877 hysteresis = <2000>; 3878 type = "critical"; 3879 }; 3880 }; 3881 }; 3882 3883 cpuss0-thermal { 3884 polling-delay-passive = <0>; 3885 polling-delay = <0>; 3886 3887 thermal-sensors = <&tsens0 7>; 3888 3889 trips { 3890 cpuss0_alert0: trip-point0 { 3891 temperature = <90000>; 3892 hysteresis = <2000>; 3893 type = "hot"; 3894 }; 3895 cpuss0_crit: cluster0_crit { 3896 temperature = <110000>; 3897 hysteresis = <2000>; 3898 type = "critical"; 3899 }; 3900 }; 3901 }; 3902 3903 cpuss1-thermal { 3904 polling-delay-passive = <0>; 3905 polling-delay = <0>; 3906 3907 thermal-sensors = <&tsens0 8>; 3908 3909 trips { 3910 cpuss1_alert0: trip-point0 { 3911 temperature = <90000>; 3912 hysteresis = <2000>; 3913 type = "hot"; 3914 }; 3915 cpuss1_crit: cluster0_crit { 3916 temperature = <110000>; 3917 hysteresis = <2000>; 3918 type = "critical"; 3919 }; 3920 }; 3921 }; 3922 3923 gpuss0-thermal { 3924 polling-delay-passive = <0>; 3925 polling-delay = <0>; 3926 3927 thermal-sensors = <&tsens0 13>; 3928 3929 trips { 3930 gpuss0_alert0: trip-point0 { 3931 temperature = <90000>; 3932 hysteresis = <2000>; 3933 type = "hot"; 3934 }; 3935 3936 gpuss0_crit: gpuss0_crit { 3937 temperature = <110000>; 3938 hysteresis = <2000>; 3939 type = "critical"; 3940 }; 3941 }; 3942 }; 3943 3944 gpuss1-thermal { 3945 polling-delay-passive = <0>; 3946 polling-delay = <0>; 3947 3948 thermal-sensors = <&tsens0 14>; 3949 3950 trips { 3951 gpuss1_alert0: trip-point0 { 3952 temperature = <90000>; 3953 hysteresis = <2000>; 3954 type = "hot"; 3955 }; 3956 3957 gpuss1_crit: gpuss1_crit { 3958 temperature = <110000>; 3959 hysteresis = <2000>; 3960 type = "critical"; 3961 }; 3962 }; 3963 }; 3964 3965 aoss1-thermal { 3966 polling-delay-passive = <0>; 3967 polling-delay = <0>; 3968 3969 thermal-sensors = <&tsens1 0>; 3970 3971 trips { 3972 aoss1_alert0: trip-point0 { 3973 temperature = <90000>; 3974 hysteresis = <2000>; 3975 type = "hot"; 3976 }; 3977 3978 aoss1_crit: aoss1_crit { 3979 temperature = <110000>; 3980 hysteresis = <2000>; 3981 type = "critical"; 3982 }; 3983 }; 3984 }; 3985 3986 cwlan-thermal { 3987 polling-delay-passive = <0>; 3988 polling-delay = <0>; 3989 3990 thermal-sensors = <&tsens1 1>; 3991 3992 trips { 3993 cwlan_alert0: trip-point0 { 3994 temperature = <90000>; 3995 hysteresis = <2000>; 3996 type = "hot"; 3997 }; 3998 3999 cwlan_crit: cwlan_crit { 4000 temperature = <110000>; 4001 hysteresis = <2000>; 4002 type = "critical"; 4003 }; 4004 }; 4005 }; 4006 4007 audio-thermal { 4008 polling-delay-passive = <0>; 4009 polling-delay = <0>; 4010 4011 thermal-sensors = <&tsens1 2>; 4012 4013 trips { 4014 audio_alert0: trip-point0 { 4015 temperature = <90000>; 4016 hysteresis = <2000>; 4017 type = "hot"; 4018 }; 4019 4020 audio_crit: audio_crit { 4021 temperature = <110000>; 4022 hysteresis = <2000>; 4023 type = "critical"; 4024 }; 4025 }; 4026 }; 4027 4028 ddr-thermal { 4029 polling-delay-passive = <0>; 4030 polling-delay = <0>; 4031 4032 thermal-sensors = <&tsens1 3>; 4033 4034 trips { 4035 ddr_alert0: trip-point0 { 4036 temperature = <90000>; 4037 hysteresis = <2000>; 4038 type = "hot"; 4039 }; 4040 4041 ddr_crit: ddr_crit { 4042 temperature = <110000>; 4043 hysteresis = <2000>; 4044 type = "critical"; 4045 }; 4046 }; 4047 }; 4048 4049 q6-hvx-thermal { 4050 polling-delay-passive = <0>; 4051 polling-delay = <0>; 4052 4053 thermal-sensors = <&tsens1 4>; 4054 4055 trips { 4056 q6_hvx_alert0: trip-point0 { 4057 temperature = <90000>; 4058 hysteresis = <2000>; 4059 type = "hot"; 4060 }; 4061 4062 q6_hvx_crit: q6_hvx_crit { 4063 temperature = <110000>; 4064 hysteresis = <2000>; 4065 type = "critical"; 4066 }; 4067 }; 4068 }; 4069 4070 camera-thermal { 4071 polling-delay-passive = <0>; 4072 polling-delay = <0>; 4073 4074 thermal-sensors = <&tsens1 5>; 4075 4076 trips { 4077 camera_alert0: trip-point0 { 4078 temperature = <90000>; 4079 hysteresis = <2000>; 4080 type = "hot"; 4081 }; 4082 4083 camera_crit: camera_crit { 4084 temperature = <110000>; 4085 hysteresis = <2000>; 4086 type = "critical"; 4087 }; 4088 }; 4089 }; 4090 4091 mdm-core-thermal { 4092 polling-delay-passive = <0>; 4093 polling-delay = <0>; 4094 4095 thermal-sensors = <&tsens1 6>; 4096 4097 trips { 4098 mdm_alert0: trip-point0 { 4099 temperature = <90000>; 4100 hysteresis = <2000>; 4101 type = "hot"; 4102 }; 4103 4104 mdm_crit: mdm_crit { 4105 temperature = <110000>; 4106 hysteresis = <2000>; 4107 type = "critical"; 4108 }; 4109 }; 4110 }; 4111 4112 mdm-dsp-thermal { 4113 polling-delay-passive = <0>; 4114 polling-delay = <0>; 4115 4116 thermal-sensors = <&tsens1 7>; 4117 4118 trips { 4119 mdm_dsp_alert0: trip-point0 { 4120 temperature = <90000>; 4121 hysteresis = <2000>; 4122 type = "hot"; 4123 }; 4124 4125 mdm_dsp_crit: mdm_dsp_crit { 4126 temperature = <110000>; 4127 hysteresis = <2000>; 4128 type = "critical"; 4129 }; 4130 }; 4131 }; 4132 4133 npu-thermal { 4134 polling-delay-passive = <0>; 4135 polling-delay = <0>; 4136 4137 thermal-sensors = <&tsens1 8>; 4138 4139 trips { 4140 npu_alert0: trip-point0 { 4141 temperature = <90000>; 4142 hysteresis = <2000>; 4143 type = "hot"; 4144 }; 4145 4146 npu_crit: npu_crit { 4147 temperature = <110000>; 4148 hysteresis = <2000>; 4149 type = "critical"; 4150 }; 4151 }; 4152 }; 4153 4154 video-thermal { 4155 polling-delay-passive = <0>; 4156 polling-delay = <0>; 4157 4158 thermal-sensors = <&tsens1 9>; 4159 4160 trips { 4161 video_alert0: trip-point0 { 4162 temperature = <90000>; 4163 hysteresis = <2000>; 4164 type = "hot"; 4165 }; 4166 4167 video_crit: video_crit { 4168 temperature = <110000>; 4169 hysteresis = <2000>; 4170 type = "critical"; 4171 }; 4172 }; 4173 }; 4174 }; 4175 4176 timer { 4177 compatible = "arm,armv8-timer"; 4178 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4179 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4180 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4181 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4182 }; 4183}; 4184