1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 aliases { 33 mmc1 = &sdhc_1; 34 mmc2 = &sdhc_2; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi3 = &spi3; 50 spi5 = &spi5; 51 spi6 = &spi6; 52 spi8 = &spi8; 53 spi10 = &spi10; 54 spi11 = &spi11; 55 }; 56 57 clocks { 58 xo_board: xo-board { 59 compatible = "fixed-clock"; 60 clock-frequency = <38400000>; 61 #clock-cells = <0>; 62 }; 63 64 sleep_clk: sleep-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <32764>; 67 #clock-cells = <0>; 68 }; 69 }; 70 71 reserved_memory: reserved-memory { 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 hyp_mem: memory@80000000 { 77 reg = <0x0 0x80000000 0x0 0x600000>; 78 no-map; 79 }; 80 81 xbl_mem: memory@80600000 { 82 reg = <0x0 0x80600000 0x0 0x200000>; 83 no-map; 84 }; 85 86 aop_mem: memory@80800000 { 87 reg = <0x0 0x80800000 0x0 0x20000>; 88 no-map; 89 }; 90 91 aop_cmd_db_mem: memory@80820000 { 92 reg = <0x0 0x80820000 0x0 0x20000>; 93 compatible = "qcom,cmd-db"; 94 no-map; 95 }; 96 97 sec_apps_mem: memory@808ff000 { 98 reg = <0x0 0x808ff000 0x0 0x1000>; 99 no-map; 100 }; 101 102 smem_mem: memory@80900000 { 103 reg = <0x0 0x80900000 0x0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@80b00000 { 108 reg = <0x0 0x80b00000 0x0 0x3900000>; 109 no-map; 110 }; 111 112 ipa_fw_mem: memory@8b700000 { 113 reg = <0 0x8b700000 0 0x10000>; 114 no-map; 115 }; 116 117 rmtfs_mem: memory@94600000 { 118 compatible = "qcom,rmtfs-mem"; 119 reg = <0x0 0x94600000 0x0 0x200000>; 120 no-map; 121 122 qcom,client-id = <1>; 123 qcom,vmid = <15>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <2>; 129 #size-cells = <0>; 130 131 CPU0: cpu@0 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo468"; 134 reg = <0x0 0x0>; 135 enable-method = "psci"; 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 137 &LITTLE_CPU_SLEEP_1 138 &CLUSTER_SLEEP_0>; 139 capacity-dmips-mhz = <415>; 140 dynamic-power-coefficient = <137>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 144 next-level-cache = <&L2_0>; 145 #cooling-cells = <2>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 L2_0: l2-cache { 148 compatible = "cache"; 149 next-level-cache = <&L3_0>; 150 L3_0: l3-cache { 151 compatible = "cache"; 152 }; 153 }; 154 }; 155 156 CPU1: cpu@100 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo468"; 159 reg = <0x0 0x100>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 capacity-dmips-mhz = <415>; 165 dynamic-power-coefficient = <137>; 166 next-level-cache = <&L2_100>; 167 operating-points-v2 = <&cpu0_opp_table>; 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 #cooling-cells = <2>; 171 qcom,freq-domain = <&cpufreq_hw 0>; 172 L2_100: l2-cache { 173 compatible = "cache"; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU2: cpu@200 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo468"; 181 reg = <0x0 0x200>; 182 enable-method = "psci"; 183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 184 &LITTLE_CPU_SLEEP_1 185 &CLUSTER_SLEEP_0>; 186 capacity-dmips-mhz = <415>; 187 dynamic-power-coefficient = <137>; 188 next-level-cache = <&L2_200>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 192 #cooling-cells = <2>; 193 qcom,freq-domain = <&cpufreq_hw 0>; 194 L2_200: l2-cache { 195 compatible = "cache"; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU3: cpu@300 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo468"; 203 reg = <0x0 0x300>; 204 enable-method = "psci"; 205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 206 &LITTLE_CPU_SLEEP_1 207 &CLUSTER_SLEEP_0>; 208 capacity-dmips-mhz = <415>; 209 dynamic-power-coefficient = <137>; 210 next-level-cache = <&L2_300>; 211 operating-points-v2 = <&cpu0_opp_table>; 212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 #cooling-cells = <2>; 215 qcom,freq-domain = <&cpufreq_hw 0>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo468"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 228 &LITTLE_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 capacity-dmips-mhz = <415>; 231 dynamic-power-coefficient = <137>; 232 next-level-cache = <&L2_400>; 233 operating-points-v2 = <&cpu0_opp_table>; 234 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 236 #cooling-cells = <2>; 237 qcom,freq-domain = <&cpufreq_hw 0>; 238 L2_400: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU5: cpu@500 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo468"; 247 reg = <0x0 0x500>; 248 enable-method = "psci"; 249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 250 &LITTLE_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252 capacity-dmips-mhz = <415>; 253 dynamic-power-coefficient = <137>; 254 next-level-cache = <&L2_500>; 255 operating-points-v2 = <&cpu0_opp_table>; 256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 257 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 258 #cooling-cells = <2>; 259 qcom,freq-domain = <&cpufreq_hw 0>; 260 L2_500: l2-cache { 261 compatible = "cache"; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU6: cpu@600 { 267 device_type = "cpu"; 268 compatible = "qcom,kryo468"; 269 reg = <0x0 0x600>; 270 enable-method = "psci"; 271 cpu-idle-states = <&BIG_CPU_SLEEP_0 272 &BIG_CPU_SLEEP_1 273 &CLUSTER_SLEEP_0>; 274 capacity-dmips-mhz = <1024>; 275 dynamic-power-coefficient = <480>; 276 next-level-cache = <&L2_600>; 277 operating-points-v2 = <&cpu6_opp_table>; 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 280 #cooling-cells = <2>; 281 qcom,freq-domain = <&cpufreq_hw 1>; 282 L2_600: l2-cache { 283 compatible = "cache"; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU7: cpu@700 { 289 device_type = "cpu"; 290 compatible = "qcom,kryo468"; 291 reg = <0x0 0x700>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 capacity-dmips-mhz = <1024>; 297 dynamic-power-coefficient = <480>; 298 next-level-cache = <&L2_700>; 299 operating-points-v2 = <&cpu6_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 302 #cooling-cells = <2>; 303 qcom,freq-domain = <&cpufreq_hw 1>; 304 L2_700: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 cpu-map { 311 cluster0 { 312 core0 { 313 cpu = <&CPU0>; 314 }; 315 316 core1 { 317 cpu = <&CPU1>; 318 }; 319 320 core2 { 321 cpu = <&CPU2>; 322 }; 323 324 core3 { 325 cpu = <&CPU3>; 326 }; 327 328 core4 { 329 cpu = <&CPU4>; 330 }; 331 332 core5 { 333 cpu = <&CPU5>; 334 }; 335 336 core6 { 337 cpu = <&CPU6>; 338 }; 339 340 core7 { 341 cpu = <&CPU7>; 342 }; 343 }; 344 }; 345 346 idle-states { 347 entry-method = "psci"; 348 349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "little-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <549>; 354 exit-latency-us = <901>; 355 min-residency-us = <1774>; 356 local-timer-stop; 357 }; 358 359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "little-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <702>; 364 exit-latency-us = <915>; 365 min-residency-us = <4001>; 366 local-timer-stop; 367 }; 368 369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "big-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <523>; 374 exit-latency-us = <1244>; 375 min-residency-us = <2207>; 376 local-timer-stop; 377 }; 378 379 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "big-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <526>; 384 exit-latency-us = <1854>; 385 min-residency-us = <5555>; 386 local-timer-stop; 387 }; 388 389 CLUSTER_SLEEP_0: cluster-sleep-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "cluster-power-down"; 392 arm,psci-suspend-param = <0x40003444>; 393 entry-latency-us = <3263>; 394 exit-latency-us = <6562>; 395 min-residency-us = <9926>; 396 local-timer-stop; 397 }; 398 }; 399 }; 400 401 cpu0_opp_table: opp-table-cpu0 { 402 compatible = "operating-points-v2"; 403 opp-shared; 404 405 cpu0_opp1: opp-300000000 { 406 opp-hz = /bits/ 64 <300000000>; 407 opp-peak-kBps = <1200000 4800000>; 408 }; 409 410 cpu0_opp2: opp-576000000 { 411 opp-hz = /bits/ 64 <576000000>; 412 opp-peak-kBps = <1200000 4800000>; 413 }; 414 415 cpu0_opp3: opp-768000000 { 416 opp-hz = /bits/ 64 <768000000>; 417 opp-peak-kBps = <1200000 4800000>; 418 }; 419 420 cpu0_opp4: opp-1017600000 { 421 opp-hz = /bits/ 64 <1017600000>; 422 opp-peak-kBps = <1804000 8908800>; 423 }; 424 425 cpu0_opp5: opp-1248000000 { 426 opp-hz = /bits/ 64 <1248000000>; 427 opp-peak-kBps = <2188000 12902400>; 428 }; 429 430 cpu0_opp6: opp-1324800000 { 431 opp-hz = /bits/ 64 <1324800000>; 432 opp-peak-kBps = <2188000 12902400>; 433 }; 434 435 cpu0_opp7: opp-1516800000 { 436 opp-hz = /bits/ 64 <1516800000>; 437 opp-peak-kBps = <3072000 15052800>; 438 }; 439 440 cpu0_opp8: opp-1612800000 { 441 opp-hz = /bits/ 64 <1612800000>; 442 opp-peak-kBps = <3072000 15052800>; 443 }; 444 445 cpu0_opp9: opp-1708800000 { 446 opp-hz = /bits/ 64 <1708800000>; 447 opp-peak-kBps = <3072000 15052800>; 448 }; 449 450 cpu0_opp10: opp-1804800000 { 451 opp-hz = /bits/ 64 <1804800000>; 452 opp-peak-kBps = <4068000 22425600>; 453 }; 454 }; 455 456 cpu6_opp_table: opp-table-cpu6 { 457 compatible = "operating-points-v2"; 458 opp-shared; 459 460 cpu6_opp1: opp-300000000 { 461 opp-hz = /bits/ 64 <300000000>; 462 opp-peak-kBps = <2188000 8908800>; 463 }; 464 465 cpu6_opp2: opp-652800000 { 466 opp-hz = /bits/ 64 <652800000>; 467 opp-peak-kBps = <2188000 8908800>; 468 }; 469 470 cpu6_opp3: opp-825600000 { 471 opp-hz = /bits/ 64 <825600000>; 472 opp-peak-kBps = <2188000 8908800>; 473 }; 474 475 cpu6_opp4: opp-979200000 { 476 opp-hz = /bits/ 64 <979200000>; 477 opp-peak-kBps = <2188000 8908800>; 478 }; 479 480 cpu6_opp5: opp-1113600000 { 481 opp-hz = /bits/ 64 <1113600000>; 482 opp-peak-kBps = <2188000 8908800>; 483 }; 484 485 cpu6_opp6: opp-1267200000 { 486 opp-hz = /bits/ 64 <1267200000>; 487 opp-peak-kBps = <4068000 12902400>; 488 }; 489 490 cpu6_opp7: opp-1555200000 { 491 opp-hz = /bits/ 64 <1555200000>; 492 opp-peak-kBps = <4068000 15052800>; 493 }; 494 495 cpu6_opp8: opp-1708800000 { 496 opp-hz = /bits/ 64 <1708800000>; 497 opp-peak-kBps = <6220000 19353600>; 498 }; 499 500 cpu6_opp9: opp-1843200000 { 501 opp-hz = /bits/ 64 <1843200000>; 502 opp-peak-kBps = <6220000 19353600>; 503 }; 504 505 cpu6_opp10: opp-1900800000 { 506 opp-hz = /bits/ 64 <1900800000>; 507 opp-peak-kBps = <6220000 22425600>; 508 }; 509 510 cpu6_opp11: opp-1996800000 { 511 opp-hz = /bits/ 64 <1996800000>; 512 opp-peak-kBps = <6220000 22425600>; 513 }; 514 515 cpu6_opp12: opp-2112000000 { 516 opp-hz = /bits/ 64 <2112000000>; 517 opp-peak-kBps = <6220000 22425600>; 518 }; 519 520 cpu6_opp13: opp-2208000000 { 521 opp-hz = /bits/ 64 <2208000000>; 522 opp-peak-kBps = <7216000 22425600>; 523 }; 524 525 cpu6_opp14: opp-2323200000 { 526 opp-hz = /bits/ 64 <2323200000>; 527 opp-peak-kBps = <7216000 22425600>; 528 }; 529 530 cpu6_opp15: opp-2400000000 { 531 opp-hz = /bits/ 64 <2400000000>; 532 opp-peak-kBps = <8532000 23347200>; 533 }; 534 535 cpu6_opp16: opp-2553600000 { 536 opp-hz = /bits/ 64 <2553600000>; 537 opp-peak-kBps = <8532000 23347200>; 538 }; 539 }; 540 541 memory@80000000 { 542 device_type = "memory"; 543 /* We expect the bootloader to fill in the size */ 544 reg = <0 0x80000000 0 0>; 545 }; 546 547 pmu { 548 compatible = "arm,armv8-pmuv3"; 549 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 550 }; 551 552 firmware { 553 scm { 554 compatible = "qcom,scm-sc7180", "qcom,scm"; 555 }; 556 }; 557 558 smem { 559 compatible = "qcom,smem"; 560 memory-region = <&smem_mem>; 561 hwlocks = <&tcsr_mutex 3>; 562 }; 563 564 smp2p-cdsp { 565 compatible = "qcom,smp2p"; 566 qcom,smem = <94>, <432>; 567 568 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 569 570 mboxes = <&apss_shared 6>; 571 572 qcom,local-pid = <0>; 573 qcom,remote-pid = <5>; 574 575 cdsp_smp2p_out: master-kernel { 576 qcom,entry-name = "master-kernel"; 577 #qcom,smem-state-cells = <1>; 578 }; 579 580 cdsp_smp2p_in: slave-kernel { 581 qcom,entry-name = "slave-kernel"; 582 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 }; 587 588 smp2p-lpass { 589 compatible = "qcom,smp2p"; 590 qcom,smem = <443>, <429>; 591 592 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 593 594 mboxes = <&apss_shared 10>; 595 596 qcom,local-pid = <0>; 597 qcom,remote-pid = <2>; 598 599 adsp_smp2p_out: master-kernel { 600 qcom,entry-name = "master-kernel"; 601 #qcom,smem-state-cells = <1>; 602 }; 603 604 adsp_smp2p_in: slave-kernel { 605 qcom,entry-name = "slave-kernel"; 606 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 }; 611 612 smp2p-mpss { 613 compatible = "qcom,smp2p"; 614 qcom,smem = <435>, <428>; 615 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 616 mboxes = <&apss_shared 14>; 617 qcom,local-pid = <0>; 618 qcom,remote-pid = <1>; 619 620 modem_smp2p_out: master-kernel { 621 qcom,entry-name = "master-kernel"; 622 #qcom,smem-state-cells = <1>; 623 }; 624 625 modem_smp2p_in: slave-kernel { 626 qcom,entry-name = "slave-kernel"; 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 }; 630 631 ipa_smp2p_out: ipa-ap-to-modem { 632 qcom,entry-name = "ipa"; 633 #qcom,smem-state-cells = <1>; 634 }; 635 636 ipa_smp2p_in: ipa-modem-to-ap { 637 qcom,entry-name = "ipa"; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 }; 641 }; 642 643 psci { 644 compatible = "arm,psci-1.0"; 645 method = "smc"; 646 }; 647 648 soc: soc@0 { 649 #address-cells = <2>; 650 #size-cells = <2>; 651 ranges = <0 0 0 0 0x10 0>; 652 dma-ranges = <0 0 0 0 0x10 0>; 653 compatible = "simple-bus"; 654 655 gcc: clock-controller@100000 { 656 compatible = "qcom,gcc-sc7180"; 657 reg = <0 0x00100000 0 0x1f0000>; 658 clocks = <&rpmhcc RPMH_CXO_CLK>, 659 <&rpmhcc RPMH_CXO_CLK_A>, 660 <&sleep_clk>; 661 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 662 #clock-cells = <1>; 663 #reset-cells = <1>; 664 #power-domain-cells = <1>; 665 power-domains = <&rpmhpd SC7180_CX>; 666 }; 667 668 qfprom: efuse@784000 { 669 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 670 reg = <0 0x00784000 0 0x7a0>, 671 <0 0x00780000 0 0x7a0>, 672 <0 0x00782000 0 0x100>, 673 <0 0x00786000 0 0x1fff>; 674 675 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 676 clock-names = "core"; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 680 qusb2p_hstx_trim: hstx-trim-primary@25b { 681 reg = <0x25b 0x1>; 682 bits = <1 3>; 683 }; 684 685 gpu_speed_bin: gpu_speed_bin@1d2 { 686 reg = <0x1d2 0x2>; 687 bits = <5 8>; 688 }; 689 }; 690 691 sdhc_1: mmc@7c4000 { 692 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 693 reg = <0 0x7c4000 0 0x1000>, 694 <0 0x07c5000 0 0x1000>; 695 reg-names = "hc", "cqhci"; 696 697 iommus = <&apps_smmu 0x60 0x0>; 698 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 700 interrupt-names = "hc_irq", "pwr_irq"; 701 702 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 703 <&gcc GCC_SDCC1_APPS_CLK>, 704 <&rpmhcc RPMH_CXO_CLK>; 705 clock-names = "iface", "core", "xo"; 706 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 707 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 708 interconnect-names = "sdhc-ddr","cpu-sdhc"; 709 power-domains = <&rpmhpd SC7180_CX>; 710 operating-points-v2 = <&sdhc1_opp_table>; 711 712 bus-width = <8>; 713 non-removable; 714 supports-cqe; 715 716 mmc-ddr-1_8v; 717 mmc-hs200-1_8v; 718 mmc-hs400-1_8v; 719 mmc-hs400-enhanced-strobe; 720 721 status = "disabled"; 722 723 sdhc1_opp_table: opp-table { 724 compatible = "operating-points-v2"; 725 726 opp-100000000 { 727 opp-hz = /bits/ 64 <100000000>; 728 required-opps = <&rpmhpd_opp_low_svs>; 729 opp-peak-kBps = <1800000 600000>; 730 opp-avg-kBps = <100000 0>; 731 }; 732 733 opp-384000000 { 734 opp-hz = /bits/ 64 <384000000>; 735 required-opps = <&rpmhpd_opp_nom>; 736 opp-peak-kBps = <5400000 1600000>; 737 opp-avg-kBps = <390000 0>; 738 }; 739 }; 740 }; 741 742 qup_opp_table: opp-table-qup { 743 compatible = "operating-points-v2"; 744 745 opp-75000000 { 746 opp-hz = /bits/ 64 <75000000>; 747 required-opps = <&rpmhpd_opp_low_svs>; 748 }; 749 750 opp-100000000 { 751 opp-hz = /bits/ 64 <100000000>; 752 required-opps = <&rpmhpd_opp_svs>; 753 }; 754 755 opp-128000000 { 756 opp-hz = /bits/ 64 <128000000>; 757 required-opps = <&rpmhpd_opp_nom>; 758 }; 759 }; 760 761 qupv3_id_0: geniqup@8c0000 { 762 compatible = "qcom,geni-se-qup"; 763 reg = <0 0x008c0000 0 0x6000>; 764 clock-names = "m-ahb", "s-ahb"; 765 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 766 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 767 #address-cells = <2>; 768 #size-cells = <2>; 769 ranges; 770 iommus = <&apps_smmu 0x43 0x0>; 771 status = "disabled"; 772 773 i2c0: i2c@880000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0 0x00880000 0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&qup_i2c0_default>; 780 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 784 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 785 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 786 interconnect-names = "qup-core", "qup-config", 787 "qup-memory"; 788 power-domains = <&rpmhpd SC7180_CX>; 789 required-opps = <&rpmhpd_opp_low_svs>; 790 status = "disabled"; 791 }; 792 793 spi0: spi@880000 { 794 compatible = "qcom,geni-spi"; 795 reg = <0 0x00880000 0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 800 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 power-domains = <&rpmhpd SC7180_CX>; 804 operating-points-v2 = <&qup_opp_table>; 805 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 806 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 807 interconnect-names = "qup-core", "qup-config"; 808 status = "disabled"; 809 }; 810 811 uart0: serial@880000 { 812 compatible = "qcom,geni-uart"; 813 reg = <0 0x00880000 0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_uart0_default>; 818 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 819 power-domains = <&rpmhpd SC7180_CX>; 820 operating-points-v2 = <&qup_opp_table>; 821 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 822 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 823 interconnect-names = "qup-core", "qup-config"; 824 status = "disabled"; 825 }; 826 827 i2c1: i2c@884000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x00884000 0 0x4000>; 830 clock-names = "se"; 831 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c1_default>; 834 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 839 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 840 interconnect-names = "qup-core", "qup-config", 841 "qup-memory"; 842 power-domains = <&rpmhpd SC7180_CX>; 843 required-opps = <&rpmhpd_opp_low_svs>; 844 status = "disabled"; 845 }; 846 847 spi1: spi@884000 { 848 compatible = "qcom,geni-spi"; 849 reg = <0 0x00884000 0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 854 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 power-domains = <&rpmhpd SC7180_CX>; 858 operating-points-v2 = <&qup_opp_table>; 859 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 860 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 861 interconnect-names = "qup-core", "qup-config"; 862 status = "disabled"; 863 }; 864 865 uart1: serial@884000 { 866 compatible = "qcom,geni-uart"; 867 reg = <0 0x00884000 0 0x4000>; 868 clock-names = "se"; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 870 pinctrl-names = "default"; 871 pinctrl-0 = <&qup_uart1_default>; 872 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 873 power-domains = <&rpmhpd SC7180_CX>; 874 operating-points-v2 = <&qup_opp_table>; 875 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 876 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 877 interconnect-names = "qup-core", "qup-config"; 878 status = "disabled"; 879 }; 880 881 i2c2: i2c@888000 { 882 compatible = "qcom,geni-i2c"; 883 reg = <0 0x00888000 0 0x4000>; 884 clock-names = "se"; 885 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&qup_i2c2_default>; 888 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 892 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 893 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 894 interconnect-names = "qup-core", "qup-config", 895 "qup-memory"; 896 power-domains = <&rpmhpd SC7180_CX>; 897 required-opps = <&rpmhpd_opp_low_svs>; 898 status = "disabled"; 899 }; 900 901 uart2: serial@888000 { 902 compatible = "qcom,geni-uart"; 903 reg = <0 0x00888000 0 0x4000>; 904 clock-names = "se"; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_uart2_default>; 908 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 909 power-domains = <&rpmhpd SC7180_CX>; 910 operating-points-v2 = <&qup_opp_table>; 911 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 913 interconnect-names = "qup-core", "qup-config"; 914 status = "disabled"; 915 }; 916 917 i2c3: i2c@88c000 { 918 compatible = "qcom,geni-i2c"; 919 reg = <0 0x0088c000 0 0x4000>; 920 clock-names = "se"; 921 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&qup_i2c3_default>; 924 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 928 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 929 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 930 interconnect-names = "qup-core", "qup-config", 931 "qup-memory"; 932 power-domains = <&rpmhpd SC7180_CX>; 933 required-opps = <&rpmhpd_opp_low_svs>; 934 status = "disabled"; 935 }; 936 937 spi3: spi@88c000 { 938 compatible = "qcom,geni-spi"; 939 reg = <0 0x0088c000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 944 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 power-domains = <&rpmhpd SC7180_CX>; 948 operating-points-v2 = <&qup_opp_table>; 949 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 950 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 951 interconnect-names = "qup-core", "qup-config"; 952 status = "disabled"; 953 }; 954 955 uart3: serial@88c000 { 956 compatible = "qcom,geni-uart"; 957 reg = <0 0x0088c000 0 0x4000>; 958 clock-names = "se"; 959 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_uart3_default>; 962 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 963 power-domains = <&rpmhpd SC7180_CX>; 964 operating-points-v2 = <&qup_opp_table>; 965 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 967 interconnect-names = "qup-core", "qup-config"; 968 status = "disabled"; 969 }; 970 971 i2c4: i2c@890000 { 972 compatible = "qcom,geni-i2c"; 973 reg = <0 0x00890000 0 0x4000>; 974 clock-names = "se"; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_i2c4_default>; 978 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 983 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 984 interconnect-names = "qup-core", "qup-config", 985 "qup-memory"; 986 power-domains = <&rpmhpd SC7180_CX>; 987 required-opps = <&rpmhpd_opp_low_svs>; 988 status = "disabled"; 989 }; 990 991 uart4: serial@890000 { 992 compatible = "qcom,geni-uart"; 993 reg = <0 0x00890000 0 0x4000>; 994 clock-names = "se"; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&qup_uart4_default>; 998 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 999 power-domains = <&rpmhpd SC7180_CX>; 1000 operating-points-v2 = <&qup_opp_table>; 1001 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1003 interconnect-names = "qup-core", "qup-config"; 1004 status = "disabled"; 1005 }; 1006 1007 i2c5: i2c@894000 { 1008 compatible = "qcom,geni-i2c"; 1009 reg = <0 0x00894000 0 0x4000>; 1010 clock-names = "se"; 1011 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&qup_i2c5_default>; 1014 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1018 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1019 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1020 interconnect-names = "qup-core", "qup-config", 1021 "qup-memory"; 1022 power-domains = <&rpmhpd SC7180_CX>; 1023 required-opps = <&rpmhpd_opp_low_svs>; 1024 status = "disabled"; 1025 }; 1026 1027 spi5: spi@894000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x00894000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1034 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 power-domains = <&rpmhpd SC7180_CX>; 1038 operating-points-v2 = <&qup_opp_table>; 1039 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1040 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1041 interconnect-names = "qup-core", "qup-config"; 1042 status = "disabled"; 1043 }; 1044 1045 uart5: serial@894000 { 1046 compatible = "qcom,geni-uart"; 1047 reg = <0 0x00894000 0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&qup_uart5_default>; 1052 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1053 power-domains = <&rpmhpd SC7180_CX>; 1054 operating-points-v2 = <&qup_opp_table>; 1055 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1056 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1057 interconnect-names = "qup-core", "qup-config"; 1058 status = "disabled"; 1059 }; 1060 }; 1061 1062 qupv3_id_1: geniqup@ac0000 { 1063 compatible = "qcom,geni-se-qup"; 1064 reg = <0 0x00ac0000 0 0x6000>; 1065 clock-names = "m-ahb", "s-ahb"; 1066 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1067 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1068 #address-cells = <2>; 1069 #size-cells = <2>; 1070 ranges; 1071 iommus = <&apps_smmu 0x4c3 0x0>; 1072 status = "disabled"; 1073 1074 i2c6: i2c@a80000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0 0x00a80000 0 0x4000>; 1077 clock-names = "se"; 1078 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_i2c6_default>; 1081 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1086 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1087 interconnect-names = "qup-core", "qup-config", 1088 "qup-memory"; 1089 power-domains = <&rpmhpd SC7180_CX>; 1090 required-opps = <&rpmhpd_opp_low_svs>; 1091 status = "disabled"; 1092 }; 1093 1094 spi6: spi@a80000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0 0x00a80000 0 0x4000>; 1097 clock-names = "se"; 1098 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1101 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 power-domains = <&rpmhpd SC7180_CX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1107 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1108 interconnect-names = "qup-core", "qup-config"; 1109 status = "disabled"; 1110 }; 1111 1112 uart6: serial@a80000 { 1113 compatible = "qcom,geni-uart"; 1114 reg = <0 0x00a80000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_uart6_default>; 1119 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1120 power-domains = <&rpmhpd SC7180_CX>; 1121 operating-points-v2 = <&qup_opp_table>; 1122 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1123 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1124 interconnect-names = "qup-core", "qup-config"; 1125 status = "disabled"; 1126 }; 1127 1128 i2c7: i2c@a84000 { 1129 compatible = "qcom,geni-i2c"; 1130 reg = <0 0x00a84000 0 0x4000>; 1131 clock-names = "se"; 1132 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_i2c7_default>; 1135 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1139 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1140 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1141 interconnect-names = "qup-core", "qup-config", 1142 "qup-memory"; 1143 power-domains = <&rpmhpd SC7180_CX>; 1144 required-opps = <&rpmhpd_opp_low_svs>; 1145 status = "disabled"; 1146 }; 1147 1148 uart7: serial@a84000 { 1149 compatible = "qcom,geni-uart"; 1150 reg = <0 0x00a84000 0 0x4000>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_uart7_default>; 1155 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1156 power-domains = <&rpmhpd SC7180_CX>; 1157 operating-points-v2 = <&qup_opp_table>; 1158 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1159 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1160 interconnect-names = "qup-core", "qup-config"; 1161 status = "disabled"; 1162 }; 1163 1164 i2c8: i2c@a88000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00a88000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c8_default>; 1171 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1175 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1176 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1177 interconnect-names = "qup-core", "qup-config", 1178 "qup-memory"; 1179 power-domains = <&rpmhpd SC7180_CX>; 1180 required-opps = <&rpmhpd_opp_low_svs>; 1181 status = "disabled"; 1182 }; 1183 1184 spi8: spi@a88000 { 1185 compatible = "qcom,geni-spi"; 1186 reg = <0 0x00a88000 0 0x4000>; 1187 clock-names = "se"; 1188 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1191 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 power-domains = <&rpmhpd SC7180_CX>; 1195 operating-points-v2 = <&qup_opp_table>; 1196 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1197 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1198 interconnect-names = "qup-core", "qup-config"; 1199 status = "disabled"; 1200 }; 1201 1202 uart8: serial@a88000 { 1203 compatible = "qcom,geni-debug-uart"; 1204 reg = <0 0x00a88000 0 0x4000>; 1205 clock-names = "se"; 1206 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_uart8_default>; 1209 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1210 power-domains = <&rpmhpd SC7180_CX>; 1211 operating-points-v2 = <&qup_opp_table>; 1212 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1213 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1214 interconnect-names = "qup-core", "qup-config"; 1215 status = "disabled"; 1216 }; 1217 1218 i2c9: i2c@a8c000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0 0x00a8c000 0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c9_default>; 1225 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1230 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1231 interconnect-names = "qup-core", "qup-config", 1232 "qup-memory"; 1233 power-domains = <&rpmhpd SC7180_CX>; 1234 required-opps = <&rpmhpd_opp_low_svs>; 1235 status = "disabled"; 1236 }; 1237 1238 uart9: serial@a8c000 { 1239 compatible = "qcom,geni-uart"; 1240 reg = <0 0x00a8c000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_uart9_default>; 1245 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1246 power-domains = <&rpmhpd SC7180_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1249 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1250 interconnect-names = "qup-core", "qup-config"; 1251 status = "disabled"; 1252 }; 1253 1254 i2c10: i2c@a90000 { 1255 compatible = "qcom,geni-i2c"; 1256 reg = <0 0x00a90000 0 0x4000>; 1257 clock-names = "se"; 1258 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&qup_i2c10_default>; 1261 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1265 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1266 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1267 interconnect-names = "qup-core", "qup-config", 1268 "qup-memory"; 1269 power-domains = <&rpmhpd SC7180_CX>; 1270 required-opps = <&rpmhpd_opp_low_svs>; 1271 status = "disabled"; 1272 }; 1273 1274 spi10: spi@a90000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0 0x00a90000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1281 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 power-domains = <&rpmhpd SC7180_CX>; 1285 operating-points-v2 = <&qup_opp_table>; 1286 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1288 interconnect-names = "qup-core", "qup-config"; 1289 status = "disabled"; 1290 }; 1291 1292 uart10: serial@a90000 { 1293 compatible = "qcom,geni-uart"; 1294 reg = <0 0x00a90000 0 0x4000>; 1295 clock-names = "se"; 1296 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_uart10_default>; 1299 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1300 power-domains = <&rpmhpd SC7180_CX>; 1301 operating-points-v2 = <&qup_opp_table>; 1302 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1303 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1304 interconnect-names = "qup-core", "qup-config"; 1305 status = "disabled"; 1306 }; 1307 1308 i2c11: i2c@a94000 { 1309 compatible = "qcom,geni-i2c"; 1310 reg = <0 0x00a94000 0 0x4000>; 1311 clock-names = "se"; 1312 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&qup_i2c11_default>; 1315 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1319 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1320 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1321 interconnect-names = "qup-core", "qup-config", 1322 "qup-memory"; 1323 power-domains = <&rpmhpd SC7180_CX>; 1324 required-opps = <&rpmhpd_opp_low_svs>; 1325 status = "disabled"; 1326 }; 1327 1328 spi11: spi@a94000 { 1329 compatible = "qcom,geni-spi"; 1330 reg = <0 0x00a94000 0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1335 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 power-domains = <&rpmhpd SC7180_CX>; 1339 operating-points-v2 = <&qup_opp_table>; 1340 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1341 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1342 interconnect-names = "qup-core", "qup-config"; 1343 status = "disabled"; 1344 }; 1345 1346 uart11: serial@a94000 { 1347 compatible = "qcom,geni-uart"; 1348 reg = <0 0x00a94000 0 0x4000>; 1349 clock-names = "se"; 1350 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&qup_uart11_default>; 1353 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1354 power-domains = <&rpmhpd SC7180_CX>; 1355 operating-points-v2 = <&qup_opp_table>; 1356 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1357 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1358 interconnect-names = "qup-core", "qup-config"; 1359 status = "disabled"; 1360 }; 1361 }; 1362 1363 config_noc: interconnect@1500000 { 1364 compatible = "qcom,sc7180-config-noc"; 1365 reg = <0 0x01500000 0 0x28000>; 1366 #interconnect-cells = <2>; 1367 qcom,bcm-voters = <&apps_bcm_voter>; 1368 }; 1369 1370 system_noc: interconnect@1620000 { 1371 compatible = "qcom,sc7180-system-noc"; 1372 reg = <0 0x01620000 0 0x17080>; 1373 #interconnect-cells = <2>; 1374 qcom,bcm-voters = <&apps_bcm_voter>; 1375 }; 1376 1377 mc_virt: interconnect@1638000 { 1378 compatible = "qcom,sc7180-mc-virt"; 1379 reg = <0 0x01638000 0 0x1000>; 1380 #interconnect-cells = <2>; 1381 qcom,bcm-voters = <&apps_bcm_voter>; 1382 }; 1383 1384 qup_virt: interconnect@1650000 { 1385 compatible = "qcom,sc7180-qup-virt"; 1386 reg = <0 0x01650000 0 0x1000>; 1387 #interconnect-cells = <2>; 1388 qcom,bcm-voters = <&apps_bcm_voter>; 1389 }; 1390 1391 aggre1_noc: interconnect@16e0000 { 1392 compatible = "qcom,sc7180-aggre1-noc"; 1393 reg = <0 0x016e0000 0 0x15080>; 1394 #interconnect-cells = <2>; 1395 qcom,bcm-voters = <&apps_bcm_voter>; 1396 }; 1397 1398 aggre2_noc: interconnect@1705000 { 1399 compatible = "qcom,sc7180-aggre2-noc"; 1400 reg = <0 0x01705000 0 0x9000>; 1401 #interconnect-cells = <2>; 1402 qcom,bcm-voters = <&apps_bcm_voter>; 1403 }; 1404 1405 compute_noc: interconnect@170e000 { 1406 compatible = "qcom,sc7180-compute-noc"; 1407 reg = <0 0x0170e000 0 0x6000>; 1408 #interconnect-cells = <2>; 1409 qcom,bcm-voters = <&apps_bcm_voter>; 1410 }; 1411 1412 mmss_noc: interconnect@1740000 { 1413 compatible = "qcom,sc7180-mmss-noc"; 1414 reg = <0 0x01740000 0 0x1c100>; 1415 #interconnect-cells = <2>; 1416 qcom,bcm-voters = <&apps_bcm_voter>; 1417 }; 1418 1419 ipa: ipa@1e40000 { 1420 compatible = "qcom,sc7180-ipa"; 1421 1422 iommus = <&apps_smmu 0x440 0x0>, 1423 <&apps_smmu 0x442 0x0>; 1424 reg = <0 0x1e40000 0 0x7000>, 1425 <0 0x1e47000 0 0x2000>, 1426 <0 0x1e04000 0 0x2c000>; 1427 reg-names = "ipa-reg", 1428 "ipa-shared", 1429 "gsi"; 1430 1431 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1432 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1433 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1434 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1435 interrupt-names = "ipa", 1436 "gsi", 1437 "ipa-clock-query", 1438 "ipa-setup-ready"; 1439 1440 clocks = <&rpmhcc RPMH_IPA_CLK>; 1441 clock-names = "core"; 1442 1443 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1444 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1445 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1446 interconnect-names = "memory", 1447 "imem", 1448 "config"; 1449 1450 qcom,qmp = <&aoss_qmp>; 1451 1452 qcom,smem-states = <&ipa_smp2p_out 0>, 1453 <&ipa_smp2p_out 1>; 1454 qcom,smem-state-names = "ipa-clock-enabled-valid", 1455 "ipa-clock-enabled"; 1456 1457 status = "disabled"; 1458 }; 1459 1460 tcsr_mutex: hwlock@1f40000 { 1461 compatible = "qcom,tcsr-mutex"; 1462 reg = <0 0x01f40000 0 0x20000>; 1463 #hwlock-cells = <1>; 1464 }; 1465 1466 tcsr_regs_1: syscon@1f60000 { 1467 compatible = "qcom,sc7180-tcsr", "syscon"; 1468 reg = <0 0x01f60000 0 0x20000>; 1469 }; 1470 1471 tcsr_regs_2: syscon@1fc0000 { 1472 compatible = "qcom,sc7180-tcsr", "syscon"; 1473 reg = <0 0x01fc0000 0 0x40000>; 1474 }; 1475 1476 tlmm: pinctrl@3500000 { 1477 compatible = "qcom,sc7180-pinctrl"; 1478 reg = <0 0x03500000 0 0x300000>, 1479 <0 0x03900000 0 0x300000>, 1480 <0 0x03d00000 0 0x300000>; 1481 reg-names = "west", "north", "south"; 1482 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1483 gpio-controller; 1484 #gpio-cells = <2>; 1485 interrupt-controller; 1486 #interrupt-cells = <2>; 1487 gpio-ranges = <&tlmm 0 0 120>; 1488 wakeup-parent = <&pdc>; 1489 1490 dp_hot_plug_det: dp-hot-plug-det-state { 1491 pins = "gpio117"; 1492 function = "dp_hot"; 1493 }; 1494 1495 qspi_clk: qspi-clk-state { 1496 pins = "gpio63"; 1497 function = "qspi_clk"; 1498 }; 1499 1500 qspi_cs0: qspi-cs0-state { 1501 pins = "gpio68"; 1502 function = "qspi_cs"; 1503 }; 1504 1505 qspi_cs1: qspi-cs1-state { 1506 pins = "gpio72"; 1507 function = "qspi_cs"; 1508 }; 1509 1510 qspi_data01: qspi-data01-state { 1511 pins = "gpio64", "gpio65"; 1512 function = "qspi_data"; 1513 }; 1514 1515 qspi_data12: qspi-data12-state { 1516 pins = "gpio66", "gpio67"; 1517 function = "qspi_data"; 1518 }; 1519 1520 qup_i2c0_default: qup-i2c0-default-state { 1521 pins = "gpio34", "gpio35"; 1522 function = "qup00"; 1523 }; 1524 1525 qup_i2c1_default: qup-i2c1-default-state { 1526 pins = "gpio0", "gpio1"; 1527 function = "qup01"; 1528 }; 1529 1530 qup_i2c2_default: qup-i2c2-default-state { 1531 pins = "gpio15", "gpio16"; 1532 function = "qup02_i2c"; 1533 }; 1534 1535 qup_i2c3_default: qup-i2c3-default-state { 1536 pins = "gpio38", "gpio39"; 1537 function = "qup03"; 1538 }; 1539 1540 qup_i2c4_default: qup-i2c4-default-state { 1541 pins = "gpio115", "gpio116"; 1542 function = "qup04_i2c"; 1543 }; 1544 1545 qup_i2c5_default: qup-i2c5-default-state { 1546 pins = "gpio25", "gpio26"; 1547 function = "qup05"; 1548 }; 1549 1550 qup_i2c6_default: qup-i2c6-default-state { 1551 pins = "gpio59", "gpio60"; 1552 function = "qup10"; 1553 }; 1554 1555 qup_i2c7_default: qup-i2c7-default-state { 1556 pins = "gpio6", "gpio7"; 1557 function = "qup11_i2c"; 1558 }; 1559 1560 qup_i2c8_default: qup-i2c8-default-state { 1561 pins = "gpio42", "gpio43"; 1562 function = "qup12"; 1563 }; 1564 1565 qup_i2c9_default: qup-i2c9-default-state { 1566 pins = "gpio46", "gpio47"; 1567 function = "qup13_i2c"; 1568 }; 1569 1570 qup_i2c10_default: qup-i2c10-default-state { 1571 pins = "gpio86", "gpio87"; 1572 function = "qup14"; 1573 }; 1574 1575 qup_i2c11_default: qup-i2c11-default-state { 1576 pins = "gpio53", "gpio54"; 1577 function = "qup15"; 1578 }; 1579 1580 qup_spi0_spi: qup-spi0-spi-state { 1581 pins = "gpio34", "gpio35", "gpio36"; 1582 function = "qup00"; 1583 }; 1584 1585 qup_spi0_cs: qup-spi0-cs-state { 1586 pins = "gpio37"; 1587 function = "qup00"; 1588 }; 1589 1590 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1591 pins = "gpio37"; 1592 function = "gpio"; 1593 }; 1594 1595 qup_spi1_spi: qup-spi1-spi-state { 1596 pins = "gpio0", "gpio1", "gpio2"; 1597 function = "qup01"; 1598 }; 1599 1600 qup_spi1_cs: qup-spi1-cs-state { 1601 pins = "gpio3"; 1602 function = "qup01"; 1603 }; 1604 1605 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1606 pins = "gpio3"; 1607 function = "gpio"; 1608 }; 1609 1610 qup_spi3_spi: qup-spi3-spi-state { 1611 pins = "gpio38", "gpio39", "gpio40"; 1612 function = "qup03"; 1613 }; 1614 1615 qup_spi3_cs: qup-spi3-cs-state { 1616 pins = "gpio41"; 1617 function = "qup03"; 1618 }; 1619 1620 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1621 pins = "gpio41"; 1622 function = "gpio"; 1623 }; 1624 1625 qup_spi5_spi: qup-spi5-spi-state { 1626 pins = "gpio25", "gpio26", "gpio27"; 1627 function = "qup05"; 1628 }; 1629 1630 qup_spi5_cs: qup-spi5-cs-state { 1631 pins = "gpio28"; 1632 function = "qup05"; 1633 }; 1634 1635 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1636 pins = "gpio28"; 1637 function = "gpio"; 1638 }; 1639 1640 qup_spi6_spi: qup-spi6-spi-state { 1641 pins = "gpio59", "gpio60", "gpio61"; 1642 function = "qup10"; 1643 }; 1644 1645 qup_spi6_cs: qup-spi6-cs-state { 1646 pins = "gpio62"; 1647 function = "qup10"; 1648 }; 1649 1650 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1651 pins = "gpio62"; 1652 function = "gpio"; 1653 }; 1654 1655 qup_spi8_spi: qup-spi8-spi-state { 1656 pins = "gpio42", "gpio43", "gpio44"; 1657 function = "qup12"; 1658 }; 1659 1660 qup_spi8_cs: qup-spi8-cs-state { 1661 pins = "gpio45"; 1662 function = "qup12"; 1663 }; 1664 1665 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1666 pins = "gpio45"; 1667 function = "gpio"; 1668 }; 1669 1670 qup_spi10_spi: qup-spi10-spi-state { 1671 pins = "gpio86", "gpio87", "gpio88"; 1672 function = "qup14"; 1673 }; 1674 1675 qup_spi10_cs: qup-spi10-cs-state { 1676 pins = "gpio89"; 1677 function = "qup14"; 1678 }; 1679 1680 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1681 pins = "gpio89"; 1682 function = "gpio"; 1683 }; 1684 1685 qup_spi11_spi: qup-spi11-spi-state { 1686 pins = "gpio53", "gpio54", "gpio55"; 1687 function = "qup15"; 1688 }; 1689 1690 qup_spi11_cs: qup-spi11-cs-state { 1691 pins = "gpio56"; 1692 function = "qup15"; 1693 }; 1694 1695 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1696 pins = "gpio56"; 1697 function = "gpio"; 1698 }; 1699 1700 qup_uart0_default: qup-uart0-default-state { 1701 qup_uart0_cts: cts-pins { 1702 pins = "gpio34"; 1703 function = "qup00"; 1704 }; 1705 1706 qup_uart0_rts: rts-pins { 1707 pins = "gpio35"; 1708 function = "qup00"; 1709 }; 1710 1711 qup_uart0_tx: tx-pins { 1712 pins = "gpio36"; 1713 function = "qup00"; 1714 }; 1715 1716 qup_uart0_rx: rx-pins { 1717 pins = "gpio37"; 1718 function = "qup00"; 1719 }; 1720 }; 1721 1722 qup_uart1_default: qup-uart1-default-state { 1723 qup_uart1_cts: cts-pins { 1724 pins = "gpio0"; 1725 function = "qup01"; 1726 }; 1727 1728 qup_uart1_rts: rts-pins { 1729 pins = "gpio1"; 1730 function = "qup01"; 1731 }; 1732 1733 qup_uart1_tx: tx-pins { 1734 pins = "gpio2"; 1735 function = "qup01"; 1736 }; 1737 1738 qup_uart1_rx: rx-pins { 1739 pins = "gpio3"; 1740 function = "qup01"; 1741 }; 1742 }; 1743 1744 qup_uart2_default: qup-uart2-default-state { 1745 qup_uart2_tx: tx-pins { 1746 pins = "gpio15"; 1747 function = "qup02_uart"; 1748 }; 1749 1750 qup_uart2_rx: rx-pins { 1751 pins = "gpio16"; 1752 function = "qup02_uart"; 1753 }; 1754 }; 1755 1756 qup_uart3_default: qup-uart3-default-state { 1757 qup_uart3_cts: cts-pins { 1758 pins = "gpio38"; 1759 function = "qup03"; 1760 }; 1761 1762 qup_uart3_rts: rts-pins { 1763 pins = "gpio39"; 1764 function = "qup03"; 1765 }; 1766 1767 qup_uart3_tx: tx-pins { 1768 pins = "gpio40"; 1769 function = "qup03"; 1770 }; 1771 1772 qup_uart3_rx: rx-pins { 1773 pins = "gpio41"; 1774 function = "qup03"; 1775 }; 1776 }; 1777 1778 qup_uart4_default: qup-uart4-default-state { 1779 qup_uart4_tx: tx-pins { 1780 pins = "gpio115"; 1781 function = "qup04_uart"; 1782 }; 1783 1784 qup_uart4_rx: rx-pins { 1785 pins = "gpio116"; 1786 function = "qup04_uart"; 1787 }; 1788 }; 1789 1790 qup_uart5_default: qup-uart5-default-state { 1791 qup_uart5_cts: cts-pins { 1792 pins = "gpio25"; 1793 function = "qup05"; 1794 }; 1795 1796 qup_uart5_rts: rts-pins { 1797 pins = "gpio26"; 1798 function = "qup05"; 1799 }; 1800 1801 qup_uart5_tx: tx-pins { 1802 pins = "gpio27"; 1803 function = "qup05"; 1804 }; 1805 1806 qup_uart5_rx: rx-pins { 1807 pins = "gpio28"; 1808 function = "qup05"; 1809 }; 1810 }; 1811 1812 qup_uart6_default: qup-uart6-default-state { 1813 qup_uart6_cts: cts-pins { 1814 pins = "gpio59"; 1815 function = "qup10"; 1816 }; 1817 1818 qup_uart6_rts: rts-pins { 1819 pins = "gpio60"; 1820 function = "qup10"; 1821 }; 1822 1823 qup_uart6_tx: tx-pins { 1824 pins = "gpio61"; 1825 function = "qup10"; 1826 }; 1827 1828 qup_uart6_rx: rx-pins { 1829 pins = "gpio62"; 1830 function = "qup10"; 1831 }; 1832 }; 1833 1834 qup_uart7_default: qup-uart7-default-state { 1835 qup_uart7_tx: tx-pins { 1836 pins = "gpio6"; 1837 function = "qup11_uart"; 1838 }; 1839 1840 qup_uart7_rx: rx-pins { 1841 pins = "gpio7"; 1842 function = "qup11_uart"; 1843 }; 1844 }; 1845 1846 qup_uart8_default: qup-uart8-default-state { 1847 qup_uart8_tx: tx-pins { 1848 pins = "gpio44"; 1849 function = "qup12"; 1850 }; 1851 1852 qup_uart8_rx: rx-pins { 1853 pins = "gpio45"; 1854 function = "qup12"; 1855 }; 1856 }; 1857 1858 qup_uart9_default: qup-uart9-default-state { 1859 qup_uart9_tx: tx-pins { 1860 pins = "gpio46"; 1861 function = "qup13_uart"; 1862 }; 1863 1864 qup_uart9_rx: rx-pins { 1865 pins = "gpio47"; 1866 function = "qup13_uart"; 1867 }; 1868 }; 1869 1870 qup_uart10_default: qup-uart10-default-state { 1871 qup_uart10_cts: cts-pins { 1872 pins = "gpio86"; 1873 function = "qup14"; 1874 }; 1875 1876 qup_uart10_rts: rts-pins { 1877 pins = "gpio87"; 1878 function = "qup14"; 1879 }; 1880 1881 qup_uart10_tx: tx-pins { 1882 pins = "gpio88"; 1883 function = "qup14"; 1884 }; 1885 1886 qup_uart10_rx: rx-pins { 1887 pins = "gpio89"; 1888 function = "qup14"; 1889 }; 1890 }; 1891 1892 qup_uart11_default: qup-uart11-default-state { 1893 qup_uart11_cts: cts-pins { 1894 pins = "gpio53"; 1895 function = "qup15"; 1896 }; 1897 1898 qup_uart11_rts: rts-pins { 1899 pins = "gpio54"; 1900 function = "qup15"; 1901 }; 1902 1903 qup_uart11_tx: tx-pins { 1904 pins = "gpio55"; 1905 function = "qup15"; 1906 }; 1907 1908 qup_uart11_rx: rx-pins { 1909 pins = "gpio56"; 1910 function = "qup15"; 1911 }; 1912 }; 1913 1914 sec_mi2s_active: sec-mi2s-active-state { 1915 pins = "gpio49", "gpio50", "gpio51"; 1916 function = "mi2s_1"; 1917 }; 1918 1919 pri_mi2s_active: pri-mi2s-active-state { 1920 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1921 function = "mi2s_0"; 1922 }; 1923 1924 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 1925 pins = "gpio57"; 1926 function = "lpass_ext"; 1927 }; 1928 }; 1929 1930 remoteproc_mpss: remoteproc@4080000 { 1931 compatible = "qcom,sc7180-mpss-pas"; 1932 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1933 reg-names = "qdsp6", "rmb"; 1934 1935 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1936 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1937 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1938 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1939 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1940 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1941 interrupt-names = "wdog", "fatal", "ready", "handover", 1942 "stop-ack", "shutdown-ack"; 1943 1944 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1945 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1946 <&gcc GCC_MSS_NAV_AXI_CLK>, 1947 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1948 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1949 <&rpmhcc RPMH_CXO_CLK>; 1950 clock-names = "iface", "bus", "nav", "snoc_axi", 1951 "mnoc_axi", "xo"; 1952 1953 power-domains = <&rpmhpd SC7180_CX>, 1954 <&rpmhpd SC7180_MX>, 1955 <&rpmhpd SC7180_MSS>; 1956 power-domain-names = "cx", "mx", "mss"; 1957 1958 memory-region = <&mpss_mem>; 1959 1960 qcom,qmp = <&aoss_qmp>; 1961 1962 qcom,smem-states = <&modem_smp2p_out 0>; 1963 qcom,smem-state-names = "stop"; 1964 1965 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1966 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1967 reset-names = "mss_restart", "pdc_reset"; 1968 1969 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1970 qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; 1971 1972 status = "disabled"; 1973 1974 glink-edge { 1975 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1976 label = "modem"; 1977 qcom,remote-pid = <1>; 1978 mboxes = <&apss_shared 12>; 1979 }; 1980 }; 1981 1982 gpu: gpu@5000000 { 1983 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1984 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1985 <0 0x05061000 0 0x800>; 1986 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1987 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1988 iommus = <&adreno_smmu 0>; 1989 operating-points-v2 = <&gpu_opp_table>; 1990 qcom,gmu = <&gmu>; 1991 1992 #cooling-cells = <2>; 1993 1994 nvmem-cells = <&gpu_speed_bin>; 1995 nvmem-cell-names = "speed_bin"; 1996 1997 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1998 interconnect-names = "gfx-mem"; 1999 2000 gpu_opp_table: opp-table { 2001 compatible = "operating-points-v2"; 2002 2003 opp-825000000 { 2004 opp-hz = /bits/ 64 <825000000>; 2005 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2006 opp-peak-kBps = <8532000>; 2007 opp-supported-hw = <0x04>; 2008 }; 2009 2010 opp-800000000 { 2011 opp-hz = /bits/ 64 <800000000>; 2012 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2013 opp-peak-kBps = <8532000>; 2014 opp-supported-hw = <0x07>; 2015 }; 2016 2017 opp-650000000 { 2018 opp-hz = /bits/ 64 <650000000>; 2019 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2020 opp-peak-kBps = <7216000>; 2021 opp-supported-hw = <0x07>; 2022 }; 2023 2024 opp-565000000 { 2025 opp-hz = /bits/ 64 <565000000>; 2026 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2027 opp-peak-kBps = <5412000>; 2028 opp-supported-hw = <0x07>; 2029 }; 2030 2031 opp-430000000 { 2032 opp-hz = /bits/ 64 <430000000>; 2033 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2034 opp-peak-kBps = <5412000>; 2035 opp-supported-hw = <0x07>; 2036 }; 2037 2038 opp-355000000 { 2039 opp-hz = /bits/ 64 <355000000>; 2040 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2041 opp-peak-kBps = <3072000>; 2042 opp-supported-hw = <0x07>; 2043 }; 2044 2045 opp-267000000 { 2046 opp-hz = /bits/ 64 <267000000>; 2047 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2048 opp-peak-kBps = <3072000>; 2049 opp-supported-hw = <0x07>; 2050 }; 2051 2052 opp-180000000 { 2053 opp-hz = /bits/ 64 <180000000>; 2054 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2055 opp-peak-kBps = <1804000>; 2056 opp-supported-hw = <0x07>; 2057 }; 2058 }; 2059 }; 2060 2061 adreno_smmu: iommu@5040000 { 2062 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2063 reg = <0 0x05040000 0 0x10000>; 2064 #iommu-cells = <1>; 2065 #global-interrupts = <2>; 2066 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2073 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2074 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2075 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2076 2077 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2078 <&gcc GCC_GPU_CFG_AHB_CLK>; 2079 clock-names = "bus", "iface"; 2080 2081 power-domains = <&gpucc CX_GDSC>; 2082 }; 2083 2084 gmu: gmu@506a000 { 2085 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2086 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2087 <0 0x0b490000 0 0x10000>; 2088 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2089 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2091 interrupt-names = "hfi", "gmu"; 2092 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2093 <&gpucc GPU_CC_CXO_CLK>, 2094 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2095 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2096 clock-names = "gmu", "cxo", "axi", "memnoc"; 2097 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2098 power-domain-names = "cx", "gx"; 2099 iommus = <&adreno_smmu 5>; 2100 operating-points-v2 = <&gmu_opp_table>; 2101 2102 gmu_opp_table: opp-table { 2103 compatible = "operating-points-v2"; 2104 2105 opp-200000000 { 2106 opp-hz = /bits/ 64 <200000000>; 2107 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2108 }; 2109 }; 2110 }; 2111 2112 gpucc: clock-controller@5090000 { 2113 compatible = "qcom,sc7180-gpucc"; 2114 reg = <0 0x05090000 0 0x9000>; 2115 clocks = <&rpmhcc RPMH_CXO_CLK>, 2116 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2117 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2118 clock-names = "bi_tcxo", 2119 "gcc_gpu_gpll0_clk_src", 2120 "gcc_gpu_gpll0_div_clk_src"; 2121 #clock-cells = <1>; 2122 #reset-cells = <1>; 2123 #power-domain-cells = <1>; 2124 }; 2125 2126 stm@6002000 { 2127 compatible = "arm,coresight-stm", "arm,primecell"; 2128 reg = <0 0x06002000 0 0x1000>, 2129 <0 0x16280000 0 0x180000>; 2130 reg-names = "stm-base", "stm-stimulus-base"; 2131 2132 clocks = <&aoss_qmp>; 2133 clock-names = "apb_pclk"; 2134 2135 out-ports { 2136 port { 2137 stm_out: endpoint { 2138 remote-endpoint = <&funnel0_in7>; 2139 }; 2140 }; 2141 }; 2142 }; 2143 2144 funnel@6041000 { 2145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2146 reg = <0 0x06041000 0 0x1000>; 2147 2148 clocks = <&aoss_qmp>; 2149 clock-names = "apb_pclk"; 2150 2151 out-ports { 2152 port { 2153 funnel0_out: endpoint { 2154 remote-endpoint = <&merge_funnel_in0>; 2155 }; 2156 }; 2157 }; 2158 2159 in-ports { 2160 #address-cells = <1>; 2161 #size-cells = <0>; 2162 2163 port@7 { 2164 reg = <7>; 2165 funnel0_in7: endpoint { 2166 remote-endpoint = <&stm_out>; 2167 }; 2168 }; 2169 }; 2170 }; 2171 2172 funnel@6042000 { 2173 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2174 reg = <0 0x06042000 0 0x1000>; 2175 2176 clocks = <&aoss_qmp>; 2177 clock-names = "apb_pclk"; 2178 2179 out-ports { 2180 port { 2181 funnel1_out: endpoint { 2182 remote-endpoint = <&merge_funnel_in1>; 2183 }; 2184 }; 2185 }; 2186 2187 in-ports { 2188 #address-cells = <1>; 2189 #size-cells = <0>; 2190 2191 port@4 { 2192 reg = <4>; 2193 funnel1_in4: endpoint { 2194 remote-endpoint = <&apss_merge_funnel_out>; 2195 }; 2196 }; 2197 }; 2198 }; 2199 2200 funnel@6045000 { 2201 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2202 reg = <0 0x06045000 0 0x1000>; 2203 2204 clocks = <&aoss_qmp>; 2205 clock-names = "apb_pclk"; 2206 2207 out-ports { 2208 port { 2209 merge_funnel_out: endpoint { 2210 remote-endpoint = <&swao_funnel_in>; 2211 }; 2212 }; 2213 }; 2214 2215 in-ports { 2216 #address-cells = <1>; 2217 #size-cells = <0>; 2218 2219 port@0 { 2220 reg = <0>; 2221 merge_funnel_in0: endpoint { 2222 remote-endpoint = <&funnel0_out>; 2223 }; 2224 }; 2225 2226 port@1 { 2227 reg = <1>; 2228 merge_funnel_in1: endpoint { 2229 remote-endpoint = <&funnel1_out>; 2230 }; 2231 }; 2232 }; 2233 }; 2234 2235 replicator@6046000 { 2236 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2237 reg = <0 0x06046000 0 0x1000>; 2238 2239 clocks = <&aoss_qmp>; 2240 clock-names = "apb_pclk"; 2241 2242 out-ports { 2243 port { 2244 replicator_out: endpoint { 2245 remote-endpoint = <&etr_in>; 2246 }; 2247 }; 2248 }; 2249 2250 in-ports { 2251 port { 2252 replicator_in: endpoint { 2253 remote-endpoint = <&swao_replicator_out>; 2254 }; 2255 }; 2256 }; 2257 }; 2258 2259 etr@6048000 { 2260 compatible = "arm,coresight-tmc", "arm,primecell"; 2261 reg = <0 0x06048000 0 0x1000>; 2262 iommus = <&apps_smmu 0x04a0 0x20>; 2263 2264 clocks = <&aoss_qmp>; 2265 clock-names = "apb_pclk"; 2266 arm,scatter-gather; 2267 2268 in-ports { 2269 port { 2270 etr_in: endpoint { 2271 remote-endpoint = <&replicator_out>; 2272 }; 2273 }; 2274 }; 2275 }; 2276 2277 funnel@6b04000 { 2278 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2279 reg = <0 0x06b04000 0 0x1000>; 2280 2281 clocks = <&aoss_qmp>; 2282 clock-names = "apb_pclk"; 2283 2284 out-ports { 2285 port { 2286 swao_funnel_out: endpoint { 2287 remote-endpoint = <&etf_in>; 2288 }; 2289 }; 2290 }; 2291 2292 in-ports { 2293 #address-cells = <1>; 2294 #size-cells = <0>; 2295 2296 port@7 { 2297 reg = <7>; 2298 swao_funnel_in: endpoint { 2299 remote-endpoint = <&merge_funnel_out>; 2300 }; 2301 }; 2302 }; 2303 }; 2304 2305 etf@6b05000 { 2306 compatible = "arm,coresight-tmc", "arm,primecell"; 2307 reg = <0 0x06b05000 0 0x1000>; 2308 2309 clocks = <&aoss_qmp>; 2310 clock-names = "apb_pclk"; 2311 2312 out-ports { 2313 port { 2314 etf_out: endpoint { 2315 remote-endpoint = <&swao_replicator_in>; 2316 }; 2317 }; 2318 }; 2319 2320 in-ports { 2321 port { 2322 etf_in: endpoint { 2323 remote-endpoint = <&swao_funnel_out>; 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 replicator@6b06000 { 2330 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2331 reg = <0 0x06b06000 0 0x1000>; 2332 2333 clocks = <&aoss_qmp>; 2334 clock-names = "apb_pclk"; 2335 qcom,replicator-loses-context; 2336 2337 out-ports { 2338 port { 2339 swao_replicator_out: endpoint { 2340 remote-endpoint = <&replicator_in>; 2341 }; 2342 }; 2343 }; 2344 2345 in-ports { 2346 port { 2347 swao_replicator_in: endpoint { 2348 remote-endpoint = <&etf_out>; 2349 }; 2350 }; 2351 }; 2352 }; 2353 2354 etm@7040000 { 2355 compatible = "arm,coresight-etm4x", "arm,primecell"; 2356 reg = <0 0x07040000 0 0x1000>; 2357 2358 cpu = <&CPU0>; 2359 2360 clocks = <&aoss_qmp>; 2361 clock-names = "apb_pclk"; 2362 arm,coresight-loses-context-with-cpu; 2363 qcom,skip-power-up; 2364 2365 out-ports { 2366 port { 2367 etm0_out: endpoint { 2368 remote-endpoint = <&apss_funnel_in0>; 2369 }; 2370 }; 2371 }; 2372 }; 2373 2374 etm@7140000 { 2375 compatible = "arm,coresight-etm4x", "arm,primecell"; 2376 reg = <0 0x07140000 0 0x1000>; 2377 2378 cpu = <&CPU1>; 2379 2380 clocks = <&aoss_qmp>; 2381 clock-names = "apb_pclk"; 2382 arm,coresight-loses-context-with-cpu; 2383 qcom,skip-power-up; 2384 2385 out-ports { 2386 port { 2387 etm1_out: endpoint { 2388 remote-endpoint = <&apss_funnel_in1>; 2389 }; 2390 }; 2391 }; 2392 }; 2393 2394 etm@7240000 { 2395 compatible = "arm,coresight-etm4x", "arm,primecell"; 2396 reg = <0 0x07240000 0 0x1000>; 2397 2398 cpu = <&CPU2>; 2399 2400 clocks = <&aoss_qmp>; 2401 clock-names = "apb_pclk"; 2402 arm,coresight-loses-context-with-cpu; 2403 qcom,skip-power-up; 2404 2405 out-ports { 2406 port { 2407 etm2_out: endpoint { 2408 remote-endpoint = <&apss_funnel_in2>; 2409 }; 2410 }; 2411 }; 2412 }; 2413 2414 etm@7340000 { 2415 compatible = "arm,coresight-etm4x", "arm,primecell"; 2416 reg = <0 0x07340000 0 0x1000>; 2417 2418 cpu = <&CPU3>; 2419 2420 clocks = <&aoss_qmp>; 2421 clock-names = "apb_pclk"; 2422 arm,coresight-loses-context-with-cpu; 2423 qcom,skip-power-up; 2424 2425 out-ports { 2426 port { 2427 etm3_out: endpoint { 2428 remote-endpoint = <&apss_funnel_in3>; 2429 }; 2430 }; 2431 }; 2432 }; 2433 2434 etm@7440000 { 2435 compatible = "arm,coresight-etm4x", "arm,primecell"; 2436 reg = <0 0x07440000 0 0x1000>; 2437 2438 cpu = <&CPU4>; 2439 2440 clocks = <&aoss_qmp>; 2441 clock-names = "apb_pclk"; 2442 arm,coresight-loses-context-with-cpu; 2443 qcom,skip-power-up; 2444 2445 out-ports { 2446 port { 2447 etm4_out: endpoint { 2448 remote-endpoint = <&apss_funnel_in4>; 2449 }; 2450 }; 2451 }; 2452 }; 2453 2454 etm@7540000 { 2455 compatible = "arm,coresight-etm4x", "arm,primecell"; 2456 reg = <0 0x07540000 0 0x1000>; 2457 2458 cpu = <&CPU5>; 2459 2460 clocks = <&aoss_qmp>; 2461 clock-names = "apb_pclk"; 2462 arm,coresight-loses-context-with-cpu; 2463 qcom,skip-power-up; 2464 2465 out-ports { 2466 port { 2467 etm5_out: endpoint { 2468 remote-endpoint = <&apss_funnel_in5>; 2469 }; 2470 }; 2471 }; 2472 }; 2473 2474 etm@7640000 { 2475 compatible = "arm,coresight-etm4x", "arm,primecell"; 2476 reg = <0 0x07640000 0 0x1000>; 2477 2478 cpu = <&CPU6>; 2479 2480 clocks = <&aoss_qmp>; 2481 clock-names = "apb_pclk"; 2482 arm,coresight-loses-context-with-cpu; 2483 qcom,skip-power-up; 2484 2485 out-ports { 2486 port { 2487 etm6_out: endpoint { 2488 remote-endpoint = <&apss_funnel_in6>; 2489 }; 2490 }; 2491 }; 2492 }; 2493 2494 etm@7740000 { 2495 compatible = "arm,coresight-etm4x", "arm,primecell"; 2496 reg = <0 0x07740000 0 0x1000>; 2497 2498 cpu = <&CPU7>; 2499 2500 clocks = <&aoss_qmp>; 2501 clock-names = "apb_pclk"; 2502 arm,coresight-loses-context-with-cpu; 2503 qcom,skip-power-up; 2504 2505 out-ports { 2506 port { 2507 etm7_out: endpoint { 2508 remote-endpoint = <&apss_funnel_in7>; 2509 }; 2510 }; 2511 }; 2512 }; 2513 2514 funnel@7800000 { /* APSS Funnel */ 2515 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2516 reg = <0 0x07800000 0 0x1000>; 2517 2518 clocks = <&aoss_qmp>; 2519 clock-names = "apb_pclk"; 2520 2521 out-ports { 2522 port { 2523 apss_funnel_out: endpoint { 2524 remote-endpoint = <&apss_merge_funnel_in>; 2525 }; 2526 }; 2527 }; 2528 2529 in-ports { 2530 #address-cells = <1>; 2531 #size-cells = <0>; 2532 2533 port@0 { 2534 reg = <0>; 2535 apss_funnel_in0: endpoint { 2536 remote-endpoint = <&etm0_out>; 2537 }; 2538 }; 2539 2540 port@1 { 2541 reg = <1>; 2542 apss_funnel_in1: endpoint { 2543 remote-endpoint = <&etm1_out>; 2544 }; 2545 }; 2546 2547 port@2 { 2548 reg = <2>; 2549 apss_funnel_in2: endpoint { 2550 remote-endpoint = <&etm2_out>; 2551 }; 2552 }; 2553 2554 port@3 { 2555 reg = <3>; 2556 apss_funnel_in3: endpoint { 2557 remote-endpoint = <&etm3_out>; 2558 }; 2559 }; 2560 2561 port@4 { 2562 reg = <4>; 2563 apss_funnel_in4: endpoint { 2564 remote-endpoint = <&etm4_out>; 2565 }; 2566 }; 2567 2568 port@5 { 2569 reg = <5>; 2570 apss_funnel_in5: endpoint { 2571 remote-endpoint = <&etm5_out>; 2572 }; 2573 }; 2574 2575 port@6 { 2576 reg = <6>; 2577 apss_funnel_in6: endpoint { 2578 remote-endpoint = <&etm6_out>; 2579 }; 2580 }; 2581 2582 port@7 { 2583 reg = <7>; 2584 apss_funnel_in7: endpoint { 2585 remote-endpoint = <&etm7_out>; 2586 }; 2587 }; 2588 }; 2589 }; 2590 2591 funnel@7810000 { 2592 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2593 reg = <0 0x07810000 0 0x1000>; 2594 2595 clocks = <&aoss_qmp>; 2596 clock-names = "apb_pclk"; 2597 2598 out-ports { 2599 port { 2600 apss_merge_funnel_out: endpoint { 2601 remote-endpoint = <&funnel1_in4>; 2602 }; 2603 }; 2604 }; 2605 2606 in-ports { 2607 port { 2608 apss_merge_funnel_in: endpoint { 2609 remote-endpoint = <&apss_funnel_out>; 2610 }; 2611 }; 2612 }; 2613 }; 2614 2615 sdhc_2: mmc@8804000 { 2616 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2617 reg = <0 0x08804000 0 0x1000>; 2618 2619 iommus = <&apps_smmu 0x80 0>; 2620 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2621 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2622 interrupt-names = "hc_irq", "pwr_irq"; 2623 2624 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2625 <&gcc GCC_SDCC2_APPS_CLK>, 2626 <&rpmhcc RPMH_CXO_CLK>; 2627 clock-names = "iface", "core", "xo"; 2628 2629 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2630 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2631 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2632 power-domains = <&rpmhpd SC7180_CX>; 2633 operating-points-v2 = <&sdhc2_opp_table>; 2634 2635 bus-width = <4>; 2636 2637 status = "disabled"; 2638 2639 sdhc2_opp_table: opp-table { 2640 compatible = "operating-points-v2"; 2641 2642 opp-100000000 { 2643 opp-hz = /bits/ 64 <100000000>; 2644 required-opps = <&rpmhpd_opp_low_svs>; 2645 opp-peak-kBps = <1800000 600000>; 2646 opp-avg-kBps = <100000 0>; 2647 }; 2648 2649 opp-202000000 { 2650 opp-hz = /bits/ 64 <202000000>; 2651 required-opps = <&rpmhpd_opp_nom>; 2652 opp-peak-kBps = <5400000 1600000>; 2653 opp-avg-kBps = <200000 0>; 2654 }; 2655 }; 2656 }; 2657 2658 qspi_opp_table: opp-table-qspi { 2659 compatible = "operating-points-v2"; 2660 2661 opp-75000000 { 2662 opp-hz = /bits/ 64 <75000000>; 2663 required-opps = <&rpmhpd_opp_low_svs>; 2664 }; 2665 2666 opp-150000000 { 2667 opp-hz = /bits/ 64 <150000000>; 2668 required-opps = <&rpmhpd_opp_svs>; 2669 }; 2670 2671 opp-300000000 { 2672 opp-hz = /bits/ 64 <300000000>; 2673 required-opps = <&rpmhpd_opp_nom>; 2674 }; 2675 }; 2676 2677 qspi: spi@88dc000 { 2678 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2679 reg = <0 0x088dc000 0 0x600>; 2680 #address-cells = <1>; 2681 #size-cells = <0>; 2682 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2683 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2684 <&gcc GCC_QSPI_CORE_CLK>; 2685 clock-names = "iface", "core"; 2686 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2687 &config_noc SLAVE_QSPI_0 0>; 2688 interconnect-names = "qspi-config"; 2689 power-domains = <&rpmhpd SC7180_CX>; 2690 operating-points-v2 = <&qspi_opp_table>; 2691 status = "disabled"; 2692 }; 2693 2694 usb_1_hsphy: phy@88e3000 { 2695 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2696 reg = <0 0x088e3000 0 0x400>; 2697 status = "disabled"; 2698 #phy-cells = <0>; 2699 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2700 <&rpmhcc RPMH_CXO_CLK>; 2701 clock-names = "cfg_ahb", "ref"; 2702 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2703 2704 nvmem-cells = <&qusb2p_hstx_trim>; 2705 }; 2706 2707 usb_1_qmpphy: phy-wrapper@88e9000 { 2708 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2709 reg = <0 0x088e9000 0 0x18c>, 2710 <0 0x088e8000 0 0x3c>, 2711 <0 0x088ea000 0 0x18c>; 2712 status = "disabled"; 2713 #address-cells = <2>; 2714 #size-cells = <2>; 2715 ranges; 2716 2717 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2718 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2719 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2720 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2721 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2722 2723 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2724 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2725 reset-names = "phy", "common"; 2726 2727 usb_1_ssphy: usb3-phy@88e9200 { 2728 reg = <0 0x088e9200 0 0x128>, 2729 <0 0x088e9400 0 0x200>, 2730 <0 0x088e9c00 0 0x218>, 2731 <0 0x088e9600 0 0x128>, 2732 <0 0x088e9800 0 0x200>, 2733 <0 0x088e9a00 0 0x18>; 2734 #clock-cells = <0>; 2735 #phy-cells = <0>; 2736 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2737 clock-names = "pipe0"; 2738 clock-output-names = "usb3_phy_pipe_clk_src"; 2739 }; 2740 2741 dp_phy: dp-phy@88ea200 { 2742 reg = <0 0x088ea200 0 0x200>, 2743 <0 0x088ea400 0 0x200>, 2744 <0 0x088eaa00 0 0x200>, 2745 <0 0x088ea600 0 0x200>, 2746 <0 0x088ea800 0 0x200>; 2747 #clock-cells = <1>; 2748 #phy-cells = <0>; 2749 }; 2750 }; 2751 2752 dc_noc: interconnect@9160000 { 2753 compatible = "qcom,sc7180-dc-noc"; 2754 reg = <0 0x09160000 0 0x03200>; 2755 #interconnect-cells = <2>; 2756 qcom,bcm-voters = <&apps_bcm_voter>; 2757 }; 2758 2759 system-cache-controller@9200000 { 2760 compatible = "qcom,sc7180-llcc"; 2761 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2762 reg-names = "llcc_base", "llcc_broadcast_base"; 2763 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2764 }; 2765 2766 gem_noc: interconnect@9680000 { 2767 compatible = "qcom,sc7180-gem-noc"; 2768 reg = <0 0x09680000 0 0x3e200>; 2769 #interconnect-cells = <2>; 2770 qcom,bcm-voters = <&apps_bcm_voter>; 2771 }; 2772 2773 npu_noc: interconnect@9990000 { 2774 compatible = "qcom,sc7180-npu-noc"; 2775 reg = <0 0x09990000 0 0x1600>; 2776 #interconnect-cells = <2>; 2777 qcom,bcm-voters = <&apps_bcm_voter>; 2778 }; 2779 2780 usb_1: usb@a6f8800 { 2781 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2782 reg = <0 0x0a6f8800 0 0x400>; 2783 status = "disabled"; 2784 #address-cells = <2>; 2785 #size-cells = <2>; 2786 ranges; 2787 dma-ranges; 2788 2789 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2790 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2791 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2792 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2793 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2794 clock-names = "cfg_noc", 2795 "core", 2796 "iface", 2797 "sleep", 2798 "mock_utmi"; 2799 2800 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2801 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2802 assigned-clock-rates = <19200000>, <150000000>; 2803 2804 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2805 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2806 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2807 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2808 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2809 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2810 2811 power-domains = <&gcc USB30_PRIM_GDSC>; 2812 required-opps = <&rpmhpd_opp_nom>; 2813 2814 resets = <&gcc GCC_USB30_PRIM_BCR>; 2815 2816 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2817 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2818 interconnect-names = "usb-ddr", "apps-usb"; 2819 2820 wakeup-source; 2821 2822 usb_1_dwc3: usb@a600000 { 2823 compatible = "snps,dwc3"; 2824 reg = <0 0x0a600000 0 0xe000>; 2825 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2826 iommus = <&apps_smmu 0x540 0>; 2827 snps,dis_u2_susphy_quirk; 2828 snps,dis_enblslpm_quirk; 2829 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2830 phy-names = "usb2-phy", "usb3-phy"; 2831 maximum-speed = "super-speed"; 2832 }; 2833 }; 2834 2835 venus: video-codec@aa00000 { 2836 compatible = "qcom,sc7180-venus"; 2837 reg = <0 0x0aa00000 0 0xff000>; 2838 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2839 power-domains = <&videocc VENUS_GDSC>, 2840 <&videocc VCODEC0_GDSC>, 2841 <&rpmhpd SC7180_CX>; 2842 power-domain-names = "venus", "vcodec0", "cx"; 2843 operating-points-v2 = <&venus_opp_table>; 2844 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2845 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2846 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2847 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2848 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2849 clock-names = "core", "iface", "bus", 2850 "vcodec0_core", "vcodec0_bus"; 2851 iommus = <&apps_smmu 0x0c00 0x60>; 2852 memory-region = <&venus_mem>; 2853 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2854 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2855 interconnect-names = "video-mem", "cpu-cfg"; 2856 2857 video-decoder { 2858 compatible = "venus-decoder"; 2859 }; 2860 2861 video-encoder { 2862 compatible = "venus-encoder"; 2863 }; 2864 2865 venus_opp_table: opp-table { 2866 compatible = "operating-points-v2"; 2867 2868 opp-150000000 { 2869 opp-hz = /bits/ 64 <150000000>; 2870 required-opps = <&rpmhpd_opp_low_svs>; 2871 }; 2872 2873 opp-270000000 { 2874 opp-hz = /bits/ 64 <270000000>; 2875 required-opps = <&rpmhpd_opp_svs>; 2876 }; 2877 2878 opp-340000000 { 2879 opp-hz = /bits/ 64 <340000000>; 2880 required-opps = <&rpmhpd_opp_svs_l1>; 2881 }; 2882 2883 opp-434000000 { 2884 opp-hz = /bits/ 64 <434000000>; 2885 required-opps = <&rpmhpd_opp_nom>; 2886 }; 2887 2888 opp-500000097 { 2889 opp-hz = /bits/ 64 <500000097>; 2890 required-opps = <&rpmhpd_opp_turbo>; 2891 }; 2892 }; 2893 }; 2894 2895 videocc: clock-controller@ab00000 { 2896 compatible = "qcom,sc7180-videocc"; 2897 reg = <0 0x0ab00000 0 0x10000>; 2898 clocks = <&rpmhcc RPMH_CXO_CLK>; 2899 clock-names = "bi_tcxo"; 2900 #clock-cells = <1>; 2901 #reset-cells = <1>; 2902 #power-domain-cells = <1>; 2903 }; 2904 2905 camnoc_virt: interconnect@ac00000 { 2906 compatible = "qcom,sc7180-camnoc-virt"; 2907 reg = <0 0x0ac00000 0 0x1000>; 2908 #interconnect-cells = <2>; 2909 qcom,bcm-voters = <&apps_bcm_voter>; 2910 }; 2911 2912 camcc: clock-controller@ad00000 { 2913 compatible = "qcom,sc7180-camcc"; 2914 reg = <0 0x0ad00000 0 0x10000>; 2915 clocks = <&rpmhcc RPMH_CXO_CLK>, 2916 <&gcc GCC_CAMERA_AHB_CLK>, 2917 <&gcc GCC_CAMERA_XO_CLK>; 2918 clock-names = "bi_tcxo", "iface", "xo"; 2919 #clock-cells = <1>; 2920 #reset-cells = <1>; 2921 #power-domain-cells = <1>; 2922 }; 2923 2924 mdss: mdss@ae00000 { 2925 compatible = "qcom,sc7180-mdss"; 2926 reg = <0 0x0ae00000 0 0x1000>; 2927 reg-names = "mdss"; 2928 2929 power-domains = <&dispcc MDSS_GDSC>; 2930 2931 clocks = <&gcc GCC_DISP_AHB_CLK>, 2932 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2933 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2934 clock-names = "iface", "ahb", "core"; 2935 2936 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2937 interrupt-controller; 2938 #interrupt-cells = <1>; 2939 2940 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2941 interconnect-names = "mdp0-mem"; 2942 2943 iommus = <&apps_smmu 0x800 0x2>; 2944 2945 #address-cells = <2>; 2946 #size-cells = <2>; 2947 ranges; 2948 2949 status = "disabled"; 2950 2951 mdp: display-controller@ae01000 { 2952 compatible = "qcom,sc7180-dpu"; 2953 reg = <0 0x0ae01000 0 0x8f000>, 2954 <0 0x0aeb0000 0 0x2008>; 2955 reg-names = "mdp", "vbif"; 2956 2957 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2958 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2959 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2960 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2961 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2962 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2963 clock-names = "bus", "iface", "rot", "lut", "core", 2964 "vsync"; 2965 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2966 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2967 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2968 assigned-clock-rates = <19200000>, 2969 <19200000>, 2970 <19200000>; 2971 operating-points-v2 = <&mdp_opp_table>; 2972 power-domains = <&rpmhpd SC7180_CX>; 2973 2974 interrupt-parent = <&mdss>; 2975 interrupts = <0>; 2976 2977 status = "disabled"; 2978 2979 ports { 2980 #address-cells = <1>; 2981 #size-cells = <0>; 2982 2983 port@0 { 2984 reg = <0>; 2985 dpu_intf1_out: endpoint { 2986 remote-endpoint = <&dsi0_in>; 2987 }; 2988 }; 2989 2990 port@2 { 2991 reg = <2>; 2992 dpu_intf0_out: endpoint { 2993 remote-endpoint = <&dp_in>; 2994 }; 2995 }; 2996 }; 2997 2998 mdp_opp_table: opp-table { 2999 compatible = "operating-points-v2"; 3000 3001 opp-200000000 { 3002 opp-hz = /bits/ 64 <200000000>; 3003 required-opps = <&rpmhpd_opp_low_svs>; 3004 }; 3005 3006 opp-300000000 { 3007 opp-hz = /bits/ 64 <300000000>; 3008 required-opps = <&rpmhpd_opp_svs>; 3009 }; 3010 3011 opp-345000000 { 3012 opp-hz = /bits/ 64 <345000000>; 3013 required-opps = <&rpmhpd_opp_svs_l1>; 3014 }; 3015 3016 opp-460000000 { 3017 opp-hz = /bits/ 64 <460000000>; 3018 required-opps = <&rpmhpd_opp_nom>; 3019 }; 3020 }; 3021 3022 }; 3023 3024 dsi0: dsi@ae94000 { 3025 compatible = "qcom,mdss-dsi-ctrl"; 3026 reg = <0 0x0ae94000 0 0x400>; 3027 reg-names = "dsi_ctrl"; 3028 3029 interrupt-parent = <&mdss>; 3030 interrupts = <4>; 3031 3032 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3033 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3034 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3035 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3036 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3037 <&gcc GCC_DISP_HF_AXI_CLK>; 3038 clock-names = "byte", 3039 "byte_intf", 3040 "pixel", 3041 "core", 3042 "iface", 3043 "bus"; 3044 3045 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3046 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 3047 3048 operating-points-v2 = <&dsi_opp_table>; 3049 power-domains = <&rpmhpd SC7180_CX>; 3050 3051 phys = <&dsi_phy>; 3052 3053 #address-cells = <1>; 3054 #size-cells = <0>; 3055 3056 status = "disabled"; 3057 3058 ports { 3059 #address-cells = <1>; 3060 #size-cells = <0>; 3061 3062 port@0 { 3063 reg = <0>; 3064 dsi0_in: endpoint { 3065 remote-endpoint = <&dpu_intf1_out>; 3066 }; 3067 }; 3068 3069 port@1 { 3070 reg = <1>; 3071 dsi0_out: endpoint { 3072 }; 3073 }; 3074 }; 3075 3076 dsi_opp_table: opp-table { 3077 compatible = "operating-points-v2"; 3078 3079 opp-187500000 { 3080 opp-hz = /bits/ 64 <187500000>; 3081 required-opps = <&rpmhpd_opp_low_svs>; 3082 }; 3083 3084 opp-300000000 { 3085 opp-hz = /bits/ 64 <300000000>; 3086 required-opps = <&rpmhpd_opp_svs>; 3087 }; 3088 3089 opp-358000000 { 3090 opp-hz = /bits/ 64 <358000000>; 3091 required-opps = <&rpmhpd_opp_svs_l1>; 3092 }; 3093 }; 3094 }; 3095 3096 dsi_phy: phy@ae94400 { 3097 compatible = "qcom,dsi-phy-10nm"; 3098 reg = <0 0x0ae94400 0 0x200>, 3099 <0 0x0ae94600 0 0x280>, 3100 <0 0x0ae94a00 0 0x1e0>; 3101 reg-names = "dsi_phy", 3102 "dsi_phy_lane", 3103 "dsi_pll"; 3104 3105 #clock-cells = <1>; 3106 #phy-cells = <0>; 3107 3108 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3109 <&rpmhcc RPMH_CXO_CLK>; 3110 clock-names = "iface", "ref"; 3111 3112 status = "disabled"; 3113 }; 3114 3115 mdss_dp: displayport-controller@ae90000 { 3116 compatible = "qcom,sc7180-dp"; 3117 status = "disabled"; 3118 3119 reg = <0 0xae90000 0 0x200>, 3120 <0 0xae90200 0 0x200>, 3121 <0 0xae90400 0 0xc00>, 3122 <0 0xae91000 0 0x400>, 3123 <0 0xae91400 0 0x400>; 3124 3125 interrupt-parent = <&mdss>; 3126 interrupts = <12>; 3127 3128 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3129 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3130 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3131 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3132 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3133 clock-names = "core_iface", "core_aux", "ctrl_link", 3134 "ctrl_link_iface", "stream_pixel"; 3135 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3136 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3137 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3138 phys = <&dp_phy>; 3139 phy-names = "dp"; 3140 3141 operating-points-v2 = <&dp_opp_table>; 3142 power-domains = <&rpmhpd SC7180_CX>; 3143 3144 #sound-dai-cells = <0>; 3145 3146 ports { 3147 #address-cells = <1>; 3148 #size-cells = <0>; 3149 port@0 { 3150 reg = <0>; 3151 dp_in: endpoint { 3152 remote-endpoint = <&dpu_intf0_out>; 3153 }; 3154 }; 3155 3156 port@1 { 3157 reg = <1>; 3158 dp_out: endpoint { }; 3159 }; 3160 }; 3161 3162 dp_opp_table: opp-table { 3163 compatible = "operating-points-v2"; 3164 3165 opp-160000000 { 3166 opp-hz = /bits/ 64 <160000000>; 3167 required-opps = <&rpmhpd_opp_low_svs>; 3168 }; 3169 3170 opp-270000000 { 3171 opp-hz = /bits/ 64 <270000000>; 3172 required-opps = <&rpmhpd_opp_svs>; 3173 }; 3174 3175 opp-540000000 { 3176 opp-hz = /bits/ 64 <540000000>; 3177 required-opps = <&rpmhpd_opp_svs_l1>; 3178 }; 3179 3180 opp-810000000 { 3181 opp-hz = /bits/ 64 <810000000>; 3182 required-opps = <&rpmhpd_opp_nom>; 3183 }; 3184 }; 3185 }; 3186 }; 3187 3188 dispcc: clock-controller@af00000 { 3189 compatible = "qcom,sc7180-dispcc"; 3190 reg = <0 0x0af00000 0 0x200000>; 3191 clocks = <&rpmhcc RPMH_CXO_CLK>, 3192 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3193 <&dsi_phy 0>, 3194 <&dsi_phy 1>, 3195 <&dp_phy 0>, 3196 <&dp_phy 1>; 3197 clock-names = "bi_tcxo", 3198 "gcc_disp_gpll0_clk_src", 3199 "dsi0_phy_pll_out_byteclk", 3200 "dsi0_phy_pll_out_dsiclk", 3201 "dp_phy_pll_link_clk", 3202 "dp_phy_pll_vco_div_clk"; 3203 #clock-cells = <1>; 3204 #reset-cells = <1>; 3205 #power-domain-cells = <1>; 3206 }; 3207 3208 pdc: interrupt-controller@b220000 { 3209 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3210 reg = <0 0x0b220000 0 0x30000>; 3211 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3212 #interrupt-cells = <2>; 3213 interrupt-parent = <&intc>; 3214 interrupt-controller; 3215 }; 3216 3217 pdc_reset: reset-controller@b2e0000 { 3218 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3219 reg = <0 0x0b2e0000 0 0x20000>; 3220 #reset-cells = <1>; 3221 }; 3222 3223 tsens0: thermal-sensor@c263000 { 3224 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3225 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3226 <0 0x0c222000 0 0x1ff>; /* SROT */ 3227 #qcom,sensors = <15>; 3228 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3230 interrupt-names = "uplow","critical"; 3231 #thermal-sensor-cells = <1>; 3232 }; 3233 3234 tsens1: thermal-sensor@c265000 { 3235 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3236 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3237 <0 0x0c223000 0 0x1ff>; /* SROT */ 3238 #qcom,sensors = <10>; 3239 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3241 interrupt-names = "uplow","critical"; 3242 #thermal-sensor-cells = <1>; 3243 }; 3244 3245 aoss_reset: reset-controller@c2a0000 { 3246 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3247 reg = <0 0x0c2a0000 0 0x31000>; 3248 #reset-cells = <1>; 3249 }; 3250 3251 aoss_qmp: power-controller@c300000 { 3252 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3253 reg = <0 0x0c300000 0 0x400>; 3254 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3255 mboxes = <&apss_shared 0>; 3256 3257 #clock-cells = <0>; 3258 }; 3259 3260 sram@c3f0000 { 3261 compatible = "qcom,rpmh-stats"; 3262 reg = <0 0x0c3f0000 0 0x400>; 3263 }; 3264 3265 spmi_bus: spmi@c440000 { 3266 compatible = "qcom,spmi-pmic-arb"; 3267 reg = <0 0x0c440000 0 0x1100>, 3268 <0 0x0c600000 0 0x2000000>, 3269 <0 0x0e600000 0 0x100000>, 3270 <0 0x0e700000 0 0xa0000>, 3271 <0 0x0c40a000 0 0x26000>; 3272 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3273 interrupt-names = "periph_irq"; 3274 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3275 qcom,ee = <0>; 3276 qcom,channel = <0>; 3277 #address-cells = <1>; 3278 #size-cells = <1>; 3279 interrupt-controller; 3280 #interrupt-cells = <4>; 3281 cell-index = <0>; 3282 }; 3283 3284 sram@146aa000 { 3285 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3286 reg = <0 0x146aa000 0 0x2000>; 3287 3288 #address-cells = <1>; 3289 #size-cells = <1>; 3290 3291 ranges = <0 0 0x146aa000 0x2000>; 3292 3293 pil-reloc@94c { 3294 compatible = "qcom,pil-reloc-info"; 3295 reg = <0x94c 0xc8>; 3296 }; 3297 }; 3298 3299 apps_smmu: iommu@15000000 { 3300 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3301 reg = <0 0x15000000 0 0x100000>; 3302 #iommu-cells = <2>; 3303 #global-interrupts = <1>; 3304 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3385 }; 3386 3387 intc: interrupt-controller@17a00000 { 3388 compatible = "arm,gic-v3"; 3389 #address-cells = <2>; 3390 #size-cells = <2>; 3391 ranges; 3392 #interrupt-cells = <3>; 3393 interrupt-controller; 3394 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3395 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3397 3398 msi-controller@17a40000 { 3399 compatible = "arm,gic-v3-its"; 3400 msi-controller; 3401 #msi-cells = <1>; 3402 reg = <0 0x17a40000 0 0x20000>; 3403 status = "disabled"; 3404 }; 3405 }; 3406 3407 apss_shared: mailbox@17c00000 { 3408 compatible = "qcom,sc7180-apss-shared"; 3409 reg = <0 0x17c00000 0 0x10000>; 3410 #mbox-cells = <1>; 3411 }; 3412 3413 watchdog@17c10000 { 3414 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3415 reg = <0 0x17c10000 0 0x1000>; 3416 clocks = <&sleep_clk>; 3417 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3418 }; 3419 3420 timer@17c20000{ 3421 #address-cells = <1>; 3422 #size-cells = <1>; 3423 ranges = <0 0 0 0x20000000>; 3424 compatible = "arm,armv7-timer-mem"; 3425 reg = <0 0x17c20000 0 0x1000>; 3426 3427 frame@17c21000 { 3428 frame-number = <0>; 3429 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3431 reg = <0x17c21000 0x1000>, 3432 <0x17c22000 0x1000>; 3433 }; 3434 3435 frame@17c23000 { 3436 frame-number = <1>; 3437 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3438 reg = <0x17c23000 0x1000>; 3439 status = "disabled"; 3440 }; 3441 3442 frame@17c25000 { 3443 frame-number = <2>; 3444 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3445 reg = <0x17c25000 0x1000>; 3446 status = "disabled"; 3447 }; 3448 3449 frame@17c27000 { 3450 frame-number = <3>; 3451 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3452 reg = <0x17c27000 0x1000>; 3453 status = "disabled"; 3454 }; 3455 3456 frame@17c29000 { 3457 frame-number = <4>; 3458 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3459 reg = <0x17c29000 0x1000>; 3460 status = "disabled"; 3461 }; 3462 3463 frame@17c2b000 { 3464 frame-number = <5>; 3465 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3466 reg = <0x17c2b000 0x1000>; 3467 status = "disabled"; 3468 }; 3469 3470 frame@17c2d000 { 3471 frame-number = <6>; 3472 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3473 reg = <0x17c2d000 0x1000>; 3474 status = "disabled"; 3475 }; 3476 }; 3477 3478 apps_rsc: rsc@18200000 { 3479 compatible = "qcom,rpmh-rsc"; 3480 reg = <0 0x18200000 0 0x10000>, 3481 <0 0x18210000 0 0x10000>, 3482 <0 0x18220000 0 0x10000>; 3483 reg-names = "drv-0", "drv-1", "drv-2"; 3484 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3487 qcom,tcs-offset = <0xd00>; 3488 qcom,drv-id = <2>; 3489 qcom,tcs-config = <ACTIVE_TCS 2>, 3490 <SLEEP_TCS 3>, 3491 <WAKE_TCS 3>, 3492 <CONTROL_TCS 1>; 3493 3494 rpmhcc: clock-controller { 3495 compatible = "qcom,sc7180-rpmh-clk"; 3496 clocks = <&xo_board>; 3497 clock-names = "xo"; 3498 #clock-cells = <1>; 3499 }; 3500 3501 rpmhpd: power-controller { 3502 compatible = "qcom,sc7180-rpmhpd"; 3503 #power-domain-cells = <1>; 3504 operating-points-v2 = <&rpmhpd_opp_table>; 3505 3506 rpmhpd_opp_table: opp-table { 3507 compatible = "operating-points-v2"; 3508 3509 rpmhpd_opp_ret: opp1 { 3510 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3511 }; 3512 3513 rpmhpd_opp_min_svs: opp2 { 3514 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3515 }; 3516 3517 rpmhpd_opp_low_svs: opp3 { 3518 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3519 }; 3520 3521 rpmhpd_opp_svs: opp4 { 3522 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3523 }; 3524 3525 rpmhpd_opp_svs_l1: opp5 { 3526 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3527 }; 3528 3529 rpmhpd_opp_svs_l2: opp6 { 3530 opp-level = <224>; 3531 }; 3532 3533 rpmhpd_opp_nom: opp7 { 3534 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3535 }; 3536 3537 rpmhpd_opp_nom_l1: opp8 { 3538 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3539 }; 3540 3541 rpmhpd_opp_nom_l2: opp9 { 3542 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3543 }; 3544 3545 rpmhpd_opp_turbo: opp10 { 3546 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3547 }; 3548 3549 rpmhpd_opp_turbo_l1: opp11 { 3550 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3551 }; 3552 }; 3553 }; 3554 3555 apps_bcm_voter: bcm-voter { 3556 compatible = "qcom,bcm-voter"; 3557 }; 3558 }; 3559 3560 osm_l3: interconnect@18321000 { 3561 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3562 reg = <0 0x18321000 0 0x1400>; 3563 3564 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3565 clock-names = "xo", "alternate"; 3566 3567 #interconnect-cells = <1>; 3568 }; 3569 3570 cpufreq_hw: cpufreq@18323000 { 3571 compatible = "qcom,cpufreq-hw"; 3572 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3573 reg-names = "freq-domain0", "freq-domain1"; 3574 3575 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3576 clock-names = "xo", "alternate"; 3577 3578 #freq-domain-cells = <1>; 3579 }; 3580 3581 wifi: wifi@18800000 { 3582 compatible = "qcom,wcn3990-wifi"; 3583 reg = <0 0x18800000 0 0x800000>; 3584 reg-names = "membase"; 3585 iommus = <&apps_smmu 0xc0 0x1>; 3586 interrupts = 3587 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3588 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3589 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3590 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3591 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3592 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3593 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3594 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3595 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3596 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3597 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3598 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3599 memory-region = <&wlan_mem>; 3600 qcom,msa-fixed-perm; 3601 status = "disabled"; 3602 }; 3603 3604 lpasscc: clock-controller@62d00000 { 3605 compatible = "qcom,sc7180-lpasscorecc"; 3606 reg = <0 0x62d00000 0 0x50000>, 3607 <0 0x62780000 0 0x30000>; 3608 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3609 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3610 <&rpmhcc RPMH_CXO_CLK>; 3611 clock-names = "iface", "bi_tcxo"; 3612 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3613 #clock-cells = <1>; 3614 #power-domain-cells = <1>; 3615 }; 3616 3617 lpass_cpu: lpass@62d87000 { 3618 compatible = "qcom,sc7180-lpass-cpu"; 3619 3620 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3621 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3622 3623 iommus = <&apps_smmu 0x1020 0>, 3624 <&apps_smmu 0x1021 0>, 3625 <&apps_smmu 0x1032 0>; 3626 3627 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3628 3629 status = "disabled"; 3630 3631 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3632 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3633 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3634 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3635 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3636 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3637 3638 clock-names = "pcnoc-sway-clk", "audio-core", 3639 "mclk0", "pcnoc-mport-clk", 3640 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3641 3642 3643 #sound-dai-cells = <1>; 3644 #address-cells = <1>; 3645 #size-cells = <0>; 3646 3647 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3649 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3650 }; 3651 3652 lpass_hm: clock-controller@63000000 { 3653 compatible = "qcom,sc7180-lpasshm"; 3654 reg = <0 0x63000000 0 0x28>; 3655 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3656 <&rpmhcc RPMH_CXO_CLK>; 3657 clock-names = "iface", "bi_tcxo"; 3658 #clock-cells = <1>; 3659 #power-domain-cells = <1>; 3660 }; 3661 }; 3662 3663 thermal-zones { 3664 cpu0_thermal: cpu0-thermal { 3665 polling-delay-passive = <250>; 3666 polling-delay = <0>; 3667 3668 thermal-sensors = <&tsens0 1>; 3669 sustainable-power = <1052>; 3670 3671 trips { 3672 cpu0_alert0: trip-point0 { 3673 temperature = <90000>; 3674 hysteresis = <2000>; 3675 type = "passive"; 3676 }; 3677 3678 cpu0_alert1: trip-point1 { 3679 temperature = <95000>; 3680 hysteresis = <2000>; 3681 type = "passive"; 3682 }; 3683 3684 cpu0_crit: cpu_crit { 3685 temperature = <110000>; 3686 hysteresis = <1000>; 3687 type = "critical"; 3688 }; 3689 }; 3690 3691 cooling-maps { 3692 map0 { 3693 trip = <&cpu0_alert0>; 3694 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3695 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3696 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3697 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3699 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3700 }; 3701 map1 { 3702 trip = <&cpu0_alert1>; 3703 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3704 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3705 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3706 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3707 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3708 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3709 }; 3710 }; 3711 }; 3712 3713 cpu1_thermal: cpu1-thermal { 3714 polling-delay-passive = <250>; 3715 polling-delay = <0>; 3716 3717 thermal-sensors = <&tsens0 2>; 3718 sustainable-power = <1052>; 3719 3720 trips { 3721 cpu1_alert0: trip-point0 { 3722 temperature = <90000>; 3723 hysteresis = <2000>; 3724 type = "passive"; 3725 }; 3726 3727 cpu1_alert1: trip-point1 { 3728 temperature = <95000>; 3729 hysteresis = <2000>; 3730 type = "passive"; 3731 }; 3732 3733 cpu1_crit: cpu_crit { 3734 temperature = <110000>; 3735 hysteresis = <1000>; 3736 type = "critical"; 3737 }; 3738 }; 3739 3740 cooling-maps { 3741 map0 { 3742 trip = <&cpu1_alert0>; 3743 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3744 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3745 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3749 }; 3750 map1 { 3751 trip = <&cpu1_alert1>; 3752 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3753 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3754 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3755 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3756 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3757 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3758 }; 3759 }; 3760 }; 3761 3762 cpu2_thermal: cpu2-thermal { 3763 polling-delay-passive = <250>; 3764 polling-delay = <0>; 3765 3766 thermal-sensors = <&tsens0 3>; 3767 sustainable-power = <1052>; 3768 3769 trips { 3770 cpu2_alert0: trip-point0 { 3771 temperature = <90000>; 3772 hysteresis = <2000>; 3773 type = "passive"; 3774 }; 3775 3776 cpu2_alert1: trip-point1 { 3777 temperature = <95000>; 3778 hysteresis = <2000>; 3779 type = "passive"; 3780 }; 3781 3782 cpu2_crit: cpu_crit { 3783 temperature = <110000>; 3784 hysteresis = <1000>; 3785 type = "critical"; 3786 }; 3787 }; 3788 3789 cooling-maps { 3790 map0 { 3791 trip = <&cpu2_alert0>; 3792 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3794 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3795 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3796 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3798 }; 3799 map1 { 3800 trip = <&cpu2_alert1>; 3801 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3802 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3803 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3804 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3805 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3807 }; 3808 }; 3809 }; 3810 3811 cpu3_thermal: cpu3-thermal { 3812 polling-delay-passive = <250>; 3813 polling-delay = <0>; 3814 3815 thermal-sensors = <&tsens0 4>; 3816 sustainable-power = <1052>; 3817 3818 trips { 3819 cpu3_alert0: trip-point0 { 3820 temperature = <90000>; 3821 hysteresis = <2000>; 3822 type = "passive"; 3823 }; 3824 3825 cpu3_alert1: trip-point1 { 3826 temperature = <95000>; 3827 hysteresis = <2000>; 3828 type = "passive"; 3829 }; 3830 3831 cpu3_crit: cpu_crit { 3832 temperature = <110000>; 3833 hysteresis = <1000>; 3834 type = "critical"; 3835 }; 3836 }; 3837 3838 cooling-maps { 3839 map0 { 3840 trip = <&cpu3_alert0>; 3841 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3846 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3847 }; 3848 map1 { 3849 trip = <&cpu3_alert1>; 3850 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3853 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3854 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3855 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3856 }; 3857 }; 3858 }; 3859 3860 cpu4_thermal: cpu4-thermal { 3861 polling-delay-passive = <250>; 3862 polling-delay = <0>; 3863 3864 thermal-sensors = <&tsens0 5>; 3865 sustainable-power = <1052>; 3866 3867 trips { 3868 cpu4_alert0: trip-point0 { 3869 temperature = <90000>; 3870 hysteresis = <2000>; 3871 type = "passive"; 3872 }; 3873 3874 cpu4_alert1: trip-point1 { 3875 temperature = <95000>; 3876 hysteresis = <2000>; 3877 type = "passive"; 3878 }; 3879 3880 cpu4_crit: cpu_crit { 3881 temperature = <110000>; 3882 hysteresis = <1000>; 3883 type = "critical"; 3884 }; 3885 }; 3886 3887 cooling-maps { 3888 map0 { 3889 trip = <&cpu4_alert0>; 3890 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3891 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3892 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3896 }; 3897 map1 { 3898 trip = <&cpu4_alert1>; 3899 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3904 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3905 }; 3906 }; 3907 }; 3908 3909 cpu5_thermal: cpu5-thermal { 3910 polling-delay-passive = <250>; 3911 polling-delay = <0>; 3912 3913 thermal-sensors = <&tsens0 6>; 3914 sustainable-power = <1052>; 3915 3916 trips { 3917 cpu5_alert0: trip-point0 { 3918 temperature = <90000>; 3919 hysteresis = <2000>; 3920 type = "passive"; 3921 }; 3922 3923 cpu5_alert1: trip-point1 { 3924 temperature = <95000>; 3925 hysteresis = <2000>; 3926 type = "passive"; 3927 }; 3928 3929 cpu5_crit: cpu_crit { 3930 temperature = <110000>; 3931 hysteresis = <1000>; 3932 type = "critical"; 3933 }; 3934 }; 3935 3936 cooling-maps { 3937 map0 { 3938 trip = <&cpu5_alert0>; 3939 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3940 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3941 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3942 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3943 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3944 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3945 }; 3946 map1 { 3947 trip = <&cpu5_alert1>; 3948 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3949 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3950 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3951 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3952 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3953 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3954 }; 3955 }; 3956 }; 3957 3958 cpu6_thermal: cpu6-thermal { 3959 polling-delay-passive = <250>; 3960 polling-delay = <0>; 3961 3962 thermal-sensors = <&tsens0 9>; 3963 sustainable-power = <1425>; 3964 3965 trips { 3966 cpu6_alert0: trip-point0 { 3967 temperature = <90000>; 3968 hysteresis = <2000>; 3969 type = "passive"; 3970 }; 3971 3972 cpu6_alert1: trip-point1 { 3973 temperature = <95000>; 3974 hysteresis = <2000>; 3975 type = "passive"; 3976 }; 3977 3978 cpu6_crit: cpu_crit { 3979 temperature = <110000>; 3980 hysteresis = <1000>; 3981 type = "critical"; 3982 }; 3983 }; 3984 3985 cooling-maps { 3986 map0 { 3987 trip = <&cpu6_alert0>; 3988 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3990 }; 3991 map1 { 3992 trip = <&cpu6_alert1>; 3993 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3994 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3995 }; 3996 }; 3997 }; 3998 3999 cpu7_thermal: cpu7-thermal { 4000 polling-delay-passive = <250>; 4001 polling-delay = <0>; 4002 4003 thermal-sensors = <&tsens0 10>; 4004 sustainable-power = <1425>; 4005 4006 trips { 4007 cpu7_alert0: trip-point0 { 4008 temperature = <90000>; 4009 hysteresis = <2000>; 4010 type = "passive"; 4011 }; 4012 4013 cpu7_alert1: trip-point1 { 4014 temperature = <95000>; 4015 hysteresis = <2000>; 4016 type = "passive"; 4017 }; 4018 4019 cpu7_crit: cpu_crit { 4020 temperature = <110000>; 4021 hysteresis = <1000>; 4022 type = "critical"; 4023 }; 4024 }; 4025 4026 cooling-maps { 4027 map0 { 4028 trip = <&cpu7_alert0>; 4029 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4030 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4031 }; 4032 map1 { 4033 trip = <&cpu7_alert1>; 4034 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4036 }; 4037 }; 4038 }; 4039 4040 cpu8_thermal: cpu8-thermal { 4041 polling-delay-passive = <250>; 4042 polling-delay = <0>; 4043 4044 thermal-sensors = <&tsens0 11>; 4045 sustainable-power = <1425>; 4046 4047 trips { 4048 cpu8_alert0: trip-point0 { 4049 temperature = <90000>; 4050 hysteresis = <2000>; 4051 type = "passive"; 4052 }; 4053 4054 cpu8_alert1: trip-point1 { 4055 temperature = <95000>; 4056 hysteresis = <2000>; 4057 type = "passive"; 4058 }; 4059 4060 cpu8_crit: cpu_crit { 4061 temperature = <110000>; 4062 hysteresis = <1000>; 4063 type = "critical"; 4064 }; 4065 }; 4066 4067 cooling-maps { 4068 map0 { 4069 trip = <&cpu8_alert0>; 4070 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4072 }; 4073 map1 { 4074 trip = <&cpu8_alert1>; 4075 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4077 }; 4078 }; 4079 }; 4080 4081 cpu9_thermal: cpu9-thermal { 4082 polling-delay-passive = <250>; 4083 polling-delay = <0>; 4084 4085 thermal-sensors = <&tsens0 12>; 4086 sustainable-power = <1425>; 4087 4088 trips { 4089 cpu9_alert0: trip-point0 { 4090 temperature = <90000>; 4091 hysteresis = <2000>; 4092 type = "passive"; 4093 }; 4094 4095 cpu9_alert1: trip-point1 { 4096 temperature = <95000>; 4097 hysteresis = <2000>; 4098 type = "passive"; 4099 }; 4100 4101 cpu9_crit: cpu_crit { 4102 temperature = <110000>; 4103 hysteresis = <1000>; 4104 type = "critical"; 4105 }; 4106 }; 4107 4108 cooling-maps { 4109 map0 { 4110 trip = <&cpu9_alert0>; 4111 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4112 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4113 }; 4114 map1 { 4115 trip = <&cpu9_alert1>; 4116 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4118 }; 4119 }; 4120 }; 4121 4122 aoss0-thermal { 4123 polling-delay-passive = <250>; 4124 polling-delay = <0>; 4125 4126 thermal-sensors = <&tsens0 0>; 4127 4128 trips { 4129 aoss0_alert0: trip-point0 { 4130 temperature = <90000>; 4131 hysteresis = <2000>; 4132 type = "hot"; 4133 }; 4134 4135 aoss0_crit: aoss0_crit { 4136 temperature = <110000>; 4137 hysteresis = <2000>; 4138 type = "critical"; 4139 }; 4140 }; 4141 }; 4142 4143 cpuss0-thermal { 4144 polling-delay-passive = <250>; 4145 polling-delay = <0>; 4146 4147 thermal-sensors = <&tsens0 7>; 4148 4149 trips { 4150 cpuss0_alert0: trip-point0 { 4151 temperature = <90000>; 4152 hysteresis = <2000>; 4153 type = "hot"; 4154 }; 4155 cpuss0_crit: cluster0_crit { 4156 temperature = <110000>; 4157 hysteresis = <2000>; 4158 type = "critical"; 4159 }; 4160 }; 4161 }; 4162 4163 cpuss1-thermal { 4164 polling-delay-passive = <250>; 4165 polling-delay = <0>; 4166 4167 thermal-sensors = <&tsens0 8>; 4168 4169 trips { 4170 cpuss1_alert0: trip-point0 { 4171 temperature = <90000>; 4172 hysteresis = <2000>; 4173 type = "hot"; 4174 }; 4175 cpuss1_crit: cluster0_crit { 4176 temperature = <110000>; 4177 hysteresis = <2000>; 4178 type = "critical"; 4179 }; 4180 }; 4181 }; 4182 4183 gpuss0-thermal { 4184 polling-delay-passive = <250>; 4185 polling-delay = <0>; 4186 4187 thermal-sensors = <&tsens0 13>; 4188 4189 trips { 4190 gpuss0_alert0: trip-point0 { 4191 temperature = <95000>; 4192 hysteresis = <2000>; 4193 type = "passive"; 4194 }; 4195 4196 gpuss0_crit: gpuss0_crit { 4197 temperature = <110000>; 4198 hysteresis = <2000>; 4199 type = "critical"; 4200 }; 4201 }; 4202 4203 cooling-maps { 4204 map0 { 4205 trip = <&gpuss0_alert0>; 4206 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4207 }; 4208 }; 4209 }; 4210 4211 gpuss1-thermal { 4212 polling-delay-passive = <250>; 4213 polling-delay = <0>; 4214 4215 thermal-sensors = <&tsens0 14>; 4216 4217 trips { 4218 gpuss1_alert0: trip-point0 { 4219 temperature = <95000>; 4220 hysteresis = <2000>; 4221 type = "passive"; 4222 }; 4223 4224 gpuss1_crit: gpuss1_crit { 4225 temperature = <110000>; 4226 hysteresis = <2000>; 4227 type = "critical"; 4228 }; 4229 }; 4230 4231 cooling-maps { 4232 map0 { 4233 trip = <&gpuss1_alert0>; 4234 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4235 }; 4236 }; 4237 }; 4238 4239 aoss1-thermal { 4240 polling-delay-passive = <250>; 4241 polling-delay = <0>; 4242 4243 thermal-sensors = <&tsens1 0>; 4244 4245 trips { 4246 aoss1_alert0: trip-point0 { 4247 temperature = <90000>; 4248 hysteresis = <2000>; 4249 type = "hot"; 4250 }; 4251 4252 aoss1_crit: aoss1_crit { 4253 temperature = <110000>; 4254 hysteresis = <2000>; 4255 type = "critical"; 4256 }; 4257 }; 4258 }; 4259 4260 cwlan-thermal { 4261 polling-delay-passive = <250>; 4262 polling-delay = <0>; 4263 4264 thermal-sensors = <&tsens1 1>; 4265 4266 trips { 4267 cwlan_alert0: trip-point0 { 4268 temperature = <90000>; 4269 hysteresis = <2000>; 4270 type = "hot"; 4271 }; 4272 4273 cwlan_crit: cwlan_crit { 4274 temperature = <110000>; 4275 hysteresis = <2000>; 4276 type = "critical"; 4277 }; 4278 }; 4279 }; 4280 4281 audio-thermal { 4282 polling-delay-passive = <250>; 4283 polling-delay = <0>; 4284 4285 thermal-sensors = <&tsens1 2>; 4286 4287 trips { 4288 audio_alert0: trip-point0 { 4289 temperature = <90000>; 4290 hysteresis = <2000>; 4291 type = "hot"; 4292 }; 4293 4294 audio_crit: audio_crit { 4295 temperature = <110000>; 4296 hysteresis = <2000>; 4297 type = "critical"; 4298 }; 4299 }; 4300 }; 4301 4302 ddr-thermal { 4303 polling-delay-passive = <250>; 4304 polling-delay = <0>; 4305 4306 thermal-sensors = <&tsens1 3>; 4307 4308 trips { 4309 ddr_alert0: trip-point0 { 4310 temperature = <90000>; 4311 hysteresis = <2000>; 4312 type = "hot"; 4313 }; 4314 4315 ddr_crit: ddr_crit { 4316 temperature = <110000>; 4317 hysteresis = <2000>; 4318 type = "critical"; 4319 }; 4320 }; 4321 }; 4322 4323 q6-hvx-thermal { 4324 polling-delay-passive = <250>; 4325 polling-delay = <0>; 4326 4327 thermal-sensors = <&tsens1 4>; 4328 4329 trips { 4330 q6_hvx_alert0: trip-point0 { 4331 temperature = <90000>; 4332 hysteresis = <2000>; 4333 type = "hot"; 4334 }; 4335 4336 q6_hvx_crit: q6_hvx_crit { 4337 temperature = <110000>; 4338 hysteresis = <2000>; 4339 type = "critical"; 4340 }; 4341 }; 4342 }; 4343 4344 camera-thermal { 4345 polling-delay-passive = <250>; 4346 polling-delay = <0>; 4347 4348 thermal-sensors = <&tsens1 5>; 4349 4350 trips { 4351 camera_alert0: trip-point0 { 4352 temperature = <90000>; 4353 hysteresis = <2000>; 4354 type = "hot"; 4355 }; 4356 4357 camera_crit: camera_crit { 4358 temperature = <110000>; 4359 hysteresis = <2000>; 4360 type = "critical"; 4361 }; 4362 }; 4363 }; 4364 4365 mdm-core-thermal { 4366 polling-delay-passive = <250>; 4367 polling-delay = <0>; 4368 4369 thermal-sensors = <&tsens1 6>; 4370 4371 trips { 4372 mdm_alert0: trip-point0 { 4373 temperature = <90000>; 4374 hysteresis = <2000>; 4375 type = "hot"; 4376 }; 4377 4378 mdm_crit: mdm_crit { 4379 temperature = <110000>; 4380 hysteresis = <2000>; 4381 type = "critical"; 4382 }; 4383 }; 4384 }; 4385 4386 mdm-dsp-thermal { 4387 polling-delay-passive = <250>; 4388 polling-delay = <0>; 4389 4390 thermal-sensors = <&tsens1 7>; 4391 4392 trips { 4393 mdm_dsp_alert0: trip-point0 { 4394 temperature = <90000>; 4395 hysteresis = <2000>; 4396 type = "hot"; 4397 }; 4398 4399 mdm_dsp_crit: mdm_dsp_crit { 4400 temperature = <110000>; 4401 hysteresis = <2000>; 4402 type = "critical"; 4403 }; 4404 }; 4405 }; 4406 4407 npu-thermal { 4408 polling-delay-passive = <250>; 4409 polling-delay = <0>; 4410 4411 thermal-sensors = <&tsens1 8>; 4412 4413 trips { 4414 npu_alert0: trip-point0 { 4415 temperature = <90000>; 4416 hysteresis = <2000>; 4417 type = "hot"; 4418 }; 4419 4420 npu_crit: npu_crit { 4421 temperature = <110000>; 4422 hysteresis = <2000>; 4423 type = "critical"; 4424 }; 4425 }; 4426 }; 4427 4428 video-thermal { 4429 polling-delay-passive = <250>; 4430 polling-delay = <0>; 4431 4432 thermal-sensors = <&tsens1 9>; 4433 4434 trips { 4435 video_alert0: trip-point0 { 4436 temperature = <90000>; 4437 hysteresis = <2000>; 4438 type = "hot"; 4439 }; 4440 4441 video_crit: video_crit { 4442 temperature = <110000>; 4443 hysteresis = <2000>; 4444 type = "critical"; 4445 }; 4446 }; 4447 }; 4448 }; 4449 4450 timer { 4451 compatible = "arm,armv8-timer"; 4452 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4453 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4454 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4455 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4456 }; 4457}; 4458