1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-aoss-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 aliases { 34 mmc1 = &sdhc_1; 35 mmc2 = &sdhc_2; 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi3 = &spi3; 51 spi5 = &spi5; 52 spi6 = &spi6; 53 spi8 = &spi8; 54 spi10 = &spi10; 55 spi11 = &spi11; 56 }; 57 58 clocks { 59 xo_board: xo-board { 60 compatible = "fixed-clock"; 61 clock-frequency = <38400000>; 62 #clock-cells = <0>; 63 }; 64 65 sleep_clk: sleep-clk { 66 compatible = "fixed-clock"; 67 clock-frequency = <32764>; 68 #clock-cells = <0>; 69 }; 70 }; 71 72 reserved_memory: reserved-memory { 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 hyp_mem: memory@80000000 { 78 reg = <0x0 0x80000000 0x0 0x600000>; 79 no-map; 80 }; 81 82 xbl_mem: memory@80600000 { 83 reg = <0x0 0x80600000 0x0 0x200000>; 84 no-map; 85 }; 86 87 aop_mem: memory@80800000 { 88 reg = <0x0 0x80800000 0x0 0x20000>; 89 no-map; 90 }; 91 92 aop_cmd_db_mem: memory@80820000 { 93 reg = <0x0 0x80820000 0x0 0x20000>; 94 compatible = "qcom,cmd-db"; 95 no-map; 96 }; 97 98 sec_apps_mem: memory@808ff000 { 99 reg = <0x0 0x808ff000 0x0 0x1000>; 100 no-map; 101 }; 102 103 smem_mem: memory@80900000 { 104 reg = <0x0 0x80900000 0x0 0x200000>; 105 no-map; 106 }; 107 108 tz_mem: memory@80b00000 { 109 reg = <0x0 0x80b00000 0x0 0x3900000>; 110 no-map; 111 }; 112 113 rmtfs_mem: memory@94600000 { 114 compatible = "qcom,rmtfs-mem"; 115 reg = <0x0 0x94600000 0x0 0x200000>; 116 no-map; 117 118 qcom,client-id = <1>; 119 qcom,vmid = <15>; 120 }; 121 }; 122 123 cpus { 124 #address-cells = <2>; 125 #size-cells = <0>; 126 127 CPU0: cpu@0 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo468"; 130 reg = <0x0 0x0>; 131 enable-method = "psci"; 132 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 133 &LITTLE_CPU_SLEEP_1 134 &CLUSTER_SLEEP_0>; 135 capacity-dmips-mhz = <1024>; 136 dynamic-power-coefficient = <100>; 137 operating-points-v2 = <&cpu0_opp_table>; 138 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 139 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 140 next-level-cache = <&L2_0>; 141 #cooling-cells = <2>; 142 qcom,freq-domain = <&cpufreq_hw 0>; 143 L2_0: l2-cache { 144 compatible = "cache"; 145 next-level-cache = <&L3_0>; 146 L3_0: l3-cache { 147 compatible = "cache"; 148 }; 149 }; 150 }; 151 152 CPU1: cpu@100 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo468"; 155 reg = <0x0 0x100>; 156 enable-method = "psci"; 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 158 &LITTLE_CPU_SLEEP_1 159 &CLUSTER_SLEEP_0>; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <100>; 162 next-level-cache = <&L2_100>; 163 operating-points-v2 = <&cpu0_opp_table>; 164 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 #cooling-cells = <2>; 167 qcom,freq-domain = <&cpufreq_hw 0>; 168 L2_100: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU2: cpu@200 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo468"; 177 reg = <0x0 0x200>; 178 enable-method = "psci"; 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 180 &LITTLE_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 capacity-dmips-mhz = <1024>; 183 dynamic-power-coefficient = <100>; 184 next-level-cache = <&L2_200>; 185 operating-points-v2 = <&cpu0_opp_table>; 186 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188 #cooling-cells = <2>; 189 qcom,freq-domain = <&cpufreq_hw 0>; 190 L2_200: l2-cache { 191 compatible = "cache"; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 CPU3: cpu@300 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo468"; 199 reg = <0x0 0x300>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 capacity-dmips-mhz = <1024>; 205 dynamic-power-coefficient = <100>; 206 next-level-cache = <&L2_300>; 207 operating-points-v2 = <&cpu0_opp_table>; 208 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 210 #cooling-cells = <2>; 211 qcom,freq-domain = <&cpufreq_hw 0>; 212 L2_300: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU4: cpu@400 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo468"; 221 reg = <0x0 0x400>; 222 enable-method = "psci"; 223 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 224 &LITTLE_CPU_SLEEP_1 225 &CLUSTER_SLEEP_0>; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <100>; 228 next-level-cache = <&L2_400>; 229 operating-points-v2 = <&cpu0_opp_table>; 230 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 232 #cooling-cells = <2>; 233 qcom,freq-domain = <&cpufreq_hw 0>; 234 L2_400: l2-cache { 235 compatible = "cache"; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU5: cpu@500 { 241 device_type = "cpu"; 242 compatible = "qcom,kryo468"; 243 reg = <0x0 0x500>; 244 enable-method = "psci"; 245 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 246 &LITTLE_CPU_SLEEP_1 247 &CLUSTER_SLEEP_0>; 248 capacity-dmips-mhz = <1024>; 249 dynamic-power-coefficient = <100>; 250 next-level-cache = <&L2_500>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 254 #cooling-cells = <2>; 255 qcom,freq-domain = <&cpufreq_hw 0>; 256 L2_500: l2-cache { 257 compatible = "cache"; 258 next-level-cache = <&L3_0>; 259 }; 260 }; 261 262 CPU6: cpu@600 { 263 device_type = "cpu"; 264 compatible = "qcom,kryo468"; 265 reg = <0x0 0x600>; 266 enable-method = "psci"; 267 cpu-idle-states = <&BIG_CPU_SLEEP_0 268 &BIG_CPU_SLEEP_1 269 &CLUSTER_SLEEP_0>; 270 capacity-dmips-mhz = <1740>; 271 dynamic-power-coefficient = <405>; 272 next-level-cache = <&L2_600>; 273 operating-points-v2 = <&cpu6_opp_table>; 274 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 275 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 276 #cooling-cells = <2>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 L2_600: l2-cache { 279 compatible = "cache"; 280 next-level-cache = <&L3_0>; 281 }; 282 }; 283 284 CPU7: cpu@700 { 285 device_type = "cpu"; 286 compatible = "qcom,kryo468"; 287 reg = <0x0 0x700>; 288 enable-method = "psci"; 289 cpu-idle-states = <&BIG_CPU_SLEEP_0 290 &BIG_CPU_SLEEP_1 291 &CLUSTER_SLEEP_0>; 292 capacity-dmips-mhz = <1740>; 293 dynamic-power-coefficient = <405>; 294 next-level-cache = <&L2_700>; 295 operating-points-v2 = <&cpu6_opp_table>; 296 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 297 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 298 #cooling-cells = <2>; 299 qcom,freq-domain = <&cpufreq_hw 1>; 300 L2_700: l2-cache { 301 compatible = "cache"; 302 next-level-cache = <&L3_0>; 303 }; 304 }; 305 306 cpu-map { 307 cluster0 { 308 core0 { 309 cpu = <&CPU0>; 310 }; 311 312 core1 { 313 cpu = <&CPU1>; 314 }; 315 316 core2 { 317 cpu = <&CPU2>; 318 }; 319 320 core3 { 321 cpu = <&CPU3>; 322 }; 323 324 core4 { 325 cpu = <&CPU4>; 326 }; 327 328 core5 { 329 cpu = <&CPU5>; 330 }; 331 332 core6 { 333 cpu = <&CPU6>; 334 }; 335 336 core7 { 337 cpu = <&CPU7>; 338 }; 339 }; 340 }; 341 342 idle-states { 343 entry-method = "psci"; 344 345 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 346 compatible = "arm,idle-state"; 347 idle-state-name = "little-power-down"; 348 arm,psci-suspend-param = <0x40000003>; 349 entry-latency-us = <549>; 350 exit-latency-us = <901>; 351 min-residency-us = <1774>; 352 local-timer-stop; 353 }; 354 355 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 356 compatible = "arm,idle-state"; 357 idle-state-name = "little-rail-power-down"; 358 arm,psci-suspend-param = <0x40000004>; 359 entry-latency-us = <702>; 360 exit-latency-us = <915>; 361 min-residency-us = <4001>; 362 local-timer-stop; 363 }; 364 365 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "big-power-down"; 368 arm,psci-suspend-param = <0x40000003>; 369 entry-latency-us = <523>; 370 exit-latency-us = <1244>; 371 min-residency-us = <2207>; 372 local-timer-stop; 373 }; 374 375 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 376 compatible = "arm,idle-state"; 377 idle-state-name = "big-rail-power-down"; 378 arm,psci-suspend-param = <0x40000004>; 379 entry-latency-us = <526>; 380 exit-latency-us = <1854>; 381 min-residency-us = <5555>; 382 local-timer-stop; 383 }; 384 385 CLUSTER_SLEEP_0: cluster-sleep-0 { 386 compatible = "arm,idle-state"; 387 idle-state-name = "cluster-power-down"; 388 arm,psci-suspend-param = <0x40003444>; 389 entry-latency-us = <3263>; 390 exit-latency-us = <6562>; 391 min-residency-us = <9926>; 392 local-timer-stop; 393 }; 394 }; 395 }; 396 397 cpu0_opp_table: cpu0_opp_table { 398 compatible = "operating-points-v2"; 399 opp-shared; 400 401 cpu0_opp1: opp-300000000 { 402 opp-hz = /bits/ 64 <300000000>; 403 opp-peak-kBps = <1200000 4800000>; 404 }; 405 406 cpu0_opp2: opp-576000000 { 407 opp-hz = /bits/ 64 <576000000>; 408 opp-peak-kBps = <1200000 4800000>; 409 }; 410 411 cpu0_opp3: opp-768000000 { 412 opp-hz = /bits/ 64 <768000000>; 413 opp-peak-kBps = <1200000 4800000>; 414 }; 415 416 cpu0_opp4: opp-1017600000 { 417 opp-hz = /bits/ 64 <1017600000>; 418 opp-peak-kBps = <1804000 8908800>; 419 }; 420 421 cpu0_opp5: opp-1248000000 { 422 opp-hz = /bits/ 64 <1248000000>; 423 opp-peak-kBps = <2188000 12902400>; 424 }; 425 426 cpu0_opp6: opp-1324800000 { 427 opp-hz = /bits/ 64 <1324800000>; 428 opp-peak-kBps = <2188000 12902400>; 429 }; 430 431 cpu0_opp7: opp-1516800000 { 432 opp-hz = /bits/ 64 <1516800000>; 433 opp-peak-kBps = <3072000 15052800>; 434 }; 435 436 cpu0_opp8: opp-1612800000 { 437 opp-hz = /bits/ 64 <1612800000>; 438 opp-peak-kBps = <3072000 15052800>; 439 }; 440 441 cpu0_opp9: opp-1708800000 { 442 opp-hz = /bits/ 64 <1708800000>; 443 opp-peak-kBps = <3072000 15052800>; 444 }; 445 446 cpu0_opp10: opp-1804800000 { 447 opp-hz = /bits/ 64 <1804800000>; 448 opp-peak-kBps = <4068000 22425600>; 449 }; 450 }; 451 452 cpu6_opp_table: cpu6_opp_table { 453 compatible = "operating-points-v2"; 454 opp-shared; 455 456 cpu6_opp1: opp-300000000 { 457 opp-hz = /bits/ 64 <300000000>; 458 opp-peak-kBps = <2188000 8908800>; 459 }; 460 461 cpu6_opp2: opp-652800000 { 462 opp-hz = /bits/ 64 <652800000>; 463 opp-peak-kBps = <2188000 8908800>; 464 }; 465 466 cpu6_opp3: opp-825600000 { 467 opp-hz = /bits/ 64 <825600000>; 468 opp-peak-kBps = <2188000 8908800>; 469 }; 470 471 cpu6_opp4: opp-979200000 { 472 opp-hz = /bits/ 64 <979200000>; 473 opp-peak-kBps = <2188000 8908800>; 474 }; 475 476 cpu6_opp5: opp-1113600000 { 477 opp-hz = /bits/ 64 <1113600000>; 478 opp-peak-kBps = <2188000 8908800>; 479 }; 480 481 cpu6_opp6: opp-1267200000 { 482 opp-hz = /bits/ 64 <1267200000>; 483 opp-peak-kBps = <4068000 12902400>; 484 }; 485 486 cpu6_opp7: opp-1555200000 { 487 opp-hz = /bits/ 64 <1555200000>; 488 opp-peak-kBps = <4068000 15052800>; 489 }; 490 491 cpu6_opp8: opp-1708800000 { 492 opp-hz = /bits/ 64 <1708800000>; 493 opp-peak-kBps = <6220000 19353600>; 494 }; 495 496 cpu6_opp9: opp-1843200000 { 497 opp-hz = /bits/ 64 <1843200000>; 498 opp-peak-kBps = <6220000 19353600>; 499 }; 500 501 cpu6_opp10: opp-1900800000 { 502 opp-hz = /bits/ 64 <1900800000>; 503 opp-peak-kBps = <6220000 22425600>; 504 }; 505 506 cpu6_opp11: opp-1996800000 { 507 opp-hz = /bits/ 64 <1996800000>; 508 opp-peak-kBps = <6220000 22425600>; 509 }; 510 511 cpu6_opp12: opp-2112000000 { 512 opp-hz = /bits/ 64 <2112000000>; 513 opp-peak-kBps = <6220000 22425600>; 514 }; 515 516 cpu6_opp13: opp-2208000000 { 517 opp-hz = /bits/ 64 <2208000000>; 518 opp-peak-kBps = <7216000 22425600>; 519 }; 520 521 cpu6_opp14: opp-2323200000 { 522 opp-hz = /bits/ 64 <2323200000>; 523 opp-peak-kBps = <7216000 22425600>; 524 }; 525 526 cpu6_opp15: opp-2400000000 { 527 opp-hz = /bits/ 64 <2400000000>; 528 opp-peak-kBps = <8532000 23347200>; 529 }; 530 531 cpu6_opp16: opp-2553600000 { 532 opp-hz = /bits/ 64 <2553600000>; 533 opp-peak-kBps = <8532000 23347200>; 534 }; 535 }; 536 537 memory@80000000 { 538 device_type = "memory"; 539 /* We expect the bootloader to fill in the size */ 540 reg = <0 0x80000000 0 0>; 541 }; 542 543 pmu { 544 compatible = "arm,armv8-pmuv3"; 545 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 546 }; 547 548 firmware { 549 scm { 550 compatible = "qcom,scm-sc7180", "qcom,scm"; 551 }; 552 }; 553 554 tcsr_mutex: hwlock { 555 compatible = "qcom,tcsr-mutex"; 556 syscon = <&tcsr_mutex_regs 0 0x1000>; 557 #hwlock-cells = <1>; 558 }; 559 560 smem { 561 compatible = "qcom,smem"; 562 memory-region = <&smem_mem>; 563 hwlocks = <&tcsr_mutex 3>; 564 }; 565 566 smp2p-cdsp { 567 compatible = "qcom,smp2p"; 568 qcom,smem = <94>, <432>; 569 570 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 571 572 mboxes = <&apss_shared 6>; 573 574 qcom,local-pid = <0>; 575 qcom,remote-pid = <5>; 576 577 cdsp_smp2p_out: master-kernel { 578 qcom,entry-name = "master-kernel"; 579 #qcom,smem-state-cells = <1>; 580 }; 581 582 cdsp_smp2p_in: slave-kernel { 583 qcom,entry-name = "slave-kernel"; 584 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 }; 589 590 smp2p-lpass { 591 compatible = "qcom,smp2p"; 592 qcom,smem = <443>, <429>; 593 594 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 595 596 mboxes = <&apss_shared 10>; 597 598 qcom,local-pid = <0>; 599 qcom,remote-pid = <2>; 600 601 adsp_smp2p_out: master-kernel { 602 qcom,entry-name = "master-kernel"; 603 #qcom,smem-state-cells = <1>; 604 }; 605 606 adsp_smp2p_in: slave-kernel { 607 qcom,entry-name = "slave-kernel"; 608 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 }; 613 614 smp2p-mpss { 615 compatible = "qcom,smp2p"; 616 qcom,smem = <435>, <428>; 617 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 618 mboxes = <&apss_shared 14>; 619 qcom,local-pid = <0>; 620 qcom,remote-pid = <1>; 621 622 modem_smp2p_out: master-kernel { 623 qcom,entry-name = "master-kernel"; 624 #qcom,smem-state-cells = <1>; 625 }; 626 627 modem_smp2p_in: slave-kernel { 628 qcom,entry-name = "slave-kernel"; 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 }; 632 633 ipa_smp2p_out: ipa-ap-to-modem { 634 qcom,entry-name = "ipa"; 635 #qcom,smem-state-cells = <1>; 636 }; 637 638 ipa_smp2p_in: ipa-modem-to-ap { 639 qcom,entry-name = "ipa"; 640 interrupt-controller; 641 #interrupt-cells = <2>; 642 }; 643 }; 644 645 psci { 646 compatible = "arm,psci-1.0"; 647 method = "smc"; 648 }; 649 650 soc: soc@0 { 651 #address-cells = <2>; 652 #size-cells = <2>; 653 ranges = <0 0 0 0 0x10 0>; 654 dma-ranges = <0 0 0 0 0x10 0>; 655 compatible = "simple-bus"; 656 657 gcc: clock-controller@100000 { 658 compatible = "qcom,gcc-sc7180"; 659 reg = <0 0x00100000 0 0x1f0000>; 660 clocks = <&rpmhcc RPMH_CXO_CLK>, 661 <&rpmhcc RPMH_CXO_CLK_A>, 662 <&sleep_clk>; 663 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 664 #clock-cells = <1>; 665 #reset-cells = <1>; 666 #power-domain-cells = <1>; 667 }; 668 669 qfprom: efuse@784000 { 670 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 671 reg = <0 0x00784000 0 0x8ff>, 672 <0 0x00780000 0 0x7a0>, 673 <0 0x00782000 0 0x100>, 674 <0 0x00786000 0 0x1fff>; 675 676 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 677 clock-names = "core"; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 681 qusb2p_hstx_trim: hstx-trim-primary@25b { 682 reg = <0x25b 0x1>; 683 bits = <1 3>; 684 }; 685 686 gpu_speed_bin: gpu_speed_bin@1d2 { 687 reg = <0x1d2 0x2>; 688 bits = <5 8>; 689 }; 690 }; 691 692 sdhc_1: sdhci@7c4000 { 693 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 694 reg = <0 0x7c4000 0 0x1000>, 695 <0 0x07c5000 0 0x1000>; 696 reg-names = "hc", "cqhci"; 697 698 iommus = <&apps_smmu 0x60 0x0>; 699 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "hc_irq", "pwr_irq"; 702 703 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 704 <&gcc GCC_SDCC1_AHB_CLK>; 705 clock-names = "core", "iface"; 706 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 707 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 708 interconnect-names = "sdhc-ddr","cpu-sdhc"; 709 power-domains = <&rpmhpd SC7180_CX>; 710 operating-points-v2 = <&sdhc1_opp_table>; 711 712 bus-width = <8>; 713 non-removable; 714 supports-cqe; 715 716 mmc-ddr-1_8v; 717 mmc-hs200-1_8v; 718 mmc-hs400-1_8v; 719 mmc-hs400-enhanced-strobe; 720 721 status = "disabled"; 722 723 sdhc1_opp_table: sdhc1-opp-table { 724 compatible = "operating-points-v2"; 725 726 opp-100000000 { 727 opp-hz = /bits/ 64 <100000000>; 728 required-opps = <&rpmhpd_opp_low_svs>; 729 opp-peak-kBps = <100000 100000>; 730 opp-avg-kBps = <100000 50000>; 731 }; 732 733 opp-384000000 { 734 opp-hz = /bits/ 64 <384000000>; 735 required-opps = <&rpmhpd_opp_svs_l1>; 736 opp-peak-kBps = <600000 900000>; 737 opp-avg-kBps = <261438 300000>; 738 }; 739 }; 740 }; 741 742 qup_opp_table: qup-opp-table { 743 compatible = "operating-points-v2"; 744 745 opp-75000000 { 746 opp-hz = /bits/ 64 <75000000>; 747 required-opps = <&rpmhpd_opp_low_svs>; 748 }; 749 750 opp-100000000 { 751 opp-hz = /bits/ 64 <100000000>; 752 required-opps = <&rpmhpd_opp_svs>; 753 }; 754 755 opp-128000000 { 756 opp-hz = /bits/ 64 <128000000>; 757 required-opps = <&rpmhpd_opp_nom>; 758 }; 759 }; 760 761 qupv3_id_0: geniqup@8c0000 { 762 compatible = "qcom,geni-se-qup"; 763 reg = <0 0x008c0000 0 0x6000>; 764 clock-names = "m-ahb", "s-ahb"; 765 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 766 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 767 #address-cells = <2>; 768 #size-cells = <2>; 769 ranges; 770 iommus = <&apps_smmu 0x43 0x0>; 771 status = "disabled"; 772 773 i2c0: i2c@880000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0 0x00880000 0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&qup_i2c0_default>; 780 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 784 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 785 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 786 interconnect-names = "qup-core", "qup-config", 787 "qup-memory"; 788 status = "disabled"; 789 }; 790 791 spi0: spi@880000 { 792 compatible = "qcom,geni-spi"; 793 reg = <0 0x00880000 0 0x4000>; 794 clock-names = "se"; 795 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 796 pinctrl-names = "default"; 797 pinctrl-0 = <&qup_spi0_default>; 798 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 power-domains = <&rpmhpd SC7180_CX>; 802 operating-points-v2 = <&qup_opp_table>; 803 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 804 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 805 interconnect-names = "qup-core", "qup-config"; 806 status = "disabled"; 807 }; 808 809 uart0: serial@880000 { 810 compatible = "qcom,geni-uart"; 811 reg = <0 0x00880000 0 0x4000>; 812 clock-names = "se"; 813 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 814 pinctrl-names = "default"; 815 pinctrl-0 = <&qup_uart0_default>; 816 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 817 power-domains = <&rpmhpd SC7180_CX>; 818 operating-points-v2 = <&qup_opp_table>; 819 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 820 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 821 interconnect-names = "qup-core", "qup-config"; 822 status = "disabled"; 823 }; 824 825 i2c1: i2c@884000 { 826 compatible = "qcom,geni-i2c"; 827 reg = <0 0x00884000 0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&qup_i2c1_default>; 832 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 836 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 837 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 838 interconnect-names = "qup-core", "qup-config", 839 "qup-memory"; 840 status = "disabled"; 841 }; 842 843 spi1: spi@884000 { 844 compatible = "qcom,geni-spi"; 845 reg = <0 0x00884000 0 0x4000>; 846 clock-names = "se"; 847 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&qup_spi1_default>; 850 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 power-domains = <&rpmhpd SC7180_CX>; 854 operating-points-v2 = <&qup_opp_table>; 855 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 856 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 857 interconnect-names = "qup-core", "qup-config"; 858 status = "disabled"; 859 }; 860 861 uart1: serial@884000 { 862 compatible = "qcom,geni-uart"; 863 reg = <0 0x00884000 0 0x4000>; 864 clock-names = "se"; 865 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&qup_uart1_default>; 868 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 869 power-domains = <&rpmhpd SC7180_CX>; 870 operating-points-v2 = <&qup_opp_table>; 871 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 872 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 873 interconnect-names = "qup-core", "qup-config"; 874 status = "disabled"; 875 }; 876 877 i2c2: i2c@888000 { 878 compatible = "qcom,geni-i2c"; 879 reg = <0 0x00888000 0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&qup_i2c2_default>; 884 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 889 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 890 interconnect-names = "qup-core", "qup-config", 891 "qup-memory"; 892 status = "disabled"; 893 }; 894 895 uart2: serial@888000 { 896 compatible = "qcom,geni-uart"; 897 reg = <0 0x00888000 0 0x4000>; 898 clock-names = "se"; 899 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 900 pinctrl-names = "default"; 901 pinctrl-0 = <&qup_uart2_default>; 902 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 903 power-domains = <&rpmhpd SC7180_CX>; 904 operating-points-v2 = <&qup_opp_table>; 905 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 906 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 907 interconnect-names = "qup-core", "qup-config"; 908 status = "disabled"; 909 }; 910 911 i2c3: i2c@88c000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0 0x0088c000 0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&qup_i2c3_default>; 918 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 922 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 923 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 924 interconnect-names = "qup-core", "qup-config", 925 "qup-memory"; 926 status = "disabled"; 927 }; 928 929 spi3: spi@88c000 { 930 compatible = "qcom,geni-spi"; 931 reg = <0 0x0088c000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_spi3_default>; 936 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 power-domains = <&rpmhpd SC7180_CX>; 940 operating-points-v2 = <&qup_opp_table>; 941 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 943 interconnect-names = "qup-core", "qup-config"; 944 status = "disabled"; 945 }; 946 947 uart3: serial@88c000 { 948 compatible = "qcom,geni-uart"; 949 reg = <0 0x0088c000 0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_uart3_default>; 954 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 955 power-domains = <&rpmhpd SC7180_CX>; 956 operating-points-v2 = <&qup_opp_table>; 957 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 959 interconnect-names = "qup-core", "qup-config"; 960 status = "disabled"; 961 }; 962 963 i2c4: i2c@890000 { 964 compatible = "qcom,geni-i2c"; 965 reg = <0 0x00890000 0 0x4000>; 966 clock-names = "se"; 967 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_i2c4_default>; 970 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 974 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 975 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 976 interconnect-names = "qup-core", "qup-config", 977 "qup-memory"; 978 status = "disabled"; 979 }; 980 981 uart4: serial@890000 { 982 compatible = "qcom,geni-uart"; 983 reg = <0 0x00890000 0 0x4000>; 984 clock-names = "se"; 985 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 986 pinctrl-names = "default"; 987 pinctrl-0 = <&qup_uart4_default>; 988 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 989 power-domains = <&rpmhpd SC7180_CX>; 990 operating-points-v2 = <&qup_opp_table>; 991 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 992 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 993 interconnect-names = "qup-core", "qup-config"; 994 status = "disabled"; 995 }; 996 997 i2c5: i2c@894000 { 998 compatible = "qcom,geni-i2c"; 999 reg = <0 0x00894000 0 0x4000>; 1000 clock-names = "se"; 1001 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_i2c5_default>; 1004 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1008 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1009 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1010 interconnect-names = "qup-core", "qup-config", 1011 "qup-memory"; 1012 status = "disabled"; 1013 }; 1014 1015 spi5: spi@894000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00894000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_spi5_default>; 1022 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 power-domains = <&rpmhpd SC7180_CX>; 1026 operating-points-v2 = <&qup_opp_table>; 1027 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1028 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1029 interconnect-names = "qup-core", "qup-config"; 1030 status = "disabled"; 1031 }; 1032 1033 uart5: serial@894000 { 1034 compatible = "qcom,geni-uart"; 1035 reg = <0 0x00894000 0 0x4000>; 1036 clock-names = "se"; 1037 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&qup_uart5_default>; 1040 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1041 power-domains = <&rpmhpd SC7180_CX>; 1042 operating-points-v2 = <&qup_opp_table>; 1043 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1044 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1045 interconnect-names = "qup-core", "qup-config"; 1046 status = "disabled"; 1047 }; 1048 }; 1049 1050 qupv3_id_1: geniqup@ac0000 { 1051 compatible = "qcom,geni-se-qup"; 1052 reg = <0 0x00ac0000 0 0x6000>; 1053 clock-names = "m-ahb", "s-ahb"; 1054 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1055 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1056 #address-cells = <2>; 1057 #size-cells = <2>; 1058 ranges; 1059 iommus = <&apps_smmu 0x4c3 0x0>; 1060 status = "disabled"; 1061 1062 i2c6: i2c@a80000 { 1063 compatible = "qcom,geni-i2c"; 1064 reg = <0 0x00a80000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&qup_i2c6_default>; 1069 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1073 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1074 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1075 interconnect-names = "qup-core", "qup-config", 1076 "qup-memory"; 1077 status = "disabled"; 1078 }; 1079 1080 spi6: spi@a80000 { 1081 compatible = "qcom,geni-spi"; 1082 reg = <0 0x00a80000 0 0x4000>; 1083 clock-names = "se"; 1084 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&qup_spi6_default>; 1087 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 power-domains = <&rpmhpd SC7180_CX>; 1091 operating-points-v2 = <&qup_opp_table>; 1092 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1093 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1094 interconnect-names = "qup-core", "qup-config"; 1095 status = "disabled"; 1096 }; 1097 1098 uart6: serial@a80000 { 1099 compatible = "qcom,geni-uart"; 1100 reg = <0 0x00a80000 0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_uart6_default>; 1105 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1106 power-domains = <&rpmhpd SC7180_CX>; 1107 operating-points-v2 = <&qup_opp_table>; 1108 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1109 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1110 interconnect-names = "qup-core", "qup-config"; 1111 status = "disabled"; 1112 }; 1113 1114 i2c7: i2c@a84000 { 1115 compatible = "qcom,geni-i2c"; 1116 reg = <0 0x00a84000 0 0x4000>; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&qup_i2c7_default>; 1121 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1125 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1126 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1127 interconnect-names = "qup-core", "qup-config", 1128 "qup-memory"; 1129 status = "disabled"; 1130 }; 1131 1132 uart7: serial@a84000 { 1133 compatible = "qcom,geni-uart"; 1134 reg = <0 0x00a84000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&qup_uart7_default>; 1139 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1140 power-domains = <&rpmhpd SC7180_CX>; 1141 operating-points-v2 = <&qup_opp_table>; 1142 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1143 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1144 interconnect-names = "qup-core", "qup-config"; 1145 status = "disabled"; 1146 }; 1147 1148 i2c8: i2c@a88000 { 1149 compatible = "qcom,geni-i2c"; 1150 reg = <0 0x00a88000 0 0x4000>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_i2c8_default>; 1155 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1159 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1160 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1161 interconnect-names = "qup-core", "qup-config", 1162 "qup-memory"; 1163 status = "disabled"; 1164 }; 1165 1166 spi8: spi@a88000 { 1167 compatible = "qcom,geni-spi"; 1168 reg = <0 0x00a88000 0 0x4000>; 1169 clock-names = "se"; 1170 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1171 pinctrl-names = "default"; 1172 pinctrl-0 = <&qup_spi8_default>; 1173 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 power-domains = <&rpmhpd SC7180_CX>; 1177 operating-points-v2 = <&qup_opp_table>; 1178 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1179 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1180 interconnect-names = "qup-core", "qup-config"; 1181 status = "disabled"; 1182 }; 1183 1184 uart8: serial@a88000 { 1185 compatible = "qcom,geni-debug-uart"; 1186 reg = <0 0x00a88000 0 0x4000>; 1187 clock-names = "se"; 1188 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_uart8_default>; 1191 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1192 power-domains = <&rpmhpd SC7180_CX>; 1193 operating-points-v2 = <&qup_opp_table>; 1194 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1196 interconnect-names = "qup-core", "qup-config"; 1197 status = "disabled"; 1198 }; 1199 1200 i2c9: i2c@a8c000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0 0x00a8c000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_i2c9_default>; 1207 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1212 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1213 interconnect-names = "qup-core", "qup-config", 1214 "qup-memory"; 1215 status = "disabled"; 1216 }; 1217 1218 uart9: serial@a8c000 { 1219 compatible = "qcom,geni-uart"; 1220 reg = <0 0x00a8c000 0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_uart9_default>; 1225 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1226 power-domains = <&rpmhpd SC7180_CX>; 1227 operating-points-v2 = <&qup_opp_table>; 1228 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1230 interconnect-names = "qup-core", "qup-config"; 1231 status = "disabled"; 1232 }; 1233 1234 i2c10: i2c@a90000 { 1235 compatible = "qcom,geni-i2c"; 1236 reg = <0 0x00a90000 0 0x4000>; 1237 clock-names = "se"; 1238 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&qup_i2c10_default>; 1241 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1245 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1246 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1247 interconnect-names = "qup-core", "qup-config", 1248 "qup-memory"; 1249 status = "disabled"; 1250 }; 1251 1252 spi10: spi@a90000 { 1253 compatible = "qcom,geni-spi"; 1254 reg = <0 0x00a90000 0 0x4000>; 1255 clock-names = "se"; 1256 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&qup_spi10_default>; 1259 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 power-domains = <&rpmhpd SC7180_CX>; 1263 operating-points-v2 = <&qup_opp_table>; 1264 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1265 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1266 interconnect-names = "qup-core", "qup-config"; 1267 status = "disabled"; 1268 }; 1269 1270 uart10: serial@a90000 { 1271 compatible = "qcom,geni-uart"; 1272 reg = <0 0x00a90000 0 0x4000>; 1273 clock-names = "se"; 1274 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1275 pinctrl-names = "default"; 1276 pinctrl-0 = <&qup_uart10_default>; 1277 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1278 power-domains = <&rpmhpd SC7180_CX>; 1279 operating-points-v2 = <&qup_opp_table>; 1280 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1281 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1282 interconnect-names = "qup-core", "qup-config"; 1283 status = "disabled"; 1284 }; 1285 1286 i2c11: i2c@a94000 { 1287 compatible = "qcom,geni-i2c"; 1288 reg = <0 0x00a94000 0 0x4000>; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_i2c11_default>; 1293 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1297 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1298 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1299 interconnect-names = "qup-core", "qup-config", 1300 "qup-memory"; 1301 status = "disabled"; 1302 }; 1303 1304 spi11: spi@a94000 { 1305 compatible = "qcom,geni-spi"; 1306 reg = <0 0x00a94000 0 0x4000>; 1307 clock-names = "se"; 1308 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1309 pinctrl-names = "default"; 1310 pinctrl-0 = <&qup_spi11_default>; 1311 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 power-domains = <&rpmhpd SC7180_CX>; 1315 operating-points-v2 = <&qup_opp_table>; 1316 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1317 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1318 interconnect-names = "qup-core", "qup-config"; 1319 status = "disabled"; 1320 }; 1321 1322 uart11: serial@a94000 { 1323 compatible = "qcom,geni-uart"; 1324 reg = <0 0x00a94000 0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_uart11_default>; 1329 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1330 power-domains = <&rpmhpd SC7180_CX>; 1331 operating-points-v2 = <&qup_opp_table>; 1332 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1333 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1334 interconnect-names = "qup-core", "qup-config"; 1335 status = "disabled"; 1336 }; 1337 }; 1338 1339 config_noc: interconnect@1500000 { 1340 compatible = "qcom,sc7180-config-noc"; 1341 reg = <0 0x01500000 0 0x28000>; 1342 #interconnect-cells = <2>; 1343 qcom,bcm-voters = <&apps_bcm_voter>; 1344 }; 1345 1346 system_noc: interconnect@1620000 { 1347 compatible = "qcom,sc7180-system-noc"; 1348 reg = <0 0x01620000 0 0x17080>; 1349 #interconnect-cells = <2>; 1350 qcom,bcm-voters = <&apps_bcm_voter>; 1351 }; 1352 1353 mc_virt: interconnect@1638000 { 1354 compatible = "qcom,sc7180-mc-virt"; 1355 reg = <0 0x01638000 0 0x1000>; 1356 #interconnect-cells = <2>; 1357 qcom,bcm-voters = <&apps_bcm_voter>; 1358 }; 1359 1360 qup_virt: interconnect@1650000 { 1361 compatible = "qcom,sc7180-qup-virt"; 1362 reg = <0 0x01650000 0 0x1000>; 1363 #interconnect-cells = <2>; 1364 qcom,bcm-voters = <&apps_bcm_voter>; 1365 }; 1366 1367 aggre1_noc: interconnect@16e0000 { 1368 compatible = "qcom,sc7180-aggre1-noc"; 1369 reg = <0 0x016e0000 0 0x15080>; 1370 #interconnect-cells = <2>; 1371 qcom,bcm-voters = <&apps_bcm_voter>; 1372 }; 1373 1374 aggre2_noc: interconnect@1705000 { 1375 compatible = "qcom,sc7180-aggre2-noc"; 1376 reg = <0 0x01705000 0 0x9000>; 1377 #interconnect-cells = <2>; 1378 qcom,bcm-voters = <&apps_bcm_voter>; 1379 }; 1380 1381 compute_noc: interconnect@170e000 { 1382 compatible = "qcom,sc7180-compute-noc"; 1383 reg = <0 0x0170e000 0 0x6000>; 1384 #interconnect-cells = <2>; 1385 qcom,bcm-voters = <&apps_bcm_voter>; 1386 }; 1387 1388 mmss_noc: interconnect@1740000 { 1389 compatible = "qcom,sc7180-mmss-noc"; 1390 reg = <0 0x01740000 0 0x1c100>; 1391 #interconnect-cells = <2>; 1392 qcom,bcm-voters = <&apps_bcm_voter>; 1393 }; 1394 1395 ipa_virt: interconnect@1e00000 { 1396 compatible = "qcom,sc7180-ipa-virt"; 1397 reg = <0 0x01e00000 0 0x1000>; 1398 #interconnect-cells = <2>; 1399 qcom,bcm-voters = <&apps_bcm_voter>; 1400 }; 1401 1402 ipa: ipa@1e40000 { 1403 compatible = "qcom,sc7180-ipa"; 1404 1405 iommus = <&apps_smmu 0x440 0x0>, 1406 <&apps_smmu 0x442 0x0>; 1407 reg = <0 0x1e40000 0 0x7000>, 1408 <0 0x1e47000 0 0x2000>, 1409 <0 0x1e04000 0 0x2c000>; 1410 reg-names = "ipa-reg", 1411 "ipa-shared", 1412 "gsi"; 1413 1414 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1415 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1416 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1417 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1418 interrupt-names = "ipa", 1419 "gsi", 1420 "ipa-clock-query", 1421 "ipa-setup-ready"; 1422 1423 clocks = <&rpmhcc RPMH_IPA_CLK>; 1424 clock-names = "core"; 1425 1426 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1427 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1428 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1429 interconnect-names = "memory", 1430 "imem", 1431 "config"; 1432 1433 qcom,smem-states = <&ipa_smp2p_out 0>, 1434 <&ipa_smp2p_out 1>; 1435 qcom,smem-state-names = "ipa-clock-enabled-valid", 1436 "ipa-clock-enabled"; 1437 1438 status = "disabled"; 1439 }; 1440 1441 tcsr_mutex_regs: syscon@1f40000 { 1442 compatible = "syscon"; 1443 reg = <0 0x01f40000 0 0x40000>; 1444 }; 1445 1446 tcsr_regs: syscon@1fc0000 { 1447 compatible = "syscon"; 1448 reg = <0 0x01fc0000 0 0x40000>; 1449 }; 1450 1451 tlmm: pinctrl@3500000 { 1452 compatible = "qcom,sc7180-pinctrl"; 1453 reg = <0 0x03500000 0 0x300000>, 1454 <0 0x03900000 0 0x300000>, 1455 <0 0x03d00000 0 0x300000>; 1456 reg-names = "west", "north", "south"; 1457 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1458 gpio-controller; 1459 #gpio-cells = <2>; 1460 interrupt-controller; 1461 #interrupt-cells = <2>; 1462 gpio-ranges = <&tlmm 0 0 120>; 1463 wakeup-parent = <&pdc>; 1464 1465 dp_hot_plug_det: dp-hot-plug-det { 1466 pinmux { 1467 pins = "gpio117"; 1468 function = "dp_hot"; 1469 }; 1470 }; 1471 1472 qspi_clk: qspi-clk { 1473 pinmux { 1474 pins = "gpio63"; 1475 function = "qspi_clk"; 1476 }; 1477 }; 1478 1479 qspi_cs0: qspi-cs0 { 1480 pinmux { 1481 pins = "gpio68"; 1482 function = "qspi_cs"; 1483 }; 1484 }; 1485 1486 qspi_cs1: qspi-cs1 { 1487 pinmux { 1488 pins = "gpio72"; 1489 function = "qspi_cs"; 1490 }; 1491 }; 1492 1493 qspi_data01: qspi-data01 { 1494 pinmux-data { 1495 pins = "gpio64", "gpio65"; 1496 function = "qspi_data"; 1497 }; 1498 }; 1499 1500 qspi_data12: qspi-data12 { 1501 pinmux-data { 1502 pins = "gpio66", "gpio67"; 1503 function = "qspi_data"; 1504 }; 1505 }; 1506 1507 qup_i2c0_default: qup-i2c0-default { 1508 pinmux { 1509 pins = "gpio34", "gpio35"; 1510 function = "qup00"; 1511 }; 1512 }; 1513 1514 qup_i2c1_default: qup-i2c1-default { 1515 pinmux { 1516 pins = "gpio0", "gpio1"; 1517 function = "qup01"; 1518 }; 1519 }; 1520 1521 qup_i2c2_default: qup-i2c2-default { 1522 pinmux { 1523 pins = "gpio15", "gpio16"; 1524 function = "qup02_i2c"; 1525 }; 1526 }; 1527 1528 qup_i2c3_default: qup-i2c3-default { 1529 pinmux { 1530 pins = "gpio38", "gpio39"; 1531 function = "qup03"; 1532 }; 1533 }; 1534 1535 qup_i2c4_default: qup-i2c4-default { 1536 pinmux { 1537 pins = "gpio115", "gpio116"; 1538 function = "qup04_i2c"; 1539 }; 1540 }; 1541 1542 qup_i2c5_default: qup-i2c5-default { 1543 pinmux { 1544 pins = "gpio25", "gpio26"; 1545 function = "qup05"; 1546 }; 1547 }; 1548 1549 qup_i2c6_default: qup-i2c6-default { 1550 pinmux { 1551 pins = "gpio59", "gpio60"; 1552 function = "qup10"; 1553 }; 1554 }; 1555 1556 qup_i2c7_default: qup-i2c7-default { 1557 pinmux { 1558 pins = "gpio6", "gpio7"; 1559 function = "qup11_i2c"; 1560 }; 1561 }; 1562 1563 qup_i2c8_default: qup-i2c8-default { 1564 pinmux { 1565 pins = "gpio42", "gpio43"; 1566 function = "qup12"; 1567 }; 1568 }; 1569 1570 qup_i2c9_default: qup-i2c9-default { 1571 pinmux { 1572 pins = "gpio46", "gpio47"; 1573 function = "qup13_i2c"; 1574 }; 1575 }; 1576 1577 qup_i2c10_default: qup-i2c10-default { 1578 pinmux { 1579 pins = "gpio86", "gpio87"; 1580 function = "qup14"; 1581 }; 1582 }; 1583 1584 qup_i2c11_default: qup-i2c11-default { 1585 pinmux { 1586 pins = "gpio53", "gpio54"; 1587 function = "qup15"; 1588 }; 1589 }; 1590 1591 qup_spi0_default: qup-spi0-default { 1592 pinmux { 1593 pins = "gpio34", "gpio35", 1594 "gpio36", "gpio37"; 1595 function = "qup00"; 1596 }; 1597 }; 1598 1599 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 1600 pinmux { 1601 pins = "gpio34", "gpio35", 1602 "gpio36"; 1603 function = "qup00"; 1604 }; 1605 1606 pinmux-cs { 1607 pins = "gpio37"; 1608 function = "gpio"; 1609 }; 1610 }; 1611 1612 qup_spi1_default: qup-spi1-default { 1613 pinmux { 1614 pins = "gpio0", "gpio1", 1615 "gpio2", "gpio3"; 1616 function = "qup01"; 1617 }; 1618 }; 1619 1620 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 1621 pinmux { 1622 pins = "gpio0", "gpio1", 1623 "gpio2"; 1624 function = "qup01"; 1625 }; 1626 1627 pinmux-cs { 1628 pins = "gpio3"; 1629 function = "gpio"; 1630 }; 1631 }; 1632 1633 qup_spi3_default: qup-spi3-default { 1634 pinmux { 1635 pins = "gpio38", "gpio39", 1636 "gpio40", "gpio41"; 1637 function = "qup03"; 1638 }; 1639 }; 1640 1641 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 1642 pinmux { 1643 pins = "gpio38", "gpio39", 1644 "gpio40"; 1645 function = "qup03"; 1646 }; 1647 1648 pinmux-cs { 1649 pins = "gpio41"; 1650 function = "gpio"; 1651 }; 1652 }; 1653 1654 qup_spi5_default: qup-spi5-default { 1655 pinmux { 1656 pins = "gpio25", "gpio26", 1657 "gpio27", "gpio28"; 1658 function = "qup05"; 1659 }; 1660 }; 1661 1662 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 1663 pinmux { 1664 pins = "gpio25", "gpio26", 1665 "gpio27"; 1666 function = "qup05"; 1667 }; 1668 1669 pinmux-cs { 1670 pins = "gpio28"; 1671 function = "gpio"; 1672 }; 1673 }; 1674 1675 qup_spi6_default: qup-spi6-default { 1676 pinmux { 1677 pins = "gpio59", "gpio60", 1678 "gpio61", "gpio62"; 1679 function = "qup10"; 1680 }; 1681 }; 1682 1683 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 1684 pinmux { 1685 pins = "gpio59", "gpio60", 1686 "gpio61"; 1687 function = "qup10"; 1688 }; 1689 1690 pinmux-cs { 1691 pins = "gpio62"; 1692 function = "gpio"; 1693 }; 1694 }; 1695 1696 qup_spi8_default: qup-spi8-default { 1697 pinmux { 1698 pins = "gpio42", "gpio43", 1699 "gpio44", "gpio45"; 1700 function = "qup12"; 1701 }; 1702 }; 1703 1704 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 1705 pinmux { 1706 pins = "gpio42", "gpio43", 1707 "gpio44"; 1708 function = "qup12"; 1709 }; 1710 1711 pinmux-cs { 1712 pins = "gpio45"; 1713 function = "gpio"; 1714 }; 1715 }; 1716 1717 qup_spi10_default: qup-spi10-default { 1718 pinmux { 1719 pins = "gpio86", "gpio87", 1720 "gpio88", "gpio89"; 1721 function = "qup14"; 1722 }; 1723 }; 1724 1725 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 1726 pinmux { 1727 pins = "gpio86", "gpio87", 1728 "gpio88"; 1729 function = "qup14"; 1730 }; 1731 1732 pinmux-cs { 1733 pins = "gpio89"; 1734 function = "gpio"; 1735 }; 1736 }; 1737 1738 qup_spi11_default: qup-spi11-default { 1739 pinmux { 1740 pins = "gpio53", "gpio54", 1741 "gpio55", "gpio56"; 1742 function = "qup15"; 1743 }; 1744 }; 1745 1746 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 1747 pinmux { 1748 pins = "gpio53", "gpio54", 1749 "gpio55"; 1750 function = "qup15"; 1751 }; 1752 1753 pinmux-cs { 1754 pins = "gpio56"; 1755 function = "gpio"; 1756 }; 1757 }; 1758 1759 qup_uart0_default: qup-uart0-default { 1760 pinmux { 1761 pins = "gpio34", "gpio35", 1762 "gpio36", "gpio37"; 1763 function = "qup00"; 1764 }; 1765 }; 1766 1767 qup_uart1_default: qup-uart1-default { 1768 pinmux { 1769 pins = "gpio0", "gpio1", 1770 "gpio2", "gpio3"; 1771 function = "qup01"; 1772 }; 1773 }; 1774 1775 qup_uart2_default: qup-uart2-default { 1776 pinmux { 1777 pins = "gpio15", "gpio16"; 1778 function = "qup02_uart"; 1779 }; 1780 }; 1781 1782 qup_uart3_default: qup-uart3-default { 1783 pinmux { 1784 pins = "gpio38", "gpio39", 1785 "gpio40", "gpio41"; 1786 function = "qup03"; 1787 }; 1788 }; 1789 1790 qup_uart4_default: qup-uart4-default { 1791 pinmux { 1792 pins = "gpio115", "gpio116"; 1793 function = "qup04_uart"; 1794 }; 1795 }; 1796 1797 qup_uart5_default: qup-uart5-default { 1798 pinmux { 1799 pins = "gpio25", "gpio26", 1800 "gpio27", "gpio28"; 1801 function = "qup05"; 1802 }; 1803 }; 1804 1805 qup_uart6_default: qup-uart6-default { 1806 pinmux { 1807 pins = "gpio59", "gpio60", 1808 "gpio61", "gpio62"; 1809 function = "qup10"; 1810 }; 1811 }; 1812 1813 qup_uart7_default: qup-uart7-default { 1814 pinmux { 1815 pins = "gpio6", "gpio7"; 1816 function = "qup11_uart"; 1817 }; 1818 }; 1819 1820 qup_uart8_default: qup-uart8-default { 1821 pinmux { 1822 pins = "gpio44", "gpio45"; 1823 function = "qup12"; 1824 }; 1825 }; 1826 1827 qup_uart9_default: qup-uart9-default { 1828 pinmux { 1829 pins = "gpio46", "gpio47"; 1830 function = "qup13_uart"; 1831 }; 1832 }; 1833 1834 qup_uart10_default: qup-uart10-default { 1835 pinmux { 1836 pins = "gpio86", "gpio87", 1837 "gpio88", "gpio89"; 1838 function = "qup14"; 1839 }; 1840 }; 1841 1842 qup_uart11_default: qup-uart11-default { 1843 pinmux { 1844 pins = "gpio53", "gpio54", 1845 "gpio55", "gpio56"; 1846 function = "qup15"; 1847 }; 1848 }; 1849 1850 sec_mi2s_active: sec-mi2s-active { 1851 pinmux { 1852 pins = "gpio49", "gpio50", "gpio51"; 1853 function = "mi2s_1"; 1854 }; 1855 }; 1856 1857 pri_mi2s_active: pri-mi2s-active { 1858 pinmux { 1859 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1860 function = "mi2s_0"; 1861 }; 1862 }; 1863 1864 pri_mi2s_mclk_active: pri-mi2s-mclk-active { 1865 pinmux { 1866 pins = "gpio57"; 1867 function = "lpass_ext"; 1868 }; 1869 }; 1870 1871 sdc1_on: sdc1-on { 1872 pinconf-clk { 1873 pins = "sdc1_clk"; 1874 bias-disable; 1875 drive-strength = <16>; 1876 }; 1877 1878 pinconf-cmd { 1879 pins = "sdc1_cmd"; 1880 bias-pull-up; 1881 drive-strength = <10>; 1882 }; 1883 1884 pinconf-data { 1885 pins = "sdc1_data"; 1886 bias-pull-up; 1887 drive-strength = <10>; 1888 }; 1889 1890 pinconf-rclk { 1891 pins = "sdc1_rclk"; 1892 bias-pull-down; 1893 }; 1894 }; 1895 1896 sdc1_off: sdc1-off { 1897 pinconf-clk { 1898 pins = "sdc1_clk"; 1899 bias-disable; 1900 drive-strength = <2>; 1901 }; 1902 1903 pinconf-cmd { 1904 pins = "sdc1_cmd"; 1905 bias-pull-up; 1906 drive-strength = <2>; 1907 }; 1908 1909 pinconf-data { 1910 pins = "sdc1_data"; 1911 bias-pull-up; 1912 drive-strength = <2>; 1913 }; 1914 1915 pinconf-rclk { 1916 pins = "sdc1_rclk"; 1917 bias-pull-down; 1918 }; 1919 }; 1920 1921 sdc2_on: sdc2-on { 1922 pinconf-clk { 1923 pins = "sdc2_clk"; 1924 bias-disable; 1925 drive-strength = <16>; 1926 }; 1927 1928 pinconf-cmd { 1929 pins = "sdc2_cmd"; 1930 bias-pull-up; 1931 drive-strength = <10>; 1932 }; 1933 1934 pinconf-data { 1935 pins = "sdc2_data"; 1936 bias-pull-up; 1937 drive-strength = <10>; 1938 }; 1939 1940 pinconf-sd-cd { 1941 pins = "gpio69"; 1942 bias-pull-up; 1943 drive-strength = <2>; 1944 }; 1945 }; 1946 1947 sdc2_off: sdc2-off { 1948 pinconf-clk { 1949 pins = "sdc2_clk"; 1950 bias-disable; 1951 drive-strength = <2>; 1952 }; 1953 1954 pinconf-cmd { 1955 pins = "sdc2_cmd"; 1956 bias-pull-up; 1957 drive-strength = <2>; 1958 }; 1959 1960 pinconf-data { 1961 pins = "sdc2_data"; 1962 bias-pull-up; 1963 drive-strength = <2>; 1964 }; 1965 1966 pinconf-sd-cd { 1967 pins = "gpio69"; 1968 bias-disable; 1969 drive-strength = <2>; 1970 }; 1971 }; 1972 }; 1973 1974 remoteproc_mpss: remoteproc@4080000 { 1975 compatible = "qcom,sc7180-mpss-pas"; 1976 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1977 reg-names = "qdsp6", "rmb"; 1978 1979 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1980 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1981 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1982 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1983 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1984 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1985 interrupt-names = "wdog", "fatal", "ready", "handover", 1986 "stop-ack", "shutdown-ack"; 1987 1988 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1989 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1990 <&gcc GCC_MSS_NAV_AXI_CLK>, 1991 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1992 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1993 <&rpmhcc RPMH_CXO_CLK>; 1994 clock-names = "iface", "bus", "nav", "snoc_axi", 1995 "mnoc_axi", "xo"; 1996 1997 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 1998 <&rpmhpd SC7180_CX>, 1999 <&rpmhpd SC7180_MX>, 2000 <&rpmhpd SC7180_MSS>; 2001 power-domain-names = "load_state", "cx", "mx", "mss"; 2002 2003 memory-region = <&mpss_mem>; 2004 2005 qcom,smem-states = <&modem_smp2p_out 0>; 2006 qcom,smem-state-names = "stop"; 2007 2008 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2009 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2010 reset-names = "mss_restart", "pdc_reset"; 2011 2012 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2013 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 2014 2015 status = "disabled"; 2016 2017 glink-edge { 2018 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2019 label = "modem"; 2020 qcom,remote-pid = <1>; 2021 mboxes = <&apss_shared 12>; 2022 }; 2023 }; 2024 2025 gpu: gpu@5000000 { 2026 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2027 #stream-id-cells = <16>; 2028 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2029 <0 0x05061000 0 0x800>; 2030 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2031 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2032 iommus = <&adreno_smmu 0>; 2033 operating-points-v2 = <&gpu_opp_table>; 2034 qcom,gmu = <&gmu>; 2035 2036 #cooling-cells = <2>; 2037 2038 nvmem-cells = <&gpu_speed_bin>; 2039 nvmem-cell-names = "speed_bin"; 2040 2041 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2042 interconnect-names = "gfx-mem"; 2043 2044 gpu_opp_table: opp-table { 2045 compatible = "operating-points-v2"; 2046 2047 opp-825000000 { 2048 opp-hz = /bits/ 64 <825000000>; 2049 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2050 opp-peak-kBps = <8532000>; 2051 opp-supported-hw = <0x04>; 2052 }; 2053 2054 opp-800000000 { 2055 opp-hz = /bits/ 64 <800000000>; 2056 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2057 opp-peak-kBps = <8532000>; 2058 opp-supported-hw = <0x07>; 2059 }; 2060 2061 opp-650000000 { 2062 opp-hz = /bits/ 64 <650000000>; 2063 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2064 opp-peak-kBps = <7216000>; 2065 opp-supported-hw = <0x07>; 2066 }; 2067 2068 opp-565000000 { 2069 opp-hz = /bits/ 64 <565000000>; 2070 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2071 opp-peak-kBps = <5412000>; 2072 opp-supported-hw = <0x07>; 2073 }; 2074 2075 opp-430000000 { 2076 opp-hz = /bits/ 64 <430000000>; 2077 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2078 opp-peak-kBps = <5412000>; 2079 opp-supported-hw = <0x07>; 2080 }; 2081 2082 opp-355000000 { 2083 opp-hz = /bits/ 64 <355000000>; 2084 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2085 opp-peak-kBps = <3072000>; 2086 opp-supported-hw = <0x07>; 2087 }; 2088 2089 opp-267000000 { 2090 opp-hz = /bits/ 64 <267000000>; 2091 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2092 opp-peak-kBps = <3072000>; 2093 opp-supported-hw = <0x07>; 2094 }; 2095 2096 opp-180000000 { 2097 opp-hz = /bits/ 64 <180000000>; 2098 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2099 opp-peak-kBps = <1804000>; 2100 opp-supported-hw = <0x07>; 2101 }; 2102 }; 2103 }; 2104 2105 adreno_smmu: iommu@5040000 { 2106 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2107 reg = <0 0x05040000 0 0x10000>; 2108 #iommu-cells = <1>; 2109 #global-interrupts = <2>; 2110 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2113 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2114 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2115 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2116 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2117 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2118 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2119 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2120 2121 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2122 <&gcc GCC_GPU_CFG_AHB_CLK>; 2123 clock-names = "bus", "iface"; 2124 2125 power-domains = <&gpucc CX_GDSC>; 2126 }; 2127 2128 gmu: gmu@506a000 { 2129 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2130 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2131 <0 0x0b490000 0 0x10000>; 2132 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2133 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2135 interrupt-names = "hfi", "gmu"; 2136 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2137 <&gpucc GPU_CC_CXO_CLK>, 2138 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2139 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2140 clock-names = "gmu", "cxo", "axi", "memnoc"; 2141 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2142 power-domain-names = "cx", "gx"; 2143 iommus = <&adreno_smmu 5>; 2144 operating-points-v2 = <&gmu_opp_table>; 2145 2146 gmu_opp_table: opp-table { 2147 compatible = "operating-points-v2"; 2148 2149 opp-200000000 { 2150 opp-hz = /bits/ 64 <200000000>; 2151 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2152 }; 2153 }; 2154 }; 2155 2156 gpucc: clock-controller@5090000 { 2157 compatible = "qcom,sc7180-gpucc"; 2158 reg = <0 0x05090000 0 0x9000>; 2159 clocks = <&rpmhcc RPMH_CXO_CLK>, 2160 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2161 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2162 clock-names = "bi_tcxo", 2163 "gcc_gpu_gpll0_clk_src", 2164 "gcc_gpu_gpll0_div_clk_src"; 2165 #clock-cells = <1>; 2166 #reset-cells = <1>; 2167 #power-domain-cells = <1>; 2168 }; 2169 2170 stm@6002000 { 2171 compatible = "arm,coresight-stm", "arm,primecell"; 2172 reg = <0 0x06002000 0 0x1000>, 2173 <0 0x16280000 0 0x180000>; 2174 reg-names = "stm-base", "stm-stimulus-base"; 2175 2176 clocks = <&aoss_qmp>; 2177 clock-names = "apb_pclk"; 2178 2179 out-ports { 2180 port { 2181 stm_out: endpoint { 2182 remote-endpoint = <&funnel0_in7>; 2183 }; 2184 }; 2185 }; 2186 }; 2187 2188 funnel@6041000 { 2189 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2190 reg = <0 0x06041000 0 0x1000>; 2191 2192 clocks = <&aoss_qmp>; 2193 clock-names = "apb_pclk"; 2194 2195 out-ports { 2196 port { 2197 funnel0_out: endpoint { 2198 remote-endpoint = <&merge_funnel_in0>; 2199 }; 2200 }; 2201 }; 2202 2203 in-ports { 2204 #address-cells = <1>; 2205 #size-cells = <0>; 2206 2207 port@7 { 2208 reg = <7>; 2209 funnel0_in7: endpoint { 2210 remote-endpoint = <&stm_out>; 2211 }; 2212 }; 2213 }; 2214 }; 2215 2216 funnel@6042000 { 2217 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2218 reg = <0 0x06042000 0 0x1000>; 2219 2220 clocks = <&aoss_qmp>; 2221 clock-names = "apb_pclk"; 2222 2223 out-ports { 2224 port { 2225 funnel1_out: endpoint { 2226 remote-endpoint = <&merge_funnel_in1>; 2227 }; 2228 }; 2229 }; 2230 2231 in-ports { 2232 #address-cells = <1>; 2233 #size-cells = <0>; 2234 2235 port@4 { 2236 reg = <4>; 2237 funnel1_in4: endpoint { 2238 remote-endpoint = <&apss_merge_funnel_out>; 2239 }; 2240 }; 2241 }; 2242 }; 2243 2244 funnel@6045000 { 2245 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2246 reg = <0 0x06045000 0 0x1000>; 2247 2248 clocks = <&aoss_qmp>; 2249 clock-names = "apb_pclk"; 2250 2251 out-ports { 2252 port { 2253 merge_funnel_out: endpoint { 2254 remote-endpoint = <&swao_funnel_in>; 2255 }; 2256 }; 2257 }; 2258 2259 in-ports { 2260 #address-cells = <1>; 2261 #size-cells = <0>; 2262 2263 port@0 { 2264 reg = <0>; 2265 merge_funnel_in0: endpoint { 2266 remote-endpoint = <&funnel0_out>; 2267 }; 2268 }; 2269 2270 port@1 { 2271 reg = <1>; 2272 merge_funnel_in1: endpoint { 2273 remote-endpoint = <&funnel1_out>; 2274 }; 2275 }; 2276 }; 2277 }; 2278 2279 replicator@6046000 { 2280 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2281 reg = <0 0x06046000 0 0x1000>; 2282 2283 clocks = <&aoss_qmp>; 2284 clock-names = "apb_pclk"; 2285 2286 out-ports { 2287 port { 2288 replicator_out: endpoint { 2289 remote-endpoint = <&etr_in>; 2290 }; 2291 }; 2292 }; 2293 2294 in-ports { 2295 port { 2296 replicator_in: endpoint { 2297 remote-endpoint = <&swao_replicator_out>; 2298 }; 2299 }; 2300 }; 2301 }; 2302 2303 etr@6048000 { 2304 compatible = "arm,coresight-tmc", "arm,primecell"; 2305 reg = <0 0x06048000 0 0x1000>; 2306 iommus = <&apps_smmu 0x04a0 0x20>; 2307 2308 clocks = <&aoss_qmp>; 2309 clock-names = "apb_pclk"; 2310 arm,scatter-gather; 2311 2312 in-ports { 2313 port { 2314 etr_in: endpoint { 2315 remote-endpoint = <&replicator_out>; 2316 }; 2317 }; 2318 }; 2319 }; 2320 2321 funnel@6b04000 { 2322 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2323 reg = <0 0x06b04000 0 0x1000>; 2324 2325 clocks = <&aoss_qmp>; 2326 clock-names = "apb_pclk"; 2327 2328 out-ports { 2329 port { 2330 swao_funnel_out: endpoint { 2331 remote-endpoint = <&etf_in>; 2332 }; 2333 }; 2334 }; 2335 2336 in-ports { 2337 #address-cells = <1>; 2338 #size-cells = <0>; 2339 2340 port@7 { 2341 reg = <7>; 2342 swao_funnel_in: endpoint { 2343 remote-endpoint = <&merge_funnel_out>; 2344 }; 2345 }; 2346 }; 2347 }; 2348 2349 etf@6b05000 { 2350 compatible = "arm,coresight-tmc", "arm,primecell"; 2351 reg = <0 0x06b05000 0 0x1000>; 2352 2353 clocks = <&aoss_qmp>; 2354 clock-names = "apb_pclk"; 2355 2356 out-ports { 2357 port { 2358 etf_out: endpoint { 2359 remote-endpoint = <&swao_replicator_in>; 2360 }; 2361 }; 2362 }; 2363 2364 in-ports { 2365 port { 2366 etf_in: endpoint { 2367 remote-endpoint = <&swao_funnel_out>; 2368 }; 2369 }; 2370 }; 2371 }; 2372 2373 replicator@6b06000 { 2374 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2375 reg = <0 0x06b06000 0 0x1000>; 2376 2377 clocks = <&aoss_qmp>; 2378 clock-names = "apb_pclk"; 2379 qcom,replicator-loses-context; 2380 2381 out-ports { 2382 port { 2383 swao_replicator_out: endpoint { 2384 remote-endpoint = <&replicator_in>; 2385 }; 2386 }; 2387 }; 2388 2389 in-ports { 2390 port { 2391 swao_replicator_in: endpoint { 2392 remote-endpoint = <&etf_out>; 2393 }; 2394 }; 2395 }; 2396 }; 2397 2398 etm@7040000 { 2399 compatible = "arm,coresight-etm4x", "arm,primecell"; 2400 reg = <0 0x07040000 0 0x1000>; 2401 2402 cpu = <&CPU0>; 2403 2404 clocks = <&aoss_qmp>; 2405 clock-names = "apb_pclk"; 2406 arm,coresight-loses-context-with-cpu; 2407 qcom,skip-power-up; 2408 2409 out-ports { 2410 port { 2411 etm0_out: endpoint { 2412 remote-endpoint = <&apss_funnel_in0>; 2413 }; 2414 }; 2415 }; 2416 }; 2417 2418 etm@7140000 { 2419 compatible = "arm,coresight-etm4x", "arm,primecell"; 2420 reg = <0 0x07140000 0 0x1000>; 2421 2422 cpu = <&CPU1>; 2423 2424 clocks = <&aoss_qmp>; 2425 clock-names = "apb_pclk"; 2426 arm,coresight-loses-context-with-cpu; 2427 qcom,skip-power-up; 2428 2429 out-ports { 2430 port { 2431 etm1_out: endpoint { 2432 remote-endpoint = <&apss_funnel_in1>; 2433 }; 2434 }; 2435 }; 2436 }; 2437 2438 etm@7240000 { 2439 compatible = "arm,coresight-etm4x", "arm,primecell"; 2440 reg = <0 0x07240000 0 0x1000>; 2441 2442 cpu = <&CPU2>; 2443 2444 clocks = <&aoss_qmp>; 2445 clock-names = "apb_pclk"; 2446 arm,coresight-loses-context-with-cpu; 2447 qcom,skip-power-up; 2448 2449 out-ports { 2450 port { 2451 etm2_out: endpoint { 2452 remote-endpoint = <&apss_funnel_in2>; 2453 }; 2454 }; 2455 }; 2456 }; 2457 2458 etm@7340000 { 2459 compatible = "arm,coresight-etm4x", "arm,primecell"; 2460 reg = <0 0x07340000 0 0x1000>; 2461 2462 cpu = <&CPU3>; 2463 2464 clocks = <&aoss_qmp>; 2465 clock-names = "apb_pclk"; 2466 arm,coresight-loses-context-with-cpu; 2467 qcom,skip-power-up; 2468 2469 out-ports { 2470 port { 2471 etm3_out: endpoint { 2472 remote-endpoint = <&apss_funnel_in3>; 2473 }; 2474 }; 2475 }; 2476 }; 2477 2478 etm@7440000 { 2479 compatible = "arm,coresight-etm4x", "arm,primecell"; 2480 reg = <0 0x07440000 0 0x1000>; 2481 2482 cpu = <&CPU4>; 2483 2484 clocks = <&aoss_qmp>; 2485 clock-names = "apb_pclk"; 2486 arm,coresight-loses-context-with-cpu; 2487 qcom,skip-power-up; 2488 2489 out-ports { 2490 port { 2491 etm4_out: endpoint { 2492 remote-endpoint = <&apss_funnel_in4>; 2493 }; 2494 }; 2495 }; 2496 }; 2497 2498 etm@7540000 { 2499 compatible = "arm,coresight-etm4x", "arm,primecell"; 2500 reg = <0 0x07540000 0 0x1000>; 2501 2502 cpu = <&CPU5>; 2503 2504 clocks = <&aoss_qmp>; 2505 clock-names = "apb_pclk"; 2506 arm,coresight-loses-context-with-cpu; 2507 qcom,skip-power-up; 2508 2509 out-ports { 2510 port { 2511 etm5_out: endpoint { 2512 remote-endpoint = <&apss_funnel_in5>; 2513 }; 2514 }; 2515 }; 2516 }; 2517 2518 etm@7640000 { 2519 compatible = "arm,coresight-etm4x", "arm,primecell"; 2520 reg = <0 0x07640000 0 0x1000>; 2521 2522 cpu = <&CPU6>; 2523 2524 clocks = <&aoss_qmp>; 2525 clock-names = "apb_pclk"; 2526 arm,coresight-loses-context-with-cpu; 2527 qcom,skip-power-up; 2528 2529 out-ports { 2530 port { 2531 etm6_out: endpoint { 2532 remote-endpoint = <&apss_funnel_in6>; 2533 }; 2534 }; 2535 }; 2536 }; 2537 2538 etm@7740000 { 2539 compatible = "arm,coresight-etm4x", "arm,primecell"; 2540 reg = <0 0x07740000 0 0x1000>; 2541 2542 cpu = <&CPU7>; 2543 2544 clocks = <&aoss_qmp>; 2545 clock-names = "apb_pclk"; 2546 arm,coresight-loses-context-with-cpu; 2547 qcom,skip-power-up; 2548 2549 out-ports { 2550 port { 2551 etm7_out: endpoint { 2552 remote-endpoint = <&apss_funnel_in7>; 2553 }; 2554 }; 2555 }; 2556 }; 2557 2558 funnel@7800000 { /* APSS Funnel */ 2559 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2560 reg = <0 0x07800000 0 0x1000>; 2561 2562 clocks = <&aoss_qmp>; 2563 clock-names = "apb_pclk"; 2564 2565 out-ports { 2566 port { 2567 apss_funnel_out: endpoint { 2568 remote-endpoint = <&apss_merge_funnel_in>; 2569 }; 2570 }; 2571 }; 2572 2573 in-ports { 2574 #address-cells = <1>; 2575 #size-cells = <0>; 2576 2577 port@0 { 2578 reg = <0>; 2579 apss_funnel_in0: endpoint { 2580 remote-endpoint = <&etm0_out>; 2581 }; 2582 }; 2583 2584 port@1 { 2585 reg = <1>; 2586 apss_funnel_in1: endpoint { 2587 remote-endpoint = <&etm1_out>; 2588 }; 2589 }; 2590 2591 port@2 { 2592 reg = <2>; 2593 apss_funnel_in2: endpoint { 2594 remote-endpoint = <&etm2_out>; 2595 }; 2596 }; 2597 2598 port@3 { 2599 reg = <3>; 2600 apss_funnel_in3: endpoint { 2601 remote-endpoint = <&etm3_out>; 2602 }; 2603 }; 2604 2605 port@4 { 2606 reg = <4>; 2607 apss_funnel_in4: endpoint { 2608 remote-endpoint = <&etm4_out>; 2609 }; 2610 }; 2611 2612 port@5 { 2613 reg = <5>; 2614 apss_funnel_in5: endpoint { 2615 remote-endpoint = <&etm5_out>; 2616 }; 2617 }; 2618 2619 port@6 { 2620 reg = <6>; 2621 apss_funnel_in6: endpoint { 2622 remote-endpoint = <&etm6_out>; 2623 }; 2624 }; 2625 2626 port@7 { 2627 reg = <7>; 2628 apss_funnel_in7: endpoint { 2629 remote-endpoint = <&etm7_out>; 2630 }; 2631 }; 2632 }; 2633 }; 2634 2635 funnel@7810000 { 2636 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2637 reg = <0 0x07810000 0 0x1000>; 2638 2639 clocks = <&aoss_qmp>; 2640 clock-names = "apb_pclk"; 2641 2642 out-ports { 2643 port { 2644 apss_merge_funnel_out: endpoint { 2645 remote-endpoint = <&funnel1_in4>; 2646 }; 2647 }; 2648 }; 2649 2650 in-ports { 2651 port { 2652 apss_merge_funnel_in: endpoint { 2653 remote-endpoint = <&apss_funnel_out>; 2654 }; 2655 }; 2656 }; 2657 }; 2658 2659 sdhc_2: sdhci@8804000 { 2660 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2661 reg = <0 0x08804000 0 0x1000>; 2662 2663 iommus = <&apps_smmu 0x80 0>; 2664 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2665 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2666 interrupt-names = "hc_irq", "pwr_irq"; 2667 2668 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2669 <&gcc GCC_SDCC2_AHB_CLK>; 2670 clock-names = "core", "iface"; 2671 2672 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2673 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2674 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2675 power-domains = <&rpmhpd SC7180_CX>; 2676 operating-points-v2 = <&sdhc2_opp_table>; 2677 2678 bus-width = <4>; 2679 2680 status = "disabled"; 2681 2682 sdhc2_opp_table: sdhc2-opp-table { 2683 compatible = "operating-points-v2"; 2684 2685 opp-100000000 { 2686 opp-hz = /bits/ 64 <100000000>; 2687 required-opps = <&rpmhpd_opp_low_svs>; 2688 opp-peak-kBps = <160000 100000>; 2689 opp-avg-kBps = <80000 50000>; 2690 }; 2691 2692 opp-202000000 { 2693 opp-hz = /bits/ 64 <202000000>; 2694 required-opps = <&rpmhpd_opp_svs_l1>; 2695 opp-peak-kBps = <200000 120000>; 2696 opp-avg-kBps = <100000 60000>; 2697 }; 2698 }; 2699 }; 2700 2701 qspi_opp_table: qspi-opp-table { 2702 compatible = "operating-points-v2"; 2703 2704 opp-75000000 { 2705 opp-hz = /bits/ 64 <75000000>; 2706 required-opps = <&rpmhpd_opp_low_svs>; 2707 }; 2708 2709 opp-150000000 { 2710 opp-hz = /bits/ 64 <150000000>; 2711 required-opps = <&rpmhpd_opp_svs>; 2712 }; 2713 2714 opp-300000000 { 2715 opp-hz = /bits/ 64 <300000000>; 2716 required-opps = <&rpmhpd_opp_nom>; 2717 }; 2718 }; 2719 2720 qspi: spi@88dc000 { 2721 compatible = "qcom,qspi-v1"; 2722 reg = <0 0x088dc000 0 0x600>; 2723 #address-cells = <1>; 2724 #size-cells = <0>; 2725 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2726 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2727 <&gcc GCC_QSPI_CORE_CLK>; 2728 clock-names = "iface", "core"; 2729 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2730 &config_noc SLAVE_QSPI_0 0>; 2731 interconnect-names = "qspi-config"; 2732 power-domains = <&rpmhpd SC7180_CX>; 2733 operating-points-v2 = <&qspi_opp_table>; 2734 status = "disabled"; 2735 }; 2736 2737 usb_1_hsphy: phy@88e3000 { 2738 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2739 reg = <0 0x088e3000 0 0x400>; 2740 status = "disabled"; 2741 #phy-cells = <0>; 2742 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2743 <&rpmhcc RPMH_CXO_CLK>; 2744 clock-names = "cfg_ahb", "ref"; 2745 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2746 2747 nvmem-cells = <&qusb2p_hstx_trim>; 2748 }; 2749 2750 usb_1_qmpphy: phy-wrapper@88e9000 { 2751 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2752 reg = <0 0x088e9000 0 0x18c>, 2753 <0 0x088e8000 0 0x3c>, 2754 <0 0x088ea000 0 0x18c>; 2755 status = "disabled"; 2756 #address-cells = <2>; 2757 #size-cells = <2>; 2758 ranges; 2759 2760 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2761 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2762 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2763 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2764 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2765 2766 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2767 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2768 reset-names = "phy", "common"; 2769 2770 usb_1_ssphy: usb3-phy@88e9200 { 2771 reg = <0 0x088e9200 0 0x128>, 2772 <0 0x088e9400 0 0x200>, 2773 <0 0x088e9c00 0 0x218>, 2774 <0 0x088e9600 0 0x128>, 2775 <0 0x088e9800 0 0x200>, 2776 <0 0x088e9a00 0 0x18>; 2777 #clock-cells = <0>; 2778 #phy-cells = <0>; 2779 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2780 clock-names = "pipe0"; 2781 clock-output-names = "usb3_phy_pipe_clk_src"; 2782 }; 2783 2784 dp_phy: dp-phy@88ea200 { 2785 reg = <0 0x088ea200 0 0x200>, 2786 <0 0x088ea400 0 0x200>, 2787 <0 0x088eaa00 0 0x200>, 2788 <0 0x088ea600 0 0x200>, 2789 <0 0x088ea800 0 0x200>; 2790 #clock-cells = <1>; 2791 #phy-cells = <0>; 2792 }; 2793 }; 2794 2795 dc_noc: interconnect@9160000 { 2796 compatible = "qcom,sc7180-dc-noc"; 2797 reg = <0 0x09160000 0 0x03200>; 2798 #interconnect-cells = <2>; 2799 qcom,bcm-voters = <&apps_bcm_voter>; 2800 }; 2801 2802 system-cache-controller@9200000 { 2803 compatible = "qcom,sc7180-llcc"; 2804 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2805 reg-names = "llcc_base", "llcc_broadcast_base"; 2806 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2807 }; 2808 2809 gem_noc: interconnect@9680000 { 2810 compatible = "qcom,sc7180-gem-noc"; 2811 reg = <0 0x09680000 0 0x3e200>; 2812 #interconnect-cells = <2>; 2813 qcom,bcm-voters = <&apps_bcm_voter>; 2814 }; 2815 2816 npu_noc: interconnect@9990000 { 2817 compatible = "qcom,sc7180-npu-noc"; 2818 reg = <0 0x09990000 0 0x1600>; 2819 #interconnect-cells = <2>; 2820 qcom,bcm-voters = <&apps_bcm_voter>; 2821 }; 2822 2823 usb_1: usb@a6f8800 { 2824 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2825 reg = <0 0x0a6f8800 0 0x400>; 2826 status = "disabled"; 2827 #address-cells = <2>; 2828 #size-cells = <2>; 2829 ranges; 2830 dma-ranges; 2831 2832 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2833 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2834 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2835 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2836 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2837 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2838 "sleep"; 2839 2840 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2841 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2842 assigned-clock-rates = <19200000>, <150000000>; 2843 2844 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2845 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2846 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2847 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2848 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2849 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2850 2851 power-domains = <&gcc USB30_PRIM_GDSC>; 2852 2853 resets = <&gcc GCC_USB30_PRIM_BCR>; 2854 2855 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2856 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2857 interconnect-names = "usb-ddr", "apps-usb"; 2858 2859 usb_1_dwc3: usb@a600000 { 2860 compatible = "snps,dwc3"; 2861 reg = <0 0x0a600000 0 0xe000>; 2862 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2863 iommus = <&apps_smmu 0x540 0>; 2864 snps,dis_u2_susphy_quirk; 2865 snps,dis_enblslpm_quirk; 2866 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2867 phy-names = "usb2-phy", "usb3-phy"; 2868 maximum-speed = "super-speed"; 2869 }; 2870 }; 2871 2872 venus: video-codec@aa00000 { 2873 compatible = "qcom,sc7180-venus"; 2874 reg = <0 0x0aa00000 0 0xff000>; 2875 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2876 power-domains = <&videocc VENUS_GDSC>, 2877 <&videocc VCODEC0_GDSC>, 2878 <&rpmhpd SC7180_CX>; 2879 power-domain-names = "venus", "vcodec0", "cx"; 2880 operating-points-v2 = <&venus_opp_table>; 2881 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2882 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2883 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2884 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2885 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2886 clock-names = "core", "iface", "bus", 2887 "vcodec0_core", "vcodec0_bus"; 2888 iommus = <&apps_smmu 0x0c00 0x60>; 2889 memory-region = <&venus_mem>; 2890 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2891 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2892 interconnect-names = "video-mem", "cpu-cfg"; 2893 2894 video-decoder { 2895 compatible = "venus-decoder"; 2896 }; 2897 2898 video-encoder { 2899 compatible = "venus-encoder"; 2900 }; 2901 2902 venus_opp_table: venus-opp-table { 2903 compatible = "operating-points-v2"; 2904 2905 opp-150000000 { 2906 opp-hz = /bits/ 64 <150000000>; 2907 required-opps = <&rpmhpd_opp_low_svs>; 2908 }; 2909 2910 opp-270000000 { 2911 opp-hz = /bits/ 64 <270000000>; 2912 required-opps = <&rpmhpd_opp_svs>; 2913 }; 2914 2915 opp-340000000 { 2916 opp-hz = /bits/ 64 <340000000>; 2917 required-opps = <&rpmhpd_opp_svs_l1>; 2918 }; 2919 2920 opp-434000000 { 2921 opp-hz = /bits/ 64 <434000000>; 2922 required-opps = <&rpmhpd_opp_nom>; 2923 }; 2924 2925 opp-500000097 { 2926 opp-hz = /bits/ 64 <500000097>; 2927 required-opps = <&rpmhpd_opp_turbo>; 2928 }; 2929 }; 2930 }; 2931 2932 videocc: clock-controller@ab00000 { 2933 compatible = "qcom,sc7180-videocc"; 2934 reg = <0 0x0ab00000 0 0x10000>; 2935 clocks = <&rpmhcc RPMH_CXO_CLK>; 2936 clock-names = "bi_tcxo"; 2937 #clock-cells = <1>; 2938 #reset-cells = <1>; 2939 #power-domain-cells = <1>; 2940 }; 2941 2942 camnoc_virt: interconnect@ac00000 { 2943 compatible = "qcom,sc7180-camnoc-virt"; 2944 reg = <0 0x0ac00000 0 0x1000>; 2945 #interconnect-cells = <2>; 2946 qcom,bcm-voters = <&apps_bcm_voter>; 2947 }; 2948 2949 camcc: clock-controller@ad00000 { 2950 compatible = "qcom,sc7180-camcc"; 2951 reg = <0 0x0ad00000 0 0x10000>; 2952 clocks = <&rpmhcc RPMH_CXO_CLK>, 2953 <&gcc GCC_CAMERA_AHB_CLK>, 2954 <&gcc GCC_CAMERA_XO_CLK>; 2955 clock-names = "bi_tcxo", "iface", "xo"; 2956 #clock-cells = <1>; 2957 #reset-cells = <1>; 2958 #power-domain-cells = <1>; 2959 }; 2960 2961 mdss: mdss@ae00000 { 2962 compatible = "qcom,sc7180-mdss"; 2963 reg = <0 0x0ae00000 0 0x1000>; 2964 reg-names = "mdss"; 2965 2966 power-domains = <&dispcc MDSS_GDSC>; 2967 2968 clocks = <&gcc GCC_DISP_AHB_CLK>, 2969 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2970 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2971 clock-names = "iface", "ahb", "core"; 2972 2973 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2974 assigned-clock-rates = <300000000>; 2975 2976 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2977 interrupt-controller; 2978 #interrupt-cells = <1>; 2979 2980 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2981 interconnect-names = "mdp0-mem"; 2982 2983 iommus = <&apps_smmu 0x800 0x2>; 2984 2985 #address-cells = <2>; 2986 #size-cells = <2>; 2987 ranges; 2988 2989 status = "disabled"; 2990 2991 mdp: mdp@ae01000 { 2992 compatible = "qcom,sc7180-dpu"; 2993 reg = <0 0x0ae01000 0 0x8f000>, 2994 <0 0x0aeb0000 0 0x2008>; 2995 reg-names = "mdp", "vbif"; 2996 2997 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2998 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2999 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3000 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3001 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3002 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3003 clock-names = "bus", "iface", "rot", "lut", "core", 3004 "vsync"; 3005 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3006 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3007 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3008 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3009 assigned-clock-rates = <300000000>, 3010 <19200000>, 3011 <19200000>, 3012 <19200000>; 3013 operating-points-v2 = <&mdp_opp_table>; 3014 power-domains = <&rpmhpd SC7180_CX>; 3015 3016 interrupt-parent = <&mdss>; 3017 interrupts = <0>; 3018 3019 status = "disabled"; 3020 3021 ports { 3022 #address-cells = <1>; 3023 #size-cells = <0>; 3024 3025 port@0 { 3026 reg = <0>; 3027 dpu_intf1_out: endpoint { 3028 remote-endpoint = <&dsi0_in>; 3029 }; 3030 }; 3031 }; 3032 3033 mdp_opp_table: mdp-opp-table { 3034 compatible = "operating-points-v2"; 3035 3036 opp-200000000 { 3037 opp-hz = /bits/ 64 <200000000>; 3038 required-opps = <&rpmhpd_opp_low_svs>; 3039 }; 3040 3041 opp-300000000 { 3042 opp-hz = /bits/ 64 <300000000>; 3043 required-opps = <&rpmhpd_opp_svs>; 3044 }; 3045 3046 opp-345000000 { 3047 opp-hz = /bits/ 64 <345000000>; 3048 required-opps = <&rpmhpd_opp_svs_l1>; 3049 }; 3050 3051 opp-460000000 { 3052 opp-hz = /bits/ 64 <460000000>; 3053 required-opps = <&rpmhpd_opp_nom>; 3054 }; 3055 }; 3056 3057 }; 3058 3059 dsi0: dsi@ae94000 { 3060 compatible = "qcom,mdss-dsi-ctrl"; 3061 reg = <0 0x0ae94000 0 0x400>; 3062 reg-names = "dsi_ctrl"; 3063 3064 interrupt-parent = <&mdss>; 3065 interrupts = <4>; 3066 3067 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3068 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3069 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3070 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3071 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3072 <&gcc GCC_DISP_HF_AXI_CLK>; 3073 clock-names = "byte", 3074 "byte_intf", 3075 "pixel", 3076 "core", 3077 "iface", 3078 "bus"; 3079 3080 operating-points-v2 = <&dsi_opp_table>; 3081 power-domains = <&rpmhpd SC7180_CX>; 3082 3083 phys = <&dsi_phy>; 3084 phy-names = "dsi"; 3085 3086 #address-cells = <1>; 3087 #size-cells = <0>; 3088 3089 status = "disabled"; 3090 3091 ports { 3092 #address-cells = <1>; 3093 #size-cells = <0>; 3094 3095 port@0 { 3096 reg = <0>; 3097 dsi0_in: endpoint { 3098 remote-endpoint = <&dpu_intf1_out>; 3099 }; 3100 }; 3101 3102 port@1 { 3103 reg = <1>; 3104 dsi0_out: endpoint { 3105 }; 3106 }; 3107 }; 3108 3109 dsi_opp_table: dsi-opp-table { 3110 compatible = "operating-points-v2"; 3111 3112 opp-187500000 { 3113 opp-hz = /bits/ 64 <187500000>; 3114 required-opps = <&rpmhpd_opp_low_svs>; 3115 }; 3116 3117 opp-300000000 { 3118 opp-hz = /bits/ 64 <300000000>; 3119 required-opps = <&rpmhpd_opp_svs>; 3120 }; 3121 3122 opp-358000000 { 3123 opp-hz = /bits/ 64 <358000000>; 3124 required-opps = <&rpmhpd_opp_svs_l1>; 3125 }; 3126 }; 3127 }; 3128 3129 dsi_phy: dsi-phy@ae94400 { 3130 compatible = "qcom,dsi-phy-10nm"; 3131 reg = <0 0x0ae94400 0 0x200>, 3132 <0 0x0ae94600 0 0x280>, 3133 <0 0x0ae94a00 0 0x1e0>; 3134 reg-names = "dsi_phy", 3135 "dsi_phy_lane", 3136 "dsi_pll"; 3137 3138 #clock-cells = <1>; 3139 #phy-cells = <0>; 3140 3141 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3142 <&rpmhcc RPMH_CXO_CLK>; 3143 clock-names = "iface", "ref"; 3144 3145 status = "disabled"; 3146 }; 3147 }; 3148 3149 dispcc: clock-controller@af00000 { 3150 compatible = "qcom,sc7180-dispcc"; 3151 reg = <0 0x0af00000 0 0x200000>; 3152 clocks = <&rpmhcc RPMH_CXO_CLK>, 3153 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3154 <&dsi_phy 0>, 3155 <&dsi_phy 1>, 3156 <&dp_phy 0>, 3157 <&dp_phy 1>; 3158 clock-names = "bi_tcxo", 3159 "gcc_disp_gpll0_clk_src", 3160 "dsi0_phy_pll_out_byteclk", 3161 "dsi0_phy_pll_out_dsiclk", 3162 "dp_phy_pll_link_clk", 3163 "dp_phy_pll_vco_div_clk"; 3164 #clock-cells = <1>; 3165 #reset-cells = <1>; 3166 #power-domain-cells = <1>; 3167 }; 3168 3169 pdc: interrupt-controller@b220000 { 3170 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3171 reg = <0 0x0b220000 0 0x30000>; 3172 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3173 #interrupt-cells = <2>; 3174 interrupt-parent = <&intc>; 3175 interrupt-controller; 3176 }; 3177 3178 pdc_reset: reset-controller@b2e0000 { 3179 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3180 reg = <0 0x0b2e0000 0 0x20000>; 3181 #reset-cells = <1>; 3182 }; 3183 3184 tsens0: thermal-sensor@c263000 { 3185 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3186 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3187 <0 0x0c222000 0 0x1ff>; /* SROT */ 3188 #qcom,sensors = <15>; 3189 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3191 interrupt-names = "uplow","critical"; 3192 #thermal-sensor-cells = <1>; 3193 }; 3194 3195 tsens1: thermal-sensor@c265000 { 3196 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3197 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3198 <0 0x0c223000 0 0x1ff>; /* SROT */ 3199 #qcom,sensors = <10>; 3200 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3202 interrupt-names = "uplow","critical"; 3203 #thermal-sensor-cells = <1>; 3204 }; 3205 3206 aoss_reset: reset-controller@c2a0000 { 3207 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3208 reg = <0 0x0c2a0000 0 0x31000>; 3209 #reset-cells = <1>; 3210 }; 3211 3212 aoss_qmp: power-controller@c300000 { 3213 compatible = "qcom,sc7180-aoss-qmp"; 3214 reg = <0 0x0c300000 0 0x100000>; 3215 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3216 mboxes = <&apss_shared 0>; 3217 3218 #clock-cells = <0>; 3219 #power-domain-cells = <1>; 3220 }; 3221 3222 spmi_bus: spmi@c440000 { 3223 compatible = "qcom,spmi-pmic-arb"; 3224 reg = <0 0x0c440000 0 0x1100>, 3225 <0 0x0c600000 0 0x2000000>, 3226 <0 0x0e600000 0 0x100000>, 3227 <0 0x0e700000 0 0xa0000>, 3228 <0 0x0c40a000 0 0x26000>; 3229 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3230 interrupt-names = "periph_irq"; 3231 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3232 qcom,ee = <0>; 3233 qcom,channel = <0>; 3234 #address-cells = <1>; 3235 #size-cells = <1>; 3236 interrupt-controller; 3237 #interrupt-cells = <4>; 3238 cell-index = <0>; 3239 }; 3240 3241 apps_smmu: iommu@15000000 { 3242 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3243 reg = <0 0x15000000 0 0x100000>; 3244 #iommu-cells = <2>; 3245 #global-interrupts = <1>; 3246 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3327 }; 3328 3329 intc: interrupt-controller@17a00000 { 3330 compatible = "arm,gic-v3"; 3331 #address-cells = <2>; 3332 #size-cells = <2>; 3333 ranges; 3334 #interrupt-cells = <3>; 3335 interrupt-controller; 3336 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3337 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3338 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3339 3340 msi-controller@17a40000 { 3341 compatible = "arm,gic-v3-its"; 3342 msi-controller; 3343 #msi-cells = <1>; 3344 reg = <0 0x17a40000 0 0x20000>; 3345 status = "disabled"; 3346 }; 3347 }; 3348 3349 apss_shared: mailbox@17c00000 { 3350 compatible = "qcom,sc7180-apss-shared"; 3351 reg = <0 0x17c00000 0 0x10000>; 3352 #mbox-cells = <1>; 3353 }; 3354 3355 watchdog@17c10000 { 3356 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3357 reg = <0 0x17c10000 0 0x1000>; 3358 clocks = <&sleep_clk>; 3359 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3360 }; 3361 3362 timer@17c20000{ 3363 #address-cells = <2>; 3364 #size-cells = <2>; 3365 ranges; 3366 compatible = "arm,armv7-timer-mem"; 3367 reg = <0 0x17c20000 0 0x1000>; 3368 3369 frame@17c21000 { 3370 frame-number = <0>; 3371 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3373 reg = <0 0x17c21000 0 0x1000>, 3374 <0 0x17c22000 0 0x1000>; 3375 }; 3376 3377 frame@17c23000 { 3378 frame-number = <1>; 3379 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3380 reg = <0 0x17c23000 0 0x1000>; 3381 status = "disabled"; 3382 }; 3383 3384 frame@17c25000 { 3385 frame-number = <2>; 3386 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3387 reg = <0 0x17c25000 0 0x1000>; 3388 status = "disabled"; 3389 }; 3390 3391 frame@17c27000 { 3392 frame-number = <3>; 3393 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3394 reg = <0 0x17c27000 0 0x1000>; 3395 status = "disabled"; 3396 }; 3397 3398 frame@17c29000 { 3399 frame-number = <4>; 3400 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3401 reg = <0 0x17c29000 0 0x1000>; 3402 status = "disabled"; 3403 }; 3404 3405 frame@17c2b000 { 3406 frame-number = <5>; 3407 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3408 reg = <0 0x17c2b000 0 0x1000>; 3409 status = "disabled"; 3410 }; 3411 3412 frame@17c2d000 { 3413 frame-number = <6>; 3414 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3415 reg = <0 0x17c2d000 0 0x1000>; 3416 status = "disabled"; 3417 }; 3418 }; 3419 3420 apps_rsc: rsc@18200000 { 3421 compatible = "qcom,rpmh-rsc"; 3422 reg = <0 0x18200000 0 0x10000>, 3423 <0 0x18210000 0 0x10000>, 3424 <0 0x18220000 0 0x10000>; 3425 reg-names = "drv-0", "drv-1", "drv-2"; 3426 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3429 qcom,tcs-offset = <0xd00>; 3430 qcom,drv-id = <2>; 3431 qcom,tcs-config = <ACTIVE_TCS 2>, 3432 <SLEEP_TCS 3>, 3433 <WAKE_TCS 3>, 3434 <CONTROL_TCS 1>; 3435 3436 rpmhcc: clock-controller { 3437 compatible = "qcom,sc7180-rpmh-clk"; 3438 clocks = <&xo_board>; 3439 clock-names = "xo"; 3440 #clock-cells = <1>; 3441 }; 3442 3443 rpmhpd: power-controller { 3444 compatible = "qcom,sc7180-rpmhpd"; 3445 #power-domain-cells = <1>; 3446 operating-points-v2 = <&rpmhpd_opp_table>; 3447 3448 rpmhpd_opp_table: opp-table { 3449 compatible = "operating-points-v2"; 3450 3451 rpmhpd_opp_ret: opp1 { 3452 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3453 }; 3454 3455 rpmhpd_opp_min_svs: opp2 { 3456 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3457 }; 3458 3459 rpmhpd_opp_low_svs: opp3 { 3460 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3461 }; 3462 3463 rpmhpd_opp_svs: opp4 { 3464 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3465 }; 3466 3467 rpmhpd_opp_svs_l1: opp5 { 3468 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3469 }; 3470 3471 rpmhpd_opp_svs_l2: opp6 { 3472 opp-level = <224>; 3473 }; 3474 3475 rpmhpd_opp_nom: opp7 { 3476 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3477 }; 3478 3479 rpmhpd_opp_nom_l1: opp8 { 3480 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3481 }; 3482 3483 rpmhpd_opp_nom_l2: opp9 { 3484 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3485 }; 3486 3487 rpmhpd_opp_turbo: opp10 { 3488 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3489 }; 3490 3491 rpmhpd_opp_turbo_l1: opp11 { 3492 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3493 }; 3494 }; 3495 }; 3496 3497 apps_bcm_voter: bcm_voter { 3498 compatible = "qcom,bcm-voter"; 3499 }; 3500 }; 3501 3502 osm_l3: interconnect@18321000 { 3503 compatible = "qcom,sc7180-osm-l3"; 3504 reg = <0 0x18321000 0 0x1400>; 3505 3506 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3507 clock-names = "xo", "alternate"; 3508 3509 #interconnect-cells = <1>; 3510 }; 3511 3512 cpufreq_hw: cpufreq@18323000 { 3513 compatible = "qcom,cpufreq-hw"; 3514 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3515 reg-names = "freq-domain0", "freq-domain1"; 3516 3517 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3518 clock-names = "xo", "alternate"; 3519 3520 #freq-domain-cells = <1>; 3521 }; 3522 3523 wifi: wifi@18800000 { 3524 compatible = "qcom,wcn3990-wifi"; 3525 reg = <0 0x18800000 0 0x800000>; 3526 reg-names = "membase"; 3527 iommus = <&apps_smmu 0xc0 0x1>; 3528 interrupts = 3529 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3530 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3531 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3532 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3533 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3534 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3535 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3536 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3537 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3538 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3539 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3540 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3541 memory-region = <&wlan_mem>; 3542 qcom,msa-fixed-perm; 3543 status = "disabled"; 3544 }; 3545 3546 lpasscc: clock-controller@62d00000 { 3547 compatible = "qcom,sc7180-lpasscorecc"; 3548 reg = <0 0x62d00000 0 0x50000>, 3549 <0 0x62780000 0 0x30000>; 3550 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3551 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3552 <&rpmhcc RPMH_CXO_CLK>; 3553 clock-names = "iface", "bi_tcxo"; 3554 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3555 #clock-cells = <1>; 3556 #power-domain-cells = <1>; 3557 }; 3558 3559 lpass_cpu: lpass@62f00000 { 3560 compatible = "qcom,sc7180-lpass-cpu"; 3561 3562 reg = <0 0x62f00000 0 0x29000>; 3563 reg-names = "lpass-lpaif"; 3564 3565 iommus = <&apps_smmu 0x1020 0>, 3566 <&apps_smmu 0x1021 0>; 3567 3568 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3569 3570 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3571 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3572 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3573 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3574 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3575 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3576 3577 clock-names = "pcnoc-sway-clk", "audio-core", 3578 "mclk0", "pcnoc-mport-clk", 3579 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3580 3581 3582 #sound-dai-cells = <1>; 3583 #address-cells = <1>; 3584 #size-cells = <0>; 3585 3586 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 3587 interrupt-names = "lpass-irq-lpaif"; 3588 }; 3589 3590 lpass_hm: clock-controller@63000000 { 3591 compatible = "qcom,sc7180-lpasshm"; 3592 reg = <0 0x63000000 0 0x28>; 3593 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3594 <&rpmhcc RPMH_CXO_CLK>; 3595 clock-names = "iface", "bi_tcxo"; 3596 #clock-cells = <1>; 3597 #power-domain-cells = <1>; 3598 }; 3599 }; 3600 3601 thermal-zones { 3602 cpu0_thermal: cpu0-thermal { 3603 polling-delay-passive = <250>; 3604 polling-delay = <0>; 3605 3606 thermal-sensors = <&tsens0 1>; 3607 sustainable-power = <768>; 3608 3609 trips { 3610 cpu0_alert0: trip-point0 { 3611 temperature = <90000>; 3612 hysteresis = <2000>; 3613 type = "passive"; 3614 }; 3615 3616 cpu0_alert1: trip-point1 { 3617 temperature = <95000>; 3618 hysteresis = <2000>; 3619 type = "passive"; 3620 }; 3621 3622 cpu0_crit: cpu_crit { 3623 temperature = <110000>; 3624 hysteresis = <1000>; 3625 type = "critical"; 3626 }; 3627 }; 3628 3629 cooling-maps { 3630 map0 { 3631 trip = <&cpu0_alert0>; 3632 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3633 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3634 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3635 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3636 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3637 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3638 }; 3639 map1 { 3640 trip = <&cpu0_alert1>; 3641 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3642 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3643 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3644 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3645 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3646 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3647 }; 3648 }; 3649 }; 3650 3651 cpu1_thermal: cpu1-thermal { 3652 polling-delay-passive = <250>; 3653 polling-delay = <0>; 3654 3655 thermal-sensors = <&tsens0 2>; 3656 sustainable-power = <768>; 3657 3658 trips { 3659 cpu1_alert0: trip-point0 { 3660 temperature = <90000>; 3661 hysteresis = <2000>; 3662 type = "passive"; 3663 }; 3664 3665 cpu1_alert1: trip-point1 { 3666 temperature = <95000>; 3667 hysteresis = <2000>; 3668 type = "passive"; 3669 }; 3670 3671 cpu1_crit: cpu_crit { 3672 temperature = <110000>; 3673 hysteresis = <1000>; 3674 type = "critical"; 3675 }; 3676 }; 3677 3678 cooling-maps { 3679 map0 { 3680 trip = <&cpu1_alert0>; 3681 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3682 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3683 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3684 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3685 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3686 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3687 }; 3688 map1 { 3689 trip = <&cpu1_alert1>; 3690 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3691 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3692 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3693 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3694 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3695 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3696 }; 3697 }; 3698 }; 3699 3700 cpu2_thermal: cpu2-thermal { 3701 polling-delay-passive = <250>; 3702 polling-delay = <0>; 3703 3704 thermal-sensors = <&tsens0 3>; 3705 sustainable-power = <768>; 3706 3707 trips { 3708 cpu2_alert0: trip-point0 { 3709 temperature = <90000>; 3710 hysteresis = <2000>; 3711 type = "passive"; 3712 }; 3713 3714 cpu2_alert1: trip-point1 { 3715 temperature = <95000>; 3716 hysteresis = <2000>; 3717 type = "passive"; 3718 }; 3719 3720 cpu2_crit: cpu_crit { 3721 temperature = <110000>; 3722 hysteresis = <1000>; 3723 type = "critical"; 3724 }; 3725 }; 3726 3727 cooling-maps { 3728 map0 { 3729 trip = <&cpu2_alert0>; 3730 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3731 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3732 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3733 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3734 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3735 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3736 }; 3737 map1 { 3738 trip = <&cpu2_alert1>; 3739 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3740 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3741 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3742 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3743 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3744 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3745 }; 3746 }; 3747 }; 3748 3749 cpu3_thermal: cpu3-thermal { 3750 polling-delay-passive = <250>; 3751 polling-delay = <0>; 3752 3753 thermal-sensors = <&tsens0 4>; 3754 sustainable-power = <768>; 3755 3756 trips { 3757 cpu3_alert0: trip-point0 { 3758 temperature = <90000>; 3759 hysteresis = <2000>; 3760 type = "passive"; 3761 }; 3762 3763 cpu3_alert1: trip-point1 { 3764 temperature = <95000>; 3765 hysteresis = <2000>; 3766 type = "passive"; 3767 }; 3768 3769 cpu3_crit: cpu_crit { 3770 temperature = <110000>; 3771 hysteresis = <1000>; 3772 type = "critical"; 3773 }; 3774 }; 3775 3776 cooling-maps { 3777 map0 { 3778 trip = <&cpu3_alert0>; 3779 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3783 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3785 }; 3786 map1 { 3787 trip = <&cpu3_alert1>; 3788 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3789 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3790 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3791 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3794 }; 3795 }; 3796 }; 3797 3798 cpu4_thermal: cpu4-thermal { 3799 polling-delay-passive = <250>; 3800 polling-delay = <0>; 3801 3802 thermal-sensors = <&tsens0 5>; 3803 sustainable-power = <768>; 3804 3805 trips { 3806 cpu4_alert0: trip-point0 { 3807 temperature = <90000>; 3808 hysteresis = <2000>; 3809 type = "passive"; 3810 }; 3811 3812 cpu4_alert1: trip-point1 { 3813 temperature = <95000>; 3814 hysteresis = <2000>; 3815 type = "passive"; 3816 }; 3817 3818 cpu4_crit: cpu_crit { 3819 temperature = <110000>; 3820 hysteresis = <1000>; 3821 type = "critical"; 3822 }; 3823 }; 3824 3825 cooling-maps { 3826 map0 { 3827 trip = <&cpu4_alert0>; 3828 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3829 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3831 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3832 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3833 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3834 }; 3835 map1 { 3836 trip = <&cpu4_alert1>; 3837 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3838 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3839 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3840 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3841 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3843 }; 3844 }; 3845 }; 3846 3847 cpu5_thermal: cpu5-thermal { 3848 polling-delay-passive = <250>; 3849 polling-delay = <0>; 3850 3851 thermal-sensors = <&tsens0 6>; 3852 sustainable-power = <768>; 3853 3854 trips { 3855 cpu5_alert0: trip-point0 { 3856 temperature = <90000>; 3857 hysteresis = <2000>; 3858 type = "passive"; 3859 }; 3860 3861 cpu5_alert1: trip-point1 { 3862 temperature = <95000>; 3863 hysteresis = <2000>; 3864 type = "passive"; 3865 }; 3866 3867 cpu5_crit: cpu_crit { 3868 temperature = <110000>; 3869 hysteresis = <1000>; 3870 type = "critical"; 3871 }; 3872 }; 3873 3874 cooling-maps { 3875 map0 { 3876 trip = <&cpu5_alert0>; 3877 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3878 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3882 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3883 }; 3884 map1 { 3885 trip = <&cpu5_alert1>; 3886 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3887 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3889 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3890 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3891 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3892 }; 3893 }; 3894 }; 3895 3896 cpu6_thermal: cpu6-thermal { 3897 polling-delay-passive = <250>; 3898 polling-delay = <0>; 3899 3900 thermal-sensors = <&tsens0 9>; 3901 sustainable-power = <1202>; 3902 3903 trips { 3904 cpu6_alert0: trip-point0 { 3905 temperature = <90000>; 3906 hysteresis = <2000>; 3907 type = "passive"; 3908 }; 3909 3910 cpu6_alert1: trip-point1 { 3911 temperature = <95000>; 3912 hysteresis = <2000>; 3913 type = "passive"; 3914 }; 3915 3916 cpu6_crit: cpu_crit { 3917 temperature = <110000>; 3918 hysteresis = <1000>; 3919 type = "critical"; 3920 }; 3921 }; 3922 3923 cooling-maps { 3924 map0 { 3925 trip = <&cpu6_alert0>; 3926 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3927 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3928 }; 3929 map1 { 3930 trip = <&cpu6_alert1>; 3931 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3933 }; 3934 }; 3935 }; 3936 3937 cpu7_thermal: cpu7-thermal { 3938 polling-delay-passive = <250>; 3939 polling-delay = <0>; 3940 3941 thermal-sensors = <&tsens0 10>; 3942 sustainable-power = <1202>; 3943 3944 trips { 3945 cpu7_alert0: trip-point0 { 3946 temperature = <90000>; 3947 hysteresis = <2000>; 3948 type = "passive"; 3949 }; 3950 3951 cpu7_alert1: trip-point1 { 3952 temperature = <95000>; 3953 hysteresis = <2000>; 3954 type = "passive"; 3955 }; 3956 3957 cpu7_crit: cpu_crit { 3958 temperature = <110000>; 3959 hysteresis = <1000>; 3960 type = "critical"; 3961 }; 3962 }; 3963 3964 cooling-maps { 3965 map0 { 3966 trip = <&cpu7_alert0>; 3967 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3968 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3969 }; 3970 map1 { 3971 trip = <&cpu7_alert1>; 3972 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3973 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3974 }; 3975 }; 3976 }; 3977 3978 cpu8_thermal: cpu8-thermal { 3979 polling-delay-passive = <250>; 3980 polling-delay = <0>; 3981 3982 thermal-sensors = <&tsens0 11>; 3983 sustainable-power = <1202>; 3984 3985 trips { 3986 cpu8_alert0: trip-point0 { 3987 temperature = <90000>; 3988 hysteresis = <2000>; 3989 type = "passive"; 3990 }; 3991 3992 cpu8_alert1: trip-point1 { 3993 temperature = <95000>; 3994 hysteresis = <2000>; 3995 type = "passive"; 3996 }; 3997 3998 cpu8_crit: cpu_crit { 3999 temperature = <110000>; 4000 hysteresis = <1000>; 4001 type = "critical"; 4002 }; 4003 }; 4004 4005 cooling-maps { 4006 map0 { 4007 trip = <&cpu8_alert0>; 4008 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4009 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4010 }; 4011 map1 { 4012 trip = <&cpu8_alert1>; 4013 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4014 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4015 }; 4016 }; 4017 }; 4018 4019 cpu9_thermal: cpu9-thermal { 4020 polling-delay-passive = <250>; 4021 polling-delay = <0>; 4022 4023 thermal-sensors = <&tsens0 12>; 4024 sustainable-power = <1202>; 4025 4026 trips { 4027 cpu9_alert0: trip-point0 { 4028 temperature = <90000>; 4029 hysteresis = <2000>; 4030 type = "passive"; 4031 }; 4032 4033 cpu9_alert1: trip-point1 { 4034 temperature = <95000>; 4035 hysteresis = <2000>; 4036 type = "passive"; 4037 }; 4038 4039 cpu9_crit: cpu_crit { 4040 temperature = <110000>; 4041 hysteresis = <1000>; 4042 type = "critical"; 4043 }; 4044 }; 4045 4046 cooling-maps { 4047 map0 { 4048 trip = <&cpu9_alert0>; 4049 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4050 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4051 }; 4052 map1 { 4053 trip = <&cpu9_alert1>; 4054 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4055 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4056 }; 4057 }; 4058 }; 4059 4060 aoss0-thermal { 4061 polling-delay-passive = <250>; 4062 polling-delay = <0>; 4063 4064 thermal-sensors = <&tsens0 0>; 4065 4066 trips { 4067 aoss0_alert0: trip-point0 { 4068 temperature = <90000>; 4069 hysteresis = <2000>; 4070 type = "hot"; 4071 }; 4072 4073 aoss0_crit: aoss0_crit { 4074 temperature = <110000>; 4075 hysteresis = <2000>; 4076 type = "critical"; 4077 }; 4078 }; 4079 }; 4080 4081 cpuss0-thermal { 4082 polling-delay-passive = <250>; 4083 polling-delay = <0>; 4084 4085 thermal-sensors = <&tsens0 7>; 4086 4087 trips { 4088 cpuss0_alert0: trip-point0 { 4089 temperature = <90000>; 4090 hysteresis = <2000>; 4091 type = "hot"; 4092 }; 4093 cpuss0_crit: cluster0_crit { 4094 temperature = <110000>; 4095 hysteresis = <2000>; 4096 type = "critical"; 4097 }; 4098 }; 4099 }; 4100 4101 cpuss1-thermal { 4102 polling-delay-passive = <250>; 4103 polling-delay = <0>; 4104 4105 thermal-sensors = <&tsens0 8>; 4106 4107 trips { 4108 cpuss1_alert0: trip-point0 { 4109 temperature = <90000>; 4110 hysteresis = <2000>; 4111 type = "hot"; 4112 }; 4113 cpuss1_crit: cluster0_crit { 4114 temperature = <110000>; 4115 hysteresis = <2000>; 4116 type = "critical"; 4117 }; 4118 }; 4119 }; 4120 4121 gpuss0-thermal { 4122 polling-delay-passive = <250>; 4123 polling-delay = <0>; 4124 4125 thermal-sensors = <&tsens0 13>; 4126 4127 trips { 4128 gpuss0_alert0: trip-point0 { 4129 temperature = <95000>; 4130 hysteresis = <2000>; 4131 type = "passive"; 4132 }; 4133 4134 gpuss0_crit: gpuss0_crit { 4135 temperature = <110000>; 4136 hysteresis = <2000>; 4137 type = "critical"; 4138 }; 4139 }; 4140 4141 cooling-maps { 4142 map0 { 4143 trip = <&gpuss0_alert0>; 4144 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4145 }; 4146 }; 4147 }; 4148 4149 gpuss1-thermal { 4150 polling-delay-passive = <250>; 4151 polling-delay = <0>; 4152 4153 thermal-sensors = <&tsens0 14>; 4154 4155 trips { 4156 gpuss1_alert0: trip-point0 { 4157 temperature = <95000>; 4158 hysteresis = <2000>; 4159 type = "passive"; 4160 }; 4161 4162 gpuss1_crit: gpuss1_crit { 4163 temperature = <110000>; 4164 hysteresis = <2000>; 4165 type = "critical"; 4166 }; 4167 }; 4168 4169 cooling-maps { 4170 map0 { 4171 trip = <&gpuss1_alert0>; 4172 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4173 }; 4174 }; 4175 }; 4176 4177 aoss1-thermal { 4178 polling-delay-passive = <250>; 4179 polling-delay = <0>; 4180 4181 thermal-sensors = <&tsens1 0>; 4182 4183 trips { 4184 aoss1_alert0: trip-point0 { 4185 temperature = <90000>; 4186 hysteresis = <2000>; 4187 type = "hot"; 4188 }; 4189 4190 aoss1_crit: aoss1_crit { 4191 temperature = <110000>; 4192 hysteresis = <2000>; 4193 type = "critical"; 4194 }; 4195 }; 4196 }; 4197 4198 cwlan-thermal { 4199 polling-delay-passive = <250>; 4200 polling-delay = <0>; 4201 4202 thermal-sensors = <&tsens1 1>; 4203 4204 trips { 4205 cwlan_alert0: trip-point0 { 4206 temperature = <90000>; 4207 hysteresis = <2000>; 4208 type = "hot"; 4209 }; 4210 4211 cwlan_crit: cwlan_crit { 4212 temperature = <110000>; 4213 hysteresis = <2000>; 4214 type = "critical"; 4215 }; 4216 }; 4217 }; 4218 4219 audio-thermal { 4220 polling-delay-passive = <250>; 4221 polling-delay = <0>; 4222 4223 thermal-sensors = <&tsens1 2>; 4224 4225 trips { 4226 audio_alert0: trip-point0 { 4227 temperature = <90000>; 4228 hysteresis = <2000>; 4229 type = "hot"; 4230 }; 4231 4232 audio_crit: audio_crit { 4233 temperature = <110000>; 4234 hysteresis = <2000>; 4235 type = "critical"; 4236 }; 4237 }; 4238 }; 4239 4240 ddr-thermal { 4241 polling-delay-passive = <250>; 4242 polling-delay = <0>; 4243 4244 thermal-sensors = <&tsens1 3>; 4245 4246 trips { 4247 ddr_alert0: trip-point0 { 4248 temperature = <90000>; 4249 hysteresis = <2000>; 4250 type = "hot"; 4251 }; 4252 4253 ddr_crit: ddr_crit { 4254 temperature = <110000>; 4255 hysteresis = <2000>; 4256 type = "critical"; 4257 }; 4258 }; 4259 }; 4260 4261 q6-hvx-thermal { 4262 polling-delay-passive = <250>; 4263 polling-delay = <0>; 4264 4265 thermal-sensors = <&tsens1 4>; 4266 4267 trips { 4268 q6_hvx_alert0: trip-point0 { 4269 temperature = <90000>; 4270 hysteresis = <2000>; 4271 type = "hot"; 4272 }; 4273 4274 q6_hvx_crit: q6_hvx_crit { 4275 temperature = <110000>; 4276 hysteresis = <2000>; 4277 type = "critical"; 4278 }; 4279 }; 4280 }; 4281 4282 camera-thermal { 4283 polling-delay-passive = <250>; 4284 polling-delay = <0>; 4285 4286 thermal-sensors = <&tsens1 5>; 4287 4288 trips { 4289 camera_alert0: trip-point0 { 4290 temperature = <90000>; 4291 hysteresis = <2000>; 4292 type = "hot"; 4293 }; 4294 4295 camera_crit: camera_crit { 4296 temperature = <110000>; 4297 hysteresis = <2000>; 4298 type = "critical"; 4299 }; 4300 }; 4301 }; 4302 4303 mdm-core-thermal { 4304 polling-delay-passive = <250>; 4305 polling-delay = <0>; 4306 4307 thermal-sensors = <&tsens1 6>; 4308 4309 trips { 4310 mdm_alert0: trip-point0 { 4311 temperature = <90000>; 4312 hysteresis = <2000>; 4313 type = "hot"; 4314 }; 4315 4316 mdm_crit: mdm_crit { 4317 temperature = <110000>; 4318 hysteresis = <2000>; 4319 type = "critical"; 4320 }; 4321 }; 4322 }; 4323 4324 mdm-dsp-thermal { 4325 polling-delay-passive = <250>; 4326 polling-delay = <0>; 4327 4328 thermal-sensors = <&tsens1 7>; 4329 4330 trips { 4331 mdm_dsp_alert0: trip-point0 { 4332 temperature = <90000>; 4333 hysteresis = <2000>; 4334 type = "hot"; 4335 }; 4336 4337 mdm_dsp_crit: mdm_dsp_crit { 4338 temperature = <110000>; 4339 hysteresis = <2000>; 4340 type = "critical"; 4341 }; 4342 }; 4343 }; 4344 4345 npu-thermal { 4346 polling-delay-passive = <250>; 4347 polling-delay = <0>; 4348 4349 thermal-sensors = <&tsens1 8>; 4350 4351 trips { 4352 npu_alert0: trip-point0 { 4353 temperature = <90000>; 4354 hysteresis = <2000>; 4355 type = "hot"; 4356 }; 4357 4358 npu_crit: npu_crit { 4359 temperature = <110000>; 4360 hysteresis = <2000>; 4361 type = "critical"; 4362 }; 4363 }; 4364 }; 4365 4366 video-thermal { 4367 polling-delay-passive = <250>; 4368 polling-delay = <0>; 4369 4370 thermal-sensors = <&tsens1 9>; 4371 4372 trips { 4373 video_alert0: trip-point0 { 4374 temperature = <90000>; 4375 hysteresis = <2000>; 4376 type = "hot"; 4377 }; 4378 4379 video_crit: video_crit { 4380 temperature = <110000>; 4381 hysteresis = <2000>; 4382 type = "critical"; 4383 }; 4384 }; 4385 }; 4386 }; 4387 4388 timer { 4389 compatible = "arm,armv8-timer"; 4390 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4391 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4392 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4393 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4394 }; 4395}; 4396