1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sc7180.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/phy/phy-qcom-qusb2.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/reset/qcom,sdm845-aoss.h> 22#include <dt-bindings/reset/qcom,sdm845-pdc.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 mmc1 = &sdhc_1; 34 mmc2 = &sdhc_2; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi3 = &spi3; 50 spi5 = &spi5; 51 spi6 = &spi6; 52 spi8 = &spi8; 53 spi10 = &spi10; 54 spi11 = &spi11; 55 }; 56 57 chosen { }; 58 59 clocks { 60 xo_board: xo-board { 61 compatible = "fixed-clock"; 62 clock-frequency = <38400000>; 63 #clock-cells = <0>; 64 }; 65 66 sleep_clk: sleep-clk { 67 compatible = "fixed-clock"; 68 clock-frequency = <32764>; 69 #clock-cells = <0>; 70 }; 71 }; 72 73 cpus { 74 #address-cells = <2>; 75 #size-cells = <0>; 76 77 CPU0: cpu@0 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo468"; 80 reg = <0x0 0x0>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 power-domains = <&CPU_PD0>; 84 power-domain-names = "psci"; 85 capacity-dmips-mhz = <415>; 86 dynamic-power-coefficient = <137>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 89 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 90 next-level-cache = <&L2_0>; 91 #cooling-cells = <2>; 92 qcom,freq-domain = <&cpufreq_hw 0>; 93 L2_0: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&L3_0>; 98 L3_0: l3-cache { 99 compatible = "cache"; 100 cache-level = <3>; 101 cache-unified; 102 }; 103 }; 104 }; 105 106 CPU1: cpu@100 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo468"; 109 reg = <0x0 0x100>; 110 clocks = <&cpufreq_hw 0>; 111 enable-method = "psci"; 112 power-domains = <&CPU_PD1>; 113 power-domain-names = "psci"; 114 capacity-dmips-mhz = <415>; 115 dynamic-power-coefficient = <137>; 116 next-level-cache = <&L2_100>; 117 operating-points-v2 = <&cpu0_opp_table>; 118 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 120 #cooling-cells = <2>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 L2_100: l2-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&L3_0>; 127 }; 128 }; 129 130 CPU2: cpu@200 { 131 device_type = "cpu"; 132 compatible = "qcom,kryo468"; 133 reg = <0x0 0x200>; 134 clocks = <&cpufreq_hw 0>; 135 enable-method = "psci"; 136 power-domains = <&CPU_PD2>; 137 power-domain-names = "psci"; 138 capacity-dmips-mhz = <415>; 139 dynamic-power-coefficient = <137>; 140 next-level-cache = <&L2_200>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 144 #cooling-cells = <2>; 145 qcom,freq-domain = <&cpufreq_hw 0>; 146 L2_200: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU3: cpu@300 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo468"; 157 reg = <0x0 0x300>; 158 clocks = <&cpufreq_hw 0>; 159 enable-method = "psci"; 160 power-domains = <&CPU_PD3>; 161 power-domain-names = "psci"; 162 capacity-dmips-mhz = <415>; 163 dynamic-power-coefficient = <137>; 164 next-level-cache = <&L2_300>; 165 operating-points-v2 = <&cpu0_opp_table>; 166 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 167 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 168 #cooling-cells = <2>; 169 qcom,freq-domain = <&cpufreq_hw 0>; 170 L2_300: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU4: cpu@400 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo468"; 181 reg = <0x0 0x400>; 182 clocks = <&cpufreq_hw 0>; 183 enable-method = "psci"; 184 power-domains = <&CPU_PD4>; 185 power-domain-names = "psci"; 186 capacity-dmips-mhz = <415>; 187 dynamic-power-coefficient = <137>; 188 next-level-cache = <&L2_400>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 192 #cooling-cells = <2>; 193 qcom,freq-domain = <&cpufreq_hw 0>; 194 L2_400: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-unified; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU5: cpu@500 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo468"; 205 reg = <0x0 0x500>; 206 clocks = <&cpufreq_hw 0>; 207 enable-method = "psci"; 208 power-domains = <&CPU_PD5>; 209 power-domain-names = "psci"; 210 capacity-dmips-mhz = <415>; 211 dynamic-power-coefficient = <137>; 212 next-level-cache = <&L2_500>; 213 operating-points-v2 = <&cpu0_opp_table>; 214 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 215 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 216 #cooling-cells = <2>; 217 qcom,freq-domain = <&cpufreq_hw 0>; 218 L2_500: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-unified; 222 next-level-cache = <&L3_0>; 223 }; 224 }; 225 226 CPU6: cpu@600 { 227 device_type = "cpu"; 228 compatible = "qcom,kryo468"; 229 reg = <0x0 0x600>; 230 clocks = <&cpufreq_hw 1>; 231 enable-method = "psci"; 232 power-domains = <&CPU_PD6>; 233 power-domain-names = "psci"; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <480>; 236 next-level-cache = <&L2_600>; 237 operating-points-v2 = <&cpu6_opp_table>; 238 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 239 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 240 #cooling-cells = <2>; 241 qcom,freq-domain = <&cpufreq_hw 1>; 242 L2_600: l2-cache { 243 compatible = "cache"; 244 cache-level = <2>; 245 cache-unified; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU7: cpu@700 { 251 device_type = "cpu"; 252 compatible = "qcom,kryo468"; 253 reg = <0x0 0x700>; 254 clocks = <&cpufreq_hw 1>; 255 enable-method = "psci"; 256 power-domains = <&CPU_PD7>; 257 power-domain-names = "psci"; 258 capacity-dmips-mhz = <1024>; 259 dynamic-power-coefficient = <480>; 260 next-level-cache = <&L2_700>; 261 operating-points-v2 = <&cpu6_opp_table>; 262 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 263 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 264 #cooling-cells = <2>; 265 qcom,freq-domain = <&cpufreq_hw 1>; 266 L2_700: l2-cache { 267 compatible = "cache"; 268 cache-level = <2>; 269 cache-unified; 270 next-level-cache = <&L3_0>; 271 }; 272 }; 273 274 cpu-map { 275 cluster0 { 276 core0 { 277 cpu = <&CPU0>; 278 }; 279 280 core1 { 281 cpu = <&CPU1>; 282 }; 283 284 core2 { 285 cpu = <&CPU2>; 286 }; 287 288 core3 { 289 cpu = <&CPU3>; 290 }; 291 292 core4 { 293 cpu = <&CPU4>; 294 }; 295 296 core5 { 297 cpu = <&CPU5>; 298 }; 299 300 core6 { 301 cpu = <&CPU6>; 302 }; 303 304 core7 { 305 cpu = <&CPU7>; 306 }; 307 }; 308 }; 309 310 idle_states: idle-states { 311 entry-method = "psci"; 312 313 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 314 compatible = "arm,idle-state"; 315 idle-state-name = "little-power-down"; 316 arm,psci-suspend-param = <0x40000003>; 317 entry-latency-us = <549>; 318 exit-latency-us = <901>; 319 min-residency-us = <1774>; 320 local-timer-stop; 321 }; 322 323 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 324 compatible = "arm,idle-state"; 325 idle-state-name = "little-rail-power-down"; 326 arm,psci-suspend-param = <0x40000004>; 327 entry-latency-us = <702>; 328 exit-latency-us = <915>; 329 min-residency-us = <4001>; 330 local-timer-stop; 331 }; 332 333 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 334 compatible = "arm,idle-state"; 335 idle-state-name = "big-power-down"; 336 arm,psci-suspend-param = <0x40000003>; 337 entry-latency-us = <523>; 338 exit-latency-us = <1244>; 339 min-residency-us = <2207>; 340 local-timer-stop; 341 }; 342 343 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 344 compatible = "arm,idle-state"; 345 idle-state-name = "big-rail-power-down"; 346 arm,psci-suspend-param = <0x40000004>; 347 entry-latency-us = <526>; 348 exit-latency-us = <1854>; 349 min-residency-us = <5555>; 350 local-timer-stop; 351 }; 352 }; 353 354 domain_idle_states: domain-idle-states { 355 CLUSTER_SLEEP_PC: cluster-sleep-0 { 356 compatible = "domain-idle-state"; 357 idle-state-name = "cluster-l3-power-collapse"; 358 arm,psci-suspend-param = <0x41000044>; 359 entry-latency-us = <2752>; 360 exit-latency-us = <3048>; 361 min-residency-us = <6118>; 362 }; 363 364 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 365 compatible = "domain-idle-state"; 366 idle-state-name = "cluster-cx-retention"; 367 arm,psci-suspend-param = <0x41001244>; 368 entry-latency-us = <3638>; 369 exit-latency-us = <4562>; 370 min-residency-us = <8467>; 371 }; 372 373 CLUSTER_AOSS_SLEEP: cluster-sleep-2 { 374 compatible = "domain-idle-state"; 375 idle-state-name = "cluster-power-down"; 376 arm,psci-suspend-param = <0x4100b244>; 377 entry-latency-us = <3263>; 378 exit-latency-us = <6562>; 379 min-residency-us = <9826>; 380 }; 381 }; 382 }; 383 384 firmware { 385 scm: scm { 386 compatible = "qcom,scm-sc7180", "qcom,scm"; 387 }; 388 }; 389 390 memory@80000000 { 391 device_type = "memory"; 392 /* We expect the bootloader to fill in the size */ 393 reg = <0 0x80000000 0 0>; 394 }; 395 396 cpu0_opp_table: opp-table-cpu0 { 397 compatible = "operating-points-v2"; 398 opp-shared; 399 400 cpu0_opp1: opp-300000000 { 401 opp-hz = /bits/ 64 <300000000>; 402 opp-peak-kBps = <1200000 4800000>; 403 }; 404 405 cpu0_opp2: opp-576000000 { 406 opp-hz = /bits/ 64 <576000000>; 407 opp-peak-kBps = <1200000 4800000>; 408 }; 409 410 cpu0_opp3: opp-768000000 { 411 opp-hz = /bits/ 64 <768000000>; 412 opp-peak-kBps = <1200000 4800000>; 413 }; 414 415 cpu0_opp4: opp-1017600000 { 416 opp-hz = /bits/ 64 <1017600000>; 417 opp-peak-kBps = <1804000 8908800>; 418 }; 419 420 cpu0_opp5: opp-1248000000 { 421 opp-hz = /bits/ 64 <1248000000>; 422 opp-peak-kBps = <2188000 12902400>; 423 }; 424 425 cpu0_opp6: opp-1324800000 { 426 opp-hz = /bits/ 64 <1324800000>; 427 opp-peak-kBps = <2188000 12902400>; 428 }; 429 430 cpu0_opp7: opp-1516800000 { 431 opp-hz = /bits/ 64 <1516800000>; 432 opp-peak-kBps = <3072000 15052800>; 433 }; 434 435 cpu0_opp8: opp-1612800000 { 436 opp-hz = /bits/ 64 <1612800000>; 437 opp-peak-kBps = <3072000 15052800>; 438 }; 439 440 cpu0_opp9: opp-1708800000 { 441 opp-hz = /bits/ 64 <1708800000>; 442 opp-peak-kBps = <3072000 15052800>; 443 }; 444 445 cpu0_opp10: opp-1804800000 { 446 opp-hz = /bits/ 64 <1804800000>; 447 opp-peak-kBps = <4068000 22425600>; 448 }; 449 }; 450 451 cpu6_opp_table: opp-table-cpu6 { 452 compatible = "operating-points-v2"; 453 opp-shared; 454 455 cpu6_opp1: opp-300000000 { 456 opp-hz = /bits/ 64 <300000000>; 457 opp-peak-kBps = <2188000 8908800>; 458 }; 459 460 cpu6_opp2: opp-652800000 { 461 opp-hz = /bits/ 64 <652800000>; 462 opp-peak-kBps = <2188000 8908800>; 463 }; 464 465 cpu6_opp3: opp-825600000 { 466 opp-hz = /bits/ 64 <825600000>; 467 opp-peak-kBps = <2188000 8908800>; 468 }; 469 470 cpu6_opp4: opp-979200000 { 471 opp-hz = /bits/ 64 <979200000>; 472 opp-peak-kBps = <2188000 8908800>; 473 }; 474 475 cpu6_opp5: opp-1113600000 { 476 opp-hz = /bits/ 64 <1113600000>; 477 opp-peak-kBps = <2188000 8908800>; 478 }; 479 480 cpu6_opp6: opp-1267200000 { 481 opp-hz = /bits/ 64 <1267200000>; 482 opp-peak-kBps = <4068000 12902400>; 483 }; 484 485 cpu6_opp7: opp-1555200000 { 486 opp-hz = /bits/ 64 <1555200000>; 487 opp-peak-kBps = <4068000 15052800>; 488 }; 489 490 cpu6_opp8: opp-1708800000 { 491 opp-hz = /bits/ 64 <1708800000>; 492 opp-peak-kBps = <6220000 19353600>; 493 }; 494 495 cpu6_opp9: opp-1843200000 { 496 opp-hz = /bits/ 64 <1843200000>; 497 opp-peak-kBps = <6220000 19353600>; 498 }; 499 500 cpu6_opp10: opp-1900800000 { 501 opp-hz = /bits/ 64 <1900800000>; 502 opp-peak-kBps = <6220000 22425600>; 503 }; 504 505 cpu6_opp11: opp-1996800000 { 506 opp-hz = /bits/ 64 <1996800000>; 507 opp-peak-kBps = <6220000 22425600>; 508 }; 509 510 cpu6_opp12: opp-2112000000 { 511 opp-hz = /bits/ 64 <2112000000>; 512 opp-peak-kBps = <6220000 22425600>; 513 }; 514 515 cpu6_opp13: opp-2208000000 { 516 opp-hz = /bits/ 64 <2208000000>; 517 opp-peak-kBps = <7216000 22425600>; 518 }; 519 520 cpu6_opp14: opp-2323200000 { 521 opp-hz = /bits/ 64 <2323200000>; 522 opp-peak-kBps = <7216000 22425600>; 523 }; 524 525 cpu6_opp15: opp-2400000000 { 526 opp-hz = /bits/ 64 <2400000000>; 527 opp-peak-kBps = <8532000 23347200>; 528 }; 529 530 cpu6_opp16: opp-2553600000 { 531 opp-hz = /bits/ 64 <2553600000>; 532 opp-peak-kBps = <8532000 23347200>; 533 }; 534 }; 535 536 qspi_opp_table: opp-table-qspi { 537 compatible = "operating-points-v2"; 538 539 opp-75000000 { 540 opp-hz = /bits/ 64 <75000000>; 541 required-opps = <&rpmhpd_opp_low_svs>; 542 }; 543 544 opp-150000000 { 545 opp-hz = /bits/ 64 <150000000>; 546 required-opps = <&rpmhpd_opp_svs>; 547 }; 548 549 opp-300000000 { 550 opp-hz = /bits/ 64 <300000000>; 551 required-opps = <&rpmhpd_opp_nom>; 552 }; 553 }; 554 555 qup_opp_table: opp-table-qup { 556 compatible = "operating-points-v2"; 557 558 opp-75000000 { 559 opp-hz = /bits/ 64 <75000000>; 560 required-opps = <&rpmhpd_opp_low_svs>; 561 }; 562 563 opp-100000000 { 564 opp-hz = /bits/ 64 <100000000>; 565 required-opps = <&rpmhpd_opp_svs>; 566 }; 567 568 opp-128000000 { 569 opp-hz = /bits/ 64 <128000000>; 570 required-opps = <&rpmhpd_opp_nom>; 571 }; 572 }; 573 574 pmu { 575 compatible = "arm,armv8-pmuv3"; 576 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 577 }; 578 579 psci { 580 compatible = "arm,psci-1.0"; 581 method = "smc"; 582 583 CPU_PD0: cpu0 { 584 #power-domain-cells = <0>; 585 power-domains = <&CLUSTER_PD>; 586 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 587 }; 588 589 CPU_PD1: cpu1 { 590 #power-domain-cells = <0>; 591 power-domains = <&CLUSTER_PD>; 592 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 593 }; 594 595 CPU_PD2: cpu2 { 596 #power-domain-cells = <0>; 597 power-domains = <&CLUSTER_PD>; 598 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 599 }; 600 601 CPU_PD3: cpu3 { 602 #power-domain-cells = <0>; 603 power-domains = <&CLUSTER_PD>; 604 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 605 }; 606 607 CPU_PD4: cpu4 { 608 #power-domain-cells = <0>; 609 power-domains = <&CLUSTER_PD>; 610 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 611 }; 612 613 CPU_PD5: cpu5 { 614 #power-domain-cells = <0>; 615 power-domains = <&CLUSTER_PD>; 616 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 617 }; 618 619 CPU_PD6: cpu6 { 620 #power-domain-cells = <0>; 621 power-domains = <&CLUSTER_PD>; 622 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 623 }; 624 625 CPU_PD7: cpu7 { 626 #power-domain-cells = <0>; 627 power-domains = <&CLUSTER_PD>; 628 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 629 }; 630 631 CLUSTER_PD: cpu-cluster0 { 632 #power-domain-cells = <0>; 633 domain-idle-states = <&CLUSTER_SLEEP_PC 634 &CLUSTER_SLEEP_CX_RET 635 &CLUSTER_AOSS_SLEEP>; 636 }; 637 }; 638 639 reserved_memory: reserved-memory { 640 #address-cells = <2>; 641 #size-cells = <2>; 642 ranges; 643 644 hyp_mem: memory@80000000 { 645 reg = <0x0 0x80000000 0x0 0x600000>; 646 no-map; 647 }; 648 649 xbl_mem: memory@80600000 { 650 reg = <0x0 0x80600000 0x0 0x200000>; 651 no-map; 652 }; 653 654 aop_mem: memory@80800000 { 655 reg = <0x0 0x80800000 0x0 0x20000>; 656 no-map; 657 }; 658 659 aop_cmd_db_mem: memory@80820000 { 660 reg = <0x0 0x80820000 0x0 0x20000>; 661 compatible = "qcom,cmd-db"; 662 no-map; 663 }; 664 665 sec_apps_mem: memory@808ff000 { 666 reg = <0x0 0x808ff000 0x0 0x1000>; 667 no-map; 668 }; 669 670 smem_mem: memory@80900000 { 671 reg = <0x0 0x80900000 0x0 0x200000>; 672 no-map; 673 }; 674 675 tz_mem: memory@80b00000 { 676 reg = <0x0 0x80b00000 0x0 0x3900000>; 677 no-map; 678 }; 679 680 ipa_fw_mem: memory@8b700000 { 681 reg = <0 0x8b700000 0 0x10000>; 682 no-map; 683 }; 684 685 rmtfs_mem: memory@94600000 { 686 compatible = "qcom,rmtfs-mem"; 687 reg = <0x0 0x94600000 0x0 0x200000>; 688 no-map; 689 690 qcom,client-id = <1>; 691 qcom,vmid = <15>; 692 }; 693 }; 694 695 smem { 696 compatible = "qcom,smem"; 697 memory-region = <&smem_mem>; 698 hwlocks = <&tcsr_mutex 3>; 699 }; 700 701 smp2p-cdsp { 702 compatible = "qcom,smp2p"; 703 qcom,smem = <94>, <432>; 704 705 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 706 707 mboxes = <&apss_shared 6>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <5>; 711 712 cdsp_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 cdsp_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 }; 724 725 smp2p-lpass { 726 compatible = "qcom,smp2p"; 727 qcom,smem = <443>, <429>; 728 729 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 730 731 mboxes = <&apss_shared 10>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <2>; 735 736 adsp_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 adsp_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-mpss { 750 compatible = "qcom,smp2p"; 751 qcom,smem = <435>, <428>; 752 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 753 mboxes = <&apss_shared 14>; 754 qcom,local-pid = <0>; 755 qcom,remote-pid = <1>; 756 757 modem_smp2p_out: master-kernel { 758 qcom,entry-name = "master-kernel"; 759 #qcom,smem-state-cells = <1>; 760 }; 761 762 modem_smp2p_in: slave-kernel { 763 qcom,entry-name = "slave-kernel"; 764 interrupt-controller; 765 #interrupt-cells = <2>; 766 }; 767 768 ipa_smp2p_out: ipa-ap-to-modem { 769 qcom,entry-name = "ipa"; 770 #qcom,smem-state-cells = <1>; 771 }; 772 773 ipa_smp2p_in: ipa-modem-to-ap { 774 qcom,entry-name = "ipa"; 775 interrupt-controller; 776 #interrupt-cells = <2>; 777 }; 778 }; 779 780 soc: soc@0 { 781 #address-cells = <2>; 782 #size-cells = <2>; 783 ranges = <0 0 0 0 0x10 0>; 784 dma-ranges = <0 0 0 0 0x10 0>; 785 compatible = "simple-bus"; 786 787 gcc: clock-controller@100000 { 788 compatible = "qcom,gcc-sc7180"; 789 reg = <0 0x00100000 0 0x1f0000>; 790 clocks = <&rpmhcc RPMH_CXO_CLK>, 791 <&rpmhcc RPMH_CXO_CLK_A>, 792 <&sleep_clk>; 793 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 794 #clock-cells = <1>; 795 #reset-cells = <1>; 796 #power-domain-cells = <1>; 797 power-domains = <&rpmhpd SC7180_CX>; 798 }; 799 800 qfprom: efuse@784000 { 801 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 802 reg = <0 0x00784000 0 0x7a0>, 803 <0 0x00780000 0 0x7a0>, 804 <0 0x00782000 0 0x100>, 805 <0 0x00786000 0 0x1fff>; 806 807 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 808 clock-names = "core"; 809 #address-cells = <1>; 810 #size-cells = <1>; 811 812 qusb2p_hstx_trim: hstx-trim-primary@25b { 813 reg = <0x25b 0x1>; 814 bits = <1 3>; 815 }; 816 817 gpu_speed_bin: gpu_speed_bin@1d2 { 818 reg = <0x1d2 0x2>; 819 bits = <5 8>; 820 }; 821 }; 822 823 sdhc_1: mmc@7c4000 { 824 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 825 reg = <0 0x007c4000 0 0x1000>, 826 <0 0x007c5000 0 0x1000>; 827 reg-names = "hc", "cqhci"; 828 829 iommus = <&apps_smmu 0x60 0x0>; 830 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "hc_irq", "pwr_irq"; 833 834 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 835 <&gcc GCC_SDCC1_APPS_CLK>, 836 <&rpmhcc RPMH_CXO_CLK>; 837 clock-names = "iface", "core", "xo"; 838 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 839 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 840 interconnect-names = "sdhc-ddr","cpu-sdhc"; 841 power-domains = <&rpmhpd SC7180_CX>; 842 operating-points-v2 = <&sdhc1_opp_table>; 843 844 bus-width = <8>; 845 non-removable; 846 supports-cqe; 847 848 mmc-ddr-1_8v; 849 mmc-hs200-1_8v; 850 mmc-hs400-1_8v; 851 mmc-hs400-enhanced-strobe; 852 853 status = "disabled"; 854 855 sdhc1_opp_table: opp-table { 856 compatible = "operating-points-v2"; 857 858 opp-100000000 { 859 opp-hz = /bits/ 64 <100000000>; 860 required-opps = <&rpmhpd_opp_low_svs>; 861 opp-peak-kBps = <1800000 600000>; 862 opp-avg-kBps = <100000 0>; 863 }; 864 865 opp-384000000 { 866 opp-hz = /bits/ 64 <384000000>; 867 required-opps = <&rpmhpd_opp_nom>; 868 opp-peak-kBps = <5400000 1600000>; 869 opp-avg-kBps = <390000 0>; 870 }; 871 }; 872 }; 873 874 qupv3_id_0: geniqup@8c0000 { 875 compatible = "qcom,geni-se-qup"; 876 reg = <0 0x008c0000 0 0x6000>; 877 clock-names = "m-ahb", "s-ahb"; 878 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 879 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 880 #address-cells = <2>; 881 #size-cells = <2>; 882 ranges; 883 iommus = <&apps_smmu 0x43 0x0>; 884 status = "disabled"; 885 886 i2c0: i2c@880000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0 0x00880000 0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c0_default>; 893 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", 900 "qup-memory"; 901 power-domains = <&rpmhpd SC7180_CX>; 902 required-opps = <&rpmhpd_opp_low_svs>; 903 status = "disabled"; 904 }; 905 906 spi0: spi@880000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x00880000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 913 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 power-domains = <&rpmhpd SC7180_CX>; 917 operating-points-v2 = <&qup_opp_table>; 918 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 920 interconnect-names = "qup-core", "qup-config"; 921 status = "disabled"; 922 }; 923 924 uart0: serial@880000 { 925 compatible = "qcom,geni-uart"; 926 reg = <0 0x00880000 0 0x4000>; 927 clock-names = "se"; 928 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 929 pinctrl-names = "default"; 930 pinctrl-0 = <&qup_uart0_default>; 931 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 932 power-domains = <&rpmhpd SC7180_CX>; 933 operating-points-v2 = <&qup_opp_table>; 934 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 935 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 936 interconnect-names = "qup-core", "qup-config"; 937 status = "disabled"; 938 }; 939 940 i2c1: i2c@884000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0 0x00884000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&qup_i2c1_default>; 947 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 952 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 953 interconnect-names = "qup-core", "qup-config", 954 "qup-memory"; 955 power-domains = <&rpmhpd SC7180_CX>; 956 required-opps = <&rpmhpd_opp_low_svs>; 957 status = "disabled"; 958 }; 959 960 spi1: spi@884000 { 961 compatible = "qcom,geni-spi"; 962 reg = <0 0x00884000 0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 967 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 power-domains = <&rpmhpd SC7180_CX>; 971 operating-points-v2 = <&qup_opp_table>; 972 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 974 interconnect-names = "qup-core", "qup-config"; 975 status = "disabled"; 976 }; 977 978 uart1: serial@884000 { 979 compatible = "qcom,geni-uart"; 980 reg = <0 0x00884000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_uart1_default>; 985 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC7180_CX>; 987 operating-points-v2 = <&qup_opp_table>; 988 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 990 interconnect-names = "qup-core", "qup-config"; 991 status = "disabled"; 992 }; 993 994 i2c2: i2c@888000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0 0x00888000 0 0x4000>; 997 clock-names = "se"; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c2_default>; 1001 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", 1008 "qup-memory"; 1009 power-domains = <&rpmhpd SC7180_CX>; 1010 required-opps = <&rpmhpd_opp_low_svs>; 1011 status = "disabled"; 1012 }; 1013 1014 uart2: serial@888000 { 1015 compatible = "qcom,geni-uart"; 1016 reg = <0 0x00888000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_uart2_default>; 1021 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1022 power-domains = <&rpmhpd SC7180_CX>; 1023 operating-points-v2 = <&qup_opp_table>; 1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1026 interconnect-names = "qup-core", "qup-config"; 1027 status = "disabled"; 1028 }; 1029 1030 i2c3: i2c@88c000 { 1031 compatible = "qcom,geni-i2c"; 1032 reg = <0 0x0088c000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_i2c3_default>; 1037 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1042 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1043 interconnect-names = "qup-core", "qup-config", 1044 "qup-memory"; 1045 power-domains = <&rpmhpd SC7180_CX>; 1046 required-opps = <&rpmhpd_opp_low_svs>; 1047 status = "disabled"; 1048 }; 1049 1050 spi3: spi@88c000 { 1051 compatible = "qcom,geni-spi"; 1052 reg = <0 0x0088c000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 1057 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 power-domains = <&rpmhpd SC7180_CX>; 1061 operating-points-v2 = <&qup_opp_table>; 1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1064 interconnect-names = "qup-core", "qup-config"; 1065 status = "disabled"; 1066 }; 1067 1068 uart3: serial@88c000 { 1069 compatible = "qcom,geni-uart"; 1070 reg = <0 0x0088c000 0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&qup_uart3_default>; 1075 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1076 power-domains = <&rpmhpd SC7180_CX>; 1077 operating-points-v2 = <&qup_opp_table>; 1078 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1080 interconnect-names = "qup-core", "qup-config"; 1081 status = "disabled"; 1082 }; 1083 1084 i2c4: i2c@890000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00890000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_i2c4_default>; 1091 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1096 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1097 interconnect-names = "qup-core", "qup-config", 1098 "qup-memory"; 1099 power-domains = <&rpmhpd SC7180_CX>; 1100 required-opps = <&rpmhpd_opp_low_svs>; 1101 status = "disabled"; 1102 }; 1103 1104 uart4: serial@890000 { 1105 compatible = "qcom,geni-uart"; 1106 reg = <0 0x00890000 0 0x4000>; 1107 clock-names = "se"; 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&qup_uart4_default>; 1111 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1112 power-domains = <&rpmhpd SC7180_CX>; 1113 operating-points-v2 = <&qup_opp_table>; 1114 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1116 interconnect-names = "qup-core", "qup-config"; 1117 status = "disabled"; 1118 }; 1119 1120 i2c5: i2c@894000 { 1121 compatible = "qcom,geni-i2c"; 1122 reg = <0 0x00894000 0 0x4000>; 1123 clock-names = "se"; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&qup_i2c5_default>; 1127 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1132 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1133 interconnect-names = "qup-core", "qup-config", 1134 "qup-memory"; 1135 power-domains = <&rpmhpd SC7180_CX>; 1136 required-opps = <&rpmhpd_opp_low_svs>; 1137 status = "disabled"; 1138 }; 1139 1140 spi5: spi@894000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00894000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1147 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 power-domains = <&rpmhpd SC7180_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1153 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1154 interconnect-names = "qup-core", "qup-config"; 1155 status = "disabled"; 1156 }; 1157 1158 uart5: serial@894000 { 1159 compatible = "qcom,geni-uart"; 1160 reg = <0 0x00894000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_uart5_default>; 1165 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1166 power-domains = <&rpmhpd SC7180_CX>; 1167 operating-points-v2 = <&qup_opp_table>; 1168 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1170 interconnect-names = "qup-core", "qup-config"; 1171 status = "disabled"; 1172 }; 1173 }; 1174 1175 qupv3_id_1: geniqup@ac0000 { 1176 compatible = "qcom,geni-se-qup"; 1177 reg = <0 0x00ac0000 0 0x6000>; 1178 clock-names = "m-ahb", "s-ahb"; 1179 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1180 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1181 #address-cells = <2>; 1182 #size-cells = <2>; 1183 ranges; 1184 iommus = <&apps_smmu 0x4c3 0x0>; 1185 status = "disabled"; 1186 1187 i2c6: i2c@a80000 { 1188 compatible = "qcom,geni-i2c"; 1189 reg = <0 0x00a80000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_i2c6_default>; 1194 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1199 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1200 interconnect-names = "qup-core", "qup-config", 1201 "qup-memory"; 1202 power-domains = <&rpmhpd SC7180_CX>; 1203 required-opps = <&rpmhpd_opp_low_svs>; 1204 status = "disabled"; 1205 }; 1206 1207 spi6: spi@a80000 { 1208 compatible = "qcom,geni-spi"; 1209 reg = <0 0x00a80000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1214 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 power-domains = <&rpmhpd SC7180_CX>; 1218 operating-points-v2 = <&qup_opp_table>; 1219 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 status = "disabled"; 1223 }; 1224 1225 uart6: serial@a80000 { 1226 compatible = "qcom,geni-uart"; 1227 reg = <0 0x00a80000 0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_uart6_default>; 1232 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1233 power-domains = <&rpmhpd SC7180_CX>; 1234 operating-points-v2 = <&qup_opp_table>; 1235 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1236 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1237 interconnect-names = "qup-core", "qup-config"; 1238 status = "disabled"; 1239 }; 1240 1241 i2c7: i2c@a84000 { 1242 compatible = "qcom,geni-i2c"; 1243 reg = <0 0x00a84000 0 0x4000>; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&qup_i2c7_default>; 1248 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1252 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1253 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1254 interconnect-names = "qup-core", "qup-config", 1255 "qup-memory"; 1256 power-domains = <&rpmhpd SC7180_CX>; 1257 required-opps = <&rpmhpd_opp_low_svs>; 1258 status = "disabled"; 1259 }; 1260 1261 uart7: serial@a84000 { 1262 compatible = "qcom,geni-uart"; 1263 reg = <0 0x00a84000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_uart7_default>; 1268 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1269 power-domains = <&rpmhpd SC7180_CX>; 1270 operating-points-v2 = <&qup_opp_table>; 1271 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1272 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1273 interconnect-names = "qup-core", "qup-config"; 1274 status = "disabled"; 1275 }; 1276 1277 i2c8: i2c@a88000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0 0x00a88000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c8_default>; 1284 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1288 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1289 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1290 interconnect-names = "qup-core", "qup-config", 1291 "qup-memory"; 1292 power-domains = <&rpmhpd SC7180_CX>; 1293 required-opps = <&rpmhpd_opp_low_svs>; 1294 status = "disabled"; 1295 }; 1296 1297 spi8: spi@a88000 { 1298 compatible = "qcom,geni-spi"; 1299 reg = <0 0x00a88000 0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1304 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 power-domains = <&rpmhpd SC7180_CX>; 1308 operating-points-v2 = <&qup_opp_table>; 1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1311 interconnect-names = "qup-core", "qup-config"; 1312 status = "disabled"; 1313 }; 1314 1315 uart8: serial@a88000 { 1316 compatible = "qcom,geni-debug-uart"; 1317 reg = <0 0x00a88000 0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_uart8_default>; 1322 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1323 power-domains = <&rpmhpd SC7180_CX>; 1324 operating-points-v2 = <&qup_opp_table>; 1325 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1327 interconnect-names = "qup-core", "qup-config"; 1328 status = "disabled"; 1329 }; 1330 1331 i2c9: i2c@a8c000 { 1332 compatible = "qcom,geni-i2c"; 1333 reg = <0 0x00a8c000 0 0x4000>; 1334 clock-names = "se"; 1335 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_i2c9_default>; 1338 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1342 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1343 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1344 interconnect-names = "qup-core", "qup-config", 1345 "qup-memory"; 1346 power-domains = <&rpmhpd SC7180_CX>; 1347 required-opps = <&rpmhpd_opp_low_svs>; 1348 status = "disabled"; 1349 }; 1350 1351 uart9: serial@a8c000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0 0x00a8c000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&qup_uart9_default>; 1358 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1359 power-domains = <&rpmhpd SC7180_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 status = "disabled"; 1365 }; 1366 1367 i2c10: i2c@a90000 { 1368 compatible = "qcom,geni-i2c"; 1369 reg = <0 0x00a90000 0 0x4000>; 1370 clock-names = "se"; 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_i2c10_default>; 1374 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1378 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1379 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1380 interconnect-names = "qup-core", "qup-config", 1381 "qup-memory"; 1382 power-domains = <&rpmhpd SC7180_CX>; 1383 required-opps = <&rpmhpd_opp_low_svs>; 1384 status = "disabled"; 1385 }; 1386 1387 spi10: spi@a90000 { 1388 compatible = "qcom,geni-spi"; 1389 reg = <0 0x00a90000 0 0x4000>; 1390 clock-names = "se"; 1391 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1394 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 power-domains = <&rpmhpd SC7180_CX>; 1398 operating-points-v2 = <&qup_opp_table>; 1399 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1401 interconnect-names = "qup-core", "qup-config"; 1402 status = "disabled"; 1403 }; 1404 1405 uart10: serial@a90000 { 1406 compatible = "qcom,geni-uart"; 1407 reg = <0 0x00a90000 0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&qup_uart10_default>; 1412 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1413 power-domains = <&rpmhpd SC7180_CX>; 1414 operating-points-v2 = <&qup_opp_table>; 1415 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1417 interconnect-names = "qup-core", "qup-config"; 1418 status = "disabled"; 1419 }; 1420 1421 i2c11: i2c@a94000 { 1422 compatible = "qcom,geni-i2c"; 1423 reg = <0 0x00a94000 0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_i2c11_default>; 1428 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1433 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1434 interconnect-names = "qup-core", "qup-config", 1435 "qup-memory"; 1436 power-domains = <&rpmhpd SC7180_CX>; 1437 required-opps = <&rpmhpd_opp_low_svs>; 1438 status = "disabled"; 1439 }; 1440 1441 spi11: spi@a94000 { 1442 compatible = "qcom,geni-spi"; 1443 reg = <0 0x00a94000 0 0x4000>; 1444 clock-names = "se"; 1445 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1448 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 power-domains = <&rpmhpd SC7180_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1454 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1455 interconnect-names = "qup-core", "qup-config"; 1456 status = "disabled"; 1457 }; 1458 1459 uart11: serial@a94000 { 1460 compatible = "qcom,geni-uart"; 1461 reg = <0 0x00a94000 0 0x4000>; 1462 clock-names = "se"; 1463 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1464 pinctrl-names = "default"; 1465 pinctrl-0 = <&qup_uart11_default>; 1466 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1467 power-domains = <&rpmhpd SC7180_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1470 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1471 interconnect-names = "qup-core", "qup-config"; 1472 status = "disabled"; 1473 }; 1474 }; 1475 1476 config_noc: interconnect@1500000 { 1477 compatible = "qcom,sc7180-config-noc"; 1478 reg = <0 0x01500000 0 0x28000>; 1479 #interconnect-cells = <2>; 1480 qcom,bcm-voters = <&apps_bcm_voter>; 1481 }; 1482 1483 system_noc: interconnect@1620000 { 1484 compatible = "qcom,sc7180-system-noc"; 1485 reg = <0 0x01620000 0 0x17080>; 1486 #interconnect-cells = <2>; 1487 qcom,bcm-voters = <&apps_bcm_voter>; 1488 }; 1489 1490 mc_virt: interconnect@1638000 { 1491 compatible = "qcom,sc7180-mc-virt"; 1492 reg = <0 0x01638000 0 0x1000>; 1493 #interconnect-cells = <2>; 1494 qcom,bcm-voters = <&apps_bcm_voter>; 1495 }; 1496 1497 qup_virt: interconnect@1650000 { 1498 compatible = "qcom,sc7180-qup-virt"; 1499 reg = <0 0x01650000 0 0x1000>; 1500 #interconnect-cells = <2>; 1501 qcom,bcm-voters = <&apps_bcm_voter>; 1502 }; 1503 1504 aggre1_noc: interconnect@16e0000 { 1505 compatible = "qcom,sc7180-aggre1-noc"; 1506 reg = <0 0x016e0000 0 0x15080>; 1507 #interconnect-cells = <2>; 1508 qcom,bcm-voters = <&apps_bcm_voter>; 1509 }; 1510 1511 aggre2_noc: interconnect@1705000 { 1512 compatible = "qcom,sc7180-aggre2-noc"; 1513 reg = <0 0x01705000 0 0x9000>; 1514 #interconnect-cells = <2>; 1515 qcom,bcm-voters = <&apps_bcm_voter>; 1516 }; 1517 1518 compute_noc: interconnect@170e000 { 1519 compatible = "qcom,sc7180-compute-noc"; 1520 reg = <0 0x0170e000 0 0x6000>; 1521 #interconnect-cells = <2>; 1522 qcom,bcm-voters = <&apps_bcm_voter>; 1523 }; 1524 1525 mmss_noc: interconnect@1740000 { 1526 compatible = "qcom,sc7180-mmss-noc"; 1527 reg = <0 0x01740000 0 0x1c100>; 1528 #interconnect-cells = <2>; 1529 qcom,bcm-voters = <&apps_bcm_voter>; 1530 }; 1531 1532 ipa: ipa@1e40000 { 1533 compatible = "qcom,sc7180-ipa"; 1534 1535 iommus = <&apps_smmu 0x440 0x0>, 1536 <&apps_smmu 0x442 0x0>; 1537 reg = <0 0x01e40000 0 0x7000>, 1538 <0 0x01e47000 0 0x2000>, 1539 <0 0x01e04000 0 0x2c000>; 1540 reg-names = "ipa-reg", 1541 "ipa-shared", 1542 "gsi"; 1543 1544 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1545 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1546 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1547 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1548 interrupt-names = "ipa", 1549 "gsi", 1550 "ipa-clock-query", 1551 "ipa-setup-ready"; 1552 1553 clocks = <&rpmhcc RPMH_IPA_CLK>; 1554 clock-names = "core"; 1555 1556 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1557 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1558 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1559 interconnect-names = "memory", 1560 "imem", 1561 "config"; 1562 1563 qcom,qmp = <&aoss_qmp>; 1564 1565 qcom,smem-states = <&ipa_smp2p_out 0>, 1566 <&ipa_smp2p_out 1>; 1567 qcom,smem-state-names = "ipa-clock-enabled-valid", 1568 "ipa-clock-enabled"; 1569 1570 status = "disabled"; 1571 }; 1572 1573 tcsr_mutex: hwlock@1f40000 { 1574 compatible = "qcom,tcsr-mutex"; 1575 reg = <0 0x01f40000 0 0x20000>; 1576 #hwlock-cells = <1>; 1577 }; 1578 1579 tcsr_regs_1: syscon@1f60000 { 1580 compatible = "qcom,sc7180-tcsr", "syscon"; 1581 reg = <0 0x01f60000 0 0x20000>; 1582 }; 1583 1584 tcsr_regs_2: syscon@1fc0000 { 1585 compatible = "qcom,sc7180-tcsr", "syscon"; 1586 reg = <0 0x01fc0000 0 0x40000>; 1587 }; 1588 1589 tlmm: pinctrl@3500000 { 1590 compatible = "qcom,sc7180-pinctrl"; 1591 reg = <0 0x03500000 0 0x300000>, 1592 <0 0x03900000 0 0x300000>, 1593 <0 0x03d00000 0 0x300000>; 1594 reg-names = "west", "north", "south"; 1595 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1596 gpio-controller; 1597 #gpio-cells = <2>; 1598 interrupt-controller; 1599 #interrupt-cells = <2>; 1600 gpio-ranges = <&tlmm 0 0 120>; 1601 wakeup-parent = <&pdc>; 1602 1603 dp_hot_plug_det: dp-hot-plug-det-state { 1604 pins = "gpio117"; 1605 function = "dp_hot"; 1606 }; 1607 1608 qspi_clk: qspi-clk-state { 1609 pins = "gpio63"; 1610 function = "qspi_clk"; 1611 }; 1612 1613 qspi_cs0: qspi-cs0-state { 1614 pins = "gpio68"; 1615 function = "qspi_cs"; 1616 }; 1617 1618 qspi_cs1: qspi-cs1-state { 1619 pins = "gpio72"; 1620 function = "qspi_cs"; 1621 }; 1622 1623 qspi_data0: qspi-data0-state { 1624 pins = "gpio64"; 1625 function = "qspi_data"; 1626 }; 1627 1628 qspi_data1: qspi-data1-state { 1629 pins = "gpio65"; 1630 function = "qspi_data"; 1631 }; 1632 1633 qspi_data23: qspi-data23-state { 1634 pins = "gpio66", "gpio67"; 1635 function = "qspi_data"; 1636 }; 1637 1638 qup_i2c0_default: qup-i2c0-default-state { 1639 pins = "gpio34", "gpio35"; 1640 function = "qup00"; 1641 }; 1642 1643 qup_i2c1_default: qup-i2c1-default-state { 1644 pins = "gpio0", "gpio1"; 1645 function = "qup01"; 1646 }; 1647 1648 qup_i2c2_default: qup-i2c2-default-state { 1649 pins = "gpio15", "gpio16"; 1650 function = "qup02_i2c"; 1651 }; 1652 1653 qup_i2c3_default: qup-i2c3-default-state { 1654 pins = "gpio38", "gpio39"; 1655 function = "qup03"; 1656 }; 1657 1658 qup_i2c4_default: qup-i2c4-default-state { 1659 pins = "gpio115", "gpio116"; 1660 function = "qup04_i2c"; 1661 }; 1662 1663 qup_i2c5_default: qup-i2c5-default-state { 1664 pins = "gpio25", "gpio26"; 1665 function = "qup05"; 1666 }; 1667 1668 qup_i2c6_default: qup-i2c6-default-state { 1669 pins = "gpio59", "gpio60"; 1670 function = "qup10"; 1671 }; 1672 1673 qup_i2c7_default: qup-i2c7-default-state { 1674 pins = "gpio6", "gpio7"; 1675 function = "qup11_i2c"; 1676 }; 1677 1678 qup_i2c8_default: qup-i2c8-default-state { 1679 pins = "gpio42", "gpio43"; 1680 function = "qup12"; 1681 }; 1682 1683 qup_i2c9_default: qup-i2c9-default-state { 1684 pins = "gpio46", "gpio47"; 1685 function = "qup13_i2c"; 1686 }; 1687 1688 qup_i2c10_default: qup-i2c10-default-state { 1689 pins = "gpio86", "gpio87"; 1690 function = "qup14"; 1691 }; 1692 1693 qup_i2c11_default: qup-i2c11-default-state { 1694 pins = "gpio53", "gpio54"; 1695 function = "qup15"; 1696 }; 1697 1698 qup_spi0_spi: qup-spi0-spi-state { 1699 pins = "gpio34", "gpio35", "gpio36"; 1700 function = "qup00"; 1701 }; 1702 1703 qup_spi0_cs: qup-spi0-cs-state { 1704 pins = "gpio37"; 1705 function = "qup00"; 1706 }; 1707 1708 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1709 pins = "gpio37"; 1710 function = "gpio"; 1711 }; 1712 1713 qup_spi1_spi: qup-spi1-spi-state { 1714 pins = "gpio0", "gpio1", "gpio2"; 1715 function = "qup01"; 1716 }; 1717 1718 qup_spi1_cs: qup-spi1-cs-state { 1719 pins = "gpio3"; 1720 function = "qup01"; 1721 }; 1722 1723 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1724 pins = "gpio3"; 1725 function = "gpio"; 1726 }; 1727 1728 qup_spi3_spi: qup-spi3-spi-state { 1729 pins = "gpio38", "gpio39", "gpio40"; 1730 function = "qup03"; 1731 }; 1732 1733 qup_spi3_cs: qup-spi3-cs-state { 1734 pins = "gpio41"; 1735 function = "qup03"; 1736 }; 1737 1738 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1739 pins = "gpio41"; 1740 function = "gpio"; 1741 }; 1742 1743 qup_spi5_spi: qup-spi5-spi-state { 1744 pins = "gpio25", "gpio26", "gpio27"; 1745 function = "qup05"; 1746 }; 1747 1748 qup_spi5_cs: qup-spi5-cs-state { 1749 pins = "gpio28"; 1750 function = "qup05"; 1751 }; 1752 1753 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1754 pins = "gpio28"; 1755 function = "gpio"; 1756 }; 1757 1758 qup_spi6_spi: qup-spi6-spi-state { 1759 pins = "gpio59", "gpio60", "gpio61"; 1760 function = "qup10"; 1761 }; 1762 1763 qup_spi6_cs: qup-spi6-cs-state { 1764 pins = "gpio62"; 1765 function = "qup10"; 1766 }; 1767 1768 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1769 pins = "gpio62"; 1770 function = "gpio"; 1771 }; 1772 1773 qup_spi8_spi: qup-spi8-spi-state { 1774 pins = "gpio42", "gpio43", "gpio44"; 1775 function = "qup12"; 1776 }; 1777 1778 qup_spi8_cs: qup-spi8-cs-state { 1779 pins = "gpio45"; 1780 function = "qup12"; 1781 }; 1782 1783 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1784 pins = "gpio45"; 1785 function = "gpio"; 1786 }; 1787 1788 qup_spi10_spi: qup-spi10-spi-state { 1789 pins = "gpio86", "gpio87", "gpio88"; 1790 function = "qup14"; 1791 }; 1792 1793 qup_spi10_cs: qup-spi10-cs-state { 1794 pins = "gpio89"; 1795 function = "qup14"; 1796 }; 1797 1798 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1799 pins = "gpio89"; 1800 function = "gpio"; 1801 }; 1802 1803 qup_spi11_spi: qup-spi11-spi-state { 1804 pins = "gpio53", "gpio54", "gpio55"; 1805 function = "qup15"; 1806 }; 1807 1808 qup_spi11_cs: qup-spi11-cs-state { 1809 pins = "gpio56"; 1810 function = "qup15"; 1811 }; 1812 1813 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1814 pins = "gpio56"; 1815 function = "gpio"; 1816 }; 1817 1818 qup_uart0_default: qup-uart0-default-state { 1819 qup_uart0_cts: cts-pins { 1820 pins = "gpio34"; 1821 function = "qup00"; 1822 }; 1823 1824 qup_uart0_rts: rts-pins { 1825 pins = "gpio35"; 1826 function = "qup00"; 1827 }; 1828 1829 qup_uart0_tx: tx-pins { 1830 pins = "gpio36"; 1831 function = "qup00"; 1832 }; 1833 1834 qup_uart0_rx: rx-pins { 1835 pins = "gpio37"; 1836 function = "qup00"; 1837 }; 1838 }; 1839 1840 qup_uart1_default: qup-uart1-default-state { 1841 qup_uart1_cts: cts-pins { 1842 pins = "gpio0"; 1843 function = "qup01"; 1844 }; 1845 1846 qup_uart1_rts: rts-pins { 1847 pins = "gpio1"; 1848 function = "qup01"; 1849 }; 1850 1851 qup_uart1_tx: tx-pins { 1852 pins = "gpio2"; 1853 function = "qup01"; 1854 }; 1855 1856 qup_uart1_rx: rx-pins { 1857 pins = "gpio3"; 1858 function = "qup01"; 1859 }; 1860 }; 1861 1862 qup_uart2_default: qup-uart2-default-state { 1863 qup_uart2_tx: tx-pins { 1864 pins = "gpio15"; 1865 function = "qup02_uart"; 1866 }; 1867 1868 qup_uart2_rx: rx-pins { 1869 pins = "gpio16"; 1870 function = "qup02_uart"; 1871 }; 1872 }; 1873 1874 qup_uart3_default: qup-uart3-default-state { 1875 qup_uart3_cts: cts-pins { 1876 pins = "gpio38"; 1877 function = "qup03"; 1878 }; 1879 1880 qup_uart3_rts: rts-pins { 1881 pins = "gpio39"; 1882 function = "qup03"; 1883 }; 1884 1885 qup_uart3_tx: tx-pins { 1886 pins = "gpio40"; 1887 function = "qup03"; 1888 }; 1889 1890 qup_uart3_rx: rx-pins { 1891 pins = "gpio41"; 1892 function = "qup03"; 1893 }; 1894 }; 1895 1896 qup_uart4_default: qup-uart4-default-state { 1897 qup_uart4_tx: tx-pins { 1898 pins = "gpio115"; 1899 function = "qup04_uart"; 1900 }; 1901 1902 qup_uart4_rx: rx-pins { 1903 pins = "gpio116"; 1904 function = "qup04_uart"; 1905 }; 1906 }; 1907 1908 qup_uart5_default: qup-uart5-default-state { 1909 qup_uart5_cts: cts-pins { 1910 pins = "gpio25"; 1911 function = "qup05"; 1912 }; 1913 1914 qup_uart5_rts: rts-pins { 1915 pins = "gpio26"; 1916 function = "qup05"; 1917 }; 1918 1919 qup_uart5_tx: tx-pins { 1920 pins = "gpio27"; 1921 function = "qup05"; 1922 }; 1923 1924 qup_uart5_rx: rx-pins { 1925 pins = "gpio28"; 1926 function = "qup05"; 1927 }; 1928 }; 1929 1930 qup_uart6_default: qup-uart6-default-state { 1931 qup_uart6_cts: cts-pins { 1932 pins = "gpio59"; 1933 function = "qup10"; 1934 }; 1935 1936 qup_uart6_rts: rts-pins { 1937 pins = "gpio60"; 1938 function = "qup10"; 1939 }; 1940 1941 qup_uart6_tx: tx-pins { 1942 pins = "gpio61"; 1943 function = "qup10"; 1944 }; 1945 1946 qup_uart6_rx: rx-pins { 1947 pins = "gpio62"; 1948 function = "qup10"; 1949 }; 1950 }; 1951 1952 qup_uart7_default: qup-uart7-default-state { 1953 qup_uart7_tx: tx-pins { 1954 pins = "gpio6"; 1955 function = "qup11_uart"; 1956 }; 1957 1958 qup_uart7_rx: rx-pins { 1959 pins = "gpio7"; 1960 function = "qup11_uart"; 1961 }; 1962 }; 1963 1964 qup_uart8_default: qup-uart8-default-state { 1965 qup_uart8_tx: tx-pins { 1966 pins = "gpio44"; 1967 function = "qup12"; 1968 }; 1969 1970 qup_uart8_rx: rx-pins { 1971 pins = "gpio45"; 1972 function = "qup12"; 1973 }; 1974 }; 1975 1976 qup_uart9_default: qup-uart9-default-state { 1977 qup_uart9_tx: tx-pins { 1978 pins = "gpio46"; 1979 function = "qup13_uart"; 1980 }; 1981 1982 qup_uart9_rx: rx-pins { 1983 pins = "gpio47"; 1984 function = "qup13_uart"; 1985 }; 1986 }; 1987 1988 qup_uart10_default: qup-uart10-default-state { 1989 qup_uart10_cts: cts-pins { 1990 pins = "gpio86"; 1991 function = "qup14"; 1992 }; 1993 1994 qup_uart10_rts: rts-pins { 1995 pins = "gpio87"; 1996 function = "qup14"; 1997 }; 1998 1999 qup_uart10_tx: tx-pins { 2000 pins = "gpio88"; 2001 function = "qup14"; 2002 }; 2003 2004 qup_uart10_rx: rx-pins { 2005 pins = "gpio89"; 2006 function = "qup14"; 2007 }; 2008 }; 2009 2010 qup_uart11_default: qup-uart11-default-state { 2011 qup_uart11_cts: cts-pins { 2012 pins = "gpio53"; 2013 function = "qup15"; 2014 }; 2015 2016 qup_uart11_rts: rts-pins { 2017 pins = "gpio54"; 2018 function = "qup15"; 2019 }; 2020 2021 qup_uart11_tx: tx-pins { 2022 pins = "gpio55"; 2023 function = "qup15"; 2024 }; 2025 2026 qup_uart11_rx: rx-pins { 2027 pins = "gpio56"; 2028 function = "qup15"; 2029 }; 2030 }; 2031 2032 sec_mi2s_active: sec-mi2s-active-state { 2033 pins = "gpio49", "gpio50", "gpio51"; 2034 function = "mi2s_1"; 2035 }; 2036 2037 pri_mi2s_active: pri-mi2s-active-state { 2038 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 2039 function = "mi2s_0"; 2040 }; 2041 2042 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 2043 pins = "gpio57"; 2044 function = "lpass_ext"; 2045 }; 2046 }; 2047 2048 remoteproc_mpss: remoteproc@4080000 { 2049 compatible = "qcom,sc7180-mpss-pas"; 2050 reg = <0 0x04080000 0 0x4040>; 2051 2052 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2053 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2054 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2055 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2056 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2057 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2058 interrupt-names = "wdog", "fatal", "ready", "handover", 2059 "stop-ack", "shutdown-ack"; 2060 2061 clocks = <&rpmhcc RPMH_CXO_CLK>; 2062 clock-names = "xo"; 2063 2064 power-domains = <&rpmhpd SC7180_CX>, 2065 <&rpmhpd SC7180_MX>, 2066 <&rpmhpd SC7180_MSS>; 2067 power-domain-names = "cx", "mx", "mss"; 2068 2069 memory-region = <&mpss_mem>; 2070 2071 qcom,qmp = <&aoss_qmp>; 2072 2073 qcom,smem-states = <&modem_smp2p_out 0>; 2074 qcom,smem-state-names = "stop"; 2075 2076 status = "disabled"; 2077 2078 glink-edge { 2079 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2080 label = "modem"; 2081 qcom,remote-pid = <1>; 2082 mboxes = <&apss_shared 12>; 2083 }; 2084 }; 2085 2086 gpu: gpu@5000000 { 2087 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2088 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2089 <0 0x05061000 0 0x800>; 2090 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2091 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2092 iommus = <&adreno_smmu 0>; 2093 operating-points-v2 = <&gpu_opp_table>; 2094 qcom,gmu = <&gmu>; 2095 2096 #cooling-cells = <2>; 2097 2098 nvmem-cells = <&gpu_speed_bin>; 2099 nvmem-cell-names = "speed_bin"; 2100 2101 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2102 interconnect-names = "gfx-mem"; 2103 2104 gpu_opp_table: opp-table { 2105 compatible = "operating-points-v2"; 2106 2107 opp-825000000 { 2108 opp-hz = /bits/ 64 <825000000>; 2109 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2110 opp-peak-kBps = <8532000>; 2111 opp-supported-hw = <0x04>; 2112 }; 2113 2114 opp-800000000 { 2115 opp-hz = /bits/ 64 <800000000>; 2116 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2117 opp-peak-kBps = <8532000>; 2118 opp-supported-hw = <0x07>; 2119 }; 2120 2121 opp-650000000 { 2122 opp-hz = /bits/ 64 <650000000>; 2123 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2124 opp-peak-kBps = <7216000>; 2125 opp-supported-hw = <0x07>; 2126 }; 2127 2128 opp-565000000 { 2129 opp-hz = /bits/ 64 <565000000>; 2130 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2131 opp-peak-kBps = <5412000>; 2132 opp-supported-hw = <0x07>; 2133 }; 2134 2135 opp-430000000 { 2136 opp-hz = /bits/ 64 <430000000>; 2137 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2138 opp-peak-kBps = <5412000>; 2139 opp-supported-hw = <0x07>; 2140 }; 2141 2142 opp-355000000 { 2143 opp-hz = /bits/ 64 <355000000>; 2144 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2145 opp-peak-kBps = <3072000>; 2146 opp-supported-hw = <0x07>; 2147 }; 2148 2149 opp-267000000 { 2150 opp-hz = /bits/ 64 <267000000>; 2151 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2152 opp-peak-kBps = <3072000>; 2153 opp-supported-hw = <0x07>; 2154 }; 2155 2156 opp-180000000 { 2157 opp-hz = /bits/ 64 <180000000>; 2158 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2159 opp-peak-kBps = <1804000>; 2160 opp-supported-hw = <0x07>; 2161 }; 2162 }; 2163 }; 2164 2165 adreno_smmu: iommu@5040000 { 2166 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2167 reg = <0 0x05040000 0 0x10000>; 2168 #iommu-cells = <1>; 2169 #global-interrupts = <2>; 2170 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2180 2181 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2182 <&gcc GCC_GPU_CFG_AHB_CLK>; 2183 clock-names = "bus", "iface"; 2184 2185 power-domains = <&gpucc CX_GDSC>; 2186 }; 2187 2188 gmu: gmu@506a000 { 2189 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2190 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2191 <0 0x0b490000 0 0x10000>; 2192 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2193 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2195 interrupt-names = "hfi", "gmu"; 2196 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2197 <&gpucc GPU_CC_CXO_CLK>, 2198 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2199 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2200 clock-names = "gmu", "cxo", "axi", "memnoc"; 2201 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2202 power-domain-names = "cx", "gx"; 2203 iommus = <&adreno_smmu 5>; 2204 operating-points-v2 = <&gmu_opp_table>; 2205 2206 gmu_opp_table: opp-table { 2207 compatible = "operating-points-v2"; 2208 2209 opp-200000000 { 2210 opp-hz = /bits/ 64 <200000000>; 2211 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2212 }; 2213 }; 2214 }; 2215 2216 gpucc: clock-controller@5090000 { 2217 compatible = "qcom,sc7180-gpucc"; 2218 reg = <0 0x05090000 0 0x9000>; 2219 clocks = <&rpmhcc RPMH_CXO_CLK>, 2220 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2221 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2222 clock-names = "bi_tcxo", 2223 "gcc_gpu_gpll0_clk_src", 2224 "gcc_gpu_gpll0_div_clk_src"; 2225 #clock-cells = <1>; 2226 #reset-cells = <1>; 2227 #power-domain-cells = <1>; 2228 }; 2229 2230 dma@10a2000 { 2231 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2232 reg = <0x0 0x010a2000 0x0 0x1000>, 2233 <0x0 0x010ae000 0x0 0x2000>; 2234 }; 2235 2236 stm@6002000 { 2237 compatible = "arm,coresight-stm", "arm,primecell"; 2238 reg = <0 0x06002000 0 0x1000>, 2239 <0 0x16280000 0 0x180000>; 2240 reg-names = "stm-base", "stm-stimulus-base"; 2241 2242 clocks = <&aoss_qmp>; 2243 clock-names = "apb_pclk"; 2244 2245 out-ports { 2246 port { 2247 stm_out: endpoint { 2248 remote-endpoint = <&funnel0_in7>; 2249 }; 2250 }; 2251 }; 2252 }; 2253 2254 funnel@6041000 { 2255 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2256 reg = <0 0x06041000 0 0x1000>; 2257 2258 clocks = <&aoss_qmp>; 2259 clock-names = "apb_pclk"; 2260 2261 out-ports { 2262 port { 2263 funnel0_out: endpoint { 2264 remote-endpoint = <&merge_funnel_in0>; 2265 }; 2266 }; 2267 }; 2268 2269 in-ports { 2270 #address-cells = <1>; 2271 #size-cells = <0>; 2272 2273 port@7 { 2274 reg = <7>; 2275 funnel0_in7: endpoint { 2276 remote-endpoint = <&stm_out>; 2277 }; 2278 }; 2279 }; 2280 }; 2281 2282 funnel@6042000 { 2283 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2284 reg = <0 0x06042000 0 0x1000>; 2285 2286 clocks = <&aoss_qmp>; 2287 clock-names = "apb_pclk"; 2288 2289 out-ports { 2290 port { 2291 funnel1_out: endpoint { 2292 remote-endpoint = <&merge_funnel_in1>; 2293 }; 2294 }; 2295 }; 2296 2297 in-ports { 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 2301 port@4 { 2302 reg = <4>; 2303 funnel1_in4: endpoint { 2304 remote-endpoint = <&apss_merge_funnel_out>; 2305 }; 2306 }; 2307 }; 2308 }; 2309 2310 funnel@6045000 { 2311 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2312 reg = <0 0x06045000 0 0x1000>; 2313 2314 clocks = <&aoss_qmp>; 2315 clock-names = "apb_pclk"; 2316 2317 out-ports { 2318 port { 2319 merge_funnel_out: endpoint { 2320 remote-endpoint = <&swao_funnel_in>; 2321 }; 2322 }; 2323 }; 2324 2325 in-ports { 2326 #address-cells = <1>; 2327 #size-cells = <0>; 2328 2329 port@0 { 2330 reg = <0>; 2331 merge_funnel_in0: endpoint { 2332 remote-endpoint = <&funnel0_out>; 2333 }; 2334 }; 2335 2336 port@1 { 2337 reg = <1>; 2338 merge_funnel_in1: endpoint { 2339 remote-endpoint = <&funnel1_out>; 2340 }; 2341 }; 2342 }; 2343 }; 2344 2345 replicator@6046000 { 2346 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2347 reg = <0 0x06046000 0 0x1000>; 2348 2349 clocks = <&aoss_qmp>; 2350 clock-names = "apb_pclk"; 2351 2352 out-ports { 2353 port { 2354 replicator_out: endpoint { 2355 remote-endpoint = <&etr_in>; 2356 }; 2357 }; 2358 }; 2359 2360 in-ports { 2361 port { 2362 replicator_in: endpoint { 2363 remote-endpoint = <&swao_replicator_out>; 2364 }; 2365 }; 2366 }; 2367 }; 2368 2369 etr@6048000 { 2370 compatible = "arm,coresight-tmc", "arm,primecell"; 2371 reg = <0 0x06048000 0 0x1000>; 2372 iommus = <&apps_smmu 0x04a0 0x20>; 2373 2374 clocks = <&aoss_qmp>; 2375 clock-names = "apb_pclk"; 2376 arm,scatter-gather; 2377 2378 in-ports { 2379 port { 2380 etr_in: endpoint { 2381 remote-endpoint = <&replicator_out>; 2382 }; 2383 }; 2384 }; 2385 }; 2386 2387 funnel@6b04000 { 2388 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2389 reg = <0 0x06b04000 0 0x1000>; 2390 2391 clocks = <&aoss_qmp>; 2392 clock-names = "apb_pclk"; 2393 2394 out-ports { 2395 port { 2396 swao_funnel_out: endpoint { 2397 remote-endpoint = <&etf_in>; 2398 }; 2399 }; 2400 }; 2401 2402 in-ports { 2403 #address-cells = <1>; 2404 #size-cells = <0>; 2405 2406 port@7 { 2407 reg = <7>; 2408 swao_funnel_in: endpoint { 2409 remote-endpoint = <&merge_funnel_out>; 2410 }; 2411 }; 2412 }; 2413 }; 2414 2415 etf@6b05000 { 2416 compatible = "arm,coresight-tmc", "arm,primecell"; 2417 reg = <0 0x06b05000 0 0x1000>; 2418 2419 clocks = <&aoss_qmp>; 2420 clock-names = "apb_pclk"; 2421 2422 out-ports { 2423 port { 2424 etf_out: endpoint { 2425 remote-endpoint = <&swao_replicator_in>; 2426 }; 2427 }; 2428 }; 2429 2430 in-ports { 2431 port { 2432 etf_in: endpoint { 2433 remote-endpoint = <&swao_funnel_out>; 2434 }; 2435 }; 2436 }; 2437 }; 2438 2439 replicator@6b06000 { 2440 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2441 reg = <0 0x06b06000 0 0x1000>; 2442 2443 clocks = <&aoss_qmp>; 2444 clock-names = "apb_pclk"; 2445 qcom,replicator-loses-context; 2446 2447 out-ports { 2448 port { 2449 swao_replicator_out: endpoint { 2450 remote-endpoint = <&replicator_in>; 2451 }; 2452 }; 2453 }; 2454 2455 in-ports { 2456 port { 2457 swao_replicator_in: endpoint { 2458 remote-endpoint = <&etf_out>; 2459 }; 2460 }; 2461 }; 2462 }; 2463 2464 etm@7040000 { 2465 compatible = "arm,coresight-etm4x", "arm,primecell"; 2466 reg = <0 0x07040000 0 0x1000>; 2467 2468 cpu = <&CPU0>; 2469 2470 clocks = <&aoss_qmp>; 2471 clock-names = "apb_pclk"; 2472 arm,coresight-loses-context-with-cpu; 2473 qcom,skip-power-up; 2474 2475 out-ports { 2476 port { 2477 etm0_out: endpoint { 2478 remote-endpoint = <&apss_funnel_in0>; 2479 }; 2480 }; 2481 }; 2482 }; 2483 2484 etm@7140000 { 2485 compatible = "arm,coresight-etm4x", "arm,primecell"; 2486 reg = <0 0x07140000 0 0x1000>; 2487 2488 cpu = <&CPU1>; 2489 2490 clocks = <&aoss_qmp>; 2491 clock-names = "apb_pclk"; 2492 arm,coresight-loses-context-with-cpu; 2493 qcom,skip-power-up; 2494 2495 out-ports { 2496 port { 2497 etm1_out: endpoint { 2498 remote-endpoint = <&apss_funnel_in1>; 2499 }; 2500 }; 2501 }; 2502 }; 2503 2504 etm@7240000 { 2505 compatible = "arm,coresight-etm4x", "arm,primecell"; 2506 reg = <0 0x07240000 0 0x1000>; 2507 2508 cpu = <&CPU2>; 2509 2510 clocks = <&aoss_qmp>; 2511 clock-names = "apb_pclk"; 2512 arm,coresight-loses-context-with-cpu; 2513 qcom,skip-power-up; 2514 2515 out-ports { 2516 port { 2517 etm2_out: endpoint { 2518 remote-endpoint = <&apss_funnel_in2>; 2519 }; 2520 }; 2521 }; 2522 }; 2523 2524 etm@7340000 { 2525 compatible = "arm,coresight-etm4x", "arm,primecell"; 2526 reg = <0 0x07340000 0 0x1000>; 2527 2528 cpu = <&CPU3>; 2529 2530 clocks = <&aoss_qmp>; 2531 clock-names = "apb_pclk"; 2532 arm,coresight-loses-context-with-cpu; 2533 qcom,skip-power-up; 2534 2535 out-ports { 2536 port { 2537 etm3_out: endpoint { 2538 remote-endpoint = <&apss_funnel_in3>; 2539 }; 2540 }; 2541 }; 2542 }; 2543 2544 etm@7440000 { 2545 compatible = "arm,coresight-etm4x", "arm,primecell"; 2546 reg = <0 0x07440000 0 0x1000>; 2547 2548 cpu = <&CPU4>; 2549 2550 clocks = <&aoss_qmp>; 2551 clock-names = "apb_pclk"; 2552 arm,coresight-loses-context-with-cpu; 2553 qcom,skip-power-up; 2554 2555 out-ports { 2556 port { 2557 etm4_out: endpoint { 2558 remote-endpoint = <&apss_funnel_in4>; 2559 }; 2560 }; 2561 }; 2562 }; 2563 2564 etm@7540000 { 2565 compatible = "arm,coresight-etm4x", "arm,primecell"; 2566 reg = <0 0x07540000 0 0x1000>; 2567 2568 cpu = <&CPU5>; 2569 2570 clocks = <&aoss_qmp>; 2571 clock-names = "apb_pclk"; 2572 arm,coresight-loses-context-with-cpu; 2573 qcom,skip-power-up; 2574 2575 out-ports { 2576 port { 2577 etm5_out: endpoint { 2578 remote-endpoint = <&apss_funnel_in5>; 2579 }; 2580 }; 2581 }; 2582 }; 2583 2584 etm@7640000 { 2585 compatible = "arm,coresight-etm4x", "arm,primecell"; 2586 reg = <0 0x07640000 0 0x1000>; 2587 2588 cpu = <&CPU6>; 2589 2590 clocks = <&aoss_qmp>; 2591 clock-names = "apb_pclk"; 2592 arm,coresight-loses-context-with-cpu; 2593 qcom,skip-power-up; 2594 2595 out-ports { 2596 port { 2597 etm6_out: endpoint { 2598 remote-endpoint = <&apss_funnel_in6>; 2599 }; 2600 }; 2601 }; 2602 }; 2603 2604 etm@7740000 { 2605 compatible = "arm,coresight-etm4x", "arm,primecell"; 2606 reg = <0 0x07740000 0 0x1000>; 2607 2608 cpu = <&CPU7>; 2609 2610 clocks = <&aoss_qmp>; 2611 clock-names = "apb_pclk"; 2612 arm,coresight-loses-context-with-cpu; 2613 qcom,skip-power-up; 2614 2615 out-ports { 2616 port { 2617 etm7_out: endpoint { 2618 remote-endpoint = <&apss_funnel_in7>; 2619 }; 2620 }; 2621 }; 2622 }; 2623 2624 funnel@7800000 { /* APSS Funnel */ 2625 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2626 reg = <0 0x07800000 0 0x1000>; 2627 2628 clocks = <&aoss_qmp>; 2629 clock-names = "apb_pclk"; 2630 2631 out-ports { 2632 port { 2633 apss_funnel_out: endpoint { 2634 remote-endpoint = <&apss_merge_funnel_in>; 2635 }; 2636 }; 2637 }; 2638 2639 in-ports { 2640 #address-cells = <1>; 2641 #size-cells = <0>; 2642 2643 port@0 { 2644 reg = <0>; 2645 apss_funnel_in0: endpoint { 2646 remote-endpoint = <&etm0_out>; 2647 }; 2648 }; 2649 2650 port@1 { 2651 reg = <1>; 2652 apss_funnel_in1: endpoint { 2653 remote-endpoint = <&etm1_out>; 2654 }; 2655 }; 2656 2657 port@2 { 2658 reg = <2>; 2659 apss_funnel_in2: endpoint { 2660 remote-endpoint = <&etm2_out>; 2661 }; 2662 }; 2663 2664 port@3 { 2665 reg = <3>; 2666 apss_funnel_in3: endpoint { 2667 remote-endpoint = <&etm3_out>; 2668 }; 2669 }; 2670 2671 port@4 { 2672 reg = <4>; 2673 apss_funnel_in4: endpoint { 2674 remote-endpoint = <&etm4_out>; 2675 }; 2676 }; 2677 2678 port@5 { 2679 reg = <5>; 2680 apss_funnel_in5: endpoint { 2681 remote-endpoint = <&etm5_out>; 2682 }; 2683 }; 2684 2685 port@6 { 2686 reg = <6>; 2687 apss_funnel_in6: endpoint { 2688 remote-endpoint = <&etm6_out>; 2689 }; 2690 }; 2691 2692 port@7 { 2693 reg = <7>; 2694 apss_funnel_in7: endpoint { 2695 remote-endpoint = <&etm7_out>; 2696 }; 2697 }; 2698 }; 2699 }; 2700 2701 funnel@7810000 { 2702 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2703 reg = <0 0x07810000 0 0x1000>; 2704 2705 clocks = <&aoss_qmp>; 2706 clock-names = "apb_pclk"; 2707 2708 out-ports { 2709 port { 2710 apss_merge_funnel_out: endpoint { 2711 remote-endpoint = <&funnel1_in4>; 2712 }; 2713 }; 2714 }; 2715 2716 in-ports { 2717 port { 2718 apss_merge_funnel_in: endpoint { 2719 remote-endpoint = <&apss_funnel_out>; 2720 }; 2721 }; 2722 }; 2723 }; 2724 2725 sdhc_2: mmc@8804000 { 2726 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2727 reg = <0 0x08804000 0 0x1000>; 2728 2729 iommus = <&apps_smmu 0x80 0>; 2730 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2731 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2732 interrupt-names = "hc_irq", "pwr_irq"; 2733 2734 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2735 <&gcc GCC_SDCC2_APPS_CLK>, 2736 <&rpmhcc RPMH_CXO_CLK>; 2737 clock-names = "iface", "core", "xo"; 2738 2739 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2740 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2741 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2742 power-domains = <&rpmhpd SC7180_CX>; 2743 operating-points-v2 = <&sdhc2_opp_table>; 2744 2745 bus-width = <4>; 2746 2747 status = "disabled"; 2748 2749 sdhc2_opp_table: opp-table { 2750 compatible = "operating-points-v2"; 2751 2752 opp-100000000 { 2753 opp-hz = /bits/ 64 <100000000>; 2754 required-opps = <&rpmhpd_opp_low_svs>; 2755 opp-peak-kBps = <1800000 600000>; 2756 opp-avg-kBps = <100000 0>; 2757 }; 2758 2759 opp-202000000 { 2760 opp-hz = /bits/ 64 <202000000>; 2761 required-opps = <&rpmhpd_opp_nom>; 2762 opp-peak-kBps = <5400000 1600000>; 2763 opp-avg-kBps = <200000 0>; 2764 }; 2765 }; 2766 }; 2767 2768 qspi: spi@88dc000 { 2769 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2770 reg = <0 0x088dc000 0 0x600>; 2771 iommus = <&apps_smmu 0x20 0x0>; 2772 #address-cells = <1>; 2773 #size-cells = <0>; 2774 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2775 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2776 <&gcc GCC_QSPI_CORE_CLK>; 2777 clock-names = "iface", "core"; 2778 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2779 &config_noc SLAVE_QSPI_0 0>; 2780 interconnect-names = "qspi-config"; 2781 power-domains = <&rpmhpd SC7180_CX>; 2782 operating-points-v2 = <&qspi_opp_table>; 2783 status = "disabled"; 2784 }; 2785 2786 usb_1_hsphy: phy@88e3000 { 2787 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2788 reg = <0 0x088e3000 0 0x400>; 2789 status = "disabled"; 2790 #phy-cells = <0>; 2791 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2792 <&rpmhcc RPMH_CXO_CLK>; 2793 clock-names = "cfg_ahb", "ref"; 2794 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2795 2796 nvmem-cells = <&qusb2p_hstx_trim>; 2797 }; 2798 2799 usb_1_qmpphy: phy@88e8000 { 2800 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2801 reg = <0 0x088e8000 0 0x3000>; 2802 status = "disabled"; 2803 2804 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2805 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2806 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2807 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 2808 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 2809 clock-names = "aux", 2810 "ref", 2811 "com_aux", 2812 "usb3_pipe", 2813 "cfg_ahb"; 2814 2815 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2816 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2817 reset-names = "phy", "common"; 2818 2819 #clock-cells = <1>; 2820 #phy-cells = <1>; 2821 }; 2822 2823 pmu@90b6300 { 2824 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon"; 2825 reg = <0 0x090b6300 0 0x600>; 2826 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2827 2828 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2829 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 2830 operating-points-v2 = <&cpu_bwmon_opp_table>; 2831 2832 cpu_bwmon_opp_table: opp-table { 2833 compatible = "operating-points-v2"; 2834 2835 opp-0 { 2836 opp-peak-kBps = <2288000>; 2837 }; 2838 2839 opp-1 { 2840 opp-peak-kBps = <4577000>; 2841 }; 2842 2843 opp-2 { 2844 opp-peak-kBps = <7110000>; 2845 }; 2846 2847 opp-3 { 2848 opp-peak-kBps = <9155000>; 2849 }; 2850 2851 opp-4 { 2852 opp-peak-kBps = <12298000>; 2853 }; 2854 2855 opp-5 { 2856 opp-peak-kBps = <14236000>; 2857 }; 2858 }; 2859 }; 2860 2861 pmu@90cd000 { 2862 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2863 reg = <0 0x090cd000 0 0x1000>; 2864 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 2865 2866 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 2867 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2868 operating-points-v2 = <&llcc_bwmon_opp_table>; 2869 2870 llcc_bwmon_opp_table: opp-table { 2871 compatible = "operating-points-v2"; 2872 2873 opp-0 { 2874 opp-peak-kBps = <1144000>; 2875 }; 2876 2877 opp-1 { 2878 opp-peak-kBps = <1720000>; 2879 }; 2880 2881 opp-2 { 2882 opp-peak-kBps = <2086000>; 2883 }; 2884 2885 opp-3 { 2886 opp-peak-kBps = <2929000>; 2887 }; 2888 2889 opp-4 { 2890 opp-peak-kBps = <3879000>; 2891 }; 2892 2893 opp-5 { 2894 opp-peak-kBps = <5931000>; 2895 }; 2896 2897 opp-6 { 2898 opp-peak-kBps = <6881000>; 2899 }; 2900 2901 opp-7 { 2902 opp-peak-kBps = <8137000>; 2903 }; 2904 }; 2905 }; 2906 2907 dc_noc: interconnect@9160000 { 2908 compatible = "qcom,sc7180-dc-noc"; 2909 reg = <0 0x09160000 0 0x03200>; 2910 #interconnect-cells = <2>; 2911 qcom,bcm-voters = <&apps_bcm_voter>; 2912 }; 2913 2914 system-cache-controller@9200000 { 2915 compatible = "qcom,sc7180-llcc"; 2916 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2917 reg-names = "llcc0_base", "llcc_broadcast_base"; 2918 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2919 }; 2920 2921 gem_noc: interconnect@9680000 { 2922 compatible = "qcom,sc7180-gem-noc"; 2923 reg = <0 0x09680000 0 0x3e200>; 2924 #interconnect-cells = <2>; 2925 qcom,bcm-voters = <&apps_bcm_voter>; 2926 }; 2927 2928 npu_noc: interconnect@9990000 { 2929 compatible = "qcom,sc7180-npu-noc"; 2930 reg = <0 0x09990000 0 0x1600>; 2931 #interconnect-cells = <2>; 2932 qcom,bcm-voters = <&apps_bcm_voter>; 2933 }; 2934 2935 usb_1: usb@a6f8800 { 2936 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2937 reg = <0 0x0a6f8800 0 0x400>; 2938 status = "disabled"; 2939 #address-cells = <2>; 2940 #size-cells = <2>; 2941 ranges; 2942 dma-ranges; 2943 2944 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2945 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2946 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2947 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2948 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2949 clock-names = "cfg_noc", 2950 "core", 2951 "iface", 2952 "sleep", 2953 "mock_utmi"; 2954 2955 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2956 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2957 assigned-clock-rates = <19200000>, <150000000>; 2958 2959 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2960 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2961 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2962 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2963 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2964 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2965 2966 power-domains = <&gcc USB30_PRIM_GDSC>; 2967 required-opps = <&rpmhpd_opp_nom>; 2968 2969 resets = <&gcc GCC_USB30_PRIM_BCR>; 2970 2971 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2973 interconnect-names = "usb-ddr", "apps-usb"; 2974 2975 wakeup-source; 2976 2977 usb_1_dwc3: usb@a600000 { 2978 compatible = "snps,dwc3"; 2979 reg = <0 0x0a600000 0 0xe000>; 2980 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2981 iommus = <&apps_smmu 0x540 0>; 2982 snps,dis_u2_susphy_quirk; 2983 snps,dis_enblslpm_quirk; 2984 snps,parkmode-disable-ss-quirk; 2985 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2986 phy-names = "usb2-phy", "usb3-phy"; 2987 maximum-speed = "super-speed"; 2988 }; 2989 }; 2990 2991 venus: video-codec@aa00000 { 2992 compatible = "qcom,sc7180-venus"; 2993 reg = <0 0x0aa00000 0 0xff000>; 2994 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2995 power-domains = <&videocc VENUS_GDSC>, 2996 <&videocc VCODEC0_GDSC>, 2997 <&rpmhpd SC7180_CX>; 2998 power-domain-names = "venus", "vcodec0", "cx"; 2999 operating-points-v2 = <&venus_opp_table>; 3000 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3001 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3002 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3003 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3004 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3005 clock-names = "core", "iface", "bus", 3006 "vcodec0_core", "vcodec0_bus"; 3007 iommus = <&apps_smmu 0x0c00 0x60>; 3008 memory-region = <&venus_mem>; 3009 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 3010 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3011 interconnect-names = "video-mem", "cpu-cfg"; 3012 3013 video-decoder { 3014 compatible = "venus-decoder"; 3015 }; 3016 3017 video-encoder { 3018 compatible = "venus-encoder"; 3019 }; 3020 3021 venus_opp_table: opp-table { 3022 compatible = "operating-points-v2"; 3023 3024 opp-150000000 { 3025 opp-hz = /bits/ 64 <150000000>; 3026 required-opps = <&rpmhpd_opp_low_svs>; 3027 }; 3028 3029 opp-270000000 { 3030 opp-hz = /bits/ 64 <270000000>; 3031 required-opps = <&rpmhpd_opp_svs>; 3032 }; 3033 3034 opp-340000000 { 3035 opp-hz = /bits/ 64 <340000000>; 3036 required-opps = <&rpmhpd_opp_svs_l1>; 3037 }; 3038 3039 opp-434000000 { 3040 opp-hz = /bits/ 64 <434000000>; 3041 required-opps = <&rpmhpd_opp_nom>; 3042 }; 3043 3044 opp-500000097 { 3045 opp-hz = /bits/ 64 <500000097>; 3046 required-opps = <&rpmhpd_opp_turbo>; 3047 }; 3048 }; 3049 }; 3050 3051 videocc: clock-controller@ab00000 { 3052 compatible = "qcom,sc7180-videocc"; 3053 reg = <0 0x0ab00000 0 0x10000>; 3054 clocks = <&rpmhcc RPMH_CXO_CLK>; 3055 clock-names = "bi_tcxo"; 3056 #clock-cells = <1>; 3057 #reset-cells = <1>; 3058 #power-domain-cells = <1>; 3059 }; 3060 3061 camnoc_virt: interconnect@ac00000 { 3062 compatible = "qcom,sc7180-camnoc-virt"; 3063 reg = <0 0x0ac00000 0 0x1000>; 3064 #interconnect-cells = <2>; 3065 qcom,bcm-voters = <&apps_bcm_voter>; 3066 }; 3067 3068 camcc: clock-controller@ad00000 { 3069 compatible = "qcom,sc7180-camcc"; 3070 reg = <0 0x0ad00000 0 0x10000>; 3071 clocks = <&rpmhcc RPMH_CXO_CLK>, 3072 <&gcc GCC_CAMERA_AHB_CLK>, 3073 <&gcc GCC_CAMERA_XO_CLK>; 3074 clock-names = "bi_tcxo", "iface", "xo"; 3075 #clock-cells = <1>; 3076 #reset-cells = <1>; 3077 #power-domain-cells = <1>; 3078 }; 3079 3080 mdss: display-subsystem@ae00000 { 3081 compatible = "qcom,sc7180-mdss"; 3082 reg = <0 0x0ae00000 0 0x1000>; 3083 reg-names = "mdss"; 3084 3085 power-domains = <&dispcc MDSS_GDSC>; 3086 3087 clocks = <&gcc GCC_DISP_AHB_CLK>, 3088 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3089 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3090 clock-names = "iface", "ahb", "core"; 3091 3092 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3093 interrupt-controller; 3094 #interrupt-cells = <1>; 3095 3096 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3097 interconnect-names = "mdp0-mem"; 3098 3099 iommus = <&apps_smmu 0x800 0x2>; 3100 3101 #address-cells = <2>; 3102 #size-cells = <2>; 3103 ranges; 3104 3105 status = "disabled"; 3106 3107 mdp: display-controller@ae01000 { 3108 compatible = "qcom,sc7180-dpu"; 3109 reg = <0 0x0ae01000 0 0x8f000>, 3110 <0 0x0aeb0000 0 0x2008>; 3111 reg-names = "mdp", "vbif"; 3112 3113 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3114 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3115 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3116 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3117 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3118 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3119 clock-names = "bus", "iface", "rot", "lut", "core", 3120 "vsync"; 3121 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3122 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3123 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3124 assigned-clock-rates = <19200000>, 3125 <19200000>, 3126 <19200000>; 3127 operating-points-v2 = <&mdp_opp_table>; 3128 power-domains = <&rpmhpd SC7180_CX>; 3129 3130 interrupt-parent = <&mdss>; 3131 interrupts = <0>; 3132 3133 ports { 3134 #address-cells = <1>; 3135 #size-cells = <0>; 3136 3137 port@0 { 3138 reg = <0>; 3139 dpu_intf1_out: endpoint { 3140 remote-endpoint = <&mdss_dsi0_in>; 3141 }; 3142 }; 3143 3144 port@2 { 3145 reg = <2>; 3146 dpu_intf0_out: endpoint { 3147 remote-endpoint = <&dp_in>; 3148 }; 3149 }; 3150 }; 3151 3152 mdp_opp_table: opp-table { 3153 compatible = "operating-points-v2"; 3154 3155 opp-200000000 { 3156 opp-hz = /bits/ 64 <200000000>; 3157 required-opps = <&rpmhpd_opp_low_svs>; 3158 }; 3159 3160 opp-300000000 { 3161 opp-hz = /bits/ 64 <300000000>; 3162 required-opps = <&rpmhpd_opp_svs>; 3163 }; 3164 3165 opp-345000000 { 3166 opp-hz = /bits/ 64 <345000000>; 3167 required-opps = <&rpmhpd_opp_svs_l1>; 3168 }; 3169 3170 opp-460000000 { 3171 opp-hz = /bits/ 64 <460000000>; 3172 required-opps = <&rpmhpd_opp_nom>; 3173 }; 3174 }; 3175 }; 3176 3177 mdss_dsi0: dsi@ae94000 { 3178 compatible = "qcom,sc7180-dsi-ctrl", 3179 "qcom,mdss-dsi-ctrl"; 3180 reg = <0 0x0ae94000 0 0x400>; 3181 reg-names = "dsi_ctrl"; 3182 3183 interrupt-parent = <&mdss>; 3184 interrupts = <4>; 3185 3186 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3187 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3188 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3189 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3190 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3191 <&gcc GCC_DISP_HF_AXI_CLK>; 3192 clock-names = "byte", 3193 "byte_intf", 3194 "pixel", 3195 "core", 3196 "iface", 3197 "bus"; 3198 3199 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3200 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3201 3202 operating-points-v2 = <&dsi_opp_table>; 3203 power-domains = <&rpmhpd SC7180_CX>; 3204 3205 phys = <&mdss_dsi0_phy>; 3206 3207 #address-cells = <1>; 3208 #size-cells = <0>; 3209 3210 status = "disabled"; 3211 3212 ports { 3213 #address-cells = <1>; 3214 #size-cells = <0>; 3215 3216 port@0 { 3217 reg = <0>; 3218 mdss_dsi0_in: endpoint { 3219 remote-endpoint = <&dpu_intf1_out>; 3220 }; 3221 }; 3222 3223 port@1 { 3224 reg = <1>; 3225 mdss_dsi0_out: endpoint { 3226 }; 3227 }; 3228 }; 3229 3230 dsi_opp_table: opp-table { 3231 compatible = "operating-points-v2"; 3232 3233 opp-187500000 { 3234 opp-hz = /bits/ 64 <187500000>; 3235 required-opps = <&rpmhpd_opp_low_svs>; 3236 }; 3237 3238 opp-300000000 { 3239 opp-hz = /bits/ 64 <300000000>; 3240 required-opps = <&rpmhpd_opp_svs>; 3241 }; 3242 3243 opp-358000000 { 3244 opp-hz = /bits/ 64 <358000000>; 3245 required-opps = <&rpmhpd_opp_svs_l1>; 3246 }; 3247 }; 3248 }; 3249 3250 mdss_dsi0_phy: phy@ae94400 { 3251 compatible = "qcom,dsi-phy-10nm"; 3252 reg = <0 0x0ae94400 0 0x200>, 3253 <0 0x0ae94600 0 0x280>, 3254 <0 0x0ae94a00 0 0x1e0>; 3255 reg-names = "dsi_phy", 3256 "dsi_phy_lane", 3257 "dsi_pll"; 3258 3259 #clock-cells = <1>; 3260 #phy-cells = <0>; 3261 3262 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3263 <&rpmhcc RPMH_CXO_CLK>; 3264 clock-names = "iface", "ref"; 3265 3266 status = "disabled"; 3267 }; 3268 3269 mdss_dp: displayport-controller@ae90000 { 3270 compatible = "qcom,sc7180-dp"; 3271 status = "disabled"; 3272 3273 reg = <0 0x0ae90000 0 0x200>, 3274 <0 0x0ae90200 0 0x200>, 3275 <0 0x0ae90400 0 0xc00>, 3276 <0 0x0ae91000 0 0x400>, 3277 <0 0x0ae91400 0 0x400>; 3278 3279 interrupt-parent = <&mdss>; 3280 interrupts = <12>; 3281 3282 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3283 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3284 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3285 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3286 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3287 clock-names = "core_iface", "core_aux", "ctrl_link", 3288 "ctrl_link_iface", "stream_pixel"; 3289 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3290 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3291 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3292 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3293 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3294 phy-names = "dp"; 3295 3296 operating-points-v2 = <&dp_opp_table>; 3297 power-domains = <&rpmhpd SC7180_CX>; 3298 3299 #sound-dai-cells = <0>; 3300 3301 ports { 3302 #address-cells = <1>; 3303 #size-cells = <0>; 3304 port@0 { 3305 reg = <0>; 3306 dp_in: endpoint { 3307 remote-endpoint = <&dpu_intf0_out>; 3308 }; 3309 }; 3310 3311 port@1 { 3312 reg = <1>; 3313 mdss_dp_out: endpoint { }; 3314 }; 3315 }; 3316 3317 dp_opp_table: opp-table { 3318 compatible = "operating-points-v2"; 3319 3320 opp-160000000 { 3321 opp-hz = /bits/ 64 <160000000>; 3322 required-opps = <&rpmhpd_opp_low_svs>; 3323 }; 3324 3325 opp-270000000 { 3326 opp-hz = /bits/ 64 <270000000>; 3327 required-opps = <&rpmhpd_opp_svs>; 3328 }; 3329 3330 opp-540000000 { 3331 opp-hz = /bits/ 64 <540000000>; 3332 required-opps = <&rpmhpd_opp_svs_l1>; 3333 }; 3334 3335 opp-810000000 { 3336 opp-hz = /bits/ 64 <810000000>; 3337 required-opps = <&rpmhpd_opp_nom>; 3338 }; 3339 }; 3340 }; 3341 }; 3342 3343 dispcc: clock-controller@af00000 { 3344 compatible = "qcom,sc7180-dispcc"; 3345 reg = <0 0x0af00000 0 0x200000>; 3346 clocks = <&rpmhcc RPMH_CXO_CLK>, 3347 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3348 <&mdss_dsi0_phy 0>, 3349 <&mdss_dsi0_phy 1>, 3350 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3351 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3352 clock-names = "bi_tcxo", 3353 "gcc_disp_gpll0_clk_src", 3354 "dsi0_phy_pll_out_byteclk", 3355 "dsi0_phy_pll_out_dsiclk", 3356 "dp_phy_pll_link_clk", 3357 "dp_phy_pll_vco_div_clk"; 3358 #clock-cells = <1>; 3359 #reset-cells = <1>; 3360 #power-domain-cells = <1>; 3361 }; 3362 3363 pdc: interrupt-controller@b220000 { 3364 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3365 reg = <0 0x0b220000 0 0x30000>; 3366 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3367 #interrupt-cells = <2>; 3368 interrupt-parent = <&intc>; 3369 interrupt-controller; 3370 }; 3371 3372 pdc_reset: reset-controller@b2e0000 { 3373 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3374 reg = <0 0x0b2e0000 0 0x20000>; 3375 #reset-cells = <1>; 3376 }; 3377 3378 tsens0: thermal-sensor@c263000 { 3379 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3380 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3381 <0 0x0c222000 0 0x1ff>; /* SROT */ 3382 #qcom,sensors = <15>; 3383 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3385 interrupt-names = "uplow","critical"; 3386 #thermal-sensor-cells = <1>; 3387 }; 3388 3389 tsens1: thermal-sensor@c265000 { 3390 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3391 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3392 <0 0x0c223000 0 0x1ff>; /* SROT */ 3393 #qcom,sensors = <10>; 3394 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3396 interrupt-names = "uplow","critical"; 3397 #thermal-sensor-cells = <1>; 3398 }; 3399 3400 aoss_reset: reset-controller@c2a0000 { 3401 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3402 reg = <0 0x0c2a0000 0 0x31000>; 3403 #reset-cells = <1>; 3404 }; 3405 3406 aoss_qmp: power-management@c300000 { 3407 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3408 reg = <0 0x0c300000 0 0x400>; 3409 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3410 mboxes = <&apss_shared 0>; 3411 3412 #clock-cells = <0>; 3413 }; 3414 3415 sram@c3f0000 { 3416 compatible = "qcom,rpmh-stats"; 3417 reg = <0 0x0c3f0000 0 0x400>; 3418 }; 3419 3420 spmi_bus: spmi@c440000 { 3421 compatible = "qcom,spmi-pmic-arb"; 3422 reg = <0 0x0c440000 0 0x1100>, 3423 <0 0x0c600000 0 0x2000000>, 3424 <0 0x0e600000 0 0x100000>, 3425 <0 0x0e700000 0 0xa0000>, 3426 <0 0x0c40a000 0 0x26000>; 3427 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3428 interrupt-names = "periph_irq"; 3429 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3430 qcom,ee = <0>; 3431 qcom,channel = <0>; 3432 #address-cells = <2>; 3433 #size-cells = <0>; 3434 interrupt-controller; 3435 #interrupt-cells = <4>; 3436 }; 3437 3438 sram@146aa000 { 3439 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3440 reg = <0 0x146aa000 0 0x2000>; 3441 3442 #address-cells = <1>; 3443 #size-cells = <1>; 3444 3445 ranges = <0 0 0x146aa000 0x2000>; 3446 3447 pil-reloc@94c { 3448 compatible = "qcom,pil-reloc-info"; 3449 reg = <0x94c 0xc8>; 3450 }; 3451 }; 3452 3453 apps_smmu: iommu@15000000 { 3454 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3455 reg = <0 0x15000000 0 0x100000>; 3456 #iommu-cells = <2>; 3457 #global-interrupts = <1>; 3458 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3539 }; 3540 3541 intc: interrupt-controller@17a00000 { 3542 compatible = "arm,gic-v3"; 3543 #address-cells = <2>; 3544 #size-cells = <2>; 3545 ranges; 3546 #interrupt-cells = <3>; 3547 interrupt-controller; 3548 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3549 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3550 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3551 3552 msi-controller@17a40000 { 3553 compatible = "arm,gic-v3-its"; 3554 msi-controller; 3555 #msi-cells = <1>; 3556 reg = <0 0x17a40000 0 0x20000>; 3557 status = "disabled"; 3558 }; 3559 }; 3560 3561 apss_shared: mailbox@17c00000 { 3562 compatible = "qcom,sc7180-apss-shared", 3563 "qcom,sdm845-apss-shared"; 3564 reg = <0 0x17c00000 0 0x10000>; 3565 #mbox-cells = <1>; 3566 }; 3567 3568 watchdog@17c10000 { 3569 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3570 reg = <0 0x17c10000 0 0x1000>; 3571 clocks = <&sleep_clk>; 3572 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3573 }; 3574 3575 timer@17c20000 { 3576 #address-cells = <1>; 3577 #size-cells = <1>; 3578 ranges = <0 0 0 0x20000000>; 3579 compatible = "arm,armv7-timer-mem"; 3580 reg = <0 0x17c20000 0 0x1000>; 3581 3582 frame@17c21000 { 3583 frame-number = <0>; 3584 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3586 reg = <0x17c21000 0x1000>, 3587 <0x17c22000 0x1000>; 3588 }; 3589 3590 frame@17c23000 { 3591 frame-number = <1>; 3592 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3593 reg = <0x17c23000 0x1000>; 3594 status = "disabled"; 3595 }; 3596 3597 frame@17c25000 { 3598 frame-number = <2>; 3599 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3600 reg = <0x17c25000 0x1000>; 3601 status = "disabled"; 3602 }; 3603 3604 frame@17c27000 { 3605 frame-number = <3>; 3606 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3607 reg = <0x17c27000 0x1000>; 3608 status = "disabled"; 3609 }; 3610 3611 frame@17c29000 { 3612 frame-number = <4>; 3613 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3614 reg = <0x17c29000 0x1000>; 3615 status = "disabled"; 3616 }; 3617 3618 frame@17c2b000 { 3619 frame-number = <5>; 3620 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3621 reg = <0x17c2b000 0x1000>; 3622 status = "disabled"; 3623 }; 3624 3625 frame@17c2d000 { 3626 frame-number = <6>; 3627 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3628 reg = <0x17c2d000 0x1000>; 3629 status = "disabled"; 3630 }; 3631 }; 3632 3633 apps_rsc: rsc@18200000 { 3634 compatible = "qcom,rpmh-rsc"; 3635 reg = <0 0x18200000 0 0x10000>, 3636 <0 0x18210000 0 0x10000>, 3637 <0 0x18220000 0 0x10000>; 3638 reg-names = "drv-0", "drv-1", "drv-2"; 3639 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3642 qcom,tcs-offset = <0xd00>; 3643 qcom,drv-id = <2>; 3644 qcom,tcs-config = <ACTIVE_TCS 2>, 3645 <SLEEP_TCS 3>, 3646 <WAKE_TCS 3>, 3647 <CONTROL_TCS 1>; 3648 power-domains = <&CLUSTER_PD>; 3649 3650 rpmhcc: clock-controller { 3651 compatible = "qcom,sc7180-rpmh-clk"; 3652 clocks = <&xo_board>; 3653 clock-names = "xo"; 3654 #clock-cells = <1>; 3655 }; 3656 3657 rpmhpd: power-controller { 3658 compatible = "qcom,sc7180-rpmhpd"; 3659 #power-domain-cells = <1>; 3660 operating-points-v2 = <&rpmhpd_opp_table>; 3661 3662 rpmhpd_opp_table: opp-table { 3663 compatible = "operating-points-v2"; 3664 3665 rpmhpd_opp_ret: opp1 { 3666 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3667 }; 3668 3669 rpmhpd_opp_min_svs: opp2 { 3670 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3671 }; 3672 3673 rpmhpd_opp_low_svs: opp3 { 3674 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3675 }; 3676 3677 rpmhpd_opp_svs: opp4 { 3678 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3679 }; 3680 3681 rpmhpd_opp_svs_l1: opp5 { 3682 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3683 }; 3684 3685 rpmhpd_opp_svs_l2: opp6 { 3686 opp-level = <224>; 3687 }; 3688 3689 rpmhpd_opp_nom: opp7 { 3690 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3691 }; 3692 3693 rpmhpd_opp_nom_l1: opp8 { 3694 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3695 }; 3696 3697 rpmhpd_opp_nom_l2: opp9 { 3698 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3699 }; 3700 3701 rpmhpd_opp_turbo: opp10 { 3702 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3703 }; 3704 3705 rpmhpd_opp_turbo_l1: opp11 { 3706 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3707 }; 3708 }; 3709 }; 3710 3711 apps_bcm_voter: bcm-voter { 3712 compatible = "qcom,bcm-voter"; 3713 }; 3714 }; 3715 3716 osm_l3: interconnect@18321000 { 3717 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3718 reg = <0 0x18321000 0 0x1400>; 3719 3720 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3721 clock-names = "xo", "alternate"; 3722 3723 #interconnect-cells = <1>; 3724 }; 3725 3726 cpufreq_hw: cpufreq@18323000 { 3727 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; 3728 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3729 reg-names = "freq-domain0", "freq-domain1"; 3730 3731 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3732 clock-names = "xo", "alternate"; 3733 3734 #freq-domain-cells = <1>; 3735 #clock-cells = <1>; 3736 }; 3737 3738 wifi: wifi@18800000 { 3739 compatible = "qcom,wcn3990-wifi"; 3740 reg = <0 0x18800000 0 0x800000>; 3741 reg-names = "membase"; 3742 iommus = <&apps_smmu 0xc0 0x1>; 3743 interrupts = 3744 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3745 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3746 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3747 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3748 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3749 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3750 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3751 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3752 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3753 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3754 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3755 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3756 memory-region = <&wlan_mem>; 3757 qcom,msa-fixed-perm; 3758 status = "disabled"; 3759 }; 3760 3761 lpasscc: clock-controller@62d00000 { 3762 compatible = "qcom,sc7180-lpasscorecc"; 3763 reg = <0 0x62d00000 0 0x50000>, 3764 <0 0x62780000 0 0x30000>; 3765 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3766 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3767 <&rpmhcc RPMH_CXO_CLK>; 3768 clock-names = "iface", "bi_tcxo"; 3769 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3770 #clock-cells = <1>; 3771 #power-domain-cells = <1>; 3772 3773 status = "reserved"; /* Controlled by ADSP */ 3774 }; 3775 3776 lpass_cpu: lpass@62d87000 { 3777 compatible = "qcom,sc7180-lpass-cpu"; 3778 3779 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3780 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3781 3782 iommus = <&apps_smmu 0x1020 0>, 3783 <&apps_smmu 0x1021 0>, 3784 <&apps_smmu 0x1032 0>; 3785 3786 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3787 required-opps = <&rpmhpd_opp_nom>; 3788 3789 status = "disabled"; 3790 3791 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3792 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3793 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3794 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3795 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3796 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3797 3798 clock-names = "pcnoc-sway-clk", "audio-core", 3799 "mclk0", "pcnoc-mport-clk", 3800 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3801 3802 3803 #sound-dai-cells = <1>; 3804 #address-cells = <1>; 3805 #size-cells = <0>; 3806 3807 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3809 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3810 }; 3811 3812 lpass_hm: clock-controller@63000000 { 3813 compatible = "qcom,sc7180-lpasshm"; 3814 reg = <0 0x63000000 0 0x28>; 3815 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3816 <&rpmhcc RPMH_CXO_CLK>; 3817 clock-names = "iface", "bi_tcxo"; 3818 power-domains = <&rpmhpd SC7180_CX>; 3819 3820 #clock-cells = <1>; 3821 #power-domain-cells = <1>; 3822 3823 status = "reserved"; /* Controlled by ADSP */ 3824 }; 3825 }; 3826 3827 thermal-zones { 3828 cpu0_thermal: cpu0-thermal { 3829 polling-delay-passive = <250>; 3830 polling-delay = <0>; 3831 3832 thermal-sensors = <&tsens0 1>; 3833 sustainable-power = <1052>; 3834 3835 trips { 3836 cpu0_alert0: trip-point0 { 3837 temperature = <90000>; 3838 hysteresis = <2000>; 3839 type = "passive"; 3840 }; 3841 3842 cpu0_alert1: trip-point1 { 3843 temperature = <95000>; 3844 hysteresis = <2000>; 3845 type = "passive"; 3846 }; 3847 3848 cpu0_crit: cpu-crit { 3849 temperature = <110000>; 3850 hysteresis = <1000>; 3851 type = "critical"; 3852 }; 3853 }; 3854 3855 cooling-maps { 3856 map0 { 3857 trip = <&cpu0_alert0>; 3858 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3860 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3862 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3863 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3864 }; 3865 map1 { 3866 trip = <&cpu0_alert1>; 3867 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3869 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3870 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3873 }; 3874 }; 3875 }; 3876 3877 cpu1_thermal: cpu1-thermal { 3878 polling-delay-passive = <250>; 3879 polling-delay = <0>; 3880 3881 thermal-sensors = <&tsens0 2>; 3882 sustainable-power = <1052>; 3883 3884 trips { 3885 cpu1_alert0: trip-point0 { 3886 temperature = <90000>; 3887 hysteresis = <2000>; 3888 type = "passive"; 3889 }; 3890 3891 cpu1_alert1: trip-point1 { 3892 temperature = <95000>; 3893 hysteresis = <2000>; 3894 type = "passive"; 3895 }; 3896 3897 cpu1_crit: cpu-crit { 3898 temperature = <110000>; 3899 hysteresis = <1000>; 3900 type = "critical"; 3901 }; 3902 }; 3903 3904 cooling-maps { 3905 map0 { 3906 trip = <&cpu1_alert0>; 3907 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3908 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3909 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3913 }; 3914 map1 { 3915 trip = <&cpu1_alert1>; 3916 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3917 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3919 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3922 }; 3923 }; 3924 }; 3925 3926 cpu2_thermal: cpu2-thermal { 3927 polling-delay-passive = <250>; 3928 polling-delay = <0>; 3929 3930 thermal-sensors = <&tsens0 3>; 3931 sustainable-power = <1052>; 3932 3933 trips { 3934 cpu2_alert0: trip-point0 { 3935 temperature = <90000>; 3936 hysteresis = <2000>; 3937 type = "passive"; 3938 }; 3939 3940 cpu2_alert1: trip-point1 { 3941 temperature = <95000>; 3942 hysteresis = <2000>; 3943 type = "passive"; 3944 }; 3945 3946 cpu2_crit: cpu-crit { 3947 temperature = <110000>; 3948 hysteresis = <1000>; 3949 type = "critical"; 3950 }; 3951 }; 3952 3953 cooling-maps { 3954 map0 { 3955 trip = <&cpu2_alert0>; 3956 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3957 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3958 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3959 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3960 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3962 }; 3963 map1 { 3964 trip = <&cpu2_alert1>; 3965 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3966 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3967 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3968 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3969 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3970 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3971 }; 3972 }; 3973 }; 3974 3975 cpu3_thermal: cpu3-thermal { 3976 polling-delay-passive = <250>; 3977 polling-delay = <0>; 3978 3979 thermal-sensors = <&tsens0 4>; 3980 sustainable-power = <1052>; 3981 3982 trips { 3983 cpu3_alert0: trip-point0 { 3984 temperature = <90000>; 3985 hysteresis = <2000>; 3986 type = "passive"; 3987 }; 3988 3989 cpu3_alert1: trip-point1 { 3990 temperature = <95000>; 3991 hysteresis = <2000>; 3992 type = "passive"; 3993 }; 3994 3995 cpu3_crit: cpu-crit { 3996 temperature = <110000>; 3997 hysteresis = <1000>; 3998 type = "critical"; 3999 }; 4000 }; 4001 4002 cooling-maps { 4003 map0 { 4004 trip = <&cpu3_alert0>; 4005 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4007 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4008 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4009 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4010 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4011 }; 4012 map1 { 4013 trip = <&cpu3_alert1>; 4014 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4015 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4016 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4017 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4018 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4019 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4020 }; 4021 }; 4022 }; 4023 4024 cpu4_thermal: cpu4-thermal { 4025 polling-delay-passive = <250>; 4026 polling-delay = <0>; 4027 4028 thermal-sensors = <&tsens0 5>; 4029 sustainable-power = <1052>; 4030 4031 trips { 4032 cpu4_alert0: trip-point0 { 4033 temperature = <90000>; 4034 hysteresis = <2000>; 4035 type = "passive"; 4036 }; 4037 4038 cpu4_alert1: trip-point1 { 4039 temperature = <95000>; 4040 hysteresis = <2000>; 4041 type = "passive"; 4042 }; 4043 4044 cpu4_crit: cpu-crit { 4045 temperature = <110000>; 4046 hysteresis = <1000>; 4047 type = "critical"; 4048 }; 4049 }; 4050 4051 cooling-maps { 4052 map0 { 4053 trip = <&cpu4_alert0>; 4054 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4055 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4056 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4057 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4058 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4059 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4060 }; 4061 map1 { 4062 trip = <&cpu4_alert1>; 4063 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4065 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4066 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4067 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4068 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4069 }; 4070 }; 4071 }; 4072 4073 cpu5_thermal: cpu5-thermal { 4074 polling-delay-passive = <250>; 4075 polling-delay = <0>; 4076 4077 thermal-sensors = <&tsens0 6>; 4078 sustainable-power = <1052>; 4079 4080 trips { 4081 cpu5_alert0: trip-point0 { 4082 temperature = <90000>; 4083 hysteresis = <2000>; 4084 type = "passive"; 4085 }; 4086 4087 cpu5_alert1: trip-point1 { 4088 temperature = <95000>; 4089 hysteresis = <2000>; 4090 type = "passive"; 4091 }; 4092 4093 cpu5_crit: cpu-crit { 4094 temperature = <110000>; 4095 hysteresis = <1000>; 4096 type = "critical"; 4097 }; 4098 }; 4099 4100 cooling-maps { 4101 map0 { 4102 trip = <&cpu5_alert0>; 4103 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4104 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4105 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4106 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4107 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4108 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4109 }; 4110 map1 { 4111 trip = <&cpu5_alert1>; 4112 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4118 }; 4119 }; 4120 }; 4121 4122 cpu6_thermal: cpu6-thermal { 4123 polling-delay-passive = <250>; 4124 polling-delay = <0>; 4125 4126 thermal-sensors = <&tsens0 9>; 4127 sustainable-power = <1425>; 4128 4129 trips { 4130 cpu6_alert0: trip-point0 { 4131 temperature = <90000>; 4132 hysteresis = <2000>; 4133 type = "passive"; 4134 }; 4135 4136 cpu6_alert1: trip-point1 { 4137 temperature = <95000>; 4138 hysteresis = <2000>; 4139 type = "passive"; 4140 }; 4141 4142 cpu6_crit: cpu-crit { 4143 temperature = <110000>; 4144 hysteresis = <1000>; 4145 type = "critical"; 4146 }; 4147 }; 4148 4149 cooling-maps { 4150 map0 { 4151 trip = <&cpu6_alert0>; 4152 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4154 }; 4155 map1 { 4156 trip = <&cpu6_alert1>; 4157 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4159 }; 4160 }; 4161 }; 4162 4163 cpu7_thermal: cpu7-thermal { 4164 polling-delay-passive = <250>; 4165 polling-delay = <0>; 4166 4167 thermal-sensors = <&tsens0 10>; 4168 sustainable-power = <1425>; 4169 4170 trips { 4171 cpu7_alert0: trip-point0 { 4172 temperature = <90000>; 4173 hysteresis = <2000>; 4174 type = "passive"; 4175 }; 4176 4177 cpu7_alert1: trip-point1 { 4178 temperature = <95000>; 4179 hysteresis = <2000>; 4180 type = "passive"; 4181 }; 4182 4183 cpu7_crit: cpu-crit { 4184 temperature = <110000>; 4185 hysteresis = <1000>; 4186 type = "critical"; 4187 }; 4188 }; 4189 4190 cooling-maps { 4191 map0 { 4192 trip = <&cpu7_alert0>; 4193 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4194 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4195 }; 4196 map1 { 4197 trip = <&cpu7_alert1>; 4198 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4199 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4200 }; 4201 }; 4202 }; 4203 4204 cpu8_thermal: cpu8-thermal { 4205 polling-delay-passive = <250>; 4206 polling-delay = <0>; 4207 4208 thermal-sensors = <&tsens0 11>; 4209 sustainable-power = <1425>; 4210 4211 trips { 4212 cpu8_alert0: trip-point0 { 4213 temperature = <90000>; 4214 hysteresis = <2000>; 4215 type = "passive"; 4216 }; 4217 4218 cpu8_alert1: trip-point1 { 4219 temperature = <95000>; 4220 hysteresis = <2000>; 4221 type = "passive"; 4222 }; 4223 4224 cpu8_crit: cpu-crit { 4225 temperature = <110000>; 4226 hysteresis = <1000>; 4227 type = "critical"; 4228 }; 4229 }; 4230 4231 cooling-maps { 4232 map0 { 4233 trip = <&cpu8_alert0>; 4234 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4235 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4236 }; 4237 map1 { 4238 trip = <&cpu8_alert1>; 4239 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4241 }; 4242 }; 4243 }; 4244 4245 cpu9_thermal: cpu9-thermal { 4246 polling-delay-passive = <250>; 4247 polling-delay = <0>; 4248 4249 thermal-sensors = <&tsens0 12>; 4250 sustainable-power = <1425>; 4251 4252 trips { 4253 cpu9_alert0: trip-point0 { 4254 temperature = <90000>; 4255 hysteresis = <2000>; 4256 type = "passive"; 4257 }; 4258 4259 cpu9_alert1: trip-point1 { 4260 temperature = <95000>; 4261 hysteresis = <2000>; 4262 type = "passive"; 4263 }; 4264 4265 cpu9_crit: cpu-crit { 4266 temperature = <110000>; 4267 hysteresis = <1000>; 4268 type = "critical"; 4269 }; 4270 }; 4271 4272 cooling-maps { 4273 map0 { 4274 trip = <&cpu9_alert0>; 4275 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4276 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4277 }; 4278 map1 { 4279 trip = <&cpu9_alert1>; 4280 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4281 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4282 }; 4283 }; 4284 }; 4285 4286 aoss0-thermal { 4287 polling-delay-passive = <250>; 4288 polling-delay = <0>; 4289 4290 thermal-sensors = <&tsens0 0>; 4291 4292 trips { 4293 aoss0_alert0: trip-point0 { 4294 temperature = <90000>; 4295 hysteresis = <2000>; 4296 type = "hot"; 4297 }; 4298 4299 aoss0_crit: aoss0-crit { 4300 temperature = <110000>; 4301 hysteresis = <2000>; 4302 type = "critical"; 4303 }; 4304 }; 4305 }; 4306 4307 cpuss0-thermal { 4308 polling-delay-passive = <250>; 4309 polling-delay = <0>; 4310 4311 thermal-sensors = <&tsens0 7>; 4312 4313 trips { 4314 cpuss0_alert0: trip-point0 { 4315 temperature = <90000>; 4316 hysteresis = <2000>; 4317 type = "hot"; 4318 }; 4319 cpuss0_crit: cluster0-crit { 4320 temperature = <110000>; 4321 hysteresis = <2000>; 4322 type = "critical"; 4323 }; 4324 }; 4325 }; 4326 4327 cpuss1-thermal { 4328 polling-delay-passive = <250>; 4329 polling-delay = <0>; 4330 4331 thermal-sensors = <&tsens0 8>; 4332 4333 trips { 4334 cpuss1_alert0: trip-point0 { 4335 temperature = <90000>; 4336 hysteresis = <2000>; 4337 type = "hot"; 4338 }; 4339 cpuss1_crit: cluster0-crit { 4340 temperature = <110000>; 4341 hysteresis = <2000>; 4342 type = "critical"; 4343 }; 4344 }; 4345 }; 4346 4347 gpuss0-thermal { 4348 polling-delay-passive = <250>; 4349 polling-delay = <0>; 4350 4351 thermal-sensors = <&tsens0 13>; 4352 4353 trips { 4354 gpuss0_alert0: trip-point0 { 4355 temperature = <95000>; 4356 hysteresis = <2000>; 4357 type = "passive"; 4358 }; 4359 4360 gpuss0_crit: gpuss0-crit { 4361 temperature = <110000>; 4362 hysteresis = <2000>; 4363 type = "critical"; 4364 }; 4365 }; 4366 4367 cooling-maps { 4368 map0 { 4369 trip = <&gpuss0_alert0>; 4370 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4371 }; 4372 }; 4373 }; 4374 4375 gpuss1-thermal { 4376 polling-delay-passive = <250>; 4377 polling-delay = <0>; 4378 4379 thermal-sensors = <&tsens0 14>; 4380 4381 trips { 4382 gpuss1_alert0: trip-point0 { 4383 temperature = <95000>; 4384 hysteresis = <2000>; 4385 type = "passive"; 4386 }; 4387 4388 gpuss1_crit: gpuss1-crit { 4389 temperature = <110000>; 4390 hysteresis = <2000>; 4391 type = "critical"; 4392 }; 4393 }; 4394 4395 cooling-maps { 4396 map0 { 4397 trip = <&gpuss1_alert0>; 4398 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4399 }; 4400 }; 4401 }; 4402 4403 aoss1-thermal { 4404 polling-delay-passive = <250>; 4405 polling-delay = <0>; 4406 4407 thermal-sensors = <&tsens1 0>; 4408 4409 trips { 4410 aoss1_alert0: trip-point0 { 4411 temperature = <90000>; 4412 hysteresis = <2000>; 4413 type = "hot"; 4414 }; 4415 4416 aoss1_crit: aoss1-crit { 4417 temperature = <110000>; 4418 hysteresis = <2000>; 4419 type = "critical"; 4420 }; 4421 }; 4422 }; 4423 4424 cwlan-thermal { 4425 polling-delay-passive = <250>; 4426 polling-delay = <0>; 4427 4428 thermal-sensors = <&tsens1 1>; 4429 4430 trips { 4431 cwlan_alert0: trip-point0 { 4432 temperature = <90000>; 4433 hysteresis = <2000>; 4434 type = "hot"; 4435 }; 4436 4437 cwlan_crit: cwlan-crit { 4438 temperature = <110000>; 4439 hysteresis = <2000>; 4440 type = "critical"; 4441 }; 4442 }; 4443 }; 4444 4445 audio-thermal { 4446 polling-delay-passive = <250>; 4447 polling-delay = <0>; 4448 4449 thermal-sensors = <&tsens1 2>; 4450 4451 trips { 4452 audio_alert0: trip-point0 { 4453 temperature = <90000>; 4454 hysteresis = <2000>; 4455 type = "hot"; 4456 }; 4457 4458 audio_crit: audio-crit { 4459 temperature = <110000>; 4460 hysteresis = <2000>; 4461 type = "critical"; 4462 }; 4463 }; 4464 }; 4465 4466 ddr-thermal { 4467 polling-delay-passive = <250>; 4468 polling-delay = <0>; 4469 4470 thermal-sensors = <&tsens1 3>; 4471 4472 trips { 4473 ddr_alert0: trip-point0 { 4474 temperature = <90000>; 4475 hysteresis = <2000>; 4476 type = "hot"; 4477 }; 4478 4479 ddr_crit: ddr-crit { 4480 temperature = <110000>; 4481 hysteresis = <2000>; 4482 type = "critical"; 4483 }; 4484 }; 4485 }; 4486 4487 q6-hvx-thermal { 4488 polling-delay-passive = <250>; 4489 polling-delay = <0>; 4490 4491 thermal-sensors = <&tsens1 4>; 4492 4493 trips { 4494 q6_hvx_alert0: trip-point0 { 4495 temperature = <90000>; 4496 hysteresis = <2000>; 4497 type = "hot"; 4498 }; 4499 4500 q6_hvx_crit: q6-hvx-crit { 4501 temperature = <110000>; 4502 hysteresis = <2000>; 4503 type = "critical"; 4504 }; 4505 }; 4506 }; 4507 4508 camera-thermal { 4509 polling-delay-passive = <250>; 4510 polling-delay = <0>; 4511 4512 thermal-sensors = <&tsens1 5>; 4513 4514 trips { 4515 camera_alert0: trip-point0 { 4516 temperature = <90000>; 4517 hysteresis = <2000>; 4518 type = "hot"; 4519 }; 4520 4521 camera_crit: camera-crit { 4522 temperature = <110000>; 4523 hysteresis = <2000>; 4524 type = "critical"; 4525 }; 4526 }; 4527 }; 4528 4529 mdm-core-thermal { 4530 polling-delay-passive = <250>; 4531 polling-delay = <0>; 4532 4533 thermal-sensors = <&tsens1 6>; 4534 4535 trips { 4536 mdm_alert0: trip-point0 { 4537 temperature = <90000>; 4538 hysteresis = <2000>; 4539 type = "hot"; 4540 }; 4541 4542 mdm_crit: mdm-crit { 4543 temperature = <110000>; 4544 hysteresis = <2000>; 4545 type = "critical"; 4546 }; 4547 }; 4548 }; 4549 4550 mdm-dsp-thermal { 4551 polling-delay-passive = <250>; 4552 polling-delay = <0>; 4553 4554 thermal-sensors = <&tsens1 7>; 4555 4556 trips { 4557 mdm_dsp_alert0: trip-point0 { 4558 temperature = <90000>; 4559 hysteresis = <2000>; 4560 type = "hot"; 4561 }; 4562 4563 mdm_dsp_crit: mdm-dsp-crit { 4564 temperature = <110000>; 4565 hysteresis = <2000>; 4566 type = "critical"; 4567 }; 4568 }; 4569 }; 4570 4571 npu-thermal { 4572 polling-delay-passive = <250>; 4573 polling-delay = <0>; 4574 4575 thermal-sensors = <&tsens1 8>; 4576 4577 trips { 4578 npu_alert0: trip-point0 { 4579 temperature = <90000>; 4580 hysteresis = <2000>; 4581 type = "hot"; 4582 }; 4583 4584 npu_crit: npu-crit { 4585 temperature = <110000>; 4586 hysteresis = <2000>; 4587 type = "critical"; 4588 }; 4589 }; 4590 }; 4591 4592 video-thermal { 4593 polling-delay-passive = <250>; 4594 polling-delay = <0>; 4595 4596 thermal-sensors = <&tsens1 9>; 4597 4598 trips { 4599 video_alert0: trip-point0 { 4600 temperature = <90000>; 4601 hysteresis = <2000>; 4602 type = "hot"; 4603 }; 4604 4605 video_crit: video-crit { 4606 temperature = <110000>; 4607 hysteresis = <2000>; 4608 type = "critical"; 4609 }; 4610 }; 4611 }; 4612 }; 4613 4614 timer { 4615 compatible = "arm,armv8-timer"; 4616 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4617 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4618 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4619 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4620 }; 4621}; 4622