1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 aliases { 33 mmc1 = &sdhc_1; 34 mmc2 = &sdhc_2; 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi3 = &spi3; 50 spi5 = &spi5; 51 spi6 = &spi6; 52 spi8 = &spi8; 53 spi10 = &spi10; 54 spi11 = &spi11; 55 }; 56 57 clocks { 58 xo_board: xo-board { 59 compatible = "fixed-clock"; 60 clock-frequency = <38400000>; 61 #clock-cells = <0>; 62 }; 63 64 sleep_clk: sleep-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <32764>; 67 #clock-cells = <0>; 68 }; 69 }; 70 71 reserved_memory: reserved-memory { 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 hyp_mem: memory@80000000 { 77 reg = <0x0 0x80000000 0x0 0x600000>; 78 no-map; 79 }; 80 81 xbl_mem: memory@80600000 { 82 reg = <0x0 0x80600000 0x0 0x200000>; 83 no-map; 84 }; 85 86 aop_mem: memory@80800000 { 87 reg = <0x0 0x80800000 0x0 0x20000>; 88 no-map; 89 }; 90 91 aop_cmd_db_mem: memory@80820000 { 92 reg = <0x0 0x80820000 0x0 0x20000>; 93 compatible = "qcom,cmd-db"; 94 no-map; 95 }; 96 97 sec_apps_mem: memory@808ff000 { 98 reg = <0x0 0x808ff000 0x0 0x1000>; 99 no-map; 100 }; 101 102 smem_mem: memory@80900000 { 103 reg = <0x0 0x80900000 0x0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@80b00000 { 108 reg = <0x0 0x80b00000 0x0 0x3900000>; 109 no-map; 110 }; 111 112 ipa_fw_mem: memory@8b700000 { 113 reg = <0 0x8b700000 0 0x10000>; 114 no-map; 115 }; 116 117 rmtfs_mem: memory@94600000 { 118 compatible = "qcom,rmtfs-mem"; 119 reg = <0x0 0x94600000 0x0 0x200000>; 120 no-map; 121 122 qcom,client-id = <1>; 123 qcom,vmid = <15>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <2>; 129 #size-cells = <0>; 130 131 CPU0: cpu@0 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo468"; 134 reg = <0x0 0x0>; 135 enable-method = "psci"; 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 137 &LITTLE_CPU_SLEEP_1 138 &CLUSTER_SLEEP_0>; 139 capacity-dmips-mhz = <415>; 140 dynamic-power-coefficient = <137>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 144 next-level-cache = <&L2_0>; 145 #cooling-cells = <2>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 L2_0: l2-cache { 148 compatible = "cache"; 149 next-level-cache = <&L3_0>; 150 L3_0: l3-cache { 151 compatible = "cache"; 152 }; 153 }; 154 }; 155 156 CPU1: cpu@100 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo468"; 159 reg = <0x0 0x100>; 160 enable-method = "psci"; 161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 162 &LITTLE_CPU_SLEEP_1 163 &CLUSTER_SLEEP_0>; 164 capacity-dmips-mhz = <415>; 165 dynamic-power-coefficient = <137>; 166 next-level-cache = <&L2_100>; 167 operating-points-v2 = <&cpu0_opp_table>; 168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 #cooling-cells = <2>; 171 qcom,freq-domain = <&cpufreq_hw 0>; 172 L2_100: l2-cache { 173 compatible = "cache"; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU2: cpu@200 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo468"; 181 reg = <0x0 0x200>; 182 enable-method = "psci"; 183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 184 &LITTLE_CPU_SLEEP_1 185 &CLUSTER_SLEEP_0>; 186 capacity-dmips-mhz = <415>; 187 dynamic-power-coefficient = <137>; 188 next-level-cache = <&L2_200>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 192 #cooling-cells = <2>; 193 qcom,freq-domain = <&cpufreq_hw 0>; 194 L2_200: l2-cache { 195 compatible = "cache"; 196 next-level-cache = <&L3_0>; 197 }; 198 }; 199 200 CPU3: cpu@300 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo468"; 203 reg = <0x0 0x300>; 204 enable-method = "psci"; 205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 206 &LITTLE_CPU_SLEEP_1 207 &CLUSTER_SLEEP_0>; 208 capacity-dmips-mhz = <415>; 209 dynamic-power-coefficient = <137>; 210 next-level-cache = <&L2_300>; 211 operating-points-v2 = <&cpu0_opp_table>; 212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 #cooling-cells = <2>; 215 qcom,freq-domain = <&cpufreq_hw 0>; 216 L2_300: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU4: cpu@400 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo468"; 225 reg = <0x0 0x400>; 226 enable-method = "psci"; 227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 228 &LITTLE_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230 capacity-dmips-mhz = <415>; 231 dynamic-power-coefficient = <137>; 232 next-level-cache = <&L2_400>; 233 operating-points-v2 = <&cpu0_opp_table>; 234 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 236 #cooling-cells = <2>; 237 qcom,freq-domain = <&cpufreq_hw 0>; 238 L2_400: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU5: cpu@500 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo468"; 247 reg = <0x0 0x500>; 248 enable-method = "psci"; 249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 250 &LITTLE_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252 capacity-dmips-mhz = <415>; 253 dynamic-power-coefficient = <137>; 254 next-level-cache = <&L2_500>; 255 operating-points-v2 = <&cpu0_opp_table>; 256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 257 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 258 #cooling-cells = <2>; 259 qcom,freq-domain = <&cpufreq_hw 0>; 260 L2_500: l2-cache { 261 compatible = "cache"; 262 next-level-cache = <&L3_0>; 263 }; 264 }; 265 266 CPU6: cpu@600 { 267 device_type = "cpu"; 268 compatible = "qcom,kryo468"; 269 reg = <0x0 0x600>; 270 enable-method = "psci"; 271 cpu-idle-states = <&BIG_CPU_SLEEP_0 272 &BIG_CPU_SLEEP_1 273 &CLUSTER_SLEEP_0>; 274 capacity-dmips-mhz = <1024>; 275 dynamic-power-coefficient = <480>; 276 next-level-cache = <&L2_600>; 277 operating-points-v2 = <&cpu6_opp_table>; 278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 280 #cooling-cells = <2>; 281 qcom,freq-domain = <&cpufreq_hw 1>; 282 L2_600: l2-cache { 283 compatible = "cache"; 284 next-level-cache = <&L3_0>; 285 }; 286 }; 287 288 CPU7: cpu@700 { 289 device_type = "cpu"; 290 compatible = "qcom,kryo468"; 291 reg = <0x0 0x700>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 capacity-dmips-mhz = <1024>; 297 dynamic-power-coefficient = <480>; 298 next-level-cache = <&L2_700>; 299 operating-points-v2 = <&cpu6_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 302 #cooling-cells = <2>; 303 qcom,freq-domain = <&cpufreq_hw 1>; 304 L2_700: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 cpu-map { 311 cluster0 { 312 core0 { 313 cpu = <&CPU0>; 314 }; 315 316 core1 { 317 cpu = <&CPU1>; 318 }; 319 320 core2 { 321 cpu = <&CPU2>; 322 }; 323 324 core3 { 325 cpu = <&CPU3>; 326 }; 327 328 core4 { 329 cpu = <&CPU4>; 330 }; 331 332 core5 { 333 cpu = <&CPU5>; 334 }; 335 336 core6 { 337 cpu = <&CPU6>; 338 }; 339 340 core7 { 341 cpu = <&CPU7>; 342 }; 343 }; 344 }; 345 346 idle-states { 347 entry-method = "psci"; 348 349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "little-power-down"; 352 arm,psci-suspend-param = <0x40000003>; 353 entry-latency-us = <549>; 354 exit-latency-us = <901>; 355 min-residency-us = <1774>; 356 local-timer-stop; 357 }; 358 359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "little-rail-power-down"; 362 arm,psci-suspend-param = <0x40000004>; 363 entry-latency-us = <702>; 364 exit-latency-us = <915>; 365 min-residency-us = <4001>; 366 local-timer-stop; 367 }; 368 369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "big-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <523>; 374 exit-latency-us = <1244>; 375 min-residency-us = <2207>; 376 local-timer-stop; 377 }; 378 379 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "big-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <526>; 384 exit-latency-us = <1854>; 385 min-residency-us = <5555>; 386 local-timer-stop; 387 }; 388 389 CLUSTER_SLEEP_0: cluster-sleep-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "cluster-power-down"; 392 arm,psci-suspend-param = <0x40003444>; 393 entry-latency-us = <3263>; 394 exit-latency-us = <6562>; 395 min-residency-us = <9926>; 396 local-timer-stop; 397 }; 398 }; 399 }; 400 401 cpu0_opp_table: cpu0_opp_table { 402 compatible = "operating-points-v2"; 403 opp-shared; 404 405 cpu0_opp1: opp-300000000 { 406 opp-hz = /bits/ 64 <300000000>; 407 opp-peak-kBps = <1200000 4800000>; 408 }; 409 410 cpu0_opp2: opp-576000000 { 411 opp-hz = /bits/ 64 <576000000>; 412 opp-peak-kBps = <1200000 4800000>; 413 }; 414 415 cpu0_opp3: opp-768000000 { 416 opp-hz = /bits/ 64 <768000000>; 417 opp-peak-kBps = <1200000 4800000>; 418 }; 419 420 cpu0_opp4: opp-1017600000 { 421 opp-hz = /bits/ 64 <1017600000>; 422 opp-peak-kBps = <1804000 8908800>; 423 }; 424 425 cpu0_opp5: opp-1248000000 { 426 opp-hz = /bits/ 64 <1248000000>; 427 opp-peak-kBps = <2188000 12902400>; 428 }; 429 430 cpu0_opp6: opp-1324800000 { 431 opp-hz = /bits/ 64 <1324800000>; 432 opp-peak-kBps = <2188000 12902400>; 433 }; 434 435 cpu0_opp7: opp-1516800000 { 436 opp-hz = /bits/ 64 <1516800000>; 437 opp-peak-kBps = <3072000 15052800>; 438 }; 439 440 cpu0_opp8: opp-1612800000 { 441 opp-hz = /bits/ 64 <1612800000>; 442 opp-peak-kBps = <3072000 15052800>; 443 }; 444 445 cpu0_opp9: opp-1708800000 { 446 opp-hz = /bits/ 64 <1708800000>; 447 opp-peak-kBps = <3072000 15052800>; 448 }; 449 450 cpu0_opp10: opp-1804800000 { 451 opp-hz = /bits/ 64 <1804800000>; 452 opp-peak-kBps = <4068000 22425600>; 453 }; 454 }; 455 456 cpu6_opp_table: cpu6_opp_table { 457 compatible = "operating-points-v2"; 458 opp-shared; 459 460 cpu6_opp1: opp-300000000 { 461 opp-hz = /bits/ 64 <300000000>; 462 opp-peak-kBps = <2188000 8908800>; 463 }; 464 465 cpu6_opp2: opp-652800000 { 466 opp-hz = /bits/ 64 <652800000>; 467 opp-peak-kBps = <2188000 8908800>; 468 }; 469 470 cpu6_opp3: opp-825600000 { 471 opp-hz = /bits/ 64 <825600000>; 472 opp-peak-kBps = <2188000 8908800>; 473 }; 474 475 cpu6_opp4: opp-979200000 { 476 opp-hz = /bits/ 64 <979200000>; 477 opp-peak-kBps = <2188000 8908800>; 478 }; 479 480 cpu6_opp5: opp-1113600000 { 481 opp-hz = /bits/ 64 <1113600000>; 482 opp-peak-kBps = <2188000 8908800>; 483 }; 484 485 cpu6_opp6: opp-1267200000 { 486 opp-hz = /bits/ 64 <1267200000>; 487 opp-peak-kBps = <4068000 12902400>; 488 }; 489 490 cpu6_opp7: opp-1555200000 { 491 opp-hz = /bits/ 64 <1555200000>; 492 opp-peak-kBps = <4068000 15052800>; 493 }; 494 495 cpu6_opp8: opp-1708800000 { 496 opp-hz = /bits/ 64 <1708800000>; 497 opp-peak-kBps = <6220000 19353600>; 498 }; 499 500 cpu6_opp9: opp-1843200000 { 501 opp-hz = /bits/ 64 <1843200000>; 502 opp-peak-kBps = <6220000 19353600>; 503 }; 504 505 cpu6_opp10: opp-1900800000 { 506 opp-hz = /bits/ 64 <1900800000>; 507 opp-peak-kBps = <6220000 22425600>; 508 }; 509 510 cpu6_opp11: opp-1996800000 { 511 opp-hz = /bits/ 64 <1996800000>; 512 opp-peak-kBps = <6220000 22425600>; 513 }; 514 515 cpu6_opp12: opp-2112000000 { 516 opp-hz = /bits/ 64 <2112000000>; 517 opp-peak-kBps = <6220000 22425600>; 518 }; 519 520 cpu6_opp13: opp-2208000000 { 521 opp-hz = /bits/ 64 <2208000000>; 522 opp-peak-kBps = <7216000 22425600>; 523 }; 524 525 cpu6_opp14: opp-2323200000 { 526 opp-hz = /bits/ 64 <2323200000>; 527 opp-peak-kBps = <7216000 22425600>; 528 }; 529 530 cpu6_opp15: opp-2400000000 { 531 opp-hz = /bits/ 64 <2400000000>; 532 opp-peak-kBps = <8532000 23347200>; 533 }; 534 535 cpu6_opp16: opp-2553600000 { 536 opp-hz = /bits/ 64 <2553600000>; 537 opp-peak-kBps = <8532000 23347200>; 538 }; 539 }; 540 541 memory@80000000 { 542 device_type = "memory"; 543 /* We expect the bootloader to fill in the size */ 544 reg = <0 0x80000000 0 0>; 545 }; 546 547 pmu { 548 compatible = "arm,armv8-pmuv3"; 549 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 550 }; 551 552 firmware { 553 scm { 554 compatible = "qcom,scm-sc7180", "qcom,scm"; 555 }; 556 }; 557 558 tcsr_mutex: hwlock { 559 compatible = "qcom,tcsr-mutex"; 560 syscon = <&tcsr_mutex_regs 0 0x1000>; 561 #hwlock-cells = <1>; 562 }; 563 564 smem { 565 compatible = "qcom,smem"; 566 memory-region = <&smem_mem>; 567 hwlocks = <&tcsr_mutex 3>; 568 }; 569 570 smp2p-cdsp { 571 compatible = "qcom,smp2p"; 572 qcom,smem = <94>, <432>; 573 574 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 575 576 mboxes = <&apss_shared 6>; 577 578 qcom,local-pid = <0>; 579 qcom,remote-pid = <5>; 580 581 cdsp_smp2p_out: master-kernel { 582 qcom,entry-name = "master-kernel"; 583 #qcom,smem-state-cells = <1>; 584 }; 585 586 cdsp_smp2p_in: slave-kernel { 587 qcom,entry-name = "slave-kernel"; 588 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 }; 592 }; 593 594 smp2p-lpass { 595 compatible = "qcom,smp2p"; 596 qcom,smem = <443>, <429>; 597 598 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 599 600 mboxes = <&apss_shared 10>; 601 602 qcom,local-pid = <0>; 603 qcom,remote-pid = <2>; 604 605 adsp_smp2p_out: master-kernel { 606 qcom,entry-name = "master-kernel"; 607 #qcom,smem-state-cells = <1>; 608 }; 609 610 adsp_smp2p_in: slave-kernel { 611 qcom,entry-name = "slave-kernel"; 612 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 }; 616 }; 617 618 smp2p-mpss { 619 compatible = "qcom,smp2p"; 620 qcom,smem = <435>, <428>; 621 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 622 mboxes = <&apss_shared 14>; 623 qcom,local-pid = <0>; 624 qcom,remote-pid = <1>; 625 626 modem_smp2p_out: master-kernel { 627 qcom,entry-name = "master-kernel"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 modem_smp2p_in: slave-kernel { 632 qcom,entry-name = "slave-kernel"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 637 ipa_smp2p_out: ipa-ap-to-modem { 638 qcom,entry-name = "ipa"; 639 #qcom,smem-state-cells = <1>; 640 }; 641 642 ipa_smp2p_in: ipa-modem-to-ap { 643 qcom,entry-name = "ipa"; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 }; 648 649 psci { 650 compatible = "arm,psci-1.0"; 651 method = "smc"; 652 }; 653 654 soc: soc@0 { 655 #address-cells = <2>; 656 #size-cells = <2>; 657 ranges = <0 0 0 0 0x10 0>; 658 dma-ranges = <0 0 0 0 0x10 0>; 659 compatible = "simple-bus"; 660 661 gcc: clock-controller@100000 { 662 compatible = "qcom,gcc-sc7180"; 663 reg = <0 0x00100000 0 0x1f0000>; 664 clocks = <&rpmhcc RPMH_CXO_CLK>, 665 <&rpmhcc RPMH_CXO_CLK_A>, 666 <&sleep_clk>; 667 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 668 #clock-cells = <1>; 669 #reset-cells = <1>; 670 #power-domain-cells = <1>; 671 }; 672 673 qfprom: efuse@784000 { 674 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 675 reg = <0 0x00784000 0 0x7a0>, 676 <0 0x00780000 0 0x7a0>, 677 <0 0x00782000 0 0x100>, 678 <0 0x00786000 0 0x1fff>; 679 680 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 681 clock-names = "core"; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 685 qusb2p_hstx_trim: hstx-trim-primary@25b { 686 reg = <0x25b 0x1>; 687 bits = <1 3>; 688 }; 689 690 gpu_speed_bin: gpu_speed_bin@1d2 { 691 reg = <0x1d2 0x2>; 692 bits = <5 8>; 693 }; 694 }; 695 696 sdhc_1: sdhci@7c4000 { 697 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 698 reg = <0 0x7c4000 0 0x1000>, 699 <0 0x07c5000 0 0x1000>; 700 reg-names = "hc", "cqhci"; 701 702 iommus = <&apps_smmu 0x60 0x0>; 703 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-names = "hc_irq", "pwr_irq"; 706 707 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 708 <&gcc GCC_SDCC1_AHB_CLK>, 709 <&rpmhcc RPMH_CXO_CLK>; 710 clock-names = "core", "iface", "xo"; 711 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 712 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 713 interconnect-names = "sdhc-ddr","cpu-sdhc"; 714 power-domains = <&rpmhpd SC7180_CX>; 715 operating-points-v2 = <&sdhc1_opp_table>; 716 717 bus-width = <8>; 718 non-removable; 719 supports-cqe; 720 721 mmc-ddr-1_8v; 722 mmc-hs200-1_8v; 723 mmc-hs400-1_8v; 724 mmc-hs400-enhanced-strobe; 725 726 status = "disabled"; 727 728 sdhc1_opp_table: sdhc1-opp-table { 729 compatible = "operating-points-v2"; 730 731 opp-100000000 { 732 opp-hz = /bits/ 64 <100000000>; 733 required-opps = <&rpmhpd_opp_low_svs>; 734 opp-peak-kBps = <1800000 600000>; 735 opp-avg-kBps = <100000 0>; 736 }; 737 738 opp-384000000 { 739 opp-hz = /bits/ 64 <384000000>; 740 required-opps = <&rpmhpd_opp_nom>; 741 opp-peak-kBps = <5400000 1600000>; 742 opp-avg-kBps = <390000 0>; 743 }; 744 }; 745 }; 746 747 qup_opp_table: qup-opp-table { 748 compatible = "operating-points-v2"; 749 750 opp-75000000 { 751 opp-hz = /bits/ 64 <75000000>; 752 required-opps = <&rpmhpd_opp_low_svs>; 753 }; 754 755 opp-100000000 { 756 opp-hz = /bits/ 64 <100000000>; 757 required-opps = <&rpmhpd_opp_svs>; 758 }; 759 760 opp-128000000 { 761 opp-hz = /bits/ 64 <128000000>; 762 required-opps = <&rpmhpd_opp_nom>; 763 }; 764 }; 765 766 qupv3_id_0: geniqup@8c0000 { 767 compatible = "qcom,geni-se-qup"; 768 reg = <0 0x008c0000 0 0x6000>; 769 clock-names = "m-ahb", "s-ahb"; 770 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 771 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 772 #address-cells = <2>; 773 #size-cells = <2>; 774 ranges; 775 iommus = <&apps_smmu 0x43 0x0>; 776 status = "disabled"; 777 778 i2c0: i2c@880000 { 779 compatible = "qcom,geni-i2c"; 780 reg = <0 0x00880000 0 0x4000>; 781 clock-names = "se"; 782 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&qup_i2c0_default>; 785 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 789 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 790 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 791 interconnect-names = "qup-core", "qup-config", 792 "qup-memory"; 793 power-domains = <&rpmhpd SC7180_CX>; 794 required-opps = <&rpmhpd_opp_low_svs>; 795 status = "disabled"; 796 }; 797 798 spi0: spi@880000 { 799 compatible = "qcom,geni-spi"; 800 reg = <0 0x00880000 0 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_spi0_default>; 805 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 power-domains = <&rpmhpd SC7180_CX>; 809 operating-points-v2 = <&qup_opp_table>; 810 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 811 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 812 interconnect-names = "qup-core", "qup-config"; 813 status = "disabled"; 814 }; 815 816 uart0: serial@880000 { 817 compatible = "qcom,geni-uart"; 818 reg = <0 0x00880000 0 0x4000>; 819 clock-names = "se"; 820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&qup_uart0_default>; 823 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 824 power-domains = <&rpmhpd SC7180_CX>; 825 operating-points-v2 = <&qup_opp_table>; 826 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 827 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 828 interconnect-names = "qup-core", "qup-config"; 829 status = "disabled"; 830 }; 831 832 i2c1: i2c@884000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0 0x00884000 0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c1_default>; 839 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 843 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 844 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 845 interconnect-names = "qup-core", "qup-config", 846 "qup-memory"; 847 power-domains = <&rpmhpd SC7180_CX>; 848 required-opps = <&rpmhpd_opp_low_svs>; 849 status = "disabled"; 850 }; 851 852 spi1: spi@884000 { 853 compatible = "qcom,geni-spi"; 854 reg = <0 0x00884000 0 0x4000>; 855 clock-names = "se"; 856 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 857 pinctrl-names = "default"; 858 pinctrl-0 = <&qup_spi1_default>; 859 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 power-domains = <&rpmhpd SC7180_CX>; 863 operating-points-v2 = <&qup_opp_table>; 864 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 865 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 866 interconnect-names = "qup-core", "qup-config"; 867 status = "disabled"; 868 }; 869 870 uart1: serial@884000 { 871 compatible = "qcom,geni-uart"; 872 reg = <0 0x00884000 0 0x4000>; 873 clock-names = "se"; 874 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&qup_uart1_default>; 877 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 878 power-domains = <&rpmhpd SC7180_CX>; 879 operating-points-v2 = <&qup_opp_table>; 880 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 881 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 882 interconnect-names = "qup-core", "qup-config"; 883 status = "disabled"; 884 }; 885 886 i2c2: i2c@888000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0 0x00888000 0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c2_default>; 893 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", 900 "qup-memory"; 901 power-domains = <&rpmhpd SC7180_CX>; 902 required-opps = <&rpmhpd_opp_low_svs>; 903 status = "disabled"; 904 }; 905 906 uart2: serial@888000 { 907 compatible = "qcom,geni-uart"; 908 reg = <0 0x00888000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_uart2_default>; 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 914 power-domains = <&rpmhpd SC7180_CX>; 915 operating-points-v2 = <&qup_opp_table>; 916 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 917 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 918 interconnect-names = "qup-core", "qup-config"; 919 status = "disabled"; 920 }; 921 922 i2c3: i2c@88c000 { 923 compatible = "qcom,geni-i2c"; 924 reg = <0 0x0088c000 0 0x4000>; 925 clock-names = "se"; 926 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&qup_i2c3_default>; 929 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 934 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", 936 "qup-memory"; 937 power-domains = <&rpmhpd SC7180_CX>; 938 required-opps = <&rpmhpd_opp_low_svs>; 939 status = "disabled"; 940 }; 941 942 spi3: spi@88c000 { 943 compatible = "qcom,geni-spi"; 944 reg = <0 0x0088c000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_spi3_default>; 949 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 power-domains = <&rpmhpd SC7180_CX>; 953 operating-points-v2 = <&qup_opp_table>; 954 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 956 interconnect-names = "qup-core", "qup-config"; 957 status = "disabled"; 958 }; 959 960 uart3: serial@88c000 { 961 compatible = "qcom,geni-uart"; 962 reg = <0 0x0088c000 0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_uart3_default>; 967 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 968 power-domains = <&rpmhpd SC7180_CX>; 969 operating-points-v2 = <&qup_opp_table>; 970 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 972 interconnect-names = "qup-core", "qup-config"; 973 status = "disabled"; 974 }; 975 976 i2c4: i2c@890000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0 0x00890000 0 0x4000>; 979 clock-names = "se"; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_i2c4_default>; 983 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 988 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 989 interconnect-names = "qup-core", "qup-config", 990 "qup-memory"; 991 power-domains = <&rpmhpd SC7180_CX>; 992 required-opps = <&rpmhpd_opp_low_svs>; 993 status = "disabled"; 994 }; 995 996 uart4: serial@890000 { 997 compatible = "qcom,geni-uart"; 998 reg = <0 0x00890000 0 0x4000>; 999 clock-names = "se"; 1000 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&qup_uart4_default>; 1003 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1004 power-domains = <&rpmhpd SC7180_CX>; 1005 operating-points-v2 = <&qup_opp_table>; 1006 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1007 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1008 interconnect-names = "qup-core", "qup-config"; 1009 status = "disabled"; 1010 }; 1011 1012 i2c5: i2c@894000 { 1013 compatible = "qcom,geni-i2c"; 1014 reg = <0 0x00894000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_i2c5_default>; 1019 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1023 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1024 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1025 interconnect-names = "qup-core", "qup-config", 1026 "qup-memory"; 1027 power-domains = <&rpmhpd SC7180_CX>; 1028 required-opps = <&rpmhpd_opp_low_svs>; 1029 status = "disabled"; 1030 }; 1031 1032 spi5: spi@894000 { 1033 compatible = "qcom,geni-spi"; 1034 reg = <0 0x00894000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_spi5_default>; 1039 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 power-domains = <&rpmhpd SC7180_CX>; 1043 operating-points-v2 = <&qup_opp_table>; 1044 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1046 interconnect-names = "qup-core", "qup-config"; 1047 status = "disabled"; 1048 }; 1049 1050 uart5: serial@894000 { 1051 compatible = "qcom,geni-uart"; 1052 reg = <0 0x00894000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&qup_uart5_default>; 1057 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1058 power-domains = <&rpmhpd SC7180_CX>; 1059 operating-points-v2 = <&qup_opp_table>; 1060 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1062 interconnect-names = "qup-core", "qup-config"; 1063 status = "disabled"; 1064 }; 1065 }; 1066 1067 qupv3_id_1: geniqup@ac0000 { 1068 compatible = "qcom,geni-se-qup"; 1069 reg = <0 0x00ac0000 0 0x6000>; 1070 clock-names = "m-ahb", "s-ahb"; 1071 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1072 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1073 #address-cells = <2>; 1074 #size-cells = <2>; 1075 ranges; 1076 iommus = <&apps_smmu 0x4c3 0x0>; 1077 status = "disabled"; 1078 1079 i2c6: i2c@a80000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x00a80000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_i2c6_default>; 1086 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1090 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1091 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1092 interconnect-names = "qup-core", "qup-config", 1093 "qup-memory"; 1094 power-domains = <&rpmhpd SC7180_CX>; 1095 required-opps = <&rpmhpd_opp_low_svs>; 1096 status = "disabled"; 1097 }; 1098 1099 spi6: spi@a80000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0 0x00a80000 0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&qup_spi6_default>; 1106 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 power-domains = <&rpmhpd SC7180_CX>; 1110 operating-points-v2 = <&qup_opp_table>; 1111 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1112 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1113 interconnect-names = "qup-core", "qup-config"; 1114 status = "disabled"; 1115 }; 1116 1117 uart6: serial@a80000 { 1118 compatible = "qcom,geni-uart"; 1119 reg = <0 0x00a80000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_uart6_default>; 1124 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1125 power-domains = <&rpmhpd SC7180_CX>; 1126 operating-points-v2 = <&qup_opp_table>; 1127 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1128 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1129 interconnect-names = "qup-core", "qup-config"; 1130 status = "disabled"; 1131 }; 1132 1133 i2c7: i2c@a84000 { 1134 compatible = "qcom,geni-i2c"; 1135 reg = <0 0x00a84000 0 0x4000>; 1136 clock-names = "se"; 1137 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_i2c7_default>; 1140 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1145 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1146 interconnect-names = "qup-core", "qup-config", 1147 "qup-memory"; 1148 power-domains = <&rpmhpd SC7180_CX>; 1149 required-opps = <&rpmhpd_opp_low_svs>; 1150 status = "disabled"; 1151 }; 1152 1153 uart7: serial@a84000 { 1154 compatible = "qcom,geni-uart"; 1155 reg = <0 0x00a84000 0 0x4000>; 1156 clock-names = "se"; 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_uart7_default>; 1160 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1161 power-domains = <&rpmhpd SC7180_CX>; 1162 operating-points-v2 = <&qup_opp_table>; 1163 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1165 interconnect-names = "qup-core", "qup-config"; 1166 status = "disabled"; 1167 }; 1168 1169 i2c8: i2c@a88000 { 1170 compatible = "qcom,geni-i2c"; 1171 reg = <0 0x00a88000 0 0x4000>; 1172 clock-names = "se"; 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_i2c8_default>; 1176 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1180 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1181 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1182 interconnect-names = "qup-core", "qup-config", 1183 "qup-memory"; 1184 power-domains = <&rpmhpd SC7180_CX>; 1185 required-opps = <&rpmhpd_opp_low_svs>; 1186 status = "disabled"; 1187 }; 1188 1189 spi8: spi@a88000 { 1190 compatible = "qcom,geni-spi"; 1191 reg = <0 0x00a88000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_spi8_default>; 1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 power-domains = <&rpmhpd SC7180_CX>; 1200 operating-points-v2 = <&qup_opp_table>; 1201 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1202 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1203 interconnect-names = "qup-core", "qup-config"; 1204 status = "disabled"; 1205 }; 1206 1207 uart8: serial@a88000 { 1208 compatible = "qcom,geni-debug-uart"; 1209 reg = <0 0x00a88000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_uart8_default>; 1214 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd SC7180_CX>; 1216 operating-points-v2 = <&qup_opp_table>; 1217 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1218 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1219 interconnect-names = "qup-core", "qup-config"; 1220 status = "disabled"; 1221 }; 1222 1223 i2c9: i2c@a8c000 { 1224 compatible = "qcom,geni-i2c"; 1225 reg = <0 0x00a8c000 0 0x4000>; 1226 clock-names = "se"; 1227 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&qup_i2c9_default>; 1230 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1234 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1235 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1236 interconnect-names = "qup-core", "qup-config", 1237 "qup-memory"; 1238 power-domains = <&rpmhpd SC7180_CX>; 1239 required-opps = <&rpmhpd_opp_low_svs>; 1240 status = "disabled"; 1241 }; 1242 1243 uart9: serial@a8c000 { 1244 compatible = "qcom,geni-uart"; 1245 reg = <0 0x00a8c000 0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_uart9_default>; 1250 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1251 power-domains = <&rpmhpd SC7180_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1255 interconnect-names = "qup-core", "qup-config"; 1256 status = "disabled"; 1257 }; 1258 1259 i2c10: i2c@a90000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0 0x00a90000 0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_i2c10_default>; 1266 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1270 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1271 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1272 interconnect-names = "qup-core", "qup-config", 1273 "qup-memory"; 1274 power-domains = <&rpmhpd SC7180_CX>; 1275 required-opps = <&rpmhpd_opp_low_svs>; 1276 status = "disabled"; 1277 }; 1278 1279 spi10: spi@a90000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0 0x00a90000 0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi10_default>; 1286 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 power-domains = <&rpmhpd SC7180_CX>; 1290 operating-points-v2 = <&qup_opp_table>; 1291 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1292 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1293 interconnect-names = "qup-core", "qup-config"; 1294 status = "disabled"; 1295 }; 1296 1297 uart10: serial@a90000 { 1298 compatible = "qcom,geni-uart"; 1299 reg = <0 0x00a90000 0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_uart10_default>; 1304 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1305 power-domains = <&rpmhpd SC7180_CX>; 1306 operating-points-v2 = <&qup_opp_table>; 1307 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1308 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 status = "disabled"; 1311 }; 1312 1313 i2c11: i2c@a94000 { 1314 compatible = "qcom,geni-i2c"; 1315 reg = <0 0x00a94000 0 0x4000>; 1316 clock-names = "se"; 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_i2c11_default>; 1320 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1324 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1325 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1326 interconnect-names = "qup-core", "qup-config", 1327 "qup-memory"; 1328 power-domains = <&rpmhpd SC7180_CX>; 1329 required-opps = <&rpmhpd_opp_low_svs>; 1330 status = "disabled"; 1331 }; 1332 1333 spi11: spi@a94000 { 1334 compatible = "qcom,geni-spi"; 1335 reg = <0 0x00a94000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_spi11_default>; 1340 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 power-domains = <&rpmhpd SC7180_CX>; 1344 operating-points-v2 = <&qup_opp_table>; 1345 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1346 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1347 interconnect-names = "qup-core", "qup-config"; 1348 status = "disabled"; 1349 }; 1350 1351 uart11: serial@a94000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0 0x00a94000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&qup_uart11_default>; 1358 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1359 power-domains = <&rpmhpd SC7180_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 status = "disabled"; 1365 }; 1366 }; 1367 1368 config_noc: interconnect@1500000 { 1369 compatible = "qcom,sc7180-config-noc"; 1370 reg = <0 0x01500000 0 0x28000>; 1371 #interconnect-cells = <2>; 1372 qcom,bcm-voters = <&apps_bcm_voter>; 1373 }; 1374 1375 system_noc: interconnect@1620000 { 1376 compatible = "qcom,sc7180-system-noc"; 1377 reg = <0 0x01620000 0 0x17080>; 1378 #interconnect-cells = <2>; 1379 qcom,bcm-voters = <&apps_bcm_voter>; 1380 }; 1381 1382 mc_virt: interconnect@1638000 { 1383 compatible = "qcom,sc7180-mc-virt"; 1384 reg = <0 0x01638000 0 0x1000>; 1385 #interconnect-cells = <2>; 1386 qcom,bcm-voters = <&apps_bcm_voter>; 1387 }; 1388 1389 qup_virt: interconnect@1650000 { 1390 compatible = "qcom,sc7180-qup-virt"; 1391 reg = <0 0x01650000 0 0x1000>; 1392 #interconnect-cells = <2>; 1393 qcom,bcm-voters = <&apps_bcm_voter>; 1394 }; 1395 1396 aggre1_noc: interconnect@16e0000 { 1397 compatible = "qcom,sc7180-aggre1-noc"; 1398 reg = <0 0x016e0000 0 0x15080>; 1399 #interconnect-cells = <2>; 1400 qcom,bcm-voters = <&apps_bcm_voter>; 1401 }; 1402 1403 aggre2_noc: interconnect@1705000 { 1404 compatible = "qcom,sc7180-aggre2-noc"; 1405 reg = <0 0x01705000 0 0x9000>; 1406 #interconnect-cells = <2>; 1407 qcom,bcm-voters = <&apps_bcm_voter>; 1408 }; 1409 1410 compute_noc: interconnect@170e000 { 1411 compatible = "qcom,sc7180-compute-noc"; 1412 reg = <0 0x0170e000 0 0x6000>; 1413 #interconnect-cells = <2>; 1414 qcom,bcm-voters = <&apps_bcm_voter>; 1415 }; 1416 1417 mmss_noc: interconnect@1740000 { 1418 compatible = "qcom,sc7180-mmss-noc"; 1419 reg = <0 0x01740000 0 0x1c100>; 1420 #interconnect-cells = <2>; 1421 qcom,bcm-voters = <&apps_bcm_voter>; 1422 }; 1423 1424 ipa_virt: interconnect@1e00000 { 1425 compatible = "qcom,sc7180-ipa-virt"; 1426 reg = <0 0x01e00000 0 0x1000>; 1427 #interconnect-cells = <2>; 1428 qcom,bcm-voters = <&apps_bcm_voter>; 1429 }; 1430 1431 ipa: ipa@1e40000 { 1432 compatible = "qcom,sc7180-ipa"; 1433 1434 iommus = <&apps_smmu 0x440 0x0>, 1435 <&apps_smmu 0x442 0x0>; 1436 reg = <0 0x1e40000 0 0x7000>, 1437 <0 0x1e47000 0 0x2000>, 1438 <0 0x1e04000 0 0x2c000>; 1439 reg-names = "ipa-reg", 1440 "ipa-shared", 1441 "gsi"; 1442 1443 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1444 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1445 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1446 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1447 interrupt-names = "ipa", 1448 "gsi", 1449 "ipa-clock-query", 1450 "ipa-setup-ready"; 1451 1452 clocks = <&rpmhcc RPMH_IPA_CLK>; 1453 clock-names = "core"; 1454 1455 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1456 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1457 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1458 interconnect-names = "memory", 1459 "imem", 1460 "config"; 1461 1462 qcom,smem-states = <&ipa_smp2p_out 0>, 1463 <&ipa_smp2p_out 1>; 1464 qcom,smem-state-names = "ipa-clock-enabled-valid", 1465 "ipa-clock-enabled"; 1466 1467 status = "disabled"; 1468 }; 1469 1470 tcsr_mutex_regs: syscon@1f40000 { 1471 compatible = "syscon"; 1472 reg = <0 0x01f40000 0 0x40000>; 1473 }; 1474 1475 tcsr_regs: syscon@1fc0000 { 1476 compatible = "syscon"; 1477 reg = <0 0x01fc0000 0 0x40000>; 1478 }; 1479 1480 tlmm: pinctrl@3500000 { 1481 compatible = "qcom,sc7180-pinctrl"; 1482 reg = <0 0x03500000 0 0x300000>, 1483 <0 0x03900000 0 0x300000>, 1484 <0 0x03d00000 0 0x300000>; 1485 reg-names = "west", "north", "south"; 1486 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1487 gpio-controller; 1488 #gpio-cells = <2>; 1489 interrupt-controller; 1490 #interrupt-cells = <2>; 1491 gpio-ranges = <&tlmm 0 0 120>; 1492 wakeup-parent = <&pdc>; 1493 1494 dp_hot_plug_det: dp-hot-plug-det { 1495 pinmux { 1496 pins = "gpio117"; 1497 function = "dp_hot"; 1498 }; 1499 }; 1500 1501 qspi_clk: qspi-clk { 1502 pinmux { 1503 pins = "gpio63"; 1504 function = "qspi_clk"; 1505 }; 1506 }; 1507 1508 qspi_cs0: qspi-cs0 { 1509 pinmux { 1510 pins = "gpio68"; 1511 function = "qspi_cs"; 1512 }; 1513 }; 1514 1515 qspi_cs1: qspi-cs1 { 1516 pinmux { 1517 pins = "gpio72"; 1518 function = "qspi_cs"; 1519 }; 1520 }; 1521 1522 qspi_data01: qspi-data01 { 1523 pinmux-data { 1524 pins = "gpio64", "gpio65"; 1525 function = "qspi_data"; 1526 }; 1527 }; 1528 1529 qspi_data12: qspi-data12 { 1530 pinmux-data { 1531 pins = "gpio66", "gpio67"; 1532 function = "qspi_data"; 1533 }; 1534 }; 1535 1536 qup_i2c0_default: qup-i2c0-default { 1537 pinmux { 1538 pins = "gpio34", "gpio35"; 1539 function = "qup00"; 1540 }; 1541 }; 1542 1543 qup_i2c1_default: qup-i2c1-default { 1544 pinmux { 1545 pins = "gpio0", "gpio1"; 1546 function = "qup01"; 1547 }; 1548 }; 1549 1550 qup_i2c2_default: qup-i2c2-default { 1551 pinmux { 1552 pins = "gpio15", "gpio16"; 1553 function = "qup02_i2c"; 1554 }; 1555 }; 1556 1557 qup_i2c3_default: qup-i2c3-default { 1558 pinmux { 1559 pins = "gpio38", "gpio39"; 1560 function = "qup03"; 1561 }; 1562 }; 1563 1564 qup_i2c4_default: qup-i2c4-default { 1565 pinmux { 1566 pins = "gpio115", "gpio116"; 1567 function = "qup04_i2c"; 1568 }; 1569 }; 1570 1571 qup_i2c5_default: qup-i2c5-default { 1572 pinmux { 1573 pins = "gpio25", "gpio26"; 1574 function = "qup05"; 1575 }; 1576 }; 1577 1578 qup_i2c6_default: qup-i2c6-default { 1579 pinmux { 1580 pins = "gpio59", "gpio60"; 1581 function = "qup10"; 1582 }; 1583 }; 1584 1585 qup_i2c7_default: qup-i2c7-default { 1586 pinmux { 1587 pins = "gpio6", "gpio7"; 1588 function = "qup11_i2c"; 1589 }; 1590 }; 1591 1592 qup_i2c8_default: qup-i2c8-default { 1593 pinmux { 1594 pins = "gpio42", "gpio43"; 1595 function = "qup12"; 1596 }; 1597 }; 1598 1599 qup_i2c9_default: qup-i2c9-default { 1600 pinmux { 1601 pins = "gpio46", "gpio47"; 1602 function = "qup13_i2c"; 1603 }; 1604 }; 1605 1606 qup_i2c10_default: qup-i2c10-default { 1607 pinmux { 1608 pins = "gpio86", "gpio87"; 1609 function = "qup14"; 1610 }; 1611 }; 1612 1613 qup_i2c11_default: qup-i2c11-default { 1614 pinmux { 1615 pins = "gpio53", "gpio54"; 1616 function = "qup15"; 1617 }; 1618 }; 1619 1620 qup_spi0_default: qup-spi0-default { 1621 pinmux { 1622 pins = "gpio34", "gpio35", 1623 "gpio36", "gpio37"; 1624 function = "qup00"; 1625 }; 1626 }; 1627 1628 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 1629 pinmux { 1630 pins = "gpio34", "gpio35", 1631 "gpio36"; 1632 function = "qup00"; 1633 }; 1634 1635 pinmux-cs { 1636 pins = "gpio37"; 1637 function = "gpio"; 1638 }; 1639 }; 1640 1641 qup_spi1_default: qup-spi1-default { 1642 pinmux { 1643 pins = "gpio0", "gpio1", 1644 "gpio2", "gpio3"; 1645 function = "qup01"; 1646 }; 1647 }; 1648 1649 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 1650 pinmux { 1651 pins = "gpio0", "gpio1", 1652 "gpio2"; 1653 function = "qup01"; 1654 }; 1655 1656 pinmux-cs { 1657 pins = "gpio3"; 1658 function = "gpio"; 1659 }; 1660 }; 1661 1662 qup_spi3_default: qup-spi3-default { 1663 pinmux { 1664 pins = "gpio38", "gpio39", 1665 "gpio40", "gpio41"; 1666 function = "qup03"; 1667 }; 1668 }; 1669 1670 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 1671 pinmux { 1672 pins = "gpio38", "gpio39", 1673 "gpio40"; 1674 function = "qup03"; 1675 }; 1676 1677 pinmux-cs { 1678 pins = "gpio41"; 1679 function = "gpio"; 1680 }; 1681 }; 1682 1683 qup_spi5_default: qup-spi5-default { 1684 pinmux { 1685 pins = "gpio25", "gpio26", 1686 "gpio27", "gpio28"; 1687 function = "qup05"; 1688 }; 1689 }; 1690 1691 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 1692 pinmux { 1693 pins = "gpio25", "gpio26", 1694 "gpio27"; 1695 function = "qup05"; 1696 }; 1697 1698 pinmux-cs { 1699 pins = "gpio28"; 1700 function = "gpio"; 1701 }; 1702 }; 1703 1704 qup_spi6_default: qup-spi6-default { 1705 pinmux { 1706 pins = "gpio59", "gpio60", 1707 "gpio61", "gpio62"; 1708 function = "qup10"; 1709 }; 1710 }; 1711 1712 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 1713 pinmux { 1714 pins = "gpio59", "gpio60", 1715 "gpio61"; 1716 function = "qup10"; 1717 }; 1718 1719 pinmux-cs { 1720 pins = "gpio62"; 1721 function = "gpio"; 1722 }; 1723 }; 1724 1725 qup_spi8_default: qup-spi8-default { 1726 pinmux { 1727 pins = "gpio42", "gpio43", 1728 "gpio44", "gpio45"; 1729 function = "qup12"; 1730 }; 1731 }; 1732 1733 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 1734 pinmux { 1735 pins = "gpio42", "gpio43", 1736 "gpio44"; 1737 function = "qup12"; 1738 }; 1739 1740 pinmux-cs { 1741 pins = "gpio45"; 1742 function = "gpio"; 1743 }; 1744 }; 1745 1746 qup_spi10_default: qup-spi10-default { 1747 pinmux { 1748 pins = "gpio86", "gpio87", 1749 "gpio88", "gpio89"; 1750 function = "qup14"; 1751 }; 1752 }; 1753 1754 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 1755 pinmux { 1756 pins = "gpio86", "gpio87", 1757 "gpio88"; 1758 function = "qup14"; 1759 }; 1760 1761 pinmux-cs { 1762 pins = "gpio89"; 1763 function = "gpio"; 1764 }; 1765 }; 1766 1767 qup_spi11_default: qup-spi11-default { 1768 pinmux { 1769 pins = "gpio53", "gpio54", 1770 "gpio55", "gpio56"; 1771 function = "qup15"; 1772 }; 1773 }; 1774 1775 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 1776 pinmux { 1777 pins = "gpio53", "gpio54", 1778 "gpio55"; 1779 function = "qup15"; 1780 }; 1781 1782 pinmux-cs { 1783 pins = "gpio56"; 1784 function = "gpio"; 1785 }; 1786 }; 1787 1788 qup_uart0_default: qup-uart0-default { 1789 pinmux { 1790 pins = "gpio34", "gpio35", 1791 "gpio36", "gpio37"; 1792 function = "qup00"; 1793 }; 1794 }; 1795 1796 qup_uart1_default: qup-uart1-default { 1797 pinmux { 1798 pins = "gpio0", "gpio1", 1799 "gpio2", "gpio3"; 1800 function = "qup01"; 1801 }; 1802 }; 1803 1804 qup_uart2_default: qup-uart2-default { 1805 pinmux { 1806 pins = "gpio15", "gpio16"; 1807 function = "qup02_uart"; 1808 }; 1809 }; 1810 1811 qup_uart3_default: qup-uart3-default { 1812 pinmux { 1813 pins = "gpio38", "gpio39", 1814 "gpio40", "gpio41"; 1815 function = "qup03"; 1816 }; 1817 }; 1818 1819 qup_uart4_default: qup-uart4-default { 1820 pinmux { 1821 pins = "gpio115", "gpio116"; 1822 function = "qup04_uart"; 1823 }; 1824 }; 1825 1826 qup_uart5_default: qup-uart5-default { 1827 pinmux { 1828 pins = "gpio25", "gpio26", 1829 "gpio27", "gpio28"; 1830 function = "qup05"; 1831 }; 1832 }; 1833 1834 qup_uart6_default: qup-uart6-default { 1835 pinmux { 1836 pins = "gpio59", "gpio60", 1837 "gpio61", "gpio62"; 1838 function = "qup10"; 1839 }; 1840 }; 1841 1842 qup_uart7_default: qup-uart7-default { 1843 pinmux { 1844 pins = "gpio6", "gpio7"; 1845 function = "qup11_uart"; 1846 }; 1847 }; 1848 1849 qup_uart8_default: qup-uart8-default { 1850 pinmux { 1851 pins = "gpio44", "gpio45"; 1852 function = "qup12"; 1853 }; 1854 }; 1855 1856 qup_uart9_default: qup-uart9-default { 1857 pinmux { 1858 pins = "gpio46", "gpio47"; 1859 function = "qup13_uart"; 1860 }; 1861 }; 1862 1863 qup_uart10_default: qup-uart10-default { 1864 pinmux { 1865 pins = "gpio86", "gpio87", 1866 "gpio88", "gpio89"; 1867 function = "qup14"; 1868 }; 1869 }; 1870 1871 qup_uart11_default: qup-uart11-default { 1872 pinmux { 1873 pins = "gpio53", "gpio54", 1874 "gpio55", "gpio56"; 1875 function = "qup15"; 1876 }; 1877 }; 1878 1879 sec_mi2s_active: sec-mi2s-active { 1880 pinmux { 1881 pins = "gpio49", "gpio50", "gpio51"; 1882 function = "mi2s_1"; 1883 }; 1884 }; 1885 1886 pri_mi2s_active: pri-mi2s-active { 1887 pinmux { 1888 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1889 function = "mi2s_0"; 1890 }; 1891 }; 1892 1893 pri_mi2s_mclk_active: pri-mi2s-mclk-active { 1894 pinmux { 1895 pins = "gpio57"; 1896 function = "lpass_ext"; 1897 }; 1898 }; 1899 }; 1900 1901 remoteproc_mpss: remoteproc@4080000 { 1902 compatible = "qcom,sc7180-mpss-pas"; 1903 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1904 reg-names = "qdsp6", "rmb"; 1905 1906 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1907 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1908 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1909 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1910 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1911 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1912 interrupt-names = "wdog", "fatal", "ready", "handover", 1913 "stop-ack", "shutdown-ack"; 1914 1915 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1916 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1917 <&gcc GCC_MSS_NAV_AXI_CLK>, 1918 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1919 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1920 <&rpmhcc RPMH_CXO_CLK>; 1921 clock-names = "iface", "bus", "nav", "snoc_axi", 1922 "mnoc_axi", "xo"; 1923 1924 power-domains = <&rpmhpd SC7180_CX>, 1925 <&rpmhpd SC7180_MX>, 1926 <&rpmhpd SC7180_MSS>; 1927 power-domain-names = "cx", "mx", "mss"; 1928 1929 memory-region = <&mpss_mem>; 1930 1931 qcom,qmp = <&aoss_qmp>; 1932 1933 qcom,smem-states = <&modem_smp2p_out 0>; 1934 qcom,smem-state-names = "stop"; 1935 1936 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1937 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1938 reset-names = "mss_restart", "pdc_reset"; 1939 1940 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1941 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 1942 1943 status = "disabled"; 1944 1945 glink-edge { 1946 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1947 label = "modem"; 1948 qcom,remote-pid = <1>; 1949 mboxes = <&apss_shared 12>; 1950 }; 1951 }; 1952 1953 gpu: gpu@5000000 { 1954 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1955 #stream-id-cells = <16>; 1956 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1957 <0 0x05061000 0 0x800>; 1958 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1959 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1960 iommus = <&adreno_smmu 0>; 1961 operating-points-v2 = <&gpu_opp_table>; 1962 qcom,gmu = <&gmu>; 1963 1964 #cooling-cells = <2>; 1965 1966 nvmem-cells = <&gpu_speed_bin>; 1967 nvmem-cell-names = "speed_bin"; 1968 1969 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1970 interconnect-names = "gfx-mem"; 1971 1972 gpu_opp_table: opp-table { 1973 compatible = "operating-points-v2"; 1974 1975 opp-825000000 { 1976 opp-hz = /bits/ 64 <825000000>; 1977 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1978 opp-peak-kBps = <8532000>; 1979 opp-supported-hw = <0x04>; 1980 }; 1981 1982 opp-800000000 { 1983 opp-hz = /bits/ 64 <800000000>; 1984 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1985 opp-peak-kBps = <8532000>; 1986 opp-supported-hw = <0x07>; 1987 }; 1988 1989 opp-650000000 { 1990 opp-hz = /bits/ 64 <650000000>; 1991 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1992 opp-peak-kBps = <7216000>; 1993 opp-supported-hw = <0x07>; 1994 }; 1995 1996 opp-565000000 { 1997 opp-hz = /bits/ 64 <565000000>; 1998 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1999 opp-peak-kBps = <5412000>; 2000 opp-supported-hw = <0x07>; 2001 }; 2002 2003 opp-430000000 { 2004 opp-hz = /bits/ 64 <430000000>; 2005 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2006 opp-peak-kBps = <5412000>; 2007 opp-supported-hw = <0x07>; 2008 }; 2009 2010 opp-355000000 { 2011 opp-hz = /bits/ 64 <355000000>; 2012 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2013 opp-peak-kBps = <3072000>; 2014 opp-supported-hw = <0x07>; 2015 }; 2016 2017 opp-267000000 { 2018 opp-hz = /bits/ 64 <267000000>; 2019 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2020 opp-peak-kBps = <3072000>; 2021 opp-supported-hw = <0x07>; 2022 }; 2023 2024 opp-180000000 { 2025 opp-hz = /bits/ 64 <180000000>; 2026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2027 opp-peak-kBps = <1804000>; 2028 opp-supported-hw = <0x07>; 2029 }; 2030 }; 2031 }; 2032 2033 adreno_smmu: iommu@5040000 { 2034 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2035 reg = <0 0x05040000 0 0x10000>; 2036 #iommu-cells = <1>; 2037 #global-interrupts = <2>; 2038 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2048 2049 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2050 <&gcc GCC_GPU_CFG_AHB_CLK>; 2051 clock-names = "bus", "iface"; 2052 2053 power-domains = <&gpucc CX_GDSC>; 2054 }; 2055 2056 gmu: gmu@506a000 { 2057 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2058 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2059 <0 0x0b490000 0 0x10000>; 2060 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2061 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2063 interrupt-names = "hfi", "gmu"; 2064 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2065 <&gpucc GPU_CC_CXO_CLK>, 2066 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2067 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2068 clock-names = "gmu", "cxo", "axi", "memnoc"; 2069 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2070 power-domain-names = "cx", "gx"; 2071 iommus = <&adreno_smmu 5>; 2072 operating-points-v2 = <&gmu_opp_table>; 2073 2074 gmu_opp_table: opp-table { 2075 compatible = "operating-points-v2"; 2076 2077 opp-200000000 { 2078 opp-hz = /bits/ 64 <200000000>; 2079 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2080 }; 2081 }; 2082 }; 2083 2084 gpucc: clock-controller@5090000 { 2085 compatible = "qcom,sc7180-gpucc"; 2086 reg = <0 0x05090000 0 0x9000>; 2087 clocks = <&rpmhcc RPMH_CXO_CLK>, 2088 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2089 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2090 clock-names = "bi_tcxo", 2091 "gcc_gpu_gpll0_clk_src", 2092 "gcc_gpu_gpll0_div_clk_src"; 2093 #clock-cells = <1>; 2094 #reset-cells = <1>; 2095 #power-domain-cells = <1>; 2096 }; 2097 2098 stm@6002000 { 2099 compatible = "arm,coresight-stm", "arm,primecell"; 2100 reg = <0 0x06002000 0 0x1000>, 2101 <0 0x16280000 0 0x180000>; 2102 reg-names = "stm-base", "stm-stimulus-base"; 2103 2104 clocks = <&aoss_qmp>; 2105 clock-names = "apb_pclk"; 2106 2107 out-ports { 2108 port { 2109 stm_out: endpoint { 2110 remote-endpoint = <&funnel0_in7>; 2111 }; 2112 }; 2113 }; 2114 }; 2115 2116 funnel@6041000 { 2117 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2118 reg = <0 0x06041000 0 0x1000>; 2119 2120 clocks = <&aoss_qmp>; 2121 clock-names = "apb_pclk"; 2122 2123 out-ports { 2124 port { 2125 funnel0_out: endpoint { 2126 remote-endpoint = <&merge_funnel_in0>; 2127 }; 2128 }; 2129 }; 2130 2131 in-ports { 2132 #address-cells = <1>; 2133 #size-cells = <0>; 2134 2135 port@7 { 2136 reg = <7>; 2137 funnel0_in7: endpoint { 2138 remote-endpoint = <&stm_out>; 2139 }; 2140 }; 2141 }; 2142 }; 2143 2144 funnel@6042000 { 2145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2146 reg = <0 0x06042000 0 0x1000>; 2147 2148 clocks = <&aoss_qmp>; 2149 clock-names = "apb_pclk"; 2150 2151 out-ports { 2152 port { 2153 funnel1_out: endpoint { 2154 remote-endpoint = <&merge_funnel_in1>; 2155 }; 2156 }; 2157 }; 2158 2159 in-ports { 2160 #address-cells = <1>; 2161 #size-cells = <0>; 2162 2163 port@4 { 2164 reg = <4>; 2165 funnel1_in4: endpoint { 2166 remote-endpoint = <&apss_merge_funnel_out>; 2167 }; 2168 }; 2169 }; 2170 }; 2171 2172 funnel@6045000 { 2173 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2174 reg = <0 0x06045000 0 0x1000>; 2175 2176 clocks = <&aoss_qmp>; 2177 clock-names = "apb_pclk"; 2178 2179 out-ports { 2180 port { 2181 merge_funnel_out: endpoint { 2182 remote-endpoint = <&swao_funnel_in>; 2183 }; 2184 }; 2185 }; 2186 2187 in-ports { 2188 #address-cells = <1>; 2189 #size-cells = <0>; 2190 2191 port@0 { 2192 reg = <0>; 2193 merge_funnel_in0: endpoint { 2194 remote-endpoint = <&funnel0_out>; 2195 }; 2196 }; 2197 2198 port@1 { 2199 reg = <1>; 2200 merge_funnel_in1: endpoint { 2201 remote-endpoint = <&funnel1_out>; 2202 }; 2203 }; 2204 }; 2205 }; 2206 2207 replicator@6046000 { 2208 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2209 reg = <0 0x06046000 0 0x1000>; 2210 2211 clocks = <&aoss_qmp>; 2212 clock-names = "apb_pclk"; 2213 2214 out-ports { 2215 port { 2216 replicator_out: endpoint { 2217 remote-endpoint = <&etr_in>; 2218 }; 2219 }; 2220 }; 2221 2222 in-ports { 2223 port { 2224 replicator_in: endpoint { 2225 remote-endpoint = <&swao_replicator_out>; 2226 }; 2227 }; 2228 }; 2229 }; 2230 2231 etr@6048000 { 2232 compatible = "arm,coresight-tmc", "arm,primecell"; 2233 reg = <0 0x06048000 0 0x1000>; 2234 iommus = <&apps_smmu 0x04a0 0x20>; 2235 2236 clocks = <&aoss_qmp>; 2237 clock-names = "apb_pclk"; 2238 arm,scatter-gather; 2239 2240 in-ports { 2241 port { 2242 etr_in: endpoint { 2243 remote-endpoint = <&replicator_out>; 2244 }; 2245 }; 2246 }; 2247 }; 2248 2249 funnel@6b04000 { 2250 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2251 reg = <0 0x06b04000 0 0x1000>; 2252 2253 clocks = <&aoss_qmp>; 2254 clock-names = "apb_pclk"; 2255 2256 out-ports { 2257 port { 2258 swao_funnel_out: endpoint { 2259 remote-endpoint = <&etf_in>; 2260 }; 2261 }; 2262 }; 2263 2264 in-ports { 2265 #address-cells = <1>; 2266 #size-cells = <0>; 2267 2268 port@7 { 2269 reg = <7>; 2270 swao_funnel_in: endpoint { 2271 remote-endpoint = <&merge_funnel_out>; 2272 }; 2273 }; 2274 }; 2275 }; 2276 2277 etf@6b05000 { 2278 compatible = "arm,coresight-tmc", "arm,primecell"; 2279 reg = <0 0x06b05000 0 0x1000>; 2280 2281 clocks = <&aoss_qmp>; 2282 clock-names = "apb_pclk"; 2283 2284 out-ports { 2285 port { 2286 etf_out: endpoint { 2287 remote-endpoint = <&swao_replicator_in>; 2288 }; 2289 }; 2290 }; 2291 2292 in-ports { 2293 port { 2294 etf_in: endpoint { 2295 remote-endpoint = <&swao_funnel_out>; 2296 }; 2297 }; 2298 }; 2299 }; 2300 2301 replicator@6b06000 { 2302 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2303 reg = <0 0x06b06000 0 0x1000>; 2304 2305 clocks = <&aoss_qmp>; 2306 clock-names = "apb_pclk"; 2307 qcom,replicator-loses-context; 2308 2309 out-ports { 2310 port { 2311 swao_replicator_out: endpoint { 2312 remote-endpoint = <&replicator_in>; 2313 }; 2314 }; 2315 }; 2316 2317 in-ports { 2318 port { 2319 swao_replicator_in: endpoint { 2320 remote-endpoint = <&etf_out>; 2321 }; 2322 }; 2323 }; 2324 }; 2325 2326 etm@7040000 { 2327 compatible = "arm,coresight-etm4x", "arm,primecell"; 2328 reg = <0 0x07040000 0 0x1000>; 2329 2330 cpu = <&CPU0>; 2331 2332 clocks = <&aoss_qmp>; 2333 clock-names = "apb_pclk"; 2334 arm,coresight-loses-context-with-cpu; 2335 qcom,skip-power-up; 2336 2337 out-ports { 2338 port { 2339 etm0_out: endpoint { 2340 remote-endpoint = <&apss_funnel_in0>; 2341 }; 2342 }; 2343 }; 2344 }; 2345 2346 etm@7140000 { 2347 compatible = "arm,coresight-etm4x", "arm,primecell"; 2348 reg = <0 0x07140000 0 0x1000>; 2349 2350 cpu = <&CPU1>; 2351 2352 clocks = <&aoss_qmp>; 2353 clock-names = "apb_pclk"; 2354 arm,coresight-loses-context-with-cpu; 2355 qcom,skip-power-up; 2356 2357 out-ports { 2358 port { 2359 etm1_out: endpoint { 2360 remote-endpoint = <&apss_funnel_in1>; 2361 }; 2362 }; 2363 }; 2364 }; 2365 2366 etm@7240000 { 2367 compatible = "arm,coresight-etm4x", "arm,primecell"; 2368 reg = <0 0x07240000 0 0x1000>; 2369 2370 cpu = <&CPU2>; 2371 2372 clocks = <&aoss_qmp>; 2373 clock-names = "apb_pclk"; 2374 arm,coresight-loses-context-with-cpu; 2375 qcom,skip-power-up; 2376 2377 out-ports { 2378 port { 2379 etm2_out: endpoint { 2380 remote-endpoint = <&apss_funnel_in2>; 2381 }; 2382 }; 2383 }; 2384 }; 2385 2386 etm@7340000 { 2387 compatible = "arm,coresight-etm4x", "arm,primecell"; 2388 reg = <0 0x07340000 0 0x1000>; 2389 2390 cpu = <&CPU3>; 2391 2392 clocks = <&aoss_qmp>; 2393 clock-names = "apb_pclk"; 2394 arm,coresight-loses-context-with-cpu; 2395 qcom,skip-power-up; 2396 2397 out-ports { 2398 port { 2399 etm3_out: endpoint { 2400 remote-endpoint = <&apss_funnel_in3>; 2401 }; 2402 }; 2403 }; 2404 }; 2405 2406 etm@7440000 { 2407 compatible = "arm,coresight-etm4x", "arm,primecell"; 2408 reg = <0 0x07440000 0 0x1000>; 2409 2410 cpu = <&CPU4>; 2411 2412 clocks = <&aoss_qmp>; 2413 clock-names = "apb_pclk"; 2414 arm,coresight-loses-context-with-cpu; 2415 qcom,skip-power-up; 2416 2417 out-ports { 2418 port { 2419 etm4_out: endpoint { 2420 remote-endpoint = <&apss_funnel_in4>; 2421 }; 2422 }; 2423 }; 2424 }; 2425 2426 etm@7540000 { 2427 compatible = "arm,coresight-etm4x", "arm,primecell"; 2428 reg = <0 0x07540000 0 0x1000>; 2429 2430 cpu = <&CPU5>; 2431 2432 clocks = <&aoss_qmp>; 2433 clock-names = "apb_pclk"; 2434 arm,coresight-loses-context-with-cpu; 2435 qcom,skip-power-up; 2436 2437 out-ports { 2438 port { 2439 etm5_out: endpoint { 2440 remote-endpoint = <&apss_funnel_in5>; 2441 }; 2442 }; 2443 }; 2444 }; 2445 2446 etm@7640000 { 2447 compatible = "arm,coresight-etm4x", "arm,primecell"; 2448 reg = <0 0x07640000 0 0x1000>; 2449 2450 cpu = <&CPU6>; 2451 2452 clocks = <&aoss_qmp>; 2453 clock-names = "apb_pclk"; 2454 arm,coresight-loses-context-with-cpu; 2455 qcom,skip-power-up; 2456 2457 out-ports { 2458 port { 2459 etm6_out: endpoint { 2460 remote-endpoint = <&apss_funnel_in6>; 2461 }; 2462 }; 2463 }; 2464 }; 2465 2466 etm@7740000 { 2467 compatible = "arm,coresight-etm4x", "arm,primecell"; 2468 reg = <0 0x07740000 0 0x1000>; 2469 2470 cpu = <&CPU7>; 2471 2472 clocks = <&aoss_qmp>; 2473 clock-names = "apb_pclk"; 2474 arm,coresight-loses-context-with-cpu; 2475 qcom,skip-power-up; 2476 2477 out-ports { 2478 port { 2479 etm7_out: endpoint { 2480 remote-endpoint = <&apss_funnel_in7>; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 funnel@7800000 { /* APSS Funnel */ 2487 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2488 reg = <0 0x07800000 0 0x1000>; 2489 2490 clocks = <&aoss_qmp>; 2491 clock-names = "apb_pclk"; 2492 2493 out-ports { 2494 port { 2495 apss_funnel_out: endpoint { 2496 remote-endpoint = <&apss_merge_funnel_in>; 2497 }; 2498 }; 2499 }; 2500 2501 in-ports { 2502 #address-cells = <1>; 2503 #size-cells = <0>; 2504 2505 port@0 { 2506 reg = <0>; 2507 apss_funnel_in0: endpoint { 2508 remote-endpoint = <&etm0_out>; 2509 }; 2510 }; 2511 2512 port@1 { 2513 reg = <1>; 2514 apss_funnel_in1: endpoint { 2515 remote-endpoint = <&etm1_out>; 2516 }; 2517 }; 2518 2519 port@2 { 2520 reg = <2>; 2521 apss_funnel_in2: endpoint { 2522 remote-endpoint = <&etm2_out>; 2523 }; 2524 }; 2525 2526 port@3 { 2527 reg = <3>; 2528 apss_funnel_in3: endpoint { 2529 remote-endpoint = <&etm3_out>; 2530 }; 2531 }; 2532 2533 port@4 { 2534 reg = <4>; 2535 apss_funnel_in4: endpoint { 2536 remote-endpoint = <&etm4_out>; 2537 }; 2538 }; 2539 2540 port@5 { 2541 reg = <5>; 2542 apss_funnel_in5: endpoint { 2543 remote-endpoint = <&etm5_out>; 2544 }; 2545 }; 2546 2547 port@6 { 2548 reg = <6>; 2549 apss_funnel_in6: endpoint { 2550 remote-endpoint = <&etm6_out>; 2551 }; 2552 }; 2553 2554 port@7 { 2555 reg = <7>; 2556 apss_funnel_in7: endpoint { 2557 remote-endpoint = <&etm7_out>; 2558 }; 2559 }; 2560 }; 2561 }; 2562 2563 funnel@7810000 { 2564 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2565 reg = <0 0x07810000 0 0x1000>; 2566 2567 clocks = <&aoss_qmp>; 2568 clock-names = "apb_pclk"; 2569 2570 out-ports { 2571 port { 2572 apss_merge_funnel_out: endpoint { 2573 remote-endpoint = <&funnel1_in4>; 2574 }; 2575 }; 2576 }; 2577 2578 in-ports { 2579 port { 2580 apss_merge_funnel_in: endpoint { 2581 remote-endpoint = <&apss_funnel_out>; 2582 }; 2583 }; 2584 }; 2585 }; 2586 2587 sdhc_2: sdhci@8804000 { 2588 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2589 reg = <0 0x08804000 0 0x1000>; 2590 2591 iommus = <&apps_smmu 0x80 0>; 2592 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2594 interrupt-names = "hc_irq", "pwr_irq"; 2595 2596 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2597 <&gcc GCC_SDCC2_AHB_CLK>, 2598 <&rpmhcc RPMH_CXO_CLK>; 2599 clock-names = "core", "iface", "xo"; 2600 2601 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2603 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2604 power-domains = <&rpmhpd SC7180_CX>; 2605 operating-points-v2 = <&sdhc2_opp_table>; 2606 2607 bus-width = <4>; 2608 2609 status = "disabled"; 2610 2611 sdhc2_opp_table: sdhc2-opp-table { 2612 compatible = "operating-points-v2"; 2613 2614 opp-100000000 { 2615 opp-hz = /bits/ 64 <100000000>; 2616 required-opps = <&rpmhpd_opp_low_svs>; 2617 opp-peak-kBps = <1800000 600000>; 2618 opp-avg-kBps = <100000 0>; 2619 }; 2620 2621 opp-202000000 { 2622 opp-hz = /bits/ 64 <202000000>; 2623 required-opps = <&rpmhpd_opp_nom>; 2624 opp-peak-kBps = <5400000 1600000>; 2625 opp-avg-kBps = <200000 0>; 2626 }; 2627 }; 2628 }; 2629 2630 qspi_opp_table: qspi-opp-table { 2631 compatible = "operating-points-v2"; 2632 2633 opp-75000000 { 2634 opp-hz = /bits/ 64 <75000000>; 2635 required-opps = <&rpmhpd_opp_low_svs>; 2636 }; 2637 2638 opp-150000000 { 2639 opp-hz = /bits/ 64 <150000000>; 2640 required-opps = <&rpmhpd_opp_svs>; 2641 }; 2642 2643 opp-300000000 { 2644 opp-hz = /bits/ 64 <300000000>; 2645 required-opps = <&rpmhpd_opp_nom>; 2646 }; 2647 }; 2648 2649 qspi: spi@88dc000 { 2650 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2651 reg = <0 0x088dc000 0 0x600>; 2652 #address-cells = <1>; 2653 #size-cells = <0>; 2654 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2655 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2656 <&gcc GCC_QSPI_CORE_CLK>; 2657 clock-names = "iface", "core"; 2658 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2659 &config_noc SLAVE_QSPI_0 0>; 2660 interconnect-names = "qspi-config"; 2661 power-domains = <&rpmhpd SC7180_CX>; 2662 operating-points-v2 = <&qspi_opp_table>; 2663 status = "disabled"; 2664 }; 2665 2666 usb_1_hsphy: phy@88e3000 { 2667 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2668 reg = <0 0x088e3000 0 0x400>; 2669 status = "disabled"; 2670 #phy-cells = <0>; 2671 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2672 <&rpmhcc RPMH_CXO_CLK>; 2673 clock-names = "cfg_ahb", "ref"; 2674 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2675 2676 nvmem-cells = <&qusb2p_hstx_trim>; 2677 }; 2678 2679 usb_1_qmpphy: phy-wrapper@88e9000 { 2680 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2681 reg = <0 0x088e9000 0 0x18c>, 2682 <0 0x088e8000 0 0x3c>, 2683 <0 0x088ea000 0 0x18c>; 2684 status = "disabled"; 2685 #address-cells = <2>; 2686 #size-cells = <2>; 2687 ranges; 2688 2689 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2690 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2691 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2692 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2693 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2694 2695 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2696 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2697 reset-names = "phy", "common"; 2698 2699 usb_1_ssphy: usb3-phy@88e9200 { 2700 reg = <0 0x088e9200 0 0x128>, 2701 <0 0x088e9400 0 0x200>, 2702 <0 0x088e9c00 0 0x218>, 2703 <0 0x088e9600 0 0x128>, 2704 <0 0x088e9800 0 0x200>, 2705 <0 0x088e9a00 0 0x18>; 2706 #clock-cells = <0>; 2707 #phy-cells = <0>; 2708 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2709 clock-names = "pipe0"; 2710 clock-output-names = "usb3_phy_pipe_clk_src"; 2711 }; 2712 2713 dp_phy: dp-phy@88ea200 { 2714 reg = <0 0x088ea200 0 0x200>, 2715 <0 0x088ea400 0 0x200>, 2716 <0 0x088eaa00 0 0x200>, 2717 <0 0x088ea600 0 0x200>, 2718 <0 0x088ea800 0 0x200>; 2719 #clock-cells = <1>; 2720 #phy-cells = <0>; 2721 }; 2722 }; 2723 2724 dc_noc: interconnect@9160000 { 2725 compatible = "qcom,sc7180-dc-noc"; 2726 reg = <0 0x09160000 0 0x03200>; 2727 #interconnect-cells = <2>; 2728 qcom,bcm-voters = <&apps_bcm_voter>; 2729 }; 2730 2731 system-cache-controller@9200000 { 2732 compatible = "qcom,sc7180-llcc"; 2733 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2734 reg-names = "llcc_base", "llcc_broadcast_base"; 2735 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2736 }; 2737 2738 gem_noc: interconnect@9680000 { 2739 compatible = "qcom,sc7180-gem-noc"; 2740 reg = <0 0x09680000 0 0x3e200>; 2741 #interconnect-cells = <2>; 2742 qcom,bcm-voters = <&apps_bcm_voter>; 2743 }; 2744 2745 npu_noc: interconnect@9990000 { 2746 compatible = "qcom,sc7180-npu-noc"; 2747 reg = <0 0x09990000 0 0x1600>; 2748 #interconnect-cells = <2>; 2749 qcom,bcm-voters = <&apps_bcm_voter>; 2750 }; 2751 2752 usb_1: usb@a6f8800 { 2753 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2754 reg = <0 0x0a6f8800 0 0x400>; 2755 status = "disabled"; 2756 #address-cells = <2>; 2757 #size-cells = <2>; 2758 ranges; 2759 dma-ranges; 2760 2761 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2762 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2763 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2764 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2765 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2766 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2767 "sleep"; 2768 2769 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2770 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2771 assigned-clock-rates = <19200000>, <150000000>; 2772 2773 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2774 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2775 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2776 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2777 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2778 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2779 2780 power-domains = <&gcc USB30_PRIM_GDSC>; 2781 2782 resets = <&gcc GCC_USB30_PRIM_BCR>; 2783 2784 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2785 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2786 interconnect-names = "usb-ddr", "apps-usb"; 2787 2788 usb_1_dwc3: dwc3@a600000 { 2789 compatible = "snps,dwc3"; 2790 reg = <0 0x0a600000 0 0xe000>; 2791 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2792 iommus = <&apps_smmu 0x540 0>; 2793 snps,dis_u2_susphy_quirk; 2794 snps,dis_enblslpm_quirk; 2795 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2796 phy-names = "usb2-phy", "usb3-phy"; 2797 maximum-speed = "super-speed"; 2798 }; 2799 }; 2800 2801 venus: video-codec@aa00000 { 2802 compatible = "qcom,sc7180-venus"; 2803 reg = <0 0x0aa00000 0 0xff000>; 2804 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2805 power-domains = <&videocc VENUS_GDSC>, 2806 <&videocc VCODEC0_GDSC>, 2807 <&rpmhpd SC7180_CX>; 2808 power-domain-names = "venus", "vcodec0", "cx"; 2809 operating-points-v2 = <&venus_opp_table>; 2810 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2811 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2812 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2813 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2814 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2815 clock-names = "core", "iface", "bus", 2816 "vcodec0_core", "vcodec0_bus"; 2817 iommus = <&apps_smmu 0x0c00 0x60>; 2818 memory-region = <&venus_mem>; 2819 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2820 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2821 interconnect-names = "video-mem", "cpu-cfg"; 2822 2823 video-decoder { 2824 compatible = "venus-decoder"; 2825 }; 2826 2827 video-encoder { 2828 compatible = "venus-encoder"; 2829 }; 2830 2831 venus_opp_table: venus-opp-table { 2832 compatible = "operating-points-v2"; 2833 2834 opp-150000000 { 2835 opp-hz = /bits/ 64 <150000000>; 2836 required-opps = <&rpmhpd_opp_low_svs>; 2837 }; 2838 2839 opp-270000000 { 2840 opp-hz = /bits/ 64 <270000000>; 2841 required-opps = <&rpmhpd_opp_svs>; 2842 }; 2843 2844 opp-340000000 { 2845 opp-hz = /bits/ 64 <340000000>; 2846 required-opps = <&rpmhpd_opp_svs_l1>; 2847 }; 2848 2849 opp-434000000 { 2850 opp-hz = /bits/ 64 <434000000>; 2851 required-opps = <&rpmhpd_opp_nom>; 2852 }; 2853 2854 opp-500000097 { 2855 opp-hz = /bits/ 64 <500000097>; 2856 required-opps = <&rpmhpd_opp_turbo>; 2857 }; 2858 }; 2859 }; 2860 2861 videocc: clock-controller@ab00000 { 2862 compatible = "qcom,sc7180-videocc"; 2863 reg = <0 0x0ab00000 0 0x10000>; 2864 clocks = <&rpmhcc RPMH_CXO_CLK>; 2865 clock-names = "bi_tcxo"; 2866 #clock-cells = <1>; 2867 #reset-cells = <1>; 2868 #power-domain-cells = <1>; 2869 }; 2870 2871 camnoc_virt: interconnect@ac00000 { 2872 compatible = "qcom,sc7180-camnoc-virt"; 2873 reg = <0 0x0ac00000 0 0x1000>; 2874 #interconnect-cells = <2>; 2875 qcom,bcm-voters = <&apps_bcm_voter>; 2876 }; 2877 2878 camcc: clock-controller@ad00000 { 2879 compatible = "qcom,sc7180-camcc"; 2880 reg = <0 0x0ad00000 0 0x10000>; 2881 clocks = <&rpmhcc RPMH_CXO_CLK>, 2882 <&gcc GCC_CAMERA_AHB_CLK>, 2883 <&gcc GCC_CAMERA_XO_CLK>; 2884 clock-names = "bi_tcxo", "iface", "xo"; 2885 #clock-cells = <1>; 2886 #reset-cells = <1>; 2887 #power-domain-cells = <1>; 2888 }; 2889 2890 mdss: mdss@ae00000 { 2891 compatible = "qcom,sc7180-mdss"; 2892 reg = <0 0x0ae00000 0 0x1000>; 2893 reg-names = "mdss"; 2894 2895 power-domains = <&dispcc MDSS_GDSC>; 2896 2897 clocks = <&gcc GCC_DISP_AHB_CLK>, 2898 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2899 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2900 clock-names = "iface", "ahb", "core"; 2901 2902 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2903 assigned-clock-rates = <300000000>; 2904 2905 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2906 interrupt-controller; 2907 #interrupt-cells = <1>; 2908 2909 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2910 interconnect-names = "mdp0-mem"; 2911 2912 iommus = <&apps_smmu 0x800 0x2>; 2913 2914 #address-cells = <2>; 2915 #size-cells = <2>; 2916 ranges; 2917 2918 status = "disabled"; 2919 2920 mdp: mdp@ae01000 { 2921 compatible = "qcom,sc7180-dpu"; 2922 reg = <0 0x0ae01000 0 0x8f000>, 2923 <0 0x0aeb0000 0 0x2008>; 2924 reg-names = "mdp", "vbif"; 2925 2926 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2927 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2928 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2929 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2930 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2931 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2932 clock-names = "bus", "iface", "rot", "lut", "core", 2933 "vsync"; 2934 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2935 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2936 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2937 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2938 assigned-clock-rates = <300000000>, 2939 <19200000>, 2940 <19200000>, 2941 <19200000>; 2942 operating-points-v2 = <&mdp_opp_table>; 2943 power-domains = <&rpmhpd SC7180_CX>; 2944 2945 interrupt-parent = <&mdss>; 2946 interrupts = <0>; 2947 2948 status = "disabled"; 2949 2950 ports { 2951 #address-cells = <1>; 2952 #size-cells = <0>; 2953 2954 port@0 { 2955 reg = <0>; 2956 dpu_intf1_out: endpoint { 2957 remote-endpoint = <&dsi0_in>; 2958 }; 2959 }; 2960 2961 port@2 { 2962 reg = <2>; 2963 dpu_intf0_out: endpoint { 2964 remote-endpoint = <&dp_in>; 2965 }; 2966 }; 2967 }; 2968 2969 mdp_opp_table: mdp-opp-table { 2970 compatible = "operating-points-v2"; 2971 2972 opp-200000000 { 2973 opp-hz = /bits/ 64 <200000000>; 2974 required-opps = <&rpmhpd_opp_low_svs>; 2975 }; 2976 2977 opp-300000000 { 2978 opp-hz = /bits/ 64 <300000000>; 2979 required-opps = <&rpmhpd_opp_svs>; 2980 }; 2981 2982 opp-345000000 { 2983 opp-hz = /bits/ 64 <345000000>; 2984 required-opps = <&rpmhpd_opp_svs_l1>; 2985 }; 2986 2987 opp-460000000 { 2988 opp-hz = /bits/ 64 <460000000>; 2989 required-opps = <&rpmhpd_opp_nom>; 2990 }; 2991 }; 2992 2993 }; 2994 2995 dsi0: dsi@ae94000 { 2996 compatible = "qcom,mdss-dsi-ctrl"; 2997 reg = <0 0x0ae94000 0 0x400>; 2998 reg-names = "dsi_ctrl"; 2999 3000 interrupt-parent = <&mdss>; 3001 interrupts = <4>; 3002 3003 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3004 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3005 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3006 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3007 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3008 <&gcc GCC_DISP_HF_AXI_CLK>; 3009 clock-names = "byte", 3010 "byte_intf", 3011 "pixel", 3012 "core", 3013 "iface", 3014 "bus"; 3015 3016 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3017 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 3018 3019 operating-points-v2 = <&dsi_opp_table>; 3020 power-domains = <&rpmhpd SC7180_CX>; 3021 3022 phys = <&dsi_phy>; 3023 phy-names = "dsi"; 3024 3025 #address-cells = <1>; 3026 #size-cells = <0>; 3027 3028 status = "disabled"; 3029 3030 ports { 3031 #address-cells = <1>; 3032 #size-cells = <0>; 3033 3034 port@0 { 3035 reg = <0>; 3036 dsi0_in: endpoint { 3037 remote-endpoint = <&dpu_intf1_out>; 3038 }; 3039 }; 3040 3041 port@1 { 3042 reg = <1>; 3043 dsi0_out: endpoint { 3044 }; 3045 }; 3046 }; 3047 3048 dsi_opp_table: dsi-opp-table { 3049 compatible = "operating-points-v2"; 3050 3051 opp-187500000 { 3052 opp-hz = /bits/ 64 <187500000>; 3053 required-opps = <&rpmhpd_opp_low_svs>; 3054 }; 3055 3056 opp-300000000 { 3057 opp-hz = /bits/ 64 <300000000>; 3058 required-opps = <&rpmhpd_opp_svs>; 3059 }; 3060 3061 opp-358000000 { 3062 opp-hz = /bits/ 64 <358000000>; 3063 required-opps = <&rpmhpd_opp_svs_l1>; 3064 }; 3065 }; 3066 }; 3067 3068 dsi_phy: dsi-phy@ae94400 { 3069 compatible = "qcom,dsi-phy-10nm"; 3070 reg = <0 0x0ae94400 0 0x200>, 3071 <0 0x0ae94600 0 0x280>, 3072 <0 0x0ae94a00 0 0x1e0>; 3073 reg-names = "dsi_phy", 3074 "dsi_phy_lane", 3075 "dsi_pll"; 3076 3077 #clock-cells = <1>; 3078 #phy-cells = <0>; 3079 3080 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3081 <&rpmhcc RPMH_CXO_CLK>; 3082 clock-names = "iface", "ref"; 3083 3084 status = "disabled"; 3085 }; 3086 3087 mdss_dp: displayport-controller@ae90000 { 3088 compatible = "qcom,sc7180-dp"; 3089 status = "disabled"; 3090 3091 reg = <0 0x0ae90000 0 0x1400>; 3092 3093 interrupt-parent = <&mdss>; 3094 interrupts = <12>; 3095 3096 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3097 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3098 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3099 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3100 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3101 clock-names = "core_iface", "core_aux", "ctrl_link", 3102 "ctrl_link_iface", "stream_pixel"; 3103 #clock-cells = <1>; 3104 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3105 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3106 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3107 phys = <&dp_phy>; 3108 phy-names = "dp"; 3109 3110 operating-points-v2 = <&dp_opp_table>; 3111 power-domains = <&rpmhpd SC7180_CX>; 3112 3113 #sound-dai-cells = <0>; 3114 3115 ports { 3116 #address-cells = <1>; 3117 #size-cells = <0>; 3118 port@0 { 3119 reg = <0>; 3120 dp_in: endpoint { 3121 remote-endpoint = <&dpu_intf0_out>; 3122 }; 3123 }; 3124 3125 port@1 { 3126 reg = <1>; 3127 dp_out: endpoint { }; 3128 }; 3129 }; 3130 3131 dp_opp_table: opp-table { 3132 compatible = "operating-points-v2"; 3133 3134 opp-160000000 { 3135 opp-hz = /bits/ 64 <160000000>; 3136 required-opps = <&rpmhpd_opp_low_svs>; 3137 }; 3138 3139 opp-270000000 { 3140 opp-hz = /bits/ 64 <270000000>; 3141 required-opps = <&rpmhpd_opp_svs>; 3142 }; 3143 3144 opp-540000000 { 3145 opp-hz = /bits/ 64 <540000000>; 3146 required-opps = <&rpmhpd_opp_svs_l1>; 3147 }; 3148 3149 opp-810000000 { 3150 opp-hz = /bits/ 64 <810000000>; 3151 required-opps = <&rpmhpd_opp_nom>; 3152 }; 3153 }; 3154 }; 3155 }; 3156 3157 dispcc: clock-controller@af00000 { 3158 compatible = "qcom,sc7180-dispcc"; 3159 reg = <0 0x0af00000 0 0x200000>; 3160 clocks = <&rpmhcc RPMH_CXO_CLK>, 3161 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3162 <&dsi_phy 0>, 3163 <&dsi_phy 1>, 3164 <&dp_phy 0>, 3165 <&dp_phy 1>; 3166 clock-names = "bi_tcxo", 3167 "gcc_disp_gpll0_clk_src", 3168 "dsi0_phy_pll_out_byteclk", 3169 "dsi0_phy_pll_out_dsiclk", 3170 "dp_phy_pll_link_clk", 3171 "dp_phy_pll_vco_div_clk"; 3172 #clock-cells = <1>; 3173 #reset-cells = <1>; 3174 #power-domain-cells = <1>; 3175 }; 3176 3177 pdc: interrupt-controller@b220000 { 3178 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3179 reg = <0 0x0b220000 0 0x30000>; 3180 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3181 #interrupt-cells = <2>; 3182 interrupt-parent = <&intc>; 3183 interrupt-controller; 3184 }; 3185 3186 pdc_reset: reset-controller@b2e0000 { 3187 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3188 reg = <0 0x0b2e0000 0 0x20000>; 3189 #reset-cells = <1>; 3190 }; 3191 3192 tsens0: thermal-sensor@c263000 { 3193 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3194 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3195 <0 0x0c222000 0 0x1ff>; /* SROT */ 3196 #qcom,sensors = <15>; 3197 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3199 interrupt-names = "uplow","critical"; 3200 #thermal-sensor-cells = <1>; 3201 }; 3202 3203 tsens1: thermal-sensor@c265000 { 3204 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3205 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3206 <0 0x0c223000 0 0x1ff>; /* SROT */ 3207 #qcom,sensors = <10>; 3208 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3210 interrupt-names = "uplow","critical"; 3211 #thermal-sensor-cells = <1>; 3212 }; 3213 3214 aoss_reset: reset-controller@c2a0000 { 3215 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3216 reg = <0 0x0c2a0000 0 0x31000>; 3217 #reset-cells = <1>; 3218 }; 3219 3220 aoss_qmp: power-controller@c300000 { 3221 compatible = "qcom,sc7180-aoss-qmp"; 3222 reg = <0 0x0c300000 0 0x400>; 3223 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3224 mboxes = <&apss_shared 0>; 3225 3226 #clock-cells = <0>; 3227 }; 3228 3229 sram@c3f0000 { 3230 compatible = "qcom,rpmh-stats"; 3231 reg = <0 0x0c3f0000 0 0x400>; 3232 }; 3233 3234 spmi_bus: spmi@c440000 { 3235 compatible = "qcom,spmi-pmic-arb"; 3236 reg = <0 0x0c440000 0 0x1100>, 3237 <0 0x0c600000 0 0x2000000>, 3238 <0 0x0e600000 0 0x100000>, 3239 <0 0x0e700000 0 0xa0000>, 3240 <0 0x0c40a000 0 0x26000>; 3241 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3242 interrupt-names = "periph_irq"; 3243 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3244 qcom,ee = <0>; 3245 qcom,channel = <0>; 3246 #address-cells = <1>; 3247 #size-cells = <1>; 3248 interrupt-controller; 3249 #interrupt-cells = <4>; 3250 cell-index = <0>; 3251 }; 3252 3253 imem@146aa000 { 3254 compatible = "simple-mfd"; 3255 reg = <0 0x146aa000 0 0x2000>; 3256 3257 #address-cells = <1>; 3258 #size-cells = <1>; 3259 3260 ranges = <0 0 0x146aa000 0x2000>; 3261 3262 pil-reloc@94c { 3263 compatible = "qcom,pil-reloc-info"; 3264 reg = <0x94c 0xc8>; 3265 }; 3266 }; 3267 3268 apps_smmu: iommu@15000000 { 3269 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3270 reg = <0 0x15000000 0 0x100000>; 3271 #iommu-cells = <2>; 3272 #global-interrupts = <1>; 3273 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3354 }; 3355 3356 intc: interrupt-controller@17a00000 { 3357 compatible = "arm,gic-v3"; 3358 #address-cells = <2>; 3359 #size-cells = <2>; 3360 ranges; 3361 #interrupt-cells = <3>; 3362 interrupt-controller; 3363 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3364 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3365 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3366 3367 msi-controller@17a40000 { 3368 compatible = "arm,gic-v3-its"; 3369 msi-controller; 3370 #msi-cells = <1>; 3371 reg = <0 0x17a40000 0 0x20000>; 3372 status = "disabled"; 3373 }; 3374 }; 3375 3376 apss_shared: mailbox@17c00000 { 3377 compatible = "qcom,sc7180-apss-shared"; 3378 reg = <0 0x17c00000 0 0x10000>; 3379 #mbox-cells = <1>; 3380 }; 3381 3382 watchdog@17c10000 { 3383 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3384 reg = <0 0x17c10000 0 0x1000>; 3385 clocks = <&sleep_clk>; 3386 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3387 }; 3388 3389 timer@17c20000{ 3390 #address-cells = <2>; 3391 #size-cells = <2>; 3392 ranges; 3393 compatible = "arm,armv7-timer-mem"; 3394 reg = <0 0x17c20000 0 0x1000>; 3395 3396 frame@17c21000 { 3397 frame-number = <0>; 3398 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3400 reg = <0 0x17c21000 0 0x1000>, 3401 <0 0x17c22000 0 0x1000>; 3402 }; 3403 3404 frame@17c23000 { 3405 frame-number = <1>; 3406 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3407 reg = <0 0x17c23000 0 0x1000>; 3408 status = "disabled"; 3409 }; 3410 3411 frame@17c25000 { 3412 frame-number = <2>; 3413 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3414 reg = <0 0x17c25000 0 0x1000>; 3415 status = "disabled"; 3416 }; 3417 3418 frame@17c27000 { 3419 frame-number = <3>; 3420 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3421 reg = <0 0x17c27000 0 0x1000>; 3422 status = "disabled"; 3423 }; 3424 3425 frame@17c29000 { 3426 frame-number = <4>; 3427 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3428 reg = <0 0x17c29000 0 0x1000>; 3429 status = "disabled"; 3430 }; 3431 3432 frame@17c2b000 { 3433 frame-number = <5>; 3434 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3435 reg = <0 0x17c2b000 0 0x1000>; 3436 status = "disabled"; 3437 }; 3438 3439 frame@17c2d000 { 3440 frame-number = <6>; 3441 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3442 reg = <0 0x17c2d000 0 0x1000>; 3443 status = "disabled"; 3444 }; 3445 }; 3446 3447 apps_rsc: rsc@18200000 { 3448 compatible = "qcom,rpmh-rsc"; 3449 reg = <0 0x18200000 0 0x10000>, 3450 <0 0x18210000 0 0x10000>, 3451 <0 0x18220000 0 0x10000>; 3452 reg-names = "drv-0", "drv-1", "drv-2"; 3453 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3456 qcom,tcs-offset = <0xd00>; 3457 qcom,drv-id = <2>; 3458 qcom,tcs-config = <ACTIVE_TCS 2>, 3459 <SLEEP_TCS 3>, 3460 <WAKE_TCS 3>, 3461 <CONTROL_TCS 1>; 3462 3463 rpmhcc: clock-controller { 3464 compatible = "qcom,sc7180-rpmh-clk"; 3465 clocks = <&xo_board>; 3466 clock-names = "xo"; 3467 #clock-cells = <1>; 3468 }; 3469 3470 rpmhpd: power-controller { 3471 compatible = "qcom,sc7180-rpmhpd"; 3472 #power-domain-cells = <1>; 3473 operating-points-v2 = <&rpmhpd_opp_table>; 3474 3475 rpmhpd_opp_table: opp-table { 3476 compatible = "operating-points-v2"; 3477 3478 rpmhpd_opp_ret: opp1 { 3479 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3480 }; 3481 3482 rpmhpd_opp_min_svs: opp2 { 3483 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3484 }; 3485 3486 rpmhpd_opp_low_svs: opp3 { 3487 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3488 }; 3489 3490 rpmhpd_opp_svs: opp4 { 3491 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3492 }; 3493 3494 rpmhpd_opp_svs_l1: opp5 { 3495 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3496 }; 3497 3498 rpmhpd_opp_svs_l2: opp6 { 3499 opp-level = <224>; 3500 }; 3501 3502 rpmhpd_opp_nom: opp7 { 3503 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3504 }; 3505 3506 rpmhpd_opp_nom_l1: opp8 { 3507 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3508 }; 3509 3510 rpmhpd_opp_nom_l2: opp9 { 3511 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3512 }; 3513 3514 rpmhpd_opp_turbo: opp10 { 3515 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3516 }; 3517 3518 rpmhpd_opp_turbo_l1: opp11 { 3519 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3520 }; 3521 }; 3522 }; 3523 3524 apps_bcm_voter: bcm_voter { 3525 compatible = "qcom,bcm-voter"; 3526 }; 3527 }; 3528 3529 osm_l3: interconnect@18321000 { 3530 compatible = "qcom,sc7180-osm-l3"; 3531 reg = <0 0x18321000 0 0x1400>; 3532 3533 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3534 clock-names = "xo", "alternate"; 3535 3536 #interconnect-cells = <1>; 3537 }; 3538 3539 cpufreq_hw: cpufreq@18323000 { 3540 compatible = "qcom,cpufreq-hw"; 3541 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3542 reg-names = "freq-domain0", "freq-domain1"; 3543 3544 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3545 clock-names = "xo", "alternate"; 3546 3547 #freq-domain-cells = <1>; 3548 }; 3549 3550 wifi: wifi@18800000 { 3551 compatible = "qcom,wcn3990-wifi"; 3552 reg = <0 0x18800000 0 0x800000>; 3553 reg-names = "membase"; 3554 iommus = <&apps_smmu 0xc0 0x1>; 3555 interrupts = 3556 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3557 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3558 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3559 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3560 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3561 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3562 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3563 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3564 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3565 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3566 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3567 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3568 memory-region = <&wlan_mem>; 3569 qcom,msa-fixed-perm; 3570 status = "disabled"; 3571 }; 3572 3573 lpasscc: clock-controller@62d00000 { 3574 compatible = "qcom,sc7180-lpasscorecc"; 3575 reg = <0 0x62d00000 0 0x50000>, 3576 <0 0x62780000 0 0x30000>; 3577 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3578 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3579 <&rpmhcc RPMH_CXO_CLK>; 3580 clock-names = "iface", "bi_tcxo"; 3581 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3582 #clock-cells = <1>; 3583 #power-domain-cells = <1>; 3584 }; 3585 3586 lpass_cpu: lpass@62d87000 { 3587 compatible = "qcom,sc7180-lpass-cpu"; 3588 3589 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3590 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3591 3592 iommus = <&apps_smmu 0x1020 0>, 3593 <&apps_smmu 0x1021 0>, 3594 <&apps_smmu 0x1032 0>; 3595 3596 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3597 3598 status = "disabled"; 3599 3600 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3601 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3602 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3603 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3604 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3605 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3606 3607 clock-names = "pcnoc-sway-clk", "audio-core", 3608 "mclk0", "pcnoc-mport-clk", 3609 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3610 3611 3612 #sound-dai-cells = <1>; 3613 #address-cells = <1>; 3614 #size-cells = <0>; 3615 3616 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3618 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3619 }; 3620 3621 lpass_hm: clock-controller@63000000 { 3622 compatible = "qcom,sc7180-lpasshm"; 3623 reg = <0 0x63000000 0 0x28>; 3624 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3625 <&rpmhcc RPMH_CXO_CLK>; 3626 clock-names = "iface", "bi_tcxo"; 3627 #clock-cells = <1>; 3628 #power-domain-cells = <1>; 3629 }; 3630 }; 3631 3632 thermal-zones { 3633 cpu0_thermal: cpu0-thermal { 3634 polling-delay-passive = <250>; 3635 polling-delay = <0>; 3636 3637 thermal-sensors = <&tsens0 1>; 3638 sustainable-power = <1052>; 3639 3640 trips { 3641 cpu0_alert0: trip-point0 { 3642 temperature = <90000>; 3643 hysteresis = <2000>; 3644 type = "passive"; 3645 }; 3646 3647 cpu0_alert1: trip-point1 { 3648 temperature = <95000>; 3649 hysteresis = <2000>; 3650 type = "passive"; 3651 }; 3652 3653 cpu0_crit: cpu_crit { 3654 temperature = <110000>; 3655 hysteresis = <1000>; 3656 type = "critical"; 3657 }; 3658 }; 3659 3660 cooling-maps { 3661 map0 { 3662 trip = <&cpu0_alert0>; 3663 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3664 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3665 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3666 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3667 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3668 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3669 }; 3670 map1 { 3671 trip = <&cpu0_alert1>; 3672 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3673 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3674 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3675 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3676 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3677 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3678 }; 3679 }; 3680 }; 3681 3682 cpu1_thermal: cpu1-thermal { 3683 polling-delay-passive = <250>; 3684 polling-delay = <0>; 3685 3686 thermal-sensors = <&tsens0 2>; 3687 sustainable-power = <1052>; 3688 3689 trips { 3690 cpu1_alert0: trip-point0 { 3691 temperature = <90000>; 3692 hysteresis = <2000>; 3693 type = "passive"; 3694 }; 3695 3696 cpu1_alert1: trip-point1 { 3697 temperature = <95000>; 3698 hysteresis = <2000>; 3699 type = "passive"; 3700 }; 3701 3702 cpu1_crit: cpu_crit { 3703 temperature = <110000>; 3704 hysteresis = <1000>; 3705 type = "critical"; 3706 }; 3707 }; 3708 3709 cooling-maps { 3710 map0 { 3711 trip = <&cpu1_alert0>; 3712 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3713 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3714 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3715 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3716 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3718 }; 3719 map1 { 3720 trip = <&cpu1_alert1>; 3721 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3722 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3723 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3724 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3727 }; 3728 }; 3729 }; 3730 3731 cpu2_thermal: cpu2-thermal { 3732 polling-delay-passive = <250>; 3733 polling-delay = <0>; 3734 3735 thermal-sensors = <&tsens0 3>; 3736 sustainable-power = <1052>; 3737 3738 trips { 3739 cpu2_alert0: trip-point0 { 3740 temperature = <90000>; 3741 hysteresis = <2000>; 3742 type = "passive"; 3743 }; 3744 3745 cpu2_alert1: trip-point1 { 3746 temperature = <95000>; 3747 hysteresis = <2000>; 3748 type = "passive"; 3749 }; 3750 3751 cpu2_crit: cpu_crit { 3752 temperature = <110000>; 3753 hysteresis = <1000>; 3754 type = "critical"; 3755 }; 3756 }; 3757 3758 cooling-maps { 3759 map0 { 3760 trip = <&cpu2_alert0>; 3761 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3762 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3764 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3765 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3767 }; 3768 map1 { 3769 trip = <&cpu2_alert1>; 3770 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3771 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3772 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3773 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3774 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3776 }; 3777 }; 3778 }; 3779 3780 cpu3_thermal: cpu3-thermal { 3781 polling-delay-passive = <250>; 3782 polling-delay = <0>; 3783 3784 thermal-sensors = <&tsens0 4>; 3785 sustainable-power = <1052>; 3786 3787 trips { 3788 cpu3_alert0: trip-point0 { 3789 temperature = <90000>; 3790 hysteresis = <2000>; 3791 type = "passive"; 3792 }; 3793 3794 cpu3_alert1: trip-point1 { 3795 temperature = <95000>; 3796 hysteresis = <2000>; 3797 type = "passive"; 3798 }; 3799 3800 cpu3_crit: cpu_crit { 3801 temperature = <110000>; 3802 hysteresis = <1000>; 3803 type = "critical"; 3804 }; 3805 }; 3806 3807 cooling-maps { 3808 map0 { 3809 trip = <&cpu3_alert0>; 3810 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3812 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3816 }; 3817 map1 { 3818 trip = <&cpu3_alert1>; 3819 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3820 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3821 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3822 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3825 }; 3826 }; 3827 }; 3828 3829 cpu4_thermal: cpu4-thermal { 3830 polling-delay-passive = <250>; 3831 polling-delay = <0>; 3832 3833 thermal-sensors = <&tsens0 5>; 3834 sustainable-power = <1052>; 3835 3836 trips { 3837 cpu4_alert0: trip-point0 { 3838 temperature = <90000>; 3839 hysteresis = <2000>; 3840 type = "passive"; 3841 }; 3842 3843 cpu4_alert1: trip-point1 { 3844 temperature = <95000>; 3845 hysteresis = <2000>; 3846 type = "passive"; 3847 }; 3848 3849 cpu4_crit: cpu_crit { 3850 temperature = <110000>; 3851 hysteresis = <1000>; 3852 type = "critical"; 3853 }; 3854 }; 3855 3856 cooling-maps { 3857 map0 { 3858 trip = <&cpu4_alert0>; 3859 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3860 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3862 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3863 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3864 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3865 }; 3866 map1 { 3867 trip = <&cpu4_alert1>; 3868 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3869 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3870 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3874 }; 3875 }; 3876 }; 3877 3878 cpu5_thermal: cpu5-thermal { 3879 polling-delay-passive = <250>; 3880 polling-delay = <0>; 3881 3882 thermal-sensors = <&tsens0 6>; 3883 sustainable-power = <1052>; 3884 3885 trips { 3886 cpu5_alert0: trip-point0 { 3887 temperature = <90000>; 3888 hysteresis = <2000>; 3889 type = "passive"; 3890 }; 3891 3892 cpu5_alert1: trip-point1 { 3893 temperature = <95000>; 3894 hysteresis = <2000>; 3895 type = "passive"; 3896 }; 3897 3898 cpu5_crit: cpu_crit { 3899 temperature = <110000>; 3900 hysteresis = <1000>; 3901 type = "critical"; 3902 }; 3903 }; 3904 3905 cooling-maps { 3906 map0 { 3907 trip = <&cpu5_alert0>; 3908 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3909 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3914 }; 3915 map1 { 3916 trip = <&cpu5_alert1>; 3917 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3919 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3923 }; 3924 }; 3925 }; 3926 3927 cpu6_thermal: cpu6-thermal { 3928 polling-delay-passive = <250>; 3929 polling-delay = <0>; 3930 3931 thermal-sensors = <&tsens0 9>; 3932 sustainable-power = <1425>; 3933 3934 trips { 3935 cpu6_alert0: trip-point0 { 3936 temperature = <90000>; 3937 hysteresis = <2000>; 3938 type = "passive"; 3939 }; 3940 3941 cpu6_alert1: trip-point1 { 3942 temperature = <95000>; 3943 hysteresis = <2000>; 3944 type = "passive"; 3945 }; 3946 3947 cpu6_crit: cpu_crit { 3948 temperature = <110000>; 3949 hysteresis = <1000>; 3950 type = "critical"; 3951 }; 3952 }; 3953 3954 cooling-maps { 3955 map0 { 3956 trip = <&cpu6_alert0>; 3957 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3958 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3959 }; 3960 map1 { 3961 trip = <&cpu6_alert1>; 3962 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3964 }; 3965 }; 3966 }; 3967 3968 cpu7_thermal: cpu7-thermal { 3969 polling-delay-passive = <250>; 3970 polling-delay = <0>; 3971 3972 thermal-sensors = <&tsens0 10>; 3973 sustainable-power = <1425>; 3974 3975 trips { 3976 cpu7_alert0: trip-point0 { 3977 temperature = <90000>; 3978 hysteresis = <2000>; 3979 type = "passive"; 3980 }; 3981 3982 cpu7_alert1: trip-point1 { 3983 temperature = <95000>; 3984 hysteresis = <2000>; 3985 type = "passive"; 3986 }; 3987 3988 cpu7_crit: cpu_crit { 3989 temperature = <110000>; 3990 hysteresis = <1000>; 3991 type = "critical"; 3992 }; 3993 }; 3994 3995 cooling-maps { 3996 map0 { 3997 trip = <&cpu7_alert0>; 3998 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4000 }; 4001 map1 { 4002 trip = <&cpu7_alert1>; 4003 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4004 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4005 }; 4006 }; 4007 }; 4008 4009 cpu8_thermal: cpu8-thermal { 4010 polling-delay-passive = <250>; 4011 polling-delay = <0>; 4012 4013 thermal-sensors = <&tsens0 11>; 4014 sustainable-power = <1425>; 4015 4016 trips { 4017 cpu8_alert0: trip-point0 { 4018 temperature = <90000>; 4019 hysteresis = <2000>; 4020 type = "passive"; 4021 }; 4022 4023 cpu8_alert1: trip-point1 { 4024 temperature = <95000>; 4025 hysteresis = <2000>; 4026 type = "passive"; 4027 }; 4028 4029 cpu8_crit: cpu_crit { 4030 temperature = <110000>; 4031 hysteresis = <1000>; 4032 type = "critical"; 4033 }; 4034 }; 4035 4036 cooling-maps { 4037 map0 { 4038 trip = <&cpu8_alert0>; 4039 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4041 }; 4042 map1 { 4043 trip = <&cpu8_alert1>; 4044 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4045 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4046 }; 4047 }; 4048 }; 4049 4050 cpu9_thermal: cpu9-thermal { 4051 polling-delay-passive = <250>; 4052 polling-delay = <0>; 4053 4054 thermal-sensors = <&tsens0 12>; 4055 sustainable-power = <1425>; 4056 4057 trips { 4058 cpu9_alert0: trip-point0 { 4059 temperature = <90000>; 4060 hysteresis = <2000>; 4061 type = "passive"; 4062 }; 4063 4064 cpu9_alert1: trip-point1 { 4065 temperature = <95000>; 4066 hysteresis = <2000>; 4067 type = "passive"; 4068 }; 4069 4070 cpu9_crit: cpu_crit { 4071 temperature = <110000>; 4072 hysteresis = <1000>; 4073 type = "critical"; 4074 }; 4075 }; 4076 4077 cooling-maps { 4078 map0 { 4079 trip = <&cpu9_alert0>; 4080 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4082 }; 4083 map1 { 4084 trip = <&cpu9_alert1>; 4085 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4087 }; 4088 }; 4089 }; 4090 4091 aoss0-thermal { 4092 polling-delay-passive = <250>; 4093 polling-delay = <0>; 4094 4095 thermal-sensors = <&tsens0 0>; 4096 4097 trips { 4098 aoss0_alert0: trip-point0 { 4099 temperature = <90000>; 4100 hysteresis = <2000>; 4101 type = "hot"; 4102 }; 4103 4104 aoss0_crit: aoss0_crit { 4105 temperature = <110000>; 4106 hysteresis = <2000>; 4107 type = "critical"; 4108 }; 4109 }; 4110 }; 4111 4112 cpuss0-thermal { 4113 polling-delay-passive = <250>; 4114 polling-delay = <0>; 4115 4116 thermal-sensors = <&tsens0 7>; 4117 4118 trips { 4119 cpuss0_alert0: trip-point0 { 4120 temperature = <90000>; 4121 hysteresis = <2000>; 4122 type = "hot"; 4123 }; 4124 cpuss0_crit: cluster0_crit { 4125 temperature = <110000>; 4126 hysteresis = <2000>; 4127 type = "critical"; 4128 }; 4129 }; 4130 }; 4131 4132 cpuss1-thermal { 4133 polling-delay-passive = <250>; 4134 polling-delay = <0>; 4135 4136 thermal-sensors = <&tsens0 8>; 4137 4138 trips { 4139 cpuss1_alert0: trip-point0 { 4140 temperature = <90000>; 4141 hysteresis = <2000>; 4142 type = "hot"; 4143 }; 4144 cpuss1_crit: cluster0_crit { 4145 temperature = <110000>; 4146 hysteresis = <2000>; 4147 type = "critical"; 4148 }; 4149 }; 4150 }; 4151 4152 gpuss0-thermal { 4153 polling-delay-passive = <250>; 4154 polling-delay = <0>; 4155 4156 thermal-sensors = <&tsens0 13>; 4157 4158 trips { 4159 gpuss0_alert0: trip-point0 { 4160 temperature = <95000>; 4161 hysteresis = <2000>; 4162 type = "passive"; 4163 }; 4164 4165 gpuss0_crit: gpuss0_crit { 4166 temperature = <110000>; 4167 hysteresis = <2000>; 4168 type = "critical"; 4169 }; 4170 }; 4171 4172 cooling-maps { 4173 map0 { 4174 trip = <&gpuss0_alert0>; 4175 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4176 }; 4177 }; 4178 }; 4179 4180 gpuss1-thermal { 4181 polling-delay-passive = <250>; 4182 polling-delay = <0>; 4183 4184 thermal-sensors = <&tsens0 14>; 4185 4186 trips { 4187 gpuss1_alert0: trip-point0 { 4188 temperature = <95000>; 4189 hysteresis = <2000>; 4190 type = "passive"; 4191 }; 4192 4193 gpuss1_crit: gpuss1_crit { 4194 temperature = <110000>; 4195 hysteresis = <2000>; 4196 type = "critical"; 4197 }; 4198 }; 4199 4200 cooling-maps { 4201 map0 { 4202 trip = <&gpuss1_alert0>; 4203 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4204 }; 4205 }; 4206 }; 4207 4208 aoss1-thermal { 4209 polling-delay-passive = <250>; 4210 polling-delay = <0>; 4211 4212 thermal-sensors = <&tsens1 0>; 4213 4214 trips { 4215 aoss1_alert0: trip-point0 { 4216 temperature = <90000>; 4217 hysteresis = <2000>; 4218 type = "hot"; 4219 }; 4220 4221 aoss1_crit: aoss1_crit { 4222 temperature = <110000>; 4223 hysteresis = <2000>; 4224 type = "critical"; 4225 }; 4226 }; 4227 }; 4228 4229 cwlan-thermal { 4230 polling-delay-passive = <250>; 4231 polling-delay = <0>; 4232 4233 thermal-sensors = <&tsens1 1>; 4234 4235 trips { 4236 cwlan_alert0: trip-point0 { 4237 temperature = <90000>; 4238 hysteresis = <2000>; 4239 type = "hot"; 4240 }; 4241 4242 cwlan_crit: cwlan_crit { 4243 temperature = <110000>; 4244 hysteresis = <2000>; 4245 type = "critical"; 4246 }; 4247 }; 4248 }; 4249 4250 audio-thermal { 4251 polling-delay-passive = <250>; 4252 polling-delay = <0>; 4253 4254 thermal-sensors = <&tsens1 2>; 4255 4256 trips { 4257 audio_alert0: trip-point0 { 4258 temperature = <90000>; 4259 hysteresis = <2000>; 4260 type = "hot"; 4261 }; 4262 4263 audio_crit: audio_crit { 4264 temperature = <110000>; 4265 hysteresis = <2000>; 4266 type = "critical"; 4267 }; 4268 }; 4269 }; 4270 4271 ddr-thermal { 4272 polling-delay-passive = <250>; 4273 polling-delay = <0>; 4274 4275 thermal-sensors = <&tsens1 3>; 4276 4277 trips { 4278 ddr_alert0: trip-point0 { 4279 temperature = <90000>; 4280 hysteresis = <2000>; 4281 type = "hot"; 4282 }; 4283 4284 ddr_crit: ddr_crit { 4285 temperature = <110000>; 4286 hysteresis = <2000>; 4287 type = "critical"; 4288 }; 4289 }; 4290 }; 4291 4292 q6-hvx-thermal { 4293 polling-delay-passive = <250>; 4294 polling-delay = <0>; 4295 4296 thermal-sensors = <&tsens1 4>; 4297 4298 trips { 4299 q6_hvx_alert0: trip-point0 { 4300 temperature = <90000>; 4301 hysteresis = <2000>; 4302 type = "hot"; 4303 }; 4304 4305 q6_hvx_crit: q6_hvx_crit { 4306 temperature = <110000>; 4307 hysteresis = <2000>; 4308 type = "critical"; 4309 }; 4310 }; 4311 }; 4312 4313 camera-thermal { 4314 polling-delay-passive = <250>; 4315 polling-delay = <0>; 4316 4317 thermal-sensors = <&tsens1 5>; 4318 4319 trips { 4320 camera_alert0: trip-point0 { 4321 temperature = <90000>; 4322 hysteresis = <2000>; 4323 type = "hot"; 4324 }; 4325 4326 camera_crit: camera_crit { 4327 temperature = <110000>; 4328 hysteresis = <2000>; 4329 type = "critical"; 4330 }; 4331 }; 4332 }; 4333 4334 mdm-core-thermal { 4335 polling-delay-passive = <250>; 4336 polling-delay = <0>; 4337 4338 thermal-sensors = <&tsens1 6>; 4339 4340 trips { 4341 mdm_alert0: trip-point0 { 4342 temperature = <90000>; 4343 hysteresis = <2000>; 4344 type = "hot"; 4345 }; 4346 4347 mdm_crit: mdm_crit { 4348 temperature = <110000>; 4349 hysteresis = <2000>; 4350 type = "critical"; 4351 }; 4352 }; 4353 }; 4354 4355 mdm-dsp-thermal { 4356 polling-delay-passive = <250>; 4357 polling-delay = <0>; 4358 4359 thermal-sensors = <&tsens1 7>; 4360 4361 trips { 4362 mdm_dsp_alert0: trip-point0 { 4363 temperature = <90000>; 4364 hysteresis = <2000>; 4365 type = "hot"; 4366 }; 4367 4368 mdm_dsp_crit: mdm_dsp_crit { 4369 temperature = <110000>; 4370 hysteresis = <2000>; 4371 type = "critical"; 4372 }; 4373 }; 4374 }; 4375 4376 npu-thermal { 4377 polling-delay-passive = <250>; 4378 polling-delay = <0>; 4379 4380 thermal-sensors = <&tsens1 8>; 4381 4382 trips { 4383 npu_alert0: trip-point0 { 4384 temperature = <90000>; 4385 hysteresis = <2000>; 4386 type = "hot"; 4387 }; 4388 4389 npu_crit: npu_crit { 4390 temperature = <110000>; 4391 hysteresis = <2000>; 4392 type = "critical"; 4393 }; 4394 }; 4395 }; 4396 4397 video-thermal { 4398 polling-delay-passive = <250>; 4399 polling-delay = <0>; 4400 4401 thermal-sensors = <&tsens1 9>; 4402 4403 trips { 4404 video_alert0: trip-point0 { 4405 temperature = <90000>; 4406 hysteresis = <2000>; 4407 type = "hot"; 4408 }; 4409 4410 video_crit: video_crit { 4411 temperature = <110000>; 4412 hysteresis = <2000>; 4413 type = "critical"; 4414 }; 4415 }; 4416 }; 4417 }; 4418 4419 timer { 4420 compatible = "arm,armv8-timer"; 4421 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4422 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4423 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4424 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4425 }; 4426}; 4427