1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-aoss-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 aliases { 34 mmc1 = &sdhc_1; 35 mmc2 = &sdhc_2; 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi3 = &spi3; 51 spi5 = &spi5; 52 spi6 = &spi6; 53 spi8 = &spi8; 54 spi10 = &spi10; 55 spi11 = &spi11; 56 }; 57 58 clocks { 59 xo_board: xo-board { 60 compatible = "fixed-clock"; 61 clock-frequency = <38400000>; 62 #clock-cells = <0>; 63 }; 64 65 sleep_clk: sleep-clk { 66 compatible = "fixed-clock"; 67 clock-frequency = <32764>; 68 #clock-cells = <0>; 69 }; 70 }; 71 72 reserved_memory: reserved-memory { 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 hyp_mem: memory@80000000 { 78 reg = <0x0 0x80000000 0x0 0x600000>; 79 no-map; 80 }; 81 82 xbl_mem: memory@80600000 { 83 reg = <0x0 0x80600000 0x0 0x200000>; 84 no-map; 85 }; 86 87 aop_mem: memory@80800000 { 88 reg = <0x0 0x80800000 0x0 0x20000>; 89 no-map; 90 }; 91 92 aop_cmd_db_mem: memory@80820000 { 93 reg = <0x0 0x80820000 0x0 0x20000>; 94 compatible = "qcom,cmd-db"; 95 no-map; 96 }; 97 98 sec_apps_mem: memory@808ff000 { 99 reg = <0x0 0x808ff000 0x0 0x1000>; 100 no-map; 101 }; 102 103 smem_mem: memory@80900000 { 104 reg = <0x0 0x80900000 0x0 0x200000>; 105 no-map; 106 }; 107 108 tz_mem: memory@80b00000 { 109 reg = <0x0 0x80b00000 0x0 0x3900000>; 110 no-map; 111 }; 112 113 rmtfs_mem: memory@94600000 { 114 compatible = "qcom,rmtfs-mem"; 115 reg = <0x0 0x94600000 0x0 0x200000>; 116 no-map; 117 118 qcom,client-id = <1>; 119 qcom,vmid = <15>; 120 }; 121 }; 122 123 cpus { 124 #address-cells = <2>; 125 #size-cells = <0>; 126 127 CPU0: cpu@0 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo468"; 130 reg = <0x0 0x0>; 131 enable-method = "psci"; 132 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 133 &LITTLE_CPU_SLEEP_1 134 &CLUSTER_SLEEP_0>; 135 capacity-dmips-mhz = <1024>; 136 dynamic-power-coefficient = <100>; 137 operating-points-v2 = <&cpu0_opp_table>; 138 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 139 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 140 next-level-cache = <&L2_0>; 141 #cooling-cells = <2>; 142 qcom,freq-domain = <&cpufreq_hw 0>; 143 L2_0: l2-cache { 144 compatible = "cache"; 145 next-level-cache = <&L3_0>; 146 L3_0: l3-cache { 147 compatible = "cache"; 148 }; 149 }; 150 }; 151 152 CPU1: cpu@100 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo468"; 155 reg = <0x0 0x100>; 156 enable-method = "psci"; 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 158 &LITTLE_CPU_SLEEP_1 159 &CLUSTER_SLEEP_0>; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <100>; 162 next-level-cache = <&L2_100>; 163 operating-points-v2 = <&cpu0_opp_table>; 164 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 #cooling-cells = <2>; 167 qcom,freq-domain = <&cpufreq_hw 0>; 168 L2_100: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU2: cpu@200 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo468"; 177 reg = <0x0 0x200>; 178 enable-method = "psci"; 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 180 &LITTLE_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 capacity-dmips-mhz = <1024>; 183 dynamic-power-coefficient = <100>; 184 next-level-cache = <&L2_200>; 185 operating-points-v2 = <&cpu0_opp_table>; 186 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188 #cooling-cells = <2>; 189 qcom,freq-domain = <&cpufreq_hw 0>; 190 L2_200: l2-cache { 191 compatible = "cache"; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 CPU3: cpu@300 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo468"; 199 reg = <0x0 0x300>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 capacity-dmips-mhz = <1024>; 205 dynamic-power-coefficient = <100>; 206 next-level-cache = <&L2_300>; 207 operating-points-v2 = <&cpu0_opp_table>; 208 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 210 #cooling-cells = <2>; 211 qcom,freq-domain = <&cpufreq_hw 0>; 212 L2_300: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU4: cpu@400 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo468"; 221 reg = <0x0 0x400>; 222 enable-method = "psci"; 223 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 224 &LITTLE_CPU_SLEEP_1 225 &CLUSTER_SLEEP_0>; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <100>; 228 next-level-cache = <&L2_400>; 229 operating-points-v2 = <&cpu0_opp_table>; 230 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 232 #cooling-cells = <2>; 233 qcom,freq-domain = <&cpufreq_hw 0>; 234 L2_400: l2-cache { 235 compatible = "cache"; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU5: cpu@500 { 241 device_type = "cpu"; 242 compatible = "qcom,kryo468"; 243 reg = <0x0 0x500>; 244 enable-method = "psci"; 245 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 246 &LITTLE_CPU_SLEEP_1 247 &CLUSTER_SLEEP_0>; 248 capacity-dmips-mhz = <1024>; 249 dynamic-power-coefficient = <100>; 250 next-level-cache = <&L2_500>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 254 #cooling-cells = <2>; 255 qcom,freq-domain = <&cpufreq_hw 0>; 256 L2_500: l2-cache { 257 compatible = "cache"; 258 next-level-cache = <&L3_0>; 259 }; 260 }; 261 262 CPU6: cpu@600 { 263 device_type = "cpu"; 264 compatible = "qcom,kryo468"; 265 reg = <0x0 0x600>; 266 enable-method = "psci"; 267 cpu-idle-states = <&BIG_CPU_SLEEP_0 268 &BIG_CPU_SLEEP_1 269 &CLUSTER_SLEEP_0>; 270 capacity-dmips-mhz = <1740>; 271 dynamic-power-coefficient = <405>; 272 next-level-cache = <&L2_600>; 273 operating-points-v2 = <&cpu6_opp_table>; 274 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 275 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 276 #cooling-cells = <2>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 L2_600: l2-cache { 279 compatible = "cache"; 280 next-level-cache = <&L3_0>; 281 }; 282 }; 283 284 CPU7: cpu@700 { 285 device_type = "cpu"; 286 compatible = "qcom,kryo468"; 287 reg = <0x0 0x700>; 288 enable-method = "psci"; 289 cpu-idle-states = <&BIG_CPU_SLEEP_0 290 &BIG_CPU_SLEEP_1 291 &CLUSTER_SLEEP_0>; 292 capacity-dmips-mhz = <1740>; 293 dynamic-power-coefficient = <405>; 294 next-level-cache = <&L2_700>; 295 operating-points-v2 = <&cpu6_opp_table>; 296 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 297 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 298 #cooling-cells = <2>; 299 qcom,freq-domain = <&cpufreq_hw 1>; 300 L2_700: l2-cache { 301 compatible = "cache"; 302 next-level-cache = <&L3_0>; 303 }; 304 }; 305 306 cpu-map { 307 cluster0 { 308 core0 { 309 cpu = <&CPU0>; 310 }; 311 312 core1 { 313 cpu = <&CPU1>; 314 }; 315 316 core2 { 317 cpu = <&CPU2>; 318 }; 319 320 core3 { 321 cpu = <&CPU3>; 322 }; 323 324 core4 { 325 cpu = <&CPU4>; 326 }; 327 328 core5 { 329 cpu = <&CPU5>; 330 }; 331 332 core6 { 333 cpu = <&CPU6>; 334 }; 335 336 core7 { 337 cpu = <&CPU7>; 338 }; 339 }; 340 }; 341 342 idle-states { 343 entry-method = "psci"; 344 345 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 346 compatible = "arm,idle-state"; 347 idle-state-name = "little-power-down"; 348 arm,psci-suspend-param = <0x40000003>; 349 entry-latency-us = <549>; 350 exit-latency-us = <901>; 351 min-residency-us = <1774>; 352 local-timer-stop; 353 }; 354 355 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 356 compatible = "arm,idle-state"; 357 idle-state-name = "little-rail-power-down"; 358 arm,psci-suspend-param = <0x40000004>; 359 entry-latency-us = <702>; 360 exit-latency-us = <915>; 361 min-residency-us = <4001>; 362 local-timer-stop; 363 }; 364 365 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "big-power-down"; 368 arm,psci-suspend-param = <0x40000003>; 369 entry-latency-us = <523>; 370 exit-latency-us = <1244>; 371 min-residency-us = <2207>; 372 local-timer-stop; 373 }; 374 375 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 376 compatible = "arm,idle-state"; 377 idle-state-name = "big-rail-power-down"; 378 arm,psci-suspend-param = <0x40000004>; 379 entry-latency-us = <526>; 380 exit-latency-us = <1854>; 381 min-residency-us = <5555>; 382 local-timer-stop; 383 }; 384 385 CLUSTER_SLEEP_0: cluster-sleep-0 { 386 compatible = "arm,idle-state"; 387 idle-state-name = "cluster-power-down"; 388 arm,psci-suspend-param = <0x40003444>; 389 entry-latency-us = <3263>; 390 exit-latency-us = <6562>; 391 min-residency-us = <9926>; 392 local-timer-stop; 393 }; 394 }; 395 }; 396 397 cpu0_opp_table: cpu0_opp_table { 398 compatible = "operating-points-v2"; 399 opp-shared; 400 401 cpu0_opp1: opp-300000000 { 402 opp-hz = /bits/ 64 <300000000>; 403 opp-peak-kBps = <1200000 4800000>; 404 }; 405 406 cpu0_opp2: opp-576000000 { 407 opp-hz = /bits/ 64 <576000000>; 408 opp-peak-kBps = <1200000 4800000>; 409 }; 410 411 cpu0_opp3: opp-768000000 { 412 opp-hz = /bits/ 64 <768000000>; 413 opp-peak-kBps = <1200000 4800000>; 414 }; 415 416 cpu0_opp4: opp-1017600000 { 417 opp-hz = /bits/ 64 <1017600000>; 418 opp-peak-kBps = <1804000 8908800>; 419 }; 420 421 cpu0_opp5: opp-1248000000 { 422 opp-hz = /bits/ 64 <1248000000>; 423 opp-peak-kBps = <2188000 12902400>; 424 }; 425 426 cpu0_opp6: opp-1324800000 { 427 opp-hz = /bits/ 64 <1324800000>; 428 opp-peak-kBps = <2188000 12902400>; 429 }; 430 431 cpu0_opp7: opp-1516800000 { 432 opp-hz = /bits/ 64 <1516800000>; 433 opp-peak-kBps = <3072000 15052800>; 434 }; 435 436 cpu0_opp8: opp-1612800000 { 437 opp-hz = /bits/ 64 <1612800000>; 438 opp-peak-kBps = <3072000 15052800>; 439 }; 440 441 cpu0_opp9: opp-1708800000 { 442 opp-hz = /bits/ 64 <1708800000>; 443 opp-peak-kBps = <3072000 15052800>; 444 }; 445 446 cpu0_opp10: opp-1804800000 { 447 opp-hz = /bits/ 64 <1804800000>; 448 opp-peak-kBps = <4068000 22425600>; 449 }; 450 }; 451 452 cpu6_opp_table: cpu6_opp_table { 453 compatible = "operating-points-v2"; 454 opp-shared; 455 456 cpu6_opp1: opp-300000000 { 457 opp-hz = /bits/ 64 <300000000>; 458 opp-peak-kBps = <2188000 8908800>; 459 }; 460 461 cpu6_opp2: opp-652800000 { 462 opp-hz = /bits/ 64 <652800000>; 463 opp-peak-kBps = <2188000 8908800>; 464 }; 465 466 cpu6_opp3: opp-825600000 { 467 opp-hz = /bits/ 64 <825600000>; 468 opp-peak-kBps = <2188000 8908800>; 469 }; 470 471 cpu6_opp4: opp-979200000 { 472 opp-hz = /bits/ 64 <979200000>; 473 opp-peak-kBps = <2188000 8908800>; 474 }; 475 476 cpu6_opp5: opp-1113600000 { 477 opp-hz = /bits/ 64 <1113600000>; 478 opp-peak-kBps = <2188000 8908800>; 479 }; 480 481 cpu6_opp6: opp-1267200000 { 482 opp-hz = /bits/ 64 <1267200000>; 483 opp-peak-kBps = <4068000 12902400>; 484 }; 485 486 cpu6_opp7: opp-1555200000 { 487 opp-hz = /bits/ 64 <1555200000>; 488 opp-peak-kBps = <4068000 15052800>; 489 }; 490 491 cpu6_opp8: opp-1708800000 { 492 opp-hz = /bits/ 64 <1708800000>; 493 opp-peak-kBps = <6220000 19353600>; 494 }; 495 496 cpu6_opp9: opp-1843200000 { 497 opp-hz = /bits/ 64 <1843200000>; 498 opp-peak-kBps = <6220000 19353600>; 499 }; 500 501 cpu6_opp10: opp-1900800000 { 502 opp-hz = /bits/ 64 <1900800000>; 503 opp-peak-kBps = <6220000 22425600>; 504 }; 505 506 cpu6_opp11: opp-1996800000 { 507 opp-hz = /bits/ 64 <1996800000>; 508 opp-peak-kBps = <6220000 22425600>; 509 }; 510 511 cpu6_opp12: opp-2112000000 { 512 opp-hz = /bits/ 64 <2112000000>; 513 opp-peak-kBps = <6220000 22425600>; 514 }; 515 516 cpu6_opp13: opp-2208000000 { 517 opp-hz = /bits/ 64 <2208000000>; 518 opp-peak-kBps = <7216000 22425600>; 519 }; 520 521 cpu6_opp14: opp-2323200000 { 522 opp-hz = /bits/ 64 <2323200000>; 523 opp-peak-kBps = <7216000 22425600>; 524 }; 525 526 cpu6_opp15: opp-2400000000 { 527 opp-hz = /bits/ 64 <2400000000>; 528 opp-peak-kBps = <8532000 23347200>; 529 }; 530 531 cpu6_opp16: opp-2553600000 { 532 opp-hz = /bits/ 64 <2553600000>; 533 opp-peak-kBps = <8532000 23347200>; 534 }; 535 }; 536 537 memory@80000000 { 538 device_type = "memory"; 539 /* We expect the bootloader to fill in the size */ 540 reg = <0 0x80000000 0 0>; 541 }; 542 543 pmu { 544 compatible = "arm,armv8-pmuv3"; 545 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 546 }; 547 548 firmware { 549 scm { 550 compatible = "qcom,scm-sc7180", "qcom,scm"; 551 }; 552 }; 553 554 tcsr_mutex: hwlock { 555 compatible = "qcom,tcsr-mutex"; 556 syscon = <&tcsr_mutex_regs 0 0x1000>; 557 #hwlock-cells = <1>; 558 }; 559 560 smem { 561 compatible = "qcom,smem"; 562 memory-region = <&smem_mem>; 563 hwlocks = <&tcsr_mutex 3>; 564 }; 565 566 smp2p-cdsp { 567 compatible = "qcom,smp2p"; 568 qcom,smem = <94>, <432>; 569 570 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 571 572 mboxes = <&apss_shared 6>; 573 574 qcom,local-pid = <0>; 575 qcom,remote-pid = <5>; 576 577 cdsp_smp2p_out: master-kernel { 578 qcom,entry-name = "master-kernel"; 579 #qcom,smem-state-cells = <1>; 580 }; 581 582 cdsp_smp2p_in: slave-kernel { 583 qcom,entry-name = "slave-kernel"; 584 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 }; 589 590 smp2p-lpass { 591 compatible = "qcom,smp2p"; 592 qcom,smem = <443>, <429>; 593 594 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 595 596 mboxes = <&apss_shared 10>; 597 598 qcom,local-pid = <0>; 599 qcom,remote-pid = <2>; 600 601 adsp_smp2p_out: master-kernel { 602 qcom,entry-name = "master-kernel"; 603 #qcom,smem-state-cells = <1>; 604 }; 605 606 adsp_smp2p_in: slave-kernel { 607 qcom,entry-name = "slave-kernel"; 608 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 }; 613 614 smp2p-mpss { 615 compatible = "qcom,smp2p"; 616 qcom,smem = <435>, <428>; 617 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 618 mboxes = <&apss_shared 14>; 619 qcom,local-pid = <0>; 620 qcom,remote-pid = <1>; 621 622 modem_smp2p_out: master-kernel { 623 qcom,entry-name = "master-kernel"; 624 #qcom,smem-state-cells = <1>; 625 }; 626 627 modem_smp2p_in: slave-kernel { 628 qcom,entry-name = "slave-kernel"; 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 }; 632 633 ipa_smp2p_out: ipa-ap-to-modem { 634 qcom,entry-name = "ipa"; 635 #qcom,smem-state-cells = <1>; 636 }; 637 638 ipa_smp2p_in: ipa-modem-to-ap { 639 qcom,entry-name = "ipa"; 640 interrupt-controller; 641 #interrupt-cells = <2>; 642 }; 643 }; 644 645 psci { 646 compatible = "arm,psci-1.0"; 647 method = "smc"; 648 }; 649 650 soc: soc@0 { 651 #address-cells = <2>; 652 #size-cells = <2>; 653 ranges = <0 0 0 0 0x10 0>; 654 dma-ranges = <0 0 0 0 0x10 0>; 655 compatible = "simple-bus"; 656 657 gcc: clock-controller@100000 { 658 compatible = "qcom,gcc-sc7180"; 659 reg = <0 0x00100000 0 0x1f0000>; 660 clocks = <&rpmhcc RPMH_CXO_CLK>, 661 <&rpmhcc RPMH_CXO_CLK_A>, 662 <&sleep_clk>; 663 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 664 #clock-cells = <1>; 665 #reset-cells = <1>; 666 #power-domain-cells = <1>; 667 }; 668 669 qfprom: efuse@784000 { 670 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 671 reg = <0 0x00784000 0 0x8ff>, 672 <0 0x00780000 0 0x7a0>, 673 <0 0x00782000 0 0x100>, 674 <0 0x00786000 0 0x1fff>; 675 676 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 677 clock-names = "core"; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 681 qusb2p_hstx_trim: hstx-trim-primary@25b { 682 reg = <0x25b 0x1>; 683 bits = <1 3>; 684 }; 685 686 gpu_speed_bin: gpu_speed_bin@1d2 { 687 reg = <0x1d2 0x2>; 688 bits = <5 8>; 689 }; 690 }; 691 692 sdhc_1: sdhci@7c4000 { 693 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 694 reg = <0 0x7c4000 0 0x1000>, 695 <0 0x07c5000 0 0x1000>; 696 reg-names = "hc", "cqhci"; 697 698 iommus = <&apps_smmu 0x60 0x0>; 699 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "hc_irq", "pwr_irq"; 702 703 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 704 <&gcc GCC_SDCC1_AHB_CLK>; 705 clock-names = "core", "iface"; 706 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 707 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 708 interconnect-names = "sdhc-ddr","cpu-sdhc"; 709 power-domains = <&rpmhpd SC7180_CX>; 710 operating-points-v2 = <&sdhc1_opp_table>; 711 712 bus-width = <8>; 713 non-removable; 714 supports-cqe; 715 716 mmc-ddr-1_8v; 717 mmc-hs200-1_8v; 718 mmc-hs400-1_8v; 719 mmc-hs400-enhanced-strobe; 720 721 status = "disabled"; 722 723 sdhc1_opp_table: sdhc1-opp-table { 724 compatible = "operating-points-v2"; 725 726 opp-100000000 { 727 opp-hz = /bits/ 64 <100000000>; 728 required-opps = <&rpmhpd_opp_low_svs>; 729 opp-peak-kBps = <100000 100000>; 730 opp-avg-kBps = <100000 50000>; 731 }; 732 733 opp-384000000 { 734 opp-hz = /bits/ 64 <384000000>; 735 required-opps = <&rpmhpd_opp_svs_l1>; 736 opp-peak-kBps = <600000 900000>; 737 opp-avg-kBps = <261438 300000>; 738 }; 739 }; 740 }; 741 742 qup_opp_table: qup-opp-table { 743 compatible = "operating-points-v2"; 744 745 opp-75000000 { 746 opp-hz = /bits/ 64 <75000000>; 747 required-opps = <&rpmhpd_opp_low_svs>; 748 }; 749 750 opp-100000000 { 751 opp-hz = /bits/ 64 <100000000>; 752 required-opps = <&rpmhpd_opp_svs>; 753 }; 754 755 opp-128000000 { 756 opp-hz = /bits/ 64 <128000000>; 757 required-opps = <&rpmhpd_opp_nom>; 758 }; 759 }; 760 761 qupv3_id_0: geniqup@8c0000 { 762 compatible = "qcom,geni-se-qup"; 763 reg = <0 0x008c0000 0 0x6000>; 764 clock-names = "m-ahb", "s-ahb"; 765 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 766 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 767 #address-cells = <2>; 768 #size-cells = <2>; 769 ranges; 770 iommus = <&apps_smmu 0x43 0x0>; 771 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; 772 interconnect-names = "qup-core"; 773 status = "disabled"; 774 775 i2c0: i2c@880000 { 776 compatible = "qcom,geni-i2c"; 777 reg = <0 0x00880000 0 0x4000>; 778 clock-names = "se"; 779 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 780 pinctrl-names = "default"; 781 pinctrl-0 = <&qup_i2c0_default>; 782 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 786 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 787 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 788 interconnect-names = "qup-core", "qup-config", 789 "qup-memory"; 790 status = "disabled"; 791 }; 792 793 spi0: spi@880000 { 794 compatible = "qcom,geni-spi"; 795 reg = <0 0x00880000 0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_spi0_default>; 800 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 power-domains = <&rpmhpd SC7180_CX>; 804 operating-points-v2 = <&qup_opp_table>; 805 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 806 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 807 interconnect-names = "qup-core", "qup-config"; 808 status = "disabled"; 809 }; 810 811 uart0: serial@880000 { 812 compatible = "qcom,geni-uart"; 813 reg = <0 0x00880000 0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_uart0_default>; 818 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 819 power-domains = <&rpmhpd SC7180_CX>; 820 operating-points-v2 = <&qup_opp_table>; 821 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 822 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 823 interconnect-names = "qup-core", "qup-config"; 824 status = "disabled"; 825 }; 826 827 i2c1: i2c@884000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x00884000 0 0x4000>; 830 clock-names = "se"; 831 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c1_default>; 834 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 839 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 840 interconnect-names = "qup-core", "qup-config", 841 "qup-memory"; 842 status = "disabled"; 843 }; 844 845 spi1: spi@884000 { 846 compatible = "qcom,geni-spi"; 847 reg = <0 0x00884000 0 0x4000>; 848 clock-names = "se"; 849 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&qup_spi1_default>; 852 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 power-domains = <&rpmhpd SC7180_CX>; 856 operating-points-v2 = <&qup_opp_table>; 857 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 858 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 859 interconnect-names = "qup-core", "qup-config"; 860 status = "disabled"; 861 }; 862 863 uart1: serial@884000 { 864 compatible = "qcom,geni-uart"; 865 reg = <0 0x00884000 0 0x4000>; 866 clock-names = "se"; 867 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&qup_uart1_default>; 870 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 871 power-domains = <&rpmhpd SC7180_CX>; 872 operating-points-v2 = <&qup_opp_table>; 873 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 874 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 875 interconnect-names = "qup-core", "qup-config"; 876 status = "disabled"; 877 }; 878 879 i2c2: i2c@888000 { 880 compatible = "qcom,geni-i2c"; 881 reg = <0 0x00888000 0 0x4000>; 882 clock-names = "se"; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 884 pinctrl-names = "default"; 885 pinctrl-0 = <&qup_i2c2_default>; 886 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 890 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 891 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 892 interconnect-names = "qup-core", "qup-config", 893 "qup-memory"; 894 status = "disabled"; 895 }; 896 897 uart2: serial@888000 { 898 compatible = "qcom,geni-uart"; 899 reg = <0 0x00888000 0 0x4000>; 900 clock-names = "se"; 901 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_uart2_default>; 904 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 905 power-domains = <&rpmhpd SC7180_CX>; 906 operating-points-v2 = <&qup_opp_table>; 907 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 908 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 909 interconnect-names = "qup-core", "qup-config"; 910 status = "disabled"; 911 }; 912 913 i2c3: i2c@88c000 { 914 compatible = "qcom,geni-i2c"; 915 reg = <0 0x0088c000 0 0x4000>; 916 clock-names = "se"; 917 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_i2c3_default>; 920 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 924 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 925 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 926 interconnect-names = "qup-core", "qup-config", 927 "qup-memory"; 928 status = "disabled"; 929 }; 930 931 spi3: spi@88c000 { 932 compatible = "qcom,geni-spi"; 933 reg = <0 0x0088c000 0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_spi3_default>; 938 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 power-domains = <&rpmhpd SC7180_CX>; 942 operating-points-v2 = <&qup_opp_table>; 943 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 944 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 945 interconnect-names = "qup-core", "qup-config"; 946 status = "disabled"; 947 }; 948 949 uart3: serial@88c000 { 950 compatible = "qcom,geni-uart"; 951 reg = <0 0x0088c000 0 0x4000>; 952 clock-names = "se"; 953 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&qup_uart3_default>; 956 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 957 power-domains = <&rpmhpd SC7180_CX>; 958 operating-points-v2 = <&qup_opp_table>; 959 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 960 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 961 interconnect-names = "qup-core", "qup-config"; 962 status = "disabled"; 963 }; 964 965 i2c4: i2c@890000 { 966 compatible = "qcom,geni-i2c"; 967 reg = <0 0x00890000 0 0x4000>; 968 clock-names = "se"; 969 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&qup_i2c4_default>; 972 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 977 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 978 interconnect-names = "qup-core", "qup-config", 979 "qup-memory"; 980 status = "disabled"; 981 }; 982 983 uart4: serial@890000 { 984 compatible = "qcom,geni-uart"; 985 reg = <0 0x00890000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_uart4_default>; 990 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 991 power-domains = <&rpmhpd SC7180_CX>; 992 operating-points-v2 = <&qup_opp_table>; 993 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 995 interconnect-names = "qup-core", "qup-config"; 996 status = "disabled"; 997 }; 998 999 i2c5: i2c@894000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00894000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&qup_i2c5_default>; 1006 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1010 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1011 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1012 interconnect-names = "qup-core", "qup-config", 1013 "qup-memory"; 1014 status = "disabled"; 1015 }; 1016 1017 spi5: spi@894000 { 1018 compatible = "qcom,geni-spi"; 1019 reg = <0 0x00894000 0 0x4000>; 1020 clock-names = "se"; 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&qup_spi5_default>; 1024 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 power-domains = <&rpmhpd SC7180_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1031 interconnect-names = "qup-core", "qup-config"; 1032 status = "disabled"; 1033 }; 1034 1035 uart5: serial@894000 { 1036 compatible = "qcom,geni-uart"; 1037 reg = <0 0x00894000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_uart5_default>; 1042 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd SC7180_CX>; 1044 operating-points-v2 = <&qup_opp_table>; 1045 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1047 interconnect-names = "qup-core", "qup-config"; 1048 status = "disabled"; 1049 }; 1050 }; 1051 1052 qupv3_id_1: geniqup@ac0000 { 1053 compatible = "qcom,geni-se-qup"; 1054 reg = <0 0x00ac0000 0 0x6000>; 1055 clock-names = "m-ahb", "s-ahb"; 1056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1058 #address-cells = <2>; 1059 #size-cells = <2>; 1060 ranges; 1061 iommus = <&apps_smmu 0x4c3 0x0>; 1062 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; 1063 interconnect-names = "qup-core"; 1064 status = "disabled"; 1065 1066 i2c6: i2c@a80000 { 1067 compatible = "qcom,geni-i2c"; 1068 reg = <0 0x00a80000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_i2c6_default>; 1073 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1078 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1079 interconnect-names = "qup-core", "qup-config", 1080 "qup-memory"; 1081 status = "disabled"; 1082 }; 1083 1084 spi6: spi@a80000 { 1085 compatible = "qcom,geni-spi"; 1086 reg = <0 0x00a80000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_spi6_default>; 1091 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 power-domains = <&rpmhpd SC7180_CX>; 1095 operating-points-v2 = <&qup_opp_table>; 1096 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1098 interconnect-names = "qup-core", "qup-config"; 1099 status = "disabled"; 1100 }; 1101 1102 uart6: serial@a80000 { 1103 compatible = "qcom,geni-uart"; 1104 reg = <0 0x00a80000 0 0x4000>; 1105 clock-names = "se"; 1106 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&qup_uart6_default>; 1109 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1110 power-domains = <&rpmhpd SC7180_CX>; 1111 operating-points-v2 = <&qup_opp_table>; 1112 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1114 interconnect-names = "qup-core", "qup-config"; 1115 status = "disabled"; 1116 }; 1117 1118 i2c7: i2c@a84000 { 1119 compatible = "qcom,geni-i2c"; 1120 reg = <0 0x00a84000 0 0x4000>; 1121 clock-names = "se"; 1122 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_i2c7_default>; 1125 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1130 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1131 interconnect-names = "qup-core", "qup-config", 1132 "qup-memory"; 1133 status = "disabled"; 1134 }; 1135 1136 uart7: serial@a84000 { 1137 compatible = "qcom,geni-uart"; 1138 reg = <0 0x00a84000 0 0x4000>; 1139 clock-names = "se"; 1140 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_uart7_default>; 1143 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1144 power-domains = <&rpmhpd SC7180_CX>; 1145 operating-points-v2 = <&qup_opp_table>; 1146 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1148 interconnect-names = "qup-core", "qup-config"; 1149 status = "disabled"; 1150 }; 1151 1152 i2c8: i2c@a88000 { 1153 compatible = "qcom,geni-i2c"; 1154 reg = <0 0x00a88000 0 0x4000>; 1155 clock-names = "se"; 1156 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_i2c8_default>; 1159 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1164 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1165 interconnect-names = "qup-core", "qup-config", 1166 "qup-memory"; 1167 status = "disabled"; 1168 }; 1169 1170 spi8: spi@a88000 { 1171 compatible = "qcom,geni-spi"; 1172 reg = <0 0x00a88000 0 0x4000>; 1173 clock-names = "se"; 1174 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_spi8_default>; 1177 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 power-domains = <&rpmhpd SC7180_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1184 interconnect-names = "qup-core", "qup-config"; 1185 status = "disabled"; 1186 }; 1187 1188 uart8: serial@a88000 { 1189 compatible = "qcom,geni-debug-uart"; 1190 reg = <0 0x00a88000 0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_uart8_default>; 1195 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1196 power-domains = <&rpmhpd SC7180_CX>; 1197 operating-points-v2 = <&qup_opp_table>; 1198 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1200 interconnect-names = "qup-core", "qup-config"; 1201 status = "disabled"; 1202 }; 1203 1204 i2c9: i2c@a8c000 { 1205 compatible = "qcom,geni-i2c"; 1206 reg = <0 0x00a8c000 0 0x4000>; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_i2c9_default>; 1211 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1216 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1217 interconnect-names = "qup-core", "qup-config", 1218 "qup-memory"; 1219 status = "disabled"; 1220 }; 1221 1222 uart9: serial@a8c000 { 1223 compatible = "qcom,geni-uart"; 1224 reg = <0 0x00a8c000 0 0x4000>; 1225 clock-names = "se"; 1226 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1227 pinctrl-names = "default"; 1228 pinctrl-0 = <&qup_uart9_default>; 1229 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1230 power-domains = <&rpmhpd SC7180_CX>; 1231 operating-points-v2 = <&qup_opp_table>; 1232 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1233 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1234 interconnect-names = "qup-core", "qup-config"; 1235 status = "disabled"; 1236 }; 1237 1238 i2c10: i2c@a90000 { 1239 compatible = "qcom,geni-i2c"; 1240 reg = <0 0x00a90000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_i2c10_default>; 1245 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1249 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1250 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1251 interconnect-names = "qup-core", "qup-config", 1252 "qup-memory"; 1253 status = "disabled"; 1254 }; 1255 1256 spi10: spi@a90000 { 1257 compatible = "qcom,geni-spi"; 1258 reg = <0 0x00a90000 0 0x4000>; 1259 clock-names = "se"; 1260 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&qup_spi10_default>; 1263 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 power-domains = <&rpmhpd SC7180_CX>; 1267 operating-points-v2 = <&qup_opp_table>; 1268 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1269 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1270 interconnect-names = "qup-core", "qup-config"; 1271 status = "disabled"; 1272 }; 1273 1274 uart10: serial@a90000 { 1275 compatible = "qcom,geni-uart"; 1276 reg = <0 0x00a90000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_uart10_default>; 1281 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd SC7180_CX>; 1283 operating-points-v2 = <&qup_opp_table>; 1284 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1285 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1286 interconnect-names = "qup-core", "qup-config"; 1287 status = "disabled"; 1288 }; 1289 1290 i2c11: i2c@a94000 { 1291 compatible = "qcom,geni-i2c"; 1292 reg = <0 0x00a94000 0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&qup_i2c11_default>; 1297 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1301 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1302 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1303 interconnect-names = "qup-core", "qup-config", 1304 "qup-memory"; 1305 status = "disabled"; 1306 }; 1307 1308 spi11: spi@a94000 { 1309 compatible = "qcom,geni-spi"; 1310 reg = <0 0x00a94000 0 0x4000>; 1311 clock-names = "se"; 1312 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&qup_spi11_default>; 1315 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 power-domains = <&rpmhpd SC7180_CX>; 1319 operating-points-v2 = <&qup_opp_table>; 1320 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1322 interconnect-names = "qup-core", "qup-config"; 1323 status = "disabled"; 1324 }; 1325 1326 uart11: serial@a94000 { 1327 compatible = "qcom,geni-uart"; 1328 reg = <0 0x00a94000 0 0x4000>; 1329 clock-names = "se"; 1330 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_uart11_default>; 1333 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1334 power-domains = <&rpmhpd SC7180_CX>; 1335 operating-points-v2 = <&qup_opp_table>; 1336 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1338 interconnect-names = "qup-core", "qup-config"; 1339 status = "disabled"; 1340 }; 1341 }; 1342 1343 config_noc: interconnect@1500000 { 1344 compatible = "qcom,sc7180-config-noc"; 1345 reg = <0 0x01500000 0 0x28000>; 1346 #interconnect-cells = <2>; 1347 qcom,bcm-voters = <&apps_bcm_voter>; 1348 }; 1349 1350 system_noc: interconnect@1620000 { 1351 compatible = "qcom,sc7180-system-noc"; 1352 reg = <0 0x01620000 0 0x17080>; 1353 #interconnect-cells = <2>; 1354 qcom,bcm-voters = <&apps_bcm_voter>; 1355 }; 1356 1357 mc_virt: interconnect@1638000 { 1358 compatible = "qcom,sc7180-mc-virt"; 1359 reg = <0 0x01638000 0 0x1000>; 1360 #interconnect-cells = <2>; 1361 qcom,bcm-voters = <&apps_bcm_voter>; 1362 }; 1363 1364 qup_virt: interconnect@1650000 { 1365 compatible = "qcom,sc7180-qup-virt"; 1366 reg = <0 0x01650000 0 0x1000>; 1367 #interconnect-cells = <2>; 1368 qcom,bcm-voters = <&apps_bcm_voter>; 1369 }; 1370 1371 aggre1_noc: interconnect@16e0000 { 1372 compatible = "qcom,sc7180-aggre1-noc"; 1373 reg = <0 0x016e0000 0 0x15080>; 1374 #interconnect-cells = <2>; 1375 qcom,bcm-voters = <&apps_bcm_voter>; 1376 }; 1377 1378 aggre2_noc: interconnect@1705000 { 1379 compatible = "qcom,sc7180-aggre2-noc"; 1380 reg = <0 0x01705000 0 0x9000>; 1381 #interconnect-cells = <2>; 1382 qcom,bcm-voters = <&apps_bcm_voter>; 1383 }; 1384 1385 compute_noc: interconnect@170e000 { 1386 compatible = "qcom,sc7180-compute-noc"; 1387 reg = <0 0x0170e000 0 0x6000>; 1388 #interconnect-cells = <2>; 1389 qcom,bcm-voters = <&apps_bcm_voter>; 1390 }; 1391 1392 mmss_noc: interconnect@1740000 { 1393 compatible = "qcom,sc7180-mmss-noc"; 1394 reg = <0 0x01740000 0 0x1c100>; 1395 #interconnect-cells = <2>; 1396 qcom,bcm-voters = <&apps_bcm_voter>; 1397 }; 1398 1399 ipa_virt: interconnect@1e00000 { 1400 compatible = "qcom,sc7180-ipa-virt"; 1401 reg = <0 0x01e00000 0 0x1000>; 1402 #interconnect-cells = <2>; 1403 qcom,bcm-voters = <&apps_bcm_voter>; 1404 }; 1405 1406 ipa: ipa@1e40000 { 1407 compatible = "qcom,sc7180-ipa"; 1408 1409 iommus = <&apps_smmu 0x440 0x0>, 1410 <&apps_smmu 0x442 0x0>; 1411 reg = <0 0x1e40000 0 0x7000>, 1412 <0 0x1e47000 0 0x2000>, 1413 <0 0x1e04000 0 0x2c000>; 1414 reg-names = "ipa-reg", 1415 "ipa-shared", 1416 "gsi"; 1417 1418 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1419 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1420 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1421 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1422 interrupt-names = "ipa", 1423 "gsi", 1424 "ipa-clock-query", 1425 "ipa-setup-ready"; 1426 1427 clocks = <&rpmhcc RPMH_IPA_CLK>; 1428 clock-names = "core"; 1429 1430 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1431 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1433 interconnect-names = "memory", 1434 "imem", 1435 "config"; 1436 1437 qcom,smem-states = <&ipa_smp2p_out 0>, 1438 <&ipa_smp2p_out 1>; 1439 qcom,smem-state-names = "ipa-clock-enabled-valid", 1440 "ipa-clock-enabled"; 1441 1442 status = "disabled"; 1443 }; 1444 1445 tcsr_mutex_regs: syscon@1f40000 { 1446 compatible = "syscon"; 1447 reg = <0 0x01f40000 0 0x40000>; 1448 }; 1449 1450 tcsr_regs: syscon@1fc0000 { 1451 compatible = "syscon"; 1452 reg = <0 0x01fc0000 0 0x40000>; 1453 }; 1454 1455 tlmm: pinctrl@3500000 { 1456 compatible = "qcom,sc7180-pinctrl"; 1457 reg = <0 0x03500000 0 0x300000>, 1458 <0 0x03900000 0 0x300000>, 1459 <0 0x03d00000 0 0x300000>; 1460 reg-names = "west", "north", "south"; 1461 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1462 gpio-controller; 1463 #gpio-cells = <2>; 1464 interrupt-controller; 1465 #interrupt-cells = <2>; 1466 gpio-ranges = <&tlmm 0 0 120>; 1467 wakeup-parent = <&pdc>; 1468 1469 dp_hot_plug_det: dp-hot-plug-det { 1470 pinmux { 1471 pins = "gpio117"; 1472 function = "dp_hot"; 1473 }; 1474 }; 1475 1476 qspi_clk: qspi-clk { 1477 pinmux { 1478 pins = "gpio63"; 1479 function = "qspi_clk"; 1480 }; 1481 }; 1482 1483 qspi_cs0: qspi-cs0 { 1484 pinmux { 1485 pins = "gpio68"; 1486 function = "qspi_cs"; 1487 }; 1488 }; 1489 1490 qspi_cs1: qspi-cs1 { 1491 pinmux { 1492 pins = "gpio72"; 1493 function = "qspi_cs"; 1494 }; 1495 }; 1496 1497 qspi_data01: qspi-data01 { 1498 pinmux-data { 1499 pins = "gpio64", "gpio65"; 1500 function = "qspi_data"; 1501 }; 1502 }; 1503 1504 qspi_data12: qspi-data12 { 1505 pinmux-data { 1506 pins = "gpio66", "gpio67"; 1507 function = "qspi_data"; 1508 }; 1509 }; 1510 1511 qup_i2c0_default: qup-i2c0-default { 1512 pinmux { 1513 pins = "gpio34", "gpio35"; 1514 function = "qup00"; 1515 }; 1516 }; 1517 1518 qup_i2c1_default: qup-i2c1-default { 1519 pinmux { 1520 pins = "gpio0", "gpio1"; 1521 function = "qup01"; 1522 }; 1523 }; 1524 1525 qup_i2c2_default: qup-i2c2-default { 1526 pinmux { 1527 pins = "gpio15", "gpio16"; 1528 function = "qup02_i2c"; 1529 }; 1530 }; 1531 1532 qup_i2c3_default: qup-i2c3-default { 1533 pinmux { 1534 pins = "gpio38", "gpio39"; 1535 function = "qup03"; 1536 }; 1537 }; 1538 1539 qup_i2c4_default: qup-i2c4-default { 1540 pinmux { 1541 pins = "gpio115", "gpio116"; 1542 function = "qup04_i2c"; 1543 }; 1544 }; 1545 1546 qup_i2c5_default: qup-i2c5-default { 1547 pinmux { 1548 pins = "gpio25", "gpio26"; 1549 function = "qup05"; 1550 }; 1551 }; 1552 1553 qup_i2c6_default: qup-i2c6-default { 1554 pinmux { 1555 pins = "gpio59", "gpio60"; 1556 function = "qup10"; 1557 }; 1558 }; 1559 1560 qup_i2c7_default: qup-i2c7-default { 1561 pinmux { 1562 pins = "gpio6", "gpio7"; 1563 function = "qup11_i2c"; 1564 }; 1565 }; 1566 1567 qup_i2c8_default: qup-i2c8-default { 1568 pinmux { 1569 pins = "gpio42", "gpio43"; 1570 function = "qup12"; 1571 }; 1572 }; 1573 1574 qup_i2c9_default: qup-i2c9-default { 1575 pinmux { 1576 pins = "gpio46", "gpio47"; 1577 function = "qup13_i2c"; 1578 }; 1579 }; 1580 1581 qup_i2c10_default: qup-i2c10-default { 1582 pinmux { 1583 pins = "gpio86", "gpio87"; 1584 function = "qup14"; 1585 }; 1586 }; 1587 1588 qup_i2c11_default: qup-i2c11-default { 1589 pinmux { 1590 pins = "gpio53", "gpio54"; 1591 function = "qup15"; 1592 }; 1593 }; 1594 1595 qup_spi0_default: qup-spi0-default { 1596 pinmux { 1597 pins = "gpio34", "gpio35", 1598 "gpio36", "gpio37"; 1599 function = "qup00"; 1600 }; 1601 }; 1602 1603 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 1604 pinmux { 1605 pins = "gpio34", "gpio35", 1606 "gpio36"; 1607 function = "qup00"; 1608 }; 1609 1610 pinmux-cs { 1611 pins = "gpio37"; 1612 function = "gpio"; 1613 }; 1614 }; 1615 1616 qup_spi1_default: qup-spi1-default { 1617 pinmux { 1618 pins = "gpio0", "gpio1", 1619 "gpio2", "gpio3"; 1620 function = "qup01"; 1621 }; 1622 }; 1623 1624 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 1625 pinmux { 1626 pins = "gpio0", "gpio1", 1627 "gpio2"; 1628 function = "qup01"; 1629 }; 1630 1631 pinmux-cs { 1632 pins = "gpio3"; 1633 function = "gpio"; 1634 }; 1635 }; 1636 1637 qup_spi3_default: qup-spi3-default { 1638 pinmux { 1639 pins = "gpio38", "gpio39", 1640 "gpio40", "gpio41"; 1641 function = "qup03"; 1642 }; 1643 }; 1644 1645 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 1646 pinmux { 1647 pins = "gpio38", "gpio39", 1648 "gpio40"; 1649 function = "qup03"; 1650 }; 1651 1652 pinmux-cs { 1653 pins = "gpio41"; 1654 function = "gpio"; 1655 }; 1656 }; 1657 1658 qup_spi5_default: qup-spi5-default { 1659 pinmux { 1660 pins = "gpio25", "gpio26", 1661 "gpio27", "gpio28"; 1662 function = "qup05"; 1663 }; 1664 }; 1665 1666 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 1667 pinmux { 1668 pins = "gpio25", "gpio26", 1669 "gpio27"; 1670 function = "qup05"; 1671 }; 1672 1673 pinmux-cs { 1674 pins = "gpio28"; 1675 function = "gpio"; 1676 }; 1677 }; 1678 1679 qup_spi6_default: qup-spi6-default { 1680 pinmux { 1681 pins = "gpio59", "gpio60", 1682 "gpio61", "gpio62"; 1683 function = "qup10"; 1684 }; 1685 }; 1686 1687 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 1688 pinmux { 1689 pins = "gpio59", "gpio60", 1690 "gpio61"; 1691 function = "qup10"; 1692 }; 1693 1694 pinmux-cs { 1695 pins = "gpio62"; 1696 function = "gpio"; 1697 }; 1698 }; 1699 1700 qup_spi8_default: qup-spi8-default { 1701 pinmux { 1702 pins = "gpio42", "gpio43", 1703 "gpio44", "gpio45"; 1704 function = "qup12"; 1705 }; 1706 }; 1707 1708 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 1709 pinmux { 1710 pins = "gpio42", "gpio43", 1711 "gpio44"; 1712 function = "qup12"; 1713 }; 1714 1715 pinmux-cs { 1716 pins = "gpio45"; 1717 function = "gpio"; 1718 }; 1719 }; 1720 1721 qup_spi10_default: qup-spi10-default { 1722 pinmux { 1723 pins = "gpio86", "gpio87", 1724 "gpio88", "gpio89"; 1725 function = "qup14"; 1726 }; 1727 }; 1728 1729 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 1730 pinmux { 1731 pins = "gpio86", "gpio87", 1732 "gpio88"; 1733 function = "qup14"; 1734 }; 1735 1736 pinmux-cs { 1737 pins = "gpio89"; 1738 function = "gpio"; 1739 }; 1740 }; 1741 1742 qup_spi11_default: qup-spi11-default { 1743 pinmux { 1744 pins = "gpio53", "gpio54", 1745 "gpio55", "gpio56"; 1746 function = "qup15"; 1747 }; 1748 }; 1749 1750 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 1751 pinmux { 1752 pins = "gpio53", "gpio54", 1753 "gpio55"; 1754 function = "qup15"; 1755 }; 1756 1757 pinmux-cs { 1758 pins = "gpio56"; 1759 function = "gpio"; 1760 }; 1761 }; 1762 1763 qup_uart0_default: qup-uart0-default { 1764 pinmux { 1765 pins = "gpio34", "gpio35", 1766 "gpio36", "gpio37"; 1767 function = "qup00"; 1768 }; 1769 }; 1770 1771 qup_uart1_default: qup-uart1-default { 1772 pinmux { 1773 pins = "gpio0", "gpio1", 1774 "gpio2", "gpio3"; 1775 function = "qup01"; 1776 }; 1777 }; 1778 1779 qup_uart2_default: qup-uart2-default { 1780 pinmux { 1781 pins = "gpio15", "gpio16"; 1782 function = "qup02_uart"; 1783 }; 1784 }; 1785 1786 qup_uart3_default: qup-uart3-default { 1787 pinmux { 1788 pins = "gpio38", "gpio39", 1789 "gpio40", "gpio41"; 1790 function = "qup03"; 1791 }; 1792 }; 1793 1794 qup_uart4_default: qup-uart4-default { 1795 pinmux { 1796 pins = "gpio115", "gpio116"; 1797 function = "qup04_uart"; 1798 }; 1799 }; 1800 1801 qup_uart5_default: qup-uart5-default { 1802 pinmux { 1803 pins = "gpio25", "gpio26", 1804 "gpio27", "gpio28"; 1805 function = "qup05"; 1806 }; 1807 }; 1808 1809 qup_uart6_default: qup-uart6-default { 1810 pinmux { 1811 pins = "gpio59", "gpio60", 1812 "gpio61", "gpio62"; 1813 function = "qup10"; 1814 }; 1815 }; 1816 1817 qup_uart7_default: qup-uart7-default { 1818 pinmux { 1819 pins = "gpio6", "gpio7"; 1820 function = "qup11_uart"; 1821 }; 1822 }; 1823 1824 qup_uart8_default: qup-uart8-default { 1825 pinmux { 1826 pins = "gpio44", "gpio45"; 1827 function = "qup12"; 1828 }; 1829 }; 1830 1831 qup_uart9_default: qup-uart9-default { 1832 pinmux { 1833 pins = "gpio46", "gpio47"; 1834 function = "qup13_uart"; 1835 }; 1836 }; 1837 1838 qup_uart10_default: qup-uart10-default { 1839 pinmux { 1840 pins = "gpio86", "gpio87", 1841 "gpio88", "gpio89"; 1842 function = "qup14"; 1843 }; 1844 }; 1845 1846 qup_uart11_default: qup-uart11-default { 1847 pinmux { 1848 pins = "gpio53", "gpio54", 1849 "gpio55", "gpio56"; 1850 function = "qup15"; 1851 }; 1852 }; 1853 1854 sec_mi2s_active: sec-mi2s-active { 1855 pinmux { 1856 pins = "gpio49", "gpio50", "gpio51"; 1857 function = "mi2s_1"; 1858 }; 1859 }; 1860 1861 pri_mi2s_active: pri-mi2s-active { 1862 pinmux { 1863 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1864 function = "mi2s_0"; 1865 }; 1866 }; 1867 1868 pri_mi2s_mclk_active: pri-mi2s-mclk-active { 1869 pinmux { 1870 pins = "gpio57"; 1871 function = "lpass_ext"; 1872 }; 1873 }; 1874 1875 sdc1_on: sdc1-on { 1876 pinconf-clk { 1877 pins = "sdc1_clk"; 1878 bias-disable; 1879 drive-strength = <16>; 1880 }; 1881 1882 pinconf-cmd { 1883 pins = "sdc1_cmd"; 1884 bias-pull-up; 1885 drive-strength = <10>; 1886 }; 1887 1888 pinconf-data { 1889 pins = "sdc1_data"; 1890 bias-pull-up; 1891 drive-strength = <10>; 1892 }; 1893 1894 pinconf-rclk { 1895 pins = "sdc1_rclk"; 1896 bias-pull-down; 1897 }; 1898 }; 1899 1900 sdc1_off: sdc1-off { 1901 pinconf-clk { 1902 pins = "sdc1_clk"; 1903 bias-disable; 1904 drive-strength = <2>; 1905 }; 1906 1907 pinconf-cmd { 1908 pins = "sdc1_cmd"; 1909 bias-pull-up; 1910 drive-strength = <2>; 1911 }; 1912 1913 pinconf-data { 1914 pins = "sdc1_data"; 1915 bias-pull-up; 1916 drive-strength = <2>; 1917 }; 1918 1919 pinconf-rclk { 1920 pins = "sdc1_rclk"; 1921 bias-pull-down; 1922 }; 1923 }; 1924 1925 sdc2_on: sdc2-on { 1926 pinconf-clk { 1927 pins = "sdc2_clk"; 1928 bias-disable; 1929 drive-strength = <16>; 1930 }; 1931 1932 pinconf-cmd { 1933 pins = "sdc2_cmd"; 1934 bias-pull-up; 1935 drive-strength = <10>; 1936 }; 1937 1938 pinconf-data { 1939 pins = "sdc2_data"; 1940 bias-pull-up; 1941 drive-strength = <10>; 1942 }; 1943 1944 pinconf-sd-cd { 1945 pins = "gpio69"; 1946 bias-pull-up; 1947 drive-strength = <2>; 1948 }; 1949 }; 1950 1951 sdc2_off: sdc2-off { 1952 pinconf-clk { 1953 pins = "sdc2_clk"; 1954 bias-disable; 1955 drive-strength = <2>; 1956 }; 1957 1958 pinconf-cmd { 1959 pins = "sdc2_cmd"; 1960 bias-pull-up; 1961 drive-strength = <2>; 1962 }; 1963 1964 pinconf-data { 1965 pins = "sdc2_data"; 1966 bias-pull-up; 1967 drive-strength = <2>; 1968 }; 1969 1970 pinconf-sd-cd { 1971 pins = "gpio69"; 1972 bias-disable; 1973 drive-strength = <2>; 1974 }; 1975 }; 1976 }; 1977 1978 remoteproc_mpss: remoteproc@4080000 { 1979 compatible = "qcom,sc7180-mpss-pas"; 1980 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1981 reg-names = "qdsp6", "rmb"; 1982 1983 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1984 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1985 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1986 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1987 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1988 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1989 interrupt-names = "wdog", "fatal", "ready", "handover", 1990 "stop-ack", "shutdown-ack"; 1991 1992 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1993 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1994 <&gcc GCC_MSS_NAV_AXI_CLK>, 1995 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1996 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1997 <&rpmhcc RPMH_CXO_CLK>; 1998 clock-names = "iface", "bus", "nav", "snoc_axi", 1999 "mnoc_axi", "xo"; 2000 2001 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 2002 <&rpmhpd SC7180_CX>, 2003 <&rpmhpd SC7180_MX>, 2004 <&rpmhpd SC7180_MSS>; 2005 power-domain-names = "load_state", "cx", "mx", "mss"; 2006 2007 memory-region = <&mpss_mem>; 2008 2009 qcom,smem-states = <&modem_smp2p_out 0>; 2010 qcom,smem-state-names = "stop"; 2011 2012 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2013 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2014 reset-names = "mss_restart", "pdc_reset"; 2015 2016 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2017 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 2018 2019 status = "disabled"; 2020 2021 glink-edge { 2022 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2023 label = "modem"; 2024 qcom,remote-pid = <1>; 2025 mboxes = <&apss_shared 12>; 2026 }; 2027 }; 2028 2029 gpu: gpu@5000000 { 2030 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2031 #stream-id-cells = <16>; 2032 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2033 <0 0x05061000 0 0x800>; 2034 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2035 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2036 iommus = <&adreno_smmu 0>; 2037 operating-points-v2 = <&gpu_opp_table>; 2038 qcom,gmu = <&gmu>; 2039 2040 #cooling-cells = <2>; 2041 2042 nvmem-cells = <&gpu_speed_bin>; 2043 nvmem-cell-names = "speed_bin"; 2044 2045 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2046 interconnect-names = "gfx-mem"; 2047 2048 gpu_opp_table: opp-table { 2049 compatible = "operating-points-v2"; 2050 2051 opp-825000000 { 2052 opp-hz = /bits/ 64 <825000000>; 2053 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2054 opp-peak-kBps = <8532000>; 2055 opp-supported-hw = <0x04>; 2056 }; 2057 2058 opp-800000000 { 2059 opp-hz = /bits/ 64 <800000000>; 2060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2061 opp-peak-kBps = <8532000>; 2062 opp-supported-hw = <0x07>; 2063 }; 2064 2065 opp-650000000 { 2066 opp-hz = /bits/ 64 <650000000>; 2067 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2068 opp-peak-kBps = <7216000>; 2069 opp-supported-hw = <0x07>; 2070 }; 2071 2072 opp-565000000 { 2073 opp-hz = /bits/ 64 <565000000>; 2074 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2075 opp-peak-kBps = <5412000>; 2076 opp-supported-hw = <0x07>; 2077 }; 2078 2079 opp-430000000 { 2080 opp-hz = /bits/ 64 <430000000>; 2081 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2082 opp-peak-kBps = <5412000>; 2083 opp-supported-hw = <0x07>; 2084 }; 2085 2086 opp-355000000 { 2087 opp-hz = /bits/ 64 <355000000>; 2088 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2089 opp-peak-kBps = <3072000>; 2090 opp-supported-hw = <0x07>; 2091 }; 2092 2093 opp-267000000 { 2094 opp-hz = /bits/ 64 <267000000>; 2095 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2096 opp-peak-kBps = <3072000>; 2097 opp-supported-hw = <0x07>; 2098 }; 2099 2100 opp-180000000 { 2101 opp-hz = /bits/ 64 <180000000>; 2102 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2103 opp-peak-kBps = <1804000>; 2104 opp-supported-hw = <0x07>; 2105 }; 2106 }; 2107 }; 2108 2109 adreno_smmu: iommu@5040000 { 2110 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2111 reg = <0 0x05040000 0 0x10000>; 2112 #iommu-cells = <1>; 2113 #global-interrupts = <2>; 2114 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2117 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2118 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2119 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2120 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2121 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2122 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2123 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2124 2125 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2126 <&gcc GCC_GPU_CFG_AHB_CLK>; 2127 clock-names = "bus", "iface"; 2128 2129 power-domains = <&gpucc CX_GDSC>; 2130 }; 2131 2132 gmu: gmu@506a000 { 2133 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2134 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2135 <0 0x0b490000 0 0x10000>; 2136 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2137 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2139 interrupt-names = "hfi", "gmu"; 2140 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2141 <&gpucc GPU_CC_CXO_CLK>, 2142 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2143 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2144 clock-names = "gmu", "cxo", "axi", "memnoc"; 2145 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2146 power-domain-names = "cx", "gx"; 2147 iommus = <&adreno_smmu 5>; 2148 operating-points-v2 = <&gmu_opp_table>; 2149 2150 gmu_opp_table: opp-table { 2151 compatible = "operating-points-v2"; 2152 2153 opp-200000000 { 2154 opp-hz = /bits/ 64 <200000000>; 2155 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2156 }; 2157 }; 2158 }; 2159 2160 gpucc: clock-controller@5090000 { 2161 compatible = "qcom,sc7180-gpucc"; 2162 reg = <0 0x05090000 0 0x9000>; 2163 clocks = <&rpmhcc RPMH_CXO_CLK>, 2164 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2165 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2166 clock-names = "bi_tcxo", 2167 "gcc_gpu_gpll0_clk_src", 2168 "gcc_gpu_gpll0_div_clk_src"; 2169 #clock-cells = <1>; 2170 #reset-cells = <1>; 2171 #power-domain-cells = <1>; 2172 }; 2173 2174 stm@6002000 { 2175 compatible = "arm,coresight-stm", "arm,primecell"; 2176 reg = <0 0x06002000 0 0x1000>, 2177 <0 0x16280000 0 0x180000>; 2178 reg-names = "stm-base", "stm-stimulus-base"; 2179 2180 clocks = <&aoss_qmp>; 2181 clock-names = "apb_pclk"; 2182 2183 out-ports { 2184 port { 2185 stm_out: endpoint { 2186 remote-endpoint = <&funnel0_in7>; 2187 }; 2188 }; 2189 }; 2190 }; 2191 2192 funnel@6041000 { 2193 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2194 reg = <0 0x06041000 0 0x1000>; 2195 2196 clocks = <&aoss_qmp>; 2197 clock-names = "apb_pclk"; 2198 2199 out-ports { 2200 port { 2201 funnel0_out: endpoint { 2202 remote-endpoint = <&merge_funnel_in0>; 2203 }; 2204 }; 2205 }; 2206 2207 in-ports { 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 2211 port@7 { 2212 reg = <7>; 2213 funnel0_in7: endpoint { 2214 remote-endpoint = <&stm_out>; 2215 }; 2216 }; 2217 }; 2218 }; 2219 2220 funnel@6042000 { 2221 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2222 reg = <0 0x06042000 0 0x1000>; 2223 2224 clocks = <&aoss_qmp>; 2225 clock-names = "apb_pclk"; 2226 2227 out-ports { 2228 port { 2229 funnel1_out: endpoint { 2230 remote-endpoint = <&merge_funnel_in1>; 2231 }; 2232 }; 2233 }; 2234 2235 in-ports { 2236 #address-cells = <1>; 2237 #size-cells = <0>; 2238 2239 port@4 { 2240 reg = <4>; 2241 funnel1_in4: endpoint { 2242 remote-endpoint = <&apss_merge_funnel_out>; 2243 }; 2244 }; 2245 }; 2246 }; 2247 2248 funnel@6045000 { 2249 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2250 reg = <0 0x06045000 0 0x1000>; 2251 2252 clocks = <&aoss_qmp>; 2253 clock-names = "apb_pclk"; 2254 2255 out-ports { 2256 port { 2257 merge_funnel_out: endpoint { 2258 remote-endpoint = <&swao_funnel_in>; 2259 }; 2260 }; 2261 }; 2262 2263 in-ports { 2264 #address-cells = <1>; 2265 #size-cells = <0>; 2266 2267 port@0 { 2268 reg = <0>; 2269 merge_funnel_in0: endpoint { 2270 remote-endpoint = <&funnel0_out>; 2271 }; 2272 }; 2273 2274 port@1 { 2275 reg = <1>; 2276 merge_funnel_in1: endpoint { 2277 remote-endpoint = <&funnel1_out>; 2278 }; 2279 }; 2280 }; 2281 }; 2282 2283 replicator@6046000 { 2284 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2285 reg = <0 0x06046000 0 0x1000>; 2286 2287 clocks = <&aoss_qmp>; 2288 clock-names = "apb_pclk"; 2289 2290 out-ports { 2291 port { 2292 replicator_out: endpoint { 2293 remote-endpoint = <&etr_in>; 2294 }; 2295 }; 2296 }; 2297 2298 in-ports { 2299 port { 2300 replicator_in: endpoint { 2301 remote-endpoint = <&swao_replicator_out>; 2302 }; 2303 }; 2304 }; 2305 }; 2306 2307 etr@6048000 { 2308 compatible = "arm,coresight-tmc", "arm,primecell"; 2309 reg = <0 0x06048000 0 0x1000>; 2310 iommus = <&apps_smmu 0x04a0 0x20>; 2311 2312 clocks = <&aoss_qmp>; 2313 clock-names = "apb_pclk"; 2314 arm,scatter-gather; 2315 2316 in-ports { 2317 port { 2318 etr_in: endpoint { 2319 remote-endpoint = <&replicator_out>; 2320 }; 2321 }; 2322 }; 2323 }; 2324 2325 funnel@6b04000 { 2326 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2327 reg = <0 0x06b04000 0 0x1000>; 2328 2329 clocks = <&aoss_qmp>; 2330 clock-names = "apb_pclk"; 2331 2332 out-ports { 2333 port { 2334 swao_funnel_out: endpoint { 2335 remote-endpoint = <&etf_in>; 2336 }; 2337 }; 2338 }; 2339 2340 in-ports { 2341 #address-cells = <1>; 2342 #size-cells = <0>; 2343 2344 port@7 { 2345 reg = <7>; 2346 swao_funnel_in: endpoint { 2347 remote-endpoint = <&merge_funnel_out>; 2348 }; 2349 }; 2350 }; 2351 }; 2352 2353 etf@6b05000 { 2354 compatible = "arm,coresight-tmc", "arm,primecell"; 2355 reg = <0 0x06b05000 0 0x1000>; 2356 2357 clocks = <&aoss_qmp>; 2358 clock-names = "apb_pclk"; 2359 2360 out-ports { 2361 port { 2362 etf_out: endpoint { 2363 remote-endpoint = <&swao_replicator_in>; 2364 }; 2365 }; 2366 }; 2367 2368 in-ports { 2369 port { 2370 etf_in: endpoint { 2371 remote-endpoint = <&swao_funnel_out>; 2372 }; 2373 }; 2374 }; 2375 }; 2376 2377 replicator@6b06000 { 2378 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2379 reg = <0 0x06b06000 0 0x1000>; 2380 2381 clocks = <&aoss_qmp>; 2382 clock-names = "apb_pclk"; 2383 qcom,replicator-loses-context; 2384 2385 out-ports { 2386 port { 2387 swao_replicator_out: endpoint { 2388 remote-endpoint = <&replicator_in>; 2389 }; 2390 }; 2391 }; 2392 2393 in-ports { 2394 port { 2395 swao_replicator_in: endpoint { 2396 remote-endpoint = <&etf_out>; 2397 }; 2398 }; 2399 }; 2400 }; 2401 2402 etm@7040000 { 2403 compatible = "arm,coresight-etm4x", "arm,primecell"; 2404 reg = <0 0x07040000 0 0x1000>; 2405 2406 cpu = <&CPU0>; 2407 2408 clocks = <&aoss_qmp>; 2409 clock-names = "apb_pclk"; 2410 arm,coresight-loses-context-with-cpu; 2411 qcom,skip-power-up; 2412 2413 out-ports { 2414 port { 2415 etm0_out: endpoint { 2416 remote-endpoint = <&apss_funnel_in0>; 2417 }; 2418 }; 2419 }; 2420 }; 2421 2422 etm@7140000 { 2423 compatible = "arm,coresight-etm4x", "arm,primecell"; 2424 reg = <0 0x07140000 0 0x1000>; 2425 2426 cpu = <&CPU1>; 2427 2428 clocks = <&aoss_qmp>; 2429 clock-names = "apb_pclk"; 2430 arm,coresight-loses-context-with-cpu; 2431 qcom,skip-power-up; 2432 2433 out-ports { 2434 port { 2435 etm1_out: endpoint { 2436 remote-endpoint = <&apss_funnel_in1>; 2437 }; 2438 }; 2439 }; 2440 }; 2441 2442 etm@7240000 { 2443 compatible = "arm,coresight-etm4x", "arm,primecell"; 2444 reg = <0 0x07240000 0 0x1000>; 2445 2446 cpu = <&CPU2>; 2447 2448 clocks = <&aoss_qmp>; 2449 clock-names = "apb_pclk"; 2450 arm,coresight-loses-context-with-cpu; 2451 qcom,skip-power-up; 2452 2453 out-ports { 2454 port { 2455 etm2_out: endpoint { 2456 remote-endpoint = <&apss_funnel_in2>; 2457 }; 2458 }; 2459 }; 2460 }; 2461 2462 etm@7340000 { 2463 compatible = "arm,coresight-etm4x", "arm,primecell"; 2464 reg = <0 0x07340000 0 0x1000>; 2465 2466 cpu = <&CPU3>; 2467 2468 clocks = <&aoss_qmp>; 2469 clock-names = "apb_pclk"; 2470 arm,coresight-loses-context-with-cpu; 2471 qcom,skip-power-up; 2472 2473 out-ports { 2474 port { 2475 etm3_out: endpoint { 2476 remote-endpoint = <&apss_funnel_in3>; 2477 }; 2478 }; 2479 }; 2480 }; 2481 2482 etm@7440000 { 2483 compatible = "arm,coresight-etm4x", "arm,primecell"; 2484 reg = <0 0x07440000 0 0x1000>; 2485 2486 cpu = <&CPU4>; 2487 2488 clocks = <&aoss_qmp>; 2489 clock-names = "apb_pclk"; 2490 arm,coresight-loses-context-with-cpu; 2491 qcom,skip-power-up; 2492 2493 out-ports { 2494 port { 2495 etm4_out: endpoint { 2496 remote-endpoint = <&apss_funnel_in4>; 2497 }; 2498 }; 2499 }; 2500 }; 2501 2502 etm@7540000 { 2503 compatible = "arm,coresight-etm4x", "arm,primecell"; 2504 reg = <0 0x07540000 0 0x1000>; 2505 2506 cpu = <&CPU5>; 2507 2508 clocks = <&aoss_qmp>; 2509 clock-names = "apb_pclk"; 2510 arm,coresight-loses-context-with-cpu; 2511 qcom,skip-power-up; 2512 2513 out-ports { 2514 port { 2515 etm5_out: endpoint { 2516 remote-endpoint = <&apss_funnel_in5>; 2517 }; 2518 }; 2519 }; 2520 }; 2521 2522 etm@7640000 { 2523 compatible = "arm,coresight-etm4x", "arm,primecell"; 2524 reg = <0 0x07640000 0 0x1000>; 2525 2526 cpu = <&CPU6>; 2527 2528 clocks = <&aoss_qmp>; 2529 clock-names = "apb_pclk"; 2530 arm,coresight-loses-context-with-cpu; 2531 qcom,skip-power-up; 2532 2533 out-ports { 2534 port { 2535 etm6_out: endpoint { 2536 remote-endpoint = <&apss_funnel_in6>; 2537 }; 2538 }; 2539 }; 2540 }; 2541 2542 etm@7740000 { 2543 compatible = "arm,coresight-etm4x", "arm,primecell"; 2544 reg = <0 0x07740000 0 0x1000>; 2545 2546 cpu = <&CPU7>; 2547 2548 clocks = <&aoss_qmp>; 2549 clock-names = "apb_pclk"; 2550 arm,coresight-loses-context-with-cpu; 2551 qcom,skip-power-up; 2552 2553 out-ports { 2554 port { 2555 etm7_out: endpoint { 2556 remote-endpoint = <&apss_funnel_in7>; 2557 }; 2558 }; 2559 }; 2560 }; 2561 2562 funnel@7800000 { /* APSS Funnel */ 2563 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2564 reg = <0 0x07800000 0 0x1000>; 2565 2566 clocks = <&aoss_qmp>; 2567 clock-names = "apb_pclk"; 2568 2569 out-ports { 2570 port { 2571 apss_funnel_out: endpoint { 2572 remote-endpoint = <&apss_merge_funnel_in>; 2573 }; 2574 }; 2575 }; 2576 2577 in-ports { 2578 #address-cells = <1>; 2579 #size-cells = <0>; 2580 2581 port@0 { 2582 reg = <0>; 2583 apss_funnel_in0: endpoint { 2584 remote-endpoint = <&etm0_out>; 2585 }; 2586 }; 2587 2588 port@1 { 2589 reg = <1>; 2590 apss_funnel_in1: endpoint { 2591 remote-endpoint = <&etm1_out>; 2592 }; 2593 }; 2594 2595 port@2 { 2596 reg = <2>; 2597 apss_funnel_in2: endpoint { 2598 remote-endpoint = <&etm2_out>; 2599 }; 2600 }; 2601 2602 port@3 { 2603 reg = <3>; 2604 apss_funnel_in3: endpoint { 2605 remote-endpoint = <&etm3_out>; 2606 }; 2607 }; 2608 2609 port@4 { 2610 reg = <4>; 2611 apss_funnel_in4: endpoint { 2612 remote-endpoint = <&etm4_out>; 2613 }; 2614 }; 2615 2616 port@5 { 2617 reg = <5>; 2618 apss_funnel_in5: endpoint { 2619 remote-endpoint = <&etm5_out>; 2620 }; 2621 }; 2622 2623 port@6 { 2624 reg = <6>; 2625 apss_funnel_in6: endpoint { 2626 remote-endpoint = <&etm6_out>; 2627 }; 2628 }; 2629 2630 port@7 { 2631 reg = <7>; 2632 apss_funnel_in7: endpoint { 2633 remote-endpoint = <&etm7_out>; 2634 }; 2635 }; 2636 }; 2637 }; 2638 2639 funnel@7810000 { 2640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2641 reg = <0 0x07810000 0 0x1000>; 2642 2643 clocks = <&aoss_qmp>; 2644 clock-names = "apb_pclk"; 2645 2646 out-ports { 2647 port { 2648 apss_merge_funnel_out: endpoint { 2649 remote-endpoint = <&funnel1_in4>; 2650 }; 2651 }; 2652 }; 2653 2654 in-ports { 2655 port { 2656 apss_merge_funnel_in: endpoint { 2657 remote-endpoint = <&apss_funnel_out>; 2658 }; 2659 }; 2660 }; 2661 }; 2662 2663 sdhc_2: sdhci@8804000 { 2664 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2665 reg = <0 0x08804000 0 0x1000>; 2666 2667 iommus = <&apps_smmu 0x80 0>; 2668 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2670 interrupt-names = "hc_irq", "pwr_irq"; 2671 2672 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2673 <&gcc GCC_SDCC2_AHB_CLK>; 2674 clock-names = "core", "iface"; 2675 2676 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2677 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2678 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2679 power-domains = <&rpmhpd SC7180_CX>; 2680 operating-points-v2 = <&sdhc2_opp_table>; 2681 2682 bus-width = <4>; 2683 2684 status = "disabled"; 2685 2686 sdhc2_opp_table: sdhc2-opp-table { 2687 compatible = "operating-points-v2"; 2688 2689 opp-100000000 { 2690 opp-hz = /bits/ 64 <100000000>; 2691 required-opps = <&rpmhpd_opp_low_svs>; 2692 opp-peak-kBps = <160000 100000>; 2693 opp-avg-kBps = <80000 50000>; 2694 }; 2695 2696 opp-202000000 { 2697 opp-hz = /bits/ 64 <202000000>; 2698 required-opps = <&rpmhpd_opp_svs_l1>; 2699 opp-peak-kBps = <200000 120000>; 2700 opp-avg-kBps = <100000 60000>; 2701 }; 2702 }; 2703 }; 2704 2705 qspi_opp_table: qspi-opp-table { 2706 compatible = "operating-points-v2"; 2707 2708 opp-75000000 { 2709 opp-hz = /bits/ 64 <75000000>; 2710 required-opps = <&rpmhpd_opp_low_svs>; 2711 }; 2712 2713 opp-150000000 { 2714 opp-hz = /bits/ 64 <150000000>; 2715 required-opps = <&rpmhpd_opp_svs>; 2716 }; 2717 2718 opp-300000000 { 2719 opp-hz = /bits/ 64 <300000000>; 2720 required-opps = <&rpmhpd_opp_nom>; 2721 }; 2722 }; 2723 2724 qspi: spi@88dc000 { 2725 compatible = "qcom,qspi-v1"; 2726 reg = <0 0x088dc000 0 0x600>; 2727 #address-cells = <1>; 2728 #size-cells = <0>; 2729 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2730 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2731 <&gcc GCC_QSPI_CORE_CLK>; 2732 clock-names = "iface", "core"; 2733 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2734 &config_noc SLAVE_QSPI_0 0>; 2735 interconnect-names = "qspi-config"; 2736 power-domains = <&rpmhpd SC7180_CX>; 2737 operating-points-v2 = <&qspi_opp_table>; 2738 status = "disabled"; 2739 }; 2740 2741 usb_1_hsphy: phy@88e3000 { 2742 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2743 reg = <0 0x088e3000 0 0x400>; 2744 status = "disabled"; 2745 #phy-cells = <0>; 2746 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2747 <&rpmhcc RPMH_CXO_CLK>; 2748 clock-names = "cfg_ahb", "ref"; 2749 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2750 2751 nvmem-cells = <&qusb2p_hstx_trim>; 2752 }; 2753 2754 usb_1_qmpphy: phy-wrapper@88e9000 { 2755 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2756 reg = <0 0x088e9000 0 0x18c>, 2757 <0 0x088e8000 0 0x38>, 2758 <0 0x088ea000 0 0x40>; 2759 status = "disabled"; 2760 #address-cells = <2>; 2761 #size-cells = <2>; 2762 ranges; 2763 2764 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2765 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2766 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2767 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2768 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2769 2770 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2771 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2772 reset-names = "phy", "common"; 2773 2774 usb_1_ssphy: usb3-phy@88e9200 { 2775 reg = <0 0x088e9200 0 0x128>, 2776 <0 0x088e9400 0 0x200>, 2777 <0 0x088e9c00 0 0x218>, 2778 <0 0x088e9600 0 0x128>, 2779 <0 0x088e9800 0 0x200>, 2780 <0 0x088e9a00 0 0x18>; 2781 #clock-cells = <0>; 2782 #phy-cells = <0>; 2783 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2784 clock-names = "pipe0"; 2785 clock-output-names = "usb3_phy_pipe_clk_src"; 2786 }; 2787 2788 dp_phy: dp-phy@88ea200 { 2789 reg = <0 0x088ea200 0 0x200>, 2790 <0 0x088ea400 0 0x200>, 2791 <0 0x088eaa00 0 0x200>, 2792 <0 0x088ea600 0 0x200>, 2793 <0 0x088ea800 0 0x200>; 2794 #clock-cells = <1>; 2795 #phy-cells = <0>; 2796 }; 2797 }; 2798 2799 dc_noc: interconnect@9160000 { 2800 compatible = "qcom,sc7180-dc-noc"; 2801 reg = <0 0x09160000 0 0x03200>; 2802 #interconnect-cells = <2>; 2803 qcom,bcm-voters = <&apps_bcm_voter>; 2804 }; 2805 2806 system-cache-controller@9200000 { 2807 compatible = "qcom,sc7180-llcc"; 2808 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2809 reg-names = "llcc_base", "llcc_broadcast_base"; 2810 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2811 }; 2812 2813 gem_noc: interconnect@9680000 { 2814 compatible = "qcom,sc7180-gem-noc"; 2815 reg = <0 0x09680000 0 0x3e200>; 2816 #interconnect-cells = <2>; 2817 qcom,bcm-voters = <&apps_bcm_voter>; 2818 }; 2819 2820 npu_noc: interconnect@9990000 { 2821 compatible = "qcom,sc7180-npu-noc"; 2822 reg = <0 0x09990000 0 0x1600>; 2823 #interconnect-cells = <2>; 2824 qcom,bcm-voters = <&apps_bcm_voter>; 2825 }; 2826 2827 usb_1: usb@a6f8800 { 2828 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2829 reg = <0 0x0a6f8800 0 0x400>; 2830 status = "disabled"; 2831 #address-cells = <2>; 2832 #size-cells = <2>; 2833 ranges; 2834 dma-ranges; 2835 2836 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2837 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2838 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2839 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2840 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2841 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2842 "sleep"; 2843 2844 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2845 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2846 assigned-clock-rates = <19200000>, <150000000>; 2847 2848 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2849 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2850 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2851 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2852 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2853 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2854 2855 power-domains = <&gcc USB30_PRIM_GDSC>; 2856 2857 resets = <&gcc GCC_USB30_PRIM_BCR>; 2858 2859 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2860 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2861 interconnect-names = "usb-ddr", "apps-usb"; 2862 2863 usb_1_dwc3: dwc3@a600000 { 2864 compatible = "snps,dwc3"; 2865 reg = <0 0x0a600000 0 0xe000>; 2866 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2867 iommus = <&apps_smmu 0x540 0>; 2868 snps,dis_u2_susphy_quirk; 2869 snps,dis_enblslpm_quirk; 2870 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2871 phy-names = "usb2-phy", "usb3-phy"; 2872 maximum-speed = "super-speed"; 2873 }; 2874 }; 2875 2876 venus: video-codec@aa00000 { 2877 compatible = "qcom,sc7180-venus"; 2878 reg = <0 0x0aa00000 0 0xff000>; 2879 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2880 power-domains = <&videocc VENUS_GDSC>, 2881 <&videocc VCODEC0_GDSC>, 2882 <&rpmhpd SC7180_CX>; 2883 power-domain-names = "venus", "vcodec0", "cx"; 2884 operating-points-v2 = <&venus_opp_table>; 2885 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2886 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2887 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2888 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2889 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2890 clock-names = "core", "iface", "bus", 2891 "vcodec0_core", "vcodec0_bus"; 2892 iommus = <&apps_smmu 0x0c00 0x60>; 2893 memory-region = <&venus_mem>; 2894 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2895 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2896 interconnect-names = "video-mem", "cpu-cfg"; 2897 2898 video-decoder { 2899 compatible = "venus-decoder"; 2900 }; 2901 2902 video-encoder { 2903 compatible = "venus-encoder"; 2904 }; 2905 2906 venus_opp_table: venus-opp-table { 2907 compatible = "operating-points-v2"; 2908 2909 opp-150000000 { 2910 opp-hz = /bits/ 64 <150000000>; 2911 required-opps = <&rpmhpd_opp_low_svs>; 2912 }; 2913 2914 opp-270000000 { 2915 opp-hz = /bits/ 64 <270000000>; 2916 required-opps = <&rpmhpd_opp_svs>; 2917 }; 2918 2919 opp-340000000 { 2920 opp-hz = /bits/ 64 <340000000>; 2921 required-opps = <&rpmhpd_opp_svs_l1>; 2922 }; 2923 2924 opp-434000000 { 2925 opp-hz = /bits/ 64 <434000000>; 2926 required-opps = <&rpmhpd_opp_nom>; 2927 }; 2928 2929 opp-500000097 { 2930 opp-hz = /bits/ 64 <500000097>; 2931 required-opps = <&rpmhpd_opp_turbo>; 2932 }; 2933 }; 2934 }; 2935 2936 videocc: clock-controller@ab00000 { 2937 compatible = "qcom,sc7180-videocc"; 2938 reg = <0 0x0ab00000 0 0x10000>; 2939 clocks = <&rpmhcc RPMH_CXO_CLK>; 2940 clock-names = "bi_tcxo"; 2941 #clock-cells = <1>; 2942 #reset-cells = <1>; 2943 #power-domain-cells = <1>; 2944 }; 2945 2946 camnoc_virt: interconnect@ac00000 { 2947 compatible = "qcom,sc7180-camnoc-virt"; 2948 reg = <0 0x0ac00000 0 0x1000>; 2949 #interconnect-cells = <2>; 2950 qcom,bcm-voters = <&apps_bcm_voter>; 2951 }; 2952 2953 camcc: clock-controller@ad00000 { 2954 compatible = "qcom,sc7180-camcc"; 2955 reg = <0 0x0ad00000 0 0x10000>; 2956 clocks = <&rpmhcc RPMH_CXO_CLK>, 2957 <&gcc GCC_CAMERA_AHB_CLK>, 2958 <&gcc GCC_CAMERA_XO_CLK>; 2959 clock-names = "bi_tcxo", "iface", "xo"; 2960 #clock-cells = <1>; 2961 #reset-cells = <1>; 2962 #power-domain-cells = <1>; 2963 }; 2964 2965 mdss: mdss@ae00000 { 2966 compatible = "qcom,sc7180-mdss"; 2967 reg = <0 0x0ae00000 0 0x1000>; 2968 reg-names = "mdss"; 2969 2970 power-domains = <&dispcc MDSS_GDSC>; 2971 2972 clocks = <&gcc GCC_DISP_AHB_CLK>, 2973 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2974 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2975 clock-names = "iface", "ahb", "core"; 2976 2977 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2978 assigned-clock-rates = <300000000>; 2979 2980 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2981 interrupt-controller; 2982 #interrupt-cells = <1>; 2983 2984 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2985 interconnect-names = "mdp0-mem"; 2986 2987 iommus = <&apps_smmu 0x800 0x2>; 2988 2989 #address-cells = <2>; 2990 #size-cells = <2>; 2991 ranges; 2992 2993 status = "disabled"; 2994 2995 mdp: mdp@ae01000 { 2996 compatible = "qcom,sc7180-dpu"; 2997 reg = <0 0x0ae01000 0 0x8f000>, 2998 <0 0x0aeb0000 0 0x2008>; 2999 reg-names = "mdp", "vbif"; 3000 3001 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3002 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3003 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3004 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3005 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3006 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3007 clock-names = "bus", "iface", "rot", "lut", "core", 3008 "vsync"; 3009 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3010 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3011 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3012 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3013 assigned-clock-rates = <300000000>, 3014 <19200000>, 3015 <19200000>, 3016 <19200000>; 3017 operating-points-v2 = <&mdp_opp_table>; 3018 power-domains = <&rpmhpd SC7180_CX>; 3019 3020 interrupt-parent = <&mdss>; 3021 interrupts = <0>; 3022 3023 status = "disabled"; 3024 3025 ports { 3026 #address-cells = <1>; 3027 #size-cells = <0>; 3028 3029 port@0 { 3030 reg = <0>; 3031 dpu_intf1_out: endpoint { 3032 remote-endpoint = <&dsi0_in>; 3033 }; 3034 }; 3035 }; 3036 3037 mdp_opp_table: mdp-opp-table { 3038 compatible = "operating-points-v2"; 3039 3040 opp-200000000 { 3041 opp-hz = /bits/ 64 <200000000>; 3042 required-opps = <&rpmhpd_opp_low_svs>; 3043 }; 3044 3045 opp-300000000 { 3046 opp-hz = /bits/ 64 <300000000>; 3047 required-opps = <&rpmhpd_opp_svs>; 3048 }; 3049 3050 opp-345000000 { 3051 opp-hz = /bits/ 64 <345000000>; 3052 required-opps = <&rpmhpd_opp_svs_l1>; 3053 }; 3054 3055 opp-460000000 { 3056 opp-hz = /bits/ 64 <460000000>; 3057 required-opps = <&rpmhpd_opp_nom>; 3058 }; 3059 }; 3060 3061 }; 3062 3063 dsi0: dsi@ae94000 { 3064 compatible = "qcom,mdss-dsi-ctrl"; 3065 reg = <0 0x0ae94000 0 0x400>; 3066 reg-names = "dsi_ctrl"; 3067 3068 interrupt-parent = <&mdss>; 3069 interrupts = <4>; 3070 3071 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3072 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3073 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3074 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3075 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3076 <&gcc GCC_DISP_HF_AXI_CLK>; 3077 clock-names = "byte", 3078 "byte_intf", 3079 "pixel", 3080 "core", 3081 "iface", 3082 "bus"; 3083 3084 operating-points-v2 = <&dsi_opp_table>; 3085 power-domains = <&rpmhpd SC7180_CX>; 3086 3087 phys = <&dsi_phy>; 3088 phy-names = "dsi"; 3089 3090 #address-cells = <1>; 3091 #size-cells = <0>; 3092 3093 status = "disabled"; 3094 3095 ports { 3096 #address-cells = <1>; 3097 #size-cells = <0>; 3098 3099 port@0 { 3100 reg = <0>; 3101 dsi0_in: endpoint { 3102 remote-endpoint = <&dpu_intf1_out>; 3103 }; 3104 }; 3105 3106 port@1 { 3107 reg = <1>; 3108 dsi0_out: endpoint { 3109 }; 3110 }; 3111 }; 3112 3113 dsi_opp_table: dsi-opp-table { 3114 compatible = "operating-points-v2"; 3115 3116 opp-187500000 { 3117 opp-hz = /bits/ 64 <187500000>; 3118 required-opps = <&rpmhpd_opp_low_svs>; 3119 }; 3120 3121 opp-300000000 { 3122 opp-hz = /bits/ 64 <300000000>; 3123 required-opps = <&rpmhpd_opp_svs>; 3124 }; 3125 3126 opp-358000000 { 3127 opp-hz = /bits/ 64 <358000000>; 3128 required-opps = <&rpmhpd_opp_svs_l1>; 3129 }; 3130 }; 3131 }; 3132 3133 dsi_phy: dsi-phy@ae94400 { 3134 compatible = "qcom,dsi-phy-10nm"; 3135 reg = <0 0x0ae94400 0 0x200>, 3136 <0 0x0ae94600 0 0x280>, 3137 <0 0x0ae94a00 0 0x1e0>; 3138 reg-names = "dsi_phy", 3139 "dsi_phy_lane", 3140 "dsi_pll"; 3141 3142 #clock-cells = <1>; 3143 #phy-cells = <0>; 3144 3145 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3146 <&rpmhcc RPMH_CXO_CLK>; 3147 clock-names = "iface", "ref"; 3148 3149 status = "disabled"; 3150 }; 3151 }; 3152 3153 dispcc: clock-controller@af00000 { 3154 compatible = "qcom,sc7180-dispcc"; 3155 reg = <0 0x0af00000 0 0x200000>; 3156 clocks = <&rpmhcc RPMH_CXO_CLK>, 3157 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3158 <&dsi_phy 0>, 3159 <&dsi_phy 1>, 3160 <&dp_phy 0>, 3161 <&dp_phy 1>; 3162 clock-names = "bi_tcxo", 3163 "gcc_disp_gpll0_clk_src", 3164 "dsi0_phy_pll_out_byteclk", 3165 "dsi0_phy_pll_out_dsiclk", 3166 "dp_phy_pll_link_clk", 3167 "dp_phy_pll_vco_div_clk"; 3168 #clock-cells = <1>; 3169 #reset-cells = <1>; 3170 #power-domain-cells = <1>; 3171 }; 3172 3173 pdc: interrupt-controller@b220000 { 3174 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3175 reg = <0 0x0b220000 0 0x30000>; 3176 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3177 #interrupt-cells = <2>; 3178 interrupt-parent = <&intc>; 3179 interrupt-controller; 3180 }; 3181 3182 pdc_reset: reset-controller@b2e0000 { 3183 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3184 reg = <0 0x0b2e0000 0 0x20000>; 3185 #reset-cells = <1>; 3186 }; 3187 3188 tsens0: thermal-sensor@c263000 { 3189 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3190 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3191 <0 0x0c222000 0 0x1ff>; /* SROT */ 3192 #qcom,sensors = <15>; 3193 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3195 interrupt-names = "uplow","critical"; 3196 #thermal-sensor-cells = <1>; 3197 }; 3198 3199 tsens1: thermal-sensor@c265000 { 3200 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3201 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3202 <0 0x0c223000 0 0x1ff>; /* SROT */ 3203 #qcom,sensors = <10>; 3204 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3206 interrupt-names = "uplow","critical"; 3207 #thermal-sensor-cells = <1>; 3208 }; 3209 3210 aoss_reset: reset-controller@c2a0000 { 3211 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3212 reg = <0 0x0c2a0000 0 0x31000>; 3213 #reset-cells = <1>; 3214 }; 3215 3216 aoss_qmp: power-controller@c300000 { 3217 compatible = "qcom,sc7180-aoss-qmp"; 3218 reg = <0 0x0c300000 0 0x100000>; 3219 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3220 mboxes = <&apss_shared 0>; 3221 3222 #clock-cells = <0>; 3223 #power-domain-cells = <1>; 3224 }; 3225 3226 spmi_bus: spmi@c440000 { 3227 compatible = "qcom,spmi-pmic-arb"; 3228 reg = <0 0x0c440000 0 0x1100>, 3229 <0 0x0c600000 0 0x2000000>, 3230 <0 0x0e600000 0 0x100000>, 3231 <0 0x0e700000 0 0xa0000>, 3232 <0 0x0c40a000 0 0x26000>; 3233 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3234 interrupt-names = "periph_irq"; 3235 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3236 qcom,ee = <0>; 3237 qcom,channel = <0>; 3238 #address-cells = <1>; 3239 #size-cells = <1>; 3240 interrupt-controller; 3241 #interrupt-cells = <4>; 3242 cell-index = <0>; 3243 }; 3244 3245 apps_smmu: iommu@15000000 { 3246 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3247 reg = <0 0x15000000 0 0x100000>; 3248 #iommu-cells = <2>; 3249 #global-interrupts = <1>; 3250 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3331 }; 3332 3333 intc: interrupt-controller@17a00000 { 3334 compatible = "arm,gic-v3"; 3335 #address-cells = <2>; 3336 #size-cells = <2>; 3337 ranges; 3338 #interrupt-cells = <3>; 3339 interrupt-controller; 3340 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3341 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3342 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3343 3344 msi-controller@17a40000 { 3345 compatible = "arm,gic-v3-its"; 3346 msi-controller; 3347 #msi-cells = <1>; 3348 reg = <0 0x17a40000 0 0x20000>; 3349 status = "disabled"; 3350 }; 3351 }; 3352 3353 apss_shared: mailbox@17c00000 { 3354 compatible = "qcom,sc7180-apss-shared"; 3355 reg = <0 0x17c00000 0 0x10000>; 3356 #mbox-cells = <1>; 3357 }; 3358 3359 watchdog@17c10000 { 3360 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3361 reg = <0 0x17c10000 0 0x1000>; 3362 clocks = <&sleep_clk>; 3363 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3364 }; 3365 3366 timer@17c20000{ 3367 #address-cells = <2>; 3368 #size-cells = <2>; 3369 ranges; 3370 compatible = "arm,armv7-timer-mem"; 3371 reg = <0 0x17c20000 0 0x1000>; 3372 3373 frame@17c21000 { 3374 frame-number = <0>; 3375 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3377 reg = <0 0x17c21000 0 0x1000>, 3378 <0 0x17c22000 0 0x1000>; 3379 }; 3380 3381 frame@17c23000 { 3382 frame-number = <1>; 3383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3384 reg = <0 0x17c23000 0 0x1000>; 3385 status = "disabled"; 3386 }; 3387 3388 frame@17c25000 { 3389 frame-number = <2>; 3390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3391 reg = <0 0x17c25000 0 0x1000>; 3392 status = "disabled"; 3393 }; 3394 3395 frame@17c27000 { 3396 frame-number = <3>; 3397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3398 reg = <0 0x17c27000 0 0x1000>; 3399 status = "disabled"; 3400 }; 3401 3402 frame@17c29000 { 3403 frame-number = <4>; 3404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3405 reg = <0 0x17c29000 0 0x1000>; 3406 status = "disabled"; 3407 }; 3408 3409 frame@17c2b000 { 3410 frame-number = <5>; 3411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3412 reg = <0 0x17c2b000 0 0x1000>; 3413 status = "disabled"; 3414 }; 3415 3416 frame@17c2d000 { 3417 frame-number = <6>; 3418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3419 reg = <0 0x17c2d000 0 0x1000>; 3420 status = "disabled"; 3421 }; 3422 }; 3423 3424 apps_rsc: rsc@18200000 { 3425 compatible = "qcom,rpmh-rsc"; 3426 reg = <0 0x18200000 0 0x10000>, 3427 <0 0x18210000 0 0x10000>, 3428 <0 0x18220000 0 0x10000>; 3429 reg-names = "drv-0", "drv-1", "drv-2"; 3430 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3433 qcom,tcs-offset = <0xd00>; 3434 qcom,drv-id = <2>; 3435 qcom,tcs-config = <ACTIVE_TCS 2>, 3436 <SLEEP_TCS 3>, 3437 <WAKE_TCS 3>, 3438 <CONTROL_TCS 1>; 3439 3440 rpmhcc: clock-controller { 3441 compatible = "qcom,sc7180-rpmh-clk"; 3442 clocks = <&xo_board>; 3443 clock-names = "xo"; 3444 #clock-cells = <1>; 3445 }; 3446 3447 rpmhpd: power-controller { 3448 compatible = "qcom,sc7180-rpmhpd"; 3449 #power-domain-cells = <1>; 3450 operating-points-v2 = <&rpmhpd_opp_table>; 3451 3452 rpmhpd_opp_table: opp-table { 3453 compatible = "operating-points-v2"; 3454 3455 rpmhpd_opp_ret: opp1 { 3456 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3457 }; 3458 3459 rpmhpd_opp_min_svs: opp2 { 3460 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3461 }; 3462 3463 rpmhpd_opp_low_svs: opp3 { 3464 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3465 }; 3466 3467 rpmhpd_opp_svs: opp4 { 3468 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3469 }; 3470 3471 rpmhpd_opp_svs_l1: opp5 { 3472 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3473 }; 3474 3475 rpmhpd_opp_svs_l2: opp6 { 3476 opp-level = <224>; 3477 }; 3478 3479 rpmhpd_opp_nom: opp7 { 3480 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3481 }; 3482 3483 rpmhpd_opp_nom_l1: opp8 { 3484 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3485 }; 3486 3487 rpmhpd_opp_nom_l2: opp9 { 3488 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3489 }; 3490 3491 rpmhpd_opp_turbo: opp10 { 3492 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3493 }; 3494 3495 rpmhpd_opp_turbo_l1: opp11 { 3496 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3497 }; 3498 }; 3499 }; 3500 3501 apps_bcm_voter: bcm_voter { 3502 compatible = "qcom,bcm-voter"; 3503 }; 3504 }; 3505 3506 osm_l3: interconnect@18321000 { 3507 compatible = "qcom,sc7180-osm-l3"; 3508 reg = <0 0x18321000 0 0x1400>; 3509 3510 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3511 clock-names = "xo", "alternate"; 3512 3513 #interconnect-cells = <1>; 3514 }; 3515 3516 cpufreq_hw: cpufreq@18323000 { 3517 compatible = "qcom,cpufreq-hw"; 3518 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3519 reg-names = "freq-domain0", "freq-domain1"; 3520 3521 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3522 clock-names = "xo", "alternate"; 3523 3524 #freq-domain-cells = <1>; 3525 }; 3526 3527 wifi: wifi@18800000 { 3528 compatible = "qcom,wcn3990-wifi"; 3529 reg = <0 0x18800000 0 0x800000>; 3530 reg-names = "membase"; 3531 iommus = <&apps_smmu 0xc0 0x1>; 3532 interrupts = 3533 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3534 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3535 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3536 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3537 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3538 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3539 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3540 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3541 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3542 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3543 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3544 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3545 memory-region = <&wlan_mem>; 3546 qcom,msa-fixed-perm; 3547 status = "disabled"; 3548 }; 3549 3550 lpasscc: clock-controller@62d00000 { 3551 compatible = "qcom,sc7180-lpasscorecc"; 3552 reg = <0 0x62d00000 0 0x50000>, 3553 <0 0x62780000 0 0x30000>; 3554 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3555 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3556 <&rpmhcc RPMH_CXO_CLK>; 3557 clock-names = "iface", "bi_tcxo"; 3558 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3559 #clock-cells = <1>; 3560 #power-domain-cells = <1>; 3561 }; 3562 3563 lpass_cpu: lpass@62f00000 { 3564 compatible = "qcom,sc7180-lpass-cpu"; 3565 3566 reg = <0 0x62f00000 0 0x29000>; 3567 reg-names = "lpass-lpaif"; 3568 3569 iommus = <&apps_smmu 0x1020 0>, 3570 <&apps_smmu 0x1021 0>; 3571 3572 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3573 3574 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3575 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3576 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3577 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3578 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3579 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3580 3581 clock-names = "pcnoc-sway-clk", "audio-core", 3582 "mclk0", "pcnoc-mport-clk", 3583 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3584 3585 3586 #sound-dai-cells = <1>; 3587 #address-cells = <1>; 3588 #size-cells = <0>; 3589 3590 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 3591 interrupt-names = "lpass-irq-lpaif"; 3592 }; 3593 3594 lpass_hm: clock-controller@63000000 { 3595 compatible = "qcom,sc7180-lpasshm"; 3596 reg = <0 0x63000000 0 0x28>; 3597 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3598 <&rpmhcc RPMH_CXO_CLK>; 3599 clock-names = "iface", "bi_tcxo"; 3600 #clock-cells = <1>; 3601 #power-domain-cells = <1>; 3602 }; 3603 }; 3604 3605 thermal-zones { 3606 cpu0_thermal: cpu0-thermal { 3607 polling-delay-passive = <250>; 3608 polling-delay = <0>; 3609 3610 thermal-sensors = <&tsens0 1>; 3611 sustainable-power = <768>; 3612 3613 trips { 3614 cpu0_alert0: trip-point0 { 3615 temperature = <90000>; 3616 hysteresis = <2000>; 3617 type = "passive"; 3618 }; 3619 3620 cpu0_alert1: trip-point1 { 3621 temperature = <95000>; 3622 hysteresis = <2000>; 3623 type = "passive"; 3624 }; 3625 3626 cpu0_crit: cpu_crit { 3627 temperature = <110000>; 3628 hysteresis = <1000>; 3629 type = "critical"; 3630 }; 3631 }; 3632 3633 cooling-maps { 3634 map0 { 3635 trip = <&cpu0_alert0>; 3636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3637 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3638 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3639 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3640 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3642 }; 3643 map1 { 3644 trip = <&cpu0_alert1>; 3645 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3646 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3647 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3648 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3649 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3650 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3651 }; 3652 }; 3653 }; 3654 3655 cpu1_thermal: cpu1-thermal { 3656 polling-delay-passive = <250>; 3657 polling-delay = <0>; 3658 3659 thermal-sensors = <&tsens0 2>; 3660 sustainable-power = <768>; 3661 3662 trips { 3663 cpu1_alert0: trip-point0 { 3664 temperature = <90000>; 3665 hysteresis = <2000>; 3666 type = "passive"; 3667 }; 3668 3669 cpu1_alert1: trip-point1 { 3670 temperature = <95000>; 3671 hysteresis = <2000>; 3672 type = "passive"; 3673 }; 3674 3675 cpu1_crit: cpu_crit { 3676 temperature = <110000>; 3677 hysteresis = <1000>; 3678 type = "critical"; 3679 }; 3680 }; 3681 3682 cooling-maps { 3683 map0 { 3684 trip = <&cpu1_alert0>; 3685 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3686 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3687 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3688 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3689 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3690 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3691 }; 3692 map1 { 3693 trip = <&cpu1_alert1>; 3694 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3695 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3696 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3697 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3699 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3700 }; 3701 }; 3702 }; 3703 3704 cpu2_thermal: cpu2-thermal { 3705 polling-delay-passive = <250>; 3706 polling-delay = <0>; 3707 3708 thermal-sensors = <&tsens0 3>; 3709 sustainable-power = <768>; 3710 3711 trips { 3712 cpu2_alert0: trip-point0 { 3713 temperature = <90000>; 3714 hysteresis = <2000>; 3715 type = "passive"; 3716 }; 3717 3718 cpu2_alert1: trip-point1 { 3719 temperature = <95000>; 3720 hysteresis = <2000>; 3721 type = "passive"; 3722 }; 3723 3724 cpu2_crit: cpu_crit { 3725 temperature = <110000>; 3726 hysteresis = <1000>; 3727 type = "critical"; 3728 }; 3729 }; 3730 3731 cooling-maps { 3732 map0 { 3733 trip = <&cpu2_alert0>; 3734 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3735 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3736 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3740 }; 3741 map1 { 3742 trip = <&cpu2_alert1>; 3743 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3744 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3745 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3749 }; 3750 }; 3751 }; 3752 3753 cpu3_thermal: cpu3-thermal { 3754 polling-delay-passive = <250>; 3755 polling-delay = <0>; 3756 3757 thermal-sensors = <&tsens0 4>; 3758 sustainable-power = <768>; 3759 3760 trips { 3761 cpu3_alert0: trip-point0 { 3762 temperature = <90000>; 3763 hysteresis = <2000>; 3764 type = "passive"; 3765 }; 3766 3767 cpu3_alert1: trip-point1 { 3768 temperature = <95000>; 3769 hysteresis = <2000>; 3770 type = "passive"; 3771 }; 3772 3773 cpu3_crit: cpu_crit { 3774 temperature = <110000>; 3775 hysteresis = <1000>; 3776 type = "critical"; 3777 }; 3778 }; 3779 3780 cooling-maps { 3781 map0 { 3782 trip = <&cpu3_alert0>; 3783 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3785 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3787 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3788 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3789 }; 3790 map1 { 3791 trip = <&cpu3_alert1>; 3792 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3794 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3795 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3796 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3798 }; 3799 }; 3800 }; 3801 3802 cpu4_thermal: cpu4-thermal { 3803 polling-delay-passive = <250>; 3804 polling-delay = <0>; 3805 3806 thermal-sensors = <&tsens0 5>; 3807 sustainable-power = <768>; 3808 3809 trips { 3810 cpu4_alert0: trip-point0 { 3811 temperature = <90000>; 3812 hysteresis = <2000>; 3813 type = "passive"; 3814 }; 3815 3816 cpu4_alert1: trip-point1 { 3817 temperature = <95000>; 3818 hysteresis = <2000>; 3819 type = "passive"; 3820 }; 3821 3822 cpu4_crit: cpu_crit { 3823 temperature = <110000>; 3824 hysteresis = <1000>; 3825 type = "critical"; 3826 }; 3827 }; 3828 3829 cooling-maps { 3830 map0 { 3831 trip = <&cpu4_alert0>; 3832 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3833 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3834 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3838 }; 3839 map1 { 3840 trip = <&cpu4_alert1>; 3841 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3846 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3847 }; 3848 }; 3849 }; 3850 3851 cpu5_thermal: cpu5-thermal { 3852 polling-delay-passive = <250>; 3853 polling-delay = <0>; 3854 3855 thermal-sensors = <&tsens0 6>; 3856 sustainable-power = <768>; 3857 3858 trips { 3859 cpu5_alert0: trip-point0 { 3860 temperature = <90000>; 3861 hysteresis = <2000>; 3862 type = "passive"; 3863 }; 3864 3865 cpu5_alert1: trip-point1 { 3866 temperature = <95000>; 3867 hysteresis = <2000>; 3868 type = "passive"; 3869 }; 3870 3871 cpu5_crit: cpu_crit { 3872 temperature = <110000>; 3873 hysteresis = <1000>; 3874 type = "critical"; 3875 }; 3876 }; 3877 3878 cooling-maps { 3879 map0 { 3880 trip = <&cpu5_alert0>; 3881 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3882 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3883 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3884 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3885 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3886 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3887 }; 3888 map1 { 3889 trip = <&cpu5_alert1>; 3890 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3891 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3892 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3896 }; 3897 }; 3898 }; 3899 3900 cpu6_thermal: cpu6-thermal { 3901 polling-delay-passive = <250>; 3902 polling-delay = <0>; 3903 3904 thermal-sensors = <&tsens0 9>; 3905 sustainable-power = <1202>; 3906 3907 trips { 3908 cpu6_alert0: trip-point0 { 3909 temperature = <90000>; 3910 hysteresis = <2000>; 3911 type = "passive"; 3912 }; 3913 3914 cpu6_alert1: trip-point1 { 3915 temperature = <95000>; 3916 hysteresis = <2000>; 3917 type = "passive"; 3918 }; 3919 3920 cpu6_crit: cpu_crit { 3921 temperature = <110000>; 3922 hysteresis = <1000>; 3923 type = "critical"; 3924 }; 3925 }; 3926 3927 cooling-maps { 3928 map0 { 3929 trip = <&cpu6_alert0>; 3930 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3932 }; 3933 map1 { 3934 trip = <&cpu6_alert1>; 3935 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3936 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3937 }; 3938 }; 3939 }; 3940 3941 cpu7_thermal: cpu7-thermal { 3942 polling-delay-passive = <250>; 3943 polling-delay = <0>; 3944 3945 thermal-sensors = <&tsens0 10>; 3946 sustainable-power = <1202>; 3947 3948 trips { 3949 cpu7_alert0: trip-point0 { 3950 temperature = <90000>; 3951 hysteresis = <2000>; 3952 type = "passive"; 3953 }; 3954 3955 cpu7_alert1: trip-point1 { 3956 temperature = <95000>; 3957 hysteresis = <2000>; 3958 type = "passive"; 3959 }; 3960 3961 cpu7_crit: cpu_crit { 3962 temperature = <110000>; 3963 hysteresis = <1000>; 3964 type = "critical"; 3965 }; 3966 }; 3967 3968 cooling-maps { 3969 map0 { 3970 trip = <&cpu7_alert0>; 3971 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3972 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3973 }; 3974 map1 { 3975 trip = <&cpu7_alert1>; 3976 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3977 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3978 }; 3979 }; 3980 }; 3981 3982 cpu8_thermal: cpu8-thermal { 3983 polling-delay-passive = <250>; 3984 polling-delay = <0>; 3985 3986 thermal-sensors = <&tsens0 11>; 3987 sustainable-power = <1202>; 3988 3989 trips { 3990 cpu8_alert0: trip-point0 { 3991 temperature = <90000>; 3992 hysteresis = <2000>; 3993 type = "passive"; 3994 }; 3995 3996 cpu8_alert1: trip-point1 { 3997 temperature = <95000>; 3998 hysteresis = <2000>; 3999 type = "passive"; 4000 }; 4001 4002 cpu8_crit: cpu_crit { 4003 temperature = <110000>; 4004 hysteresis = <1000>; 4005 type = "critical"; 4006 }; 4007 }; 4008 4009 cooling-maps { 4010 map0 { 4011 trip = <&cpu8_alert0>; 4012 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4013 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4014 }; 4015 map1 { 4016 trip = <&cpu8_alert1>; 4017 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4018 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4019 }; 4020 }; 4021 }; 4022 4023 cpu9_thermal: cpu9-thermal { 4024 polling-delay-passive = <250>; 4025 polling-delay = <0>; 4026 4027 thermal-sensors = <&tsens0 12>; 4028 sustainable-power = <1202>; 4029 4030 trips { 4031 cpu9_alert0: trip-point0 { 4032 temperature = <90000>; 4033 hysteresis = <2000>; 4034 type = "passive"; 4035 }; 4036 4037 cpu9_alert1: trip-point1 { 4038 temperature = <95000>; 4039 hysteresis = <2000>; 4040 type = "passive"; 4041 }; 4042 4043 cpu9_crit: cpu_crit { 4044 temperature = <110000>; 4045 hysteresis = <1000>; 4046 type = "critical"; 4047 }; 4048 }; 4049 4050 cooling-maps { 4051 map0 { 4052 trip = <&cpu9_alert0>; 4053 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4054 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4055 }; 4056 map1 { 4057 trip = <&cpu9_alert1>; 4058 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4059 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4060 }; 4061 }; 4062 }; 4063 4064 aoss0-thermal { 4065 polling-delay-passive = <250>; 4066 polling-delay = <0>; 4067 4068 thermal-sensors = <&tsens0 0>; 4069 4070 trips { 4071 aoss0_alert0: trip-point0 { 4072 temperature = <90000>; 4073 hysteresis = <2000>; 4074 type = "hot"; 4075 }; 4076 4077 aoss0_crit: aoss0_crit { 4078 temperature = <110000>; 4079 hysteresis = <2000>; 4080 type = "critical"; 4081 }; 4082 }; 4083 }; 4084 4085 cpuss0-thermal { 4086 polling-delay-passive = <250>; 4087 polling-delay = <0>; 4088 4089 thermal-sensors = <&tsens0 7>; 4090 4091 trips { 4092 cpuss0_alert0: trip-point0 { 4093 temperature = <90000>; 4094 hysteresis = <2000>; 4095 type = "hot"; 4096 }; 4097 cpuss0_crit: cluster0_crit { 4098 temperature = <110000>; 4099 hysteresis = <2000>; 4100 type = "critical"; 4101 }; 4102 }; 4103 }; 4104 4105 cpuss1-thermal { 4106 polling-delay-passive = <250>; 4107 polling-delay = <0>; 4108 4109 thermal-sensors = <&tsens0 8>; 4110 4111 trips { 4112 cpuss1_alert0: trip-point0 { 4113 temperature = <90000>; 4114 hysteresis = <2000>; 4115 type = "hot"; 4116 }; 4117 cpuss1_crit: cluster0_crit { 4118 temperature = <110000>; 4119 hysteresis = <2000>; 4120 type = "critical"; 4121 }; 4122 }; 4123 }; 4124 4125 gpuss0-thermal { 4126 polling-delay-passive = <250>; 4127 polling-delay = <0>; 4128 4129 thermal-sensors = <&tsens0 13>; 4130 4131 trips { 4132 gpuss0_alert0: trip-point0 { 4133 temperature = <95000>; 4134 hysteresis = <2000>; 4135 type = "passive"; 4136 }; 4137 4138 gpuss0_crit: gpuss0_crit { 4139 temperature = <110000>; 4140 hysteresis = <2000>; 4141 type = "critical"; 4142 }; 4143 }; 4144 4145 cooling-maps { 4146 map0 { 4147 trip = <&gpuss0_alert0>; 4148 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4149 }; 4150 }; 4151 }; 4152 4153 gpuss1-thermal { 4154 polling-delay-passive = <250>; 4155 polling-delay = <0>; 4156 4157 thermal-sensors = <&tsens0 14>; 4158 4159 trips { 4160 gpuss1_alert0: trip-point0 { 4161 temperature = <95000>; 4162 hysteresis = <2000>; 4163 type = "passive"; 4164 }; 4165 4166 gpuss1_crit: gpuss1_crit { 4167 temperature = <110000>; 4168 hysteresis = <2000>; 4169 type = "critical"; 4170 }; 4171 }; 4172 4173 cooling-maps { 4174 map0 { 4175 trip = <&gpuss1_alert0>; 4176 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4177 }; 4178 }; 4179 }; 4180 4181 aoss1-thermal { 4182 polling-delay-passive = <250>; 4183 polling-delay = <0>; 4184 4185 thermal-sensors = <&tsens1 0>; 4186 4187 trips { 4188 aoss1_alert0: trip-point0 { 4189 temperature = <90000>; 4190 hysteresis = <2000>; 4191 type = "hot"; 4192 }; 4193 4194 aoss1_crit: aoss1_crit { 4195 temperature = <110000>; 4196 hysteresis = <2000>; 4197 type = "critical"; 4198 }; 4199 }; 4200 }; 4201 4202 cwlan-thermal { 4203 polling-delay-passive = <250>; 4204 polling-delay = <0>; 4205 4206 thermal-sensors = <&tsens1 1>; 4207 4208 trips { 4209 cwlan_alert0: trip-point0 { 4210 temperature = <90000>; 4211 hysteresis = <2000>; 4212 type = "hot"; 4213 }; 4214 4215 cwlan_crit: cwlan_crit { 4216 temperature = <110000>; 4217 hysteresis = <2000>; 4218 type = "critical"; 4219 }; 4220 }; 4221 }; 4222 4223 audio-thermal { 4224 polling-delay-passive = <250>; 4225 polling-delay = <0>; 4226 4227 thermal-sensors = <&tsens1 2>; 4228 4229 trips { 4230 audio_alert0: trip-point0 { 4231 temperature = <90000>; 4232 hysteresis = <2000>; 4233 type = "hot"; 4234 }; 4235 4236 audio_crit: audio_crit { 4237 temperature = <110000>; 4238 hysteresis = <2000>; 4239 type = "critical"; 4240 }; 4241 }; 4242 }; 4243 4244 ddr-thermal { 4245 polling-delay-passive = <250>; 4246 polling-delay = <0>; 4247 4248 thermal-sensors = <&tsens1 3>; 4249 4250 trips { 4251 ddr_alert0: trip-point0 { 4252 temperature = <90000>; 4253 hysteresis = <2000>; 4254 type = "hot"; 4255 }; 4256 4257 ddr_crit: ddr_crit { 4258 temperature = <110000>; 4259 hysteresis = <2000>; 4260 type = "critical"; 4261 }; 4262 }; 4263 }; 4264 4265 q6-hvx-thermal { 4266 polling-delay-passive = <250>; 4267 polling-delay = <0>; 4268 4269 thermal-sensors = <&tsens1 4>; 4270 4271 trips { 4272 q6_hvx_alert0: trip-point0 { 4273 temperature = <90000>; 4274 hysteresis = <2000>; 4275 type = "hot"; 4276 }; 4277 4278 q6_hvx_crit: q6_hvx_crit { 4279 temperature = <110000>; 4280 hysteresis = <2000>; 4281 type = "critical"; 4282 }; 4283 }; 4284 }; 4285 4286 camera-thermal { 4287 polling-delay-passive = <250>; 4288 polling-delay = <0>; 4289 4290 thermal-sensors = <&tsens1 5>; 4291 4292 trips { 4293 camera_alert0: trip-point0 { 4294 temperature = <90000>; 4295 hysteresis = <2000>; 4296 type = "hot"; 4297 }; 4298 4299 camera_crit: camera_crit { 4300 temperature = <110000>; 4301 hysteresis = <2000>; 4302 type = "critical"; 4303 }; 4304 }; 4305 }; 4306 4307 mdm-core-thermal { 4308 polling-delay-passive = <250>; 4309 polling-delay = <0>; 4310 4311 thermal-sensors = <&tsens1 6>; 4312 4313 trips { 4314 mdm_alert0: trip-point0 { 4315 temperature = <90000>; 4316 hysteresis = <2000>; 4317 type = "hot"; 4318 }; 4319 4320 mdm_crit: mdm_crit { 4321 temperature = <110000>; 4322 hysteresis = <2000>; 4323 type = "critical"; 4324 }; 4325 }; 4326 }; 4327 4328 mdm-dsp-thermal { 4329 polling-delay-passive = <250>; 4330 polling-delay = <0>; 4331 4332 thermal-sensors = <&tsens1 7>; 4333 4334 trips { 4335 mdm_dsp_alert0: trip-point0 { 4336 temperature = <90000>; 4337 hysteresis = <2000>; 4338 type = "hot"; 4339 }; 4340 4341 mdm_dsp_crit: mdm_dsp_crit { 4342 temperature = <110000>; 4343 hysteresis = <2000>; 4344 type = "critical"; 4345 }; 4346 }; 4347 }; 4348 4349 npu-thermal { 4350 polling-delay-passive = <250>; 4351 polling-delay = <0>; 4352 4353 thermal-sensors = <&tsens1 8>; 4354 4355 trips { 4356 npu_alert0: trip-point0 { 4357 temperature = <90000>; 4358 hysteresis = <2000>; 4359 type = "hot"; 4360 }; 4361 4362 npu_crit: npu_crit { 4363 temperature = <110000>; 4364 hysteresis = <2000>; 4365 type = "critical"; 4366 }; 4367 }; 4368 }; 4369 4370 video-thermal { 4371 polling-delay-passive = <250>; 4372 polling-delay = <0>; 4373 4374 thermal-sensors = <&tsens1 9>; 4375 4376 trips { 4377 video_alert0: trip-point0 { 4378 temperature = <90000>; 4379 hysteresis = <2000>; 4380 type = "hot"; 4381 }; 4382 4383 video_crit: video_crit { 4384 temperature = <110000>; 4385 hysteresis = <2000>; 4386 type = "critical"; 4387 }; 4388 }; 4389 }; 4390 }; 4391 4392 timer { 4393 compatible = "arm,armv8-timer"; 4394 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4395 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4396 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4397 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4398 }; 4399}; 4400