1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sc7180.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qusb2.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 aliases { 32 mmc1 = &sdhc_1; 33 mmc2 = &sdhc_2; 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi3 = &spi3; 49 spi5 = &spi5; 50 spi6 = &spi6; 51 spi8 = &spi8; 52 spi10 = &spi10; 53 spi11 = &spi11; 54 }; 55 56 chosen { }; 57 58 clocks { 59 xo_board: xo-board { 60 compatible = "fixed-clock"; 61 clock-frequency = <38400000>; 62 #clock-cells = <0>; 63 }; 64 65 sleep_clk: sleep-clk { 66 compatible = "fixed-clock"; 67 clock-frequency = <32764>; 68 #clock-cells = <0>; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <2>; 74 #size-cells = <0>; 75 76 CPU0: cpu@0 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo468"; 79 reg = <0x0 0x0>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 power-domains = <&CPU_PD0>; 83 power-domain-names = "psci"; 84 capacity-dmips-mhz = <415>; 85 dynamic-power-coefficient = <137>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 89 next-level-cache = <&L2_0>; 90 #cooling-cells = <2>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 L2_0: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&L3_0>; 97 L3_0: l3-cache { 98 compatible = "cache"; 99 cache-level = <3>; 100 cache-unified; 101 }; 102 }; 103 }; 104 105 CPU1: cpu@100 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo468"; 108 reg = <0x0 0x100>; 109 clocks = <&cpufreq_hw 0>; 110 enable-method = "psci"; 111 power-domains = <&CPU_PD1>; 112 power-domain-names = "psci"; 113 capacity-dmips-mhz = <415>; 114 dynamic-power-coefficient = <137>; 115 next-level-cache = <&L2_100>; 116 operating-points-v2 = <&cpu0_opp_table>; 117 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 118 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 119 #cooling-cells = <2>; 120 qcom,freq-domain = <&cpufreq_hw 0>; 121 L2_100: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 cache-unified; 125 next-level-cache = <&L3_0>; 126 }; 127 }; 128 129 CPU2: cpu@200 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo468"; 132 reg = <0x0 0x200>; 133 clocks = <&cpufreq_hw 0>; 134 enable-method = "psci"; 135 power-domains = <&CPU_PD2>; 136 power-domain-names = "psci"; 137 capacity-dmips-mhz = <415>; 138 dynamic-power-coefficient = <137>; 139 next-level-cache = <&L2_200>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 142 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 143 #cooling-cells = <2>; 144 qcom,freq-domain = <&cpufreq_hw 0>; 145 L2_200: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU3: cpu@300 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo468"; 156 reg = <0x0 0x300>; 157 clocks = <&cpufreq_hw 0>; 158 enable-method = "psci"; 159 power-domains = <&CPU_PD3>; 160 power-domain-names = "psci"; 161 capacity-dmips-mhz = <415>; 162 dynamic-power-coefficient = <137>; 163 next-level-cache = <&L2_300>; 164 operating-points-v2 = <&cpu0_opp_table>; 165 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167 #cooling-cells = <2>; 168 qcom,freq-domain = <&cpufreq_hw 0>; 169 L2_300: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU4: cpu@400 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo468"; 180 reg = <0x0 0x400>; 181 clocks = <&cpufreq_hw 0>; 182 enable-method = "psci"; 183 power-domains = <&CPU_PD4>; 184 power-domain-names = "psci"; 185 capacity-dmips-mhz = <415>; 186 dynamic-power-coefficient = <137>; 187 next-level-cache = <&L2_400>; 188 operating-points-v2 = <&cpu0_opp_table>; 189 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 190 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 191 #cooling-cells = <2>; 192 qcom,freq-domain = <&cpufreq_hw 0>; 193 L2_400: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU5: cpu@500 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo468"; 204 reg = <0x0 0x500>; 205 clocks = <&cpufreq_hw 0>; 206 enable-method = "psci"; 207 power-domains = <&CPU_PD5>; 208 power-domain-names = "psci"; 209 capacity-dmips-mhz = <415>; 210 dynamic-power-coefficient = <137>; 211 next-level-cache = <&L2_500>; 212 operating-points-v2 = <&cpu0_opp_table>; 213 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 214 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 215 #cooling-cells = <2>; 216 qcom,freq-domain = <&cpufreq_hw 0>; 217 L2_500: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 CPU6: cpu@600 { 226 device_type = "cpu"; 227 compatible = "qcom,kryo468"; 228 reg = <0x0 0x600>; 229 clocks = <&cpufreq_hw 1>; 230 enable-method = "psci"; 231 power-domains = <&CPU_PD6>; 232 power-domain-names = "psci"; 233 capacity-dmips-mhz = <1024>; 234 dynamic-power-coefficient = <480>; 235 next-level-cache = <&L2_600>; 236 operating-points-v2 = <&cpu6_opp_table>; 237 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 238 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 239 #cooling-cells = <2>; 240 qcom,freq-domain = <&cpufreq_hw 1>; 241 L2_600: l2-cache { 242 compatible = "cache"; 243 cache-level = <2>; 244 cache-unified; 245 next-level-cache = <&L3_0>; 246 }; 247 }; 248 249 CPU7: cpu@700 { 250 device_type = "cpu"; 251 compatible = "qcom,kryo468"; 252 reg = <0x0 0x700>; 253 clocks = <&cpufreq_hw 1>; 254 enable-method = "psci"; 255 power-domains = <&CPU_PD7>; 256 power-domain-names = "psci"; 257 capacity-dmips-mhz = <1024>; 258 dynamic-power-coefficient = <480>; 259 next-level-cache = <&L2_700>; 260 operating-points-v2 = <&cpu6_opp_table>; 261 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 262 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 263 #cooling-cells = <2>; 264 qcom,freq-domain = <&cpufreq_hw 1>; 265 L2_700: l2-cache { 266 compatible = "cache"; 267 cache-level = <2>; 268 cache-unified; 269 next-level-cache = <&L3_0>; 270 }; 271 }; 272 273 cpu-map { 274 cluster0 { 275 core0 { 276 cpu = <&CPU0>; 277 }; 278 279 core1 { 280 cpu = <&CPU1>; 281 }; 282 283 core2 { 284 cpu = <&CPU2>; 285 }; 286 287 core3 { 288 cpu = <&CPU3>; 289 }; 290 291 core4 { 292 cpu = <&CPU4>; 293 }; 294 295 core5 { 296 cpu = <&CPU5>; 297 }; 298 299 core6 { 300 cpu = <&CPU6>; 301 }; 302 303 core7 { 304 cpu = <&CPU7>; 305 }; 306 }; 307 }; 308 309 idle_states: idle-states { 310 entry-method = "psci"; 311 312 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 313 compatible = "arm,idle-state"; 314 idle-state-name = "little-power-down"; 315 arm,psci-suspend-param = <0x40000003>; 316 entry-latency-us = <549>; 317 exit-latency-us = <901>; 318 min-residency-us = <1774>; 319 local-timer-stop; 320 }; 321 322 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 323 compatible = "arm,idle-state"; 324 idle-state-name = "little-rail-power-down"; 325 arm,psci-suspend-param = <0x40000004>; 326 entry-latency-us = <702>; 327 exit-latency-us = <915>; 328 min-residency-us = <4001>; 329 local-timer-stop; 330 }; 331 332 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 333 compatible = "arm,idle-state"; 334 idle-state-name = "big-power-down"; 335 arm,psci-suspend-param = <0x40000003>; 336 entry-latency-us = <523>; 337 exit-latency-us = <1244>; 338 min-residency-us = <2207>; 339 local-timer-stop; 340 }; 341 342 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "big-rail-power-down"; 345 arm,psci-suspend-param = <0x40000004>; 346 entry-latency-us = <526>; 347 exit-latency-us = <1854>; 348 min-residency-us = <5555>; 349 local-timer-stop; 350 }; 351 }; 352 353 domain_idle_states: domain-idle-states { 354 CLUSTER_SLEEP_PC: cluster-sleep-0 { 355 compatible = "domain-idle-state"; 356 idle-state-name = "cluster-l3-power-collapse"; 357 arm,psci-suspend-param = <0x41000044>; 358 entry-latency-us = <2752>; 359 exit-latency-us = <3048>; 360 min-residency-us = <6118>; 361 }; 362 363 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 364 compatible = "domain-idle-state"; 365 idle-state-name = "cluster-cx-retention"; 366 arm,psci-suspend-param = <0x41001244>; 367 entry-latency-us = <3638>; 368 exit-latency-us = <4562>; 369 min-residency-us = <8467>; 370 }; 371 372 CLUSTER_AOSS_SLEEP: cluster-sleep-2 { 373 compatible = "domain-idle-state"; 374 idle-state-name = "cluster-power-down"; 375 arm,psci-suspend-param = <0x4100b244>; 376 entry-latency-us = <3263>; 377 exit-latency-us = <6562>; 378 min-residency-us = <9826>; 379 }; 380 }; 381 }; 382 383 firmware { 384 scm: scm { 385 compatible = "qcom,scm-sc7180", "qcom,scm"; 386 }; 387 }; 388 389 memory@80000000 { 390 device_type = "memory"; 391 /* We expect the bootloader to fill in the size */ 392 reg = <0 0x80000000 0 0>; 393 }; 394 395 cpu0_opp_table: opp-table-cpu0 { 396 compatible = "operating-points-v2"; 397 opp-shared; 398 399 cpu0_opp1: opp-300000000 { 400 opp-hz = /bits/ 64 <300000000>; 401 opp-peak-kBps = <1200000 4800000>; 402 }; 403 404 cpu0_opp2: opp-576000000 { 405 opp-hz = /bits/ 64 <576000000>; 406 opp-peak-kBps = <1200000 4800000>; 407 }; 408 409 cpu0_opp3: opp-768000000 { 410 opp-hz = /bits/ 64 <768000000>; 411 opp-peak-kBps = <1200000 4800000>; 412 }; 413 414 cpu0_opp4: opp-1017600000 { 415 opp-hz = /bits/ 64 <1017600000>; 416 opp-peak-kBps = <1804000 8908800>; 417 }; 418 419 cpu0_opp5: opp-1248000000 { 420 opp-hz = /bits/ 64 <1248000000>; 421 opp-peak-kBps = <2188000 12902400>; 422 }; 423 424 cpu0_opp6: opp-1324800000 { 425 opp-hz = /bits/ 64 <1324800000>; 426 opp-peak-kBps = <2188000 12902400>; 427 }; 428 429 cpu0_opp7: opp-1516800000 { 430 opp-hz = /bits/ 64 <1516800000>; 431 opp-peak-kBps = <3072000 15052800>; 432 }; 433 434 cpu0_opp8: opp-1612800000 { 435 opp-hz = /bits/ 64 <1612800000>; 436 opp-peak-kBps = <3072000 15052800>; 437 }; 438 439 cpu0_opp9: opp-1708800000 { 440 opp-hz = /bits/ 64 <1708800000>; 441 opp-peak-kBps = <3072000 15052800>; 442 }; 443 444 cpu0_opp10: opp-1804800000 { 445 opp-hz = /bits/ 64 <1804800000>; 446 opp-peak-kBps = <4068000 22425600>; 447 }; 448 }; 449 450 cpu6_opp_table: opp-table-cpu6 { 451 compatible = "operating-points-v2"; 452 opp-shared; 453 454 cpu6_opp1: opp-300000000 { 455 opp-hz = /bits/ 64 <300000000>; 456 opp-peak-kBps = <2188000 8908800>; 457 }; 458 459 cpu6_opp2: opp-652800000 { 460 opp-hz = /bits/ 64 <652800000>; 461 opp-peak-kBps = <2188000 8908800>; 462 }; 463 464 cpu6_opp3: opp-825600000 { 465 opp-hz = /bits/ 64 <825600000>; 466 opp-peak-kBps = <2188000 8908800>; 467 }; 468 469 cpu6_opp4: opp-979200000 { 470 opp-hz = /bits/ 64 <979200000>; 471 opp-peak-kBps = <2188000 8908800>; 472 }; 473 474 cpu6_opp5: opp-1113600000 { 475 opp-hz = /bits/ 64 <1113600000>; 476 opp-peak-kBps = <2188000 8908800>; 477 }; 478 479 cpu6_opp6: opp-1267200000 { 480 opp-hz = /bits/ 64 <1267200000>; 481 opp-peak-kBps = <4068000 12902400>; 482 }; 483 484 cpu6_opp7: opp-1555200000 { 485 opp-hz = /bits/ 64 <1555200000>; 486 opp-peak-kBps = <4068000 15052800>; 487 }; 488 489 cpu6_opp8: opp-1708800000 { 490 opp-hz = /bits/ 64 <1708800000>; 491 opp-peak-kBps = <6220000 19353600>; 492 }; 493 494 cpu6_opp9: opp-1843200000 { 495 opp-hz = /bits/ 64 <1843200000>; 496 opp-peak-kBps = <6220000 19353600>; 497 }; 498 499 cpu6_opp10: opp-1900800000 { 500 opp-hz = /bits/ 64 <1900800000>; 501 opp-peak-kBps = <6220000 22425600>; 502 }; 503 504 cpu6_opp11: opp-1996800000 { 505 opp-hz = /bits/ 64 <1996800000>; 506 opp-peak-kBps = <6220000 22425600>; 507 }; 508 509 cpu6_opp12: opp-2112000000 { 510 opp-hz = /bits/ 64 <2112000000>; 511 opp-peak-kBps = <6220000 22425600>; 512 }; 513 514 cpu6_opp13: opp-2208000000 { 515 opp-hz = /bits/ 64 <2208000000>; 516 opp-peak-kBps = <7216000 22425600>; 517 }; 518 519 cpu6_opp14: opp-2323200000 { 520 opp-hz = /bits/ 64 <2323200000>; 521 opp-peak-kBps = <7216000 22425600>; 522 }; 523 524 cpu6_opp15: opp-2400000000 { 525 opp-hz = /bits/ 64 <2400000000>; 526 opp-peak-kBps = <8532000 23347200>; 527 }; 528 529 cpu6_opp16: opp-2553600000 { 530 opp-hz = /bits/ 64 <2553600000>; 531 opp-peak-kBps = <8532000 23347200>; 532 }; 533 }; 534 535 qspi_opp_table: opp-table-qspi { 536 compatible = "operating-points-v2"; 537 538 opp-75000000 { 539 opp-hz = /bits/ 64 <75000000>; 540 required-opps = <&rpmhpd_opp_low_svs>; 541 }; 542 543 opp-150000000 { 544 opp-hz = /bits/ 64 <150000000>; 545 required-opps = <&rpmhpd_opp_svs>; 546 }; 547 548 opp-300000000 { 549 opp-hz = /bits/ 64 <300000000>; 550 required-opps = <&rpmhpd_opp_nom>; 551 }; 552 }; 553 554 qup_opp_table: opp-table-qup { 555 compatible = "operating-points-v2"; 556 557 opp-75000000 { 558 opp-hz = /bits/ 64 <75000000>; 559 required-opps = <&rpmhpd_opp_low_svs>; 560 }; 561 562 opp-100000000 { 563 opp-hz = /bits/ 64 <100000000>; 564 required-opps = <&rpmhpd_opp_svs>; 565 }; 566 567 opp-128000000 { 568 opp-hz = /bits/ 64 <128000000>; 569 required-opps = <&rpmhpd_opp_nom>; 570 }; 571 }; 572 573 pmu { 574 compatible = "arm,armv8-pmuv3"; 575 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 576 }; 577 578 psci { 579 compatible = "arm,psci-1.0"; 580 method = "smc"; 581 582 CPU_PD0: cpu0 { 583 #power-domain-cells = <0>; 584 power-domains = <&CLUSTER_PD>; 585 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 586 }; 587 588 CPU_PD1: cpu1 { 589 #power-domain-cells = <0>; 590 power-domains = <&CLUSTER_PD>; 591 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 592 }; 593 594 CPU_PD2: cpu2 { 595 #power-domain-cells = <0>; 596 power-domains = <&CLUSTER_PD>; 597 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 598 }; 599 600 CPU_PD3: cpu3 { 601 #power-domain-cells = <0>; 602 power-domains = <&CLUSTER_PD>; 603 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 604 }; 605 606 CPU_PD4: cpu4 { 607 #power-domain-cells = <0>; 608 power-domains = <&CLUSTER_PD>; 609 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 610 }; 611 612 CPU_PD5: cpu5 { 613 #power-domain-cells = <0>; 614 power-domains = <&CLUSTER_PD>; 615 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 616 }; 617 618 CPU_PD6: cpu6 { 619 #power-domain-cells = <0>; 620 power-domains = <&CLUSTER_PD>; 621 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 622 }; 623 624 CPU_PD7: cpu7 { 625 #power-domain-cells = <0>; 626 power-domains = <&CLUSTER_PD>; 627 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 628 }; 629 630 CLUSTER_PD: cpu-cluster0 { 631 #power-domain-cells = <0>; 632 domain-idle-states = <&CLUSTER_SLEEP_PC 633 &CLUSTER_SLEEP_CX_RET 634 &CLUSTER_AOSS_SLEEP>; 635 }; 636 }; 637 638 reserved_memory: reserved-memory { 639 #address-cells = <2>; 640 #size-cells = <2>; 641 ranges; 642 643 hyp_mem: memory@80000000 { 644 reg = <0x0 0x80000000 0x0 0x600000>; 645 no-map; 646 }; 647 648 xbl_mem: memory@80600000 { 649 reg = <0x0 0x80600000 0x0 0x200000>; 650 no-map; 651 }; 652 653 aop_mem: memory@80800000 { 654 reg = <0x0 0x80800000 0x0 0x20000>; 655 no-map; 656 }; 657 658 aop_cmd_db_mem: memory@80820000 { 659 reg = <0x0 0x80820000 0x0 0x20000>; 660 compatible = "qcom,cmd-db"; 661 no-map; 662 }; 663 664 sec_apps_mem: memory@808ff000 { 665 reg = <0x0 0x808ff000 0x0 0x1000>; 666 no-map; 667 }; 668 669 smem_mem: memory@80900000 { 670 reg = <0x0 0x80900000 0x0 0x200000>; 671 no-map; 672 }; 673 674 tz_mem: memory@80b00000 { 675 reg = <0x0 0x80b00000 0x0 0x3900000>; 676 no-map; 677 }; 678 679 ipa_fw_mem: memory@8b700000 { 680 reg = <0 0x8b700000 0 0x10000>; 681 no-map; 682 }; 683 684 rmtfs_mem: memory@94600000 { 685 compatible = "qcom,rmtfs-mem"; 686 reg = <0x0 0x94600000 0x0 0x200000>; 687 no-map; 688 689 qcom,client-id = <1>; 690 qcom,vmid = <15>; 691 }; 692 }; 693 694 smem { 695 compatible = "qcom,smem"; 696 memory-region = <&smem_mem>; 697 hwlocks = <&tcsr_mutex 3>; 698 }; 699 700 smp2p-cdsp { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <94>, <432>; 703 704 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 705 706 mboxes = <&apss_shared 6>; 707 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <5>; 710 711 cdsp_smp2p_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 cdsp_smp2p_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-lpass { 725 compatible = "qcom,smp2p"; 726 qcom,smem = <443>, <429>; 727 728 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 729 730 mboxes = <&apss_shared 10>; 731 732 qcom,local-pid = <0>; 733 qcom,remote-pid = <2>; 734 735 adsp_smp2p_out: master-kernel { 736 qcom,entry-name = "master-kernel"; 737 #qcom,smem-state-cells = <1>; 738 }; 739 740 adsp_smp2p_in: slave-kernel { 741 qcom,entry-name = "slave-kernel"; 742 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 }; 747 748 smp2p-mpss { 749 compatible = "qcom,smp2p"; 750 qcom,smem = <435>, <428>; 751 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 752 mboxes = <&apss_shared 14>; 753 qcom,local-pid = <0>; 754 qcom,remote-pid = <1>; 755 756 modem_smp2p_out: master-kernel { 757 qcom,entry-name = "master-kernel"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 modem_smp2p_in: slave-kernel { 762 qcom,entry-name = "slave-kernel"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 767 ipa_smp2p_out: ipa-ap-to-modem { 768 qcom,entry-name = "ipa"; 769 #qcom,smem-state-cells = <1>; 770 }; 771 772 ipa_smp2p_in: ipa-modem-to-ap { 773 qcom,entry-name = "ipa"; 774 interrupt-controller; 775 #interrupt-cells = <2>; 776 }; 777 }; 778 779 soc: soc@0 { 780 #address-cells = <2>; 781 #size-cells = <2>; 782 ranges = <0 0 0 0 0x10 0>; 783 dma-ranges = <0 0 0 0 0x10 0>; 784 compatible = "simple-bus"; 785 786 gcc: clock-controller@100000 { 787 compatible = "qcom,gcc-sc7180"; 788 reg = <0 0x00100000 0 0x1f0000>; 789 clocks = <&rpmhcc RPMH_CXO_CLK>, 790 <&rpmhcc RPMH_CXO_CLK_A>, 791 <&sleep_clk>; 792 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 793 #clock-cells = <1>; 794 #reset-cells = <1>; 795 #power-domain-cells = <1>; 796 power-domains = <&rpmhpd SC7180_CX>; 797 }; 798 799 qfprom: efuse@784000 { 800 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 801 reg = <0 0x00784000 0 0x7a0>, 802 <0 0x00780000 0 0x7a0>, 803 <0 0x00782000 0 0x100>, 804 <0 0x00786000 0 0x1fff>; 805 806 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 807 clock-names = "core"; 808 #address-cells = <1>; 809 #size-cells = <1>; 810 811 qusb2p_hstx_trim: hstx-trim-primary@25b { 812 reg = <0x25b 0x1>; 813 bits = <1 3>; 814 }; 815 816 gpu_speed_bin: gpu_speed_bin@1d2 { 817 reg = <0x1d2 0x2>; 818 bits = <5 8>; 819 }; 820 }; 821 822 sdhc_1: mmc@7c4000 { 823 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 824 reg = <0 0x007c4000 0 0x1000>, 825 <0 0x007c5000 0 0x1000>; 826 reg-names = "hc", "cqhci"; 827 828 iommus = <&apps_smmu 0x60 0x0>; 829 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 831 interrupt-names = "hc_irq", "pwr_irq"; 832 833 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 834 <&gcc GCC_SDCC1_APPS_CLK>, 835 <&rpmhcc RPMH_CXO_CLK>; 836 clock-names = "iface", "core", "xo"; 837 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 839 interconnect-names = "sdhc-ddr","cpu-sdhc"; 840 power-domains = <&rpmhpd SC7180_CX>; 841 operating-points-v2 = <&sdhc1_opp_table>; 842 843 bus-width = <8>; 844 non-removable; 845 supports-cqe; 846 847 mmc-ddr-1_8v; 848 mmc-hs200-1_8v; 849 mmc-hs400-1_8v; 850 mmc-hs400-enhanced-strobe; 851 852 status = "disabled"; 853 854 sdhc1_opp_table: opp-table { 855 compatible = "operating-points-v2"; 856 857 opp-100000000 { 858 opp-hz = /bits/ 64 <100000000>; 859 required-opps = <&rpmhpd_opp_low_svs>; 860 opp-peak-kBps = <1800000 600000>; 861 opp-avg-kBps = <100000 0>; 862 }; 863 864 opp-384000000 { 865 opp-hz = /bits/ 64 <384000000>; 866 required-opps = <&rpmhpd_opp_nom>; 867 opp-peak-kBps = <5400000 1600000>; 868 opp-avg-kBps = <390000 0>; 869 }; 870 }; 871 }; 872 873 qupv3_id_0: geniqup@8c0000 { 874 compatible = "qcom,geni-se-qup"; 875 reg = <0 0x008c0000 0 0x6000>; 876 clock-names = "m-ahb", "s-ahb"; 877 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 878 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 879 #address-cells = <2>; 880 #size-cells = <2>; 881 ranges; 882 iommus = <&apps_smmu 0x43 0x0>; 883 status = "disabled"; 884 885 i2c0: i2c@880000 { 886 compatible = "qcom,geni-i2c"; 887 reg = <0 0x00880000 0 0x4000>; 888 clock-names = "se"; 889 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 890 pinctrl-names = "default"; 891 pinctrl-0 = <&qup_i2c0_default>; 892 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 897 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 898 interconnect-names = "qup-core", "qup-config", 899 "qup-memory"; 900 power-domains = <&rpmhpd SC7180_CX>; 901 required-opps = <&rpmhpd_opp_low_svs>; 902 status = "disabled"; 903 }; 904 905 spi0: spi@880000 { 906 compatible = "qcom,geni-spi"; 907 reg = <0 0x00880000 0 0x4000>; 908 clock-names = "se"; 909 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 910 pinctrl-names = "default"; 911 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 912 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 power-domains = <&rpmhpd SC7180_CX>; 916 operating-points-v2 = <&qup_opp_table>; 917 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 919 interconnect-names = "qup-core", "qup-config"; 920 status = "disabled"; 921 }; 922 923 uart0: serial@880000 { 924 compatible = "qcom,geni-uart"; 925 reg = <0 0x00880000 0 0x4000>; 926 clock-names = "se"; 927 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 928 pinctrl-names = "default"; 929 pinctrl-0 = <&qup_uart0_default>; 930 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 931 power-domains = <&rpmhpd SC7180_CX>; 932 operating-points-v2 = <&qup_opp_table>; 933 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 934 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 935 interconnect-names = "qup-core", "qup-config"; 936 status = "disabled"; 937 }; 938 939 i2c1: i2c@884000 { 940 compatible = "qcom,geni-i2c"; 941 reg = <0 0x00884000 0 0x4000>; 942 clock-names = "se"; 943 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&qup_i2c1_default>; 946 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 950 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 951 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 952 interconnect-names = "qup-core", "qup-config", 953 "qup-memory"; 954 power-domains = <&rpmhpd SC7180_CX>; 955 required-opps = <&rpmhpd_opp_low_svs>; 956 status = "disabled"; 957 }; 958 959 spi1: spi@884000 { 960 compatible = "qcom,geni-spi"; 961 reg = <0 0x00884000 0 0x4000>; 962 clock-names = "se"; 963 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 966 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 power-domains = <&rpmhpd SC7180_CX>; 970 operating-points-v2 = <&qup_opp_table>; 971 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 973 interconnect-names = "qup-core", "qup-config"; 974 status = "disabled"; 975 }; 976 977 uart1: serial@884000 { 978 compatible = "qcom,geni-uart"; 979 reg = <0 0x00884000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_uart1_default>; 984 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 985 power-domains = <&rpmhpd SC7180_CX>; 986 operating-points-v2 = <&qup_opp_table>; 987 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 989 interconnect-names = "qup-core", "qup-config"; 990 status = "disabled"; 991 }; 992 993 i2c2: i2c@888000 { 994 compatible = "qcom,geni-i2c"; 995 reg = <0 0x00888000 0 0x4000>; 996 clock-names = "se"; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&qup_i2c2_default>; 1000 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1005 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1006 interconnect-names = "qup-core", "qup-config", 1007 "qup-memory"; 1008 power-domains = <&rpmhpd SC7180_CX>; 1009 required-opps = <&rpmhpd_opp_low_svs>; 1010 status = "disabled"; 1011 }; 1012 1013 uart2: serial@888000 { 1014 compatible = "qcom,geni-uart"; 1015 reg = <0 0x00888000 0 0x4000>; 1016 clock-names = "se"; 1017 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_uart2_default>; 1020 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1021 power-domains = <&rpmhpd SC7180_CX>; 1022 operating-points-v2 = <&qup_opp_table>; 1023 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1024 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1025 interconnect-names = "qup-core", "qup-config"; 1026 status = "disabled"; 1027 }; 1028 1029 i2c3: i2c@88c000 { 1030 compatible = "qcom,geni-i2c"; 1031 reg = <0 0x0088c000 0 0x4000>; 1032 clock-names = "se"; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_i2c3_default>; 1036 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1040 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1041 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1042 interconnect-names = "qup-core", "qup-config", 1043 "qup-memory"; 1044 power-domains = <&rpmhpd SC7180_CX>; 1045 required-opps = <&rpmhpd_opp_low_svs>; 1046 status = "disabled"; 1047 }; 1048 1049 spi3: spi@88c000 { 1050 compatible = "qcom,geni-spi"; 1051 reg = <0 0x0088c000 0 0x4000>; 1052 clock-names = "se"; 1053 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1054 pinctrl-names = "default"; 1055 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 1056 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 power-domains = <&rpmhpd SC7180_CX>; 1060 operating-points-v2 = <&qup_opp_table>; 1061 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1063 interconnect-names = "qup-core", "qup-config"; 1064 status = "disabled"; 1065 }; 1066 1067 uart3: serial@88c000 { 1068 compatible = "qcom,geni-uart"; 1069 reg = <0 0x0088c000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_uart3_default>; 1074 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1075 power-domains = <&rpmhpd SC7180_CX>; 1076 operating-points-v2 = <&qup_opp_table>; 1077 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1079 interconnect-names = "qup-core", "qup-config"; 1080 status = "disabled"; 1081 }; 1082 1083 i2c4: i2c@890000 { 1084 compatible = "qcom,geni-i2c"; 1085 reg = <0 0x00890000 0 0x4000>; 1086 clock-names = "se"; 1087 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_i2c4_default>; 1090 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1095 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1096 interconnect-names = "qup-core", "qup-config", 1097 "qup-memory"; 1098 power-domains = <&rpmhpd SC7180_CX>; 1099 required-opps = <&rpmhpd_opp_low_svs>; 1100 status = "disabled"; 1101 }; 1102 1103 uart4: serial@890000 { 1104 compatible = "qcom,geni-uart"; 1105 reg = <0 0x00890000 0 0x4000>; 1106 clock-names = "se"; 1107 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&qup_uart4_default>; 1110 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1111 power-domains = <&rpmhpd SC7180_CX>; 1112 operating-points-v2 = <&qup_opp_table>; 1113 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1114 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1115 interconnect-names = "qup-core", "qup-config"; 1116 status = "disabled"; 1117 }; 1118 1119 i2c5: i2c@894000 { 1120 compatible = "qcom,geni-i2c"; 1121 reg = <0 0x00894000 0 0x4000>; 1122 clock-names = "se"; 1123 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&qup_i2c5_default>; 1126 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1131 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1132 interconnect-names = "qup-core", "qup-config", 1133 "qup-memory"; 1134 power-domains = <&rpmhpd SC7180_CX>; 1135 required-opps = <&rpmhpd_opp_low_svs>; 1136 status = "disabled"; 1137 }; 1138 1139 spi5: spi@894000 { 1140 compatible = "qcom,geni-spi"; 1141 reg = <0 0x00894000 0 0x4000>; 1142 clock-names = "se"; 1143 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1144 pinctrl-names = "default"; 1145 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1146 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 power-domains = <&rpmhpd SC7180_CX>; 1150 operating-points-v2 = <&qup_opp_table>; 1151 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1153 interconnect-names = "qup-core", "qup-config"; 1154 status = "disabled"; 1155 }; 1156 1157 uart5: serial@894000 { 1158 compatible = "qcom,geni-uart"; 1159 reg = <0 0x00894000 0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_uart5_default>; 1164 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1165 power-domains = <&rpmhpd SC7180_CX>; 1166 operating-points-v2 = <&qup_opp_table>; 1167 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1168 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1169 interconnect-names = "qup-core", "qup-config"; 1170 status = "disabled"; 1171 }; 1172 }; 1173 1174 qupv3_id_1: geniqup@ac0000 { 1175 compatible = "qcom,geni-se-qup"; 1176 reg = <0 0x00ac0000 0 0x6000>; 1177 clock-names = "m-ahb", "s-ahb"; 1178 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1179 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1180 #address-cells = <2>; 1181 #size-cells = <2>; 1182 ranges; 1183 iommus = <&apps_smmu 0x4c3 0x0>; 1184 status = "disabled"; 1185 1186 i2c6: i2c@a80000 { 1187 compatible = "qcom,geni-i2c"; 1188 reg = <0 0x00a80000 0 0x4000>; 1189 clock-names = "se"; 1190 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&qup_i2c6_default>; 1193 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1197 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1198 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1199 interconnect-names = "qup-core", "qup-config", 1200 "qup-memory"; 1201 power-domains = <&rpmhpd SC7180_CX>; 1202 required-opps = <&rpmhpd_opp_low_svs>; 1203 status = "disabled"; 1204 }; 1205 1206 spi6: spi@a80000 { 1207 compatible = "qcom,geni-spi"; 1208 reg = <0 0x00a80000 0 0x4000>; 1209 clock-names = "se"; 1210 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1213 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 power-domains = <&rpmhpd SC7180_CX>; 1217 operating-points-v2 = <&qup_opp_table>; 1218 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1220 interconnect-names = "qup-core", "qup-config"; 1221 status = "disabled"; 1222 }; 1223 1224 uart6: serial@a80000 { 1225 compatible = "qcom,geni-uart"; 1226 reg = <0 0x00a80000 0 0x4000>; 1227 clock-names = "se"; 1228 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&qup_uart6_default>; 1231 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1232 power-domains = <&rpmhpd SC7180_CX>; 1233 operating-points-v2 = <&qup_opp_table>; 1234 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1235 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1236 interconnect-names = "qup-core", "qup-config"; 1237 status = "disabled"; 1238 }; 1239 1240 i2c7: i2c@a84000 { 1241 compatible = "qcom,geni-i2c"; 1242 reg = <0 0x00a84000 0 0x4000>; 1243 clock-names = "se"; 1244 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&qup_i2c7_default>; 1247 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1251 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1252 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1253 interconnect-names = "qup-core", "qup-config", 1254 "qup-memory"; 1255 power-domains = <&rpmhpd SC7180_CX>; 1256 required-opps = <&rpmhpd_opp_low_svs>; 1257 status = "disabled"; 1258 }; 1259 1260 uart7: serial@a84000 { 1261 compatible = "qcom,geni-uart"; 1262 reg = <0 0x00a84000 0 0x4000>; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_uart7_default>; 1267 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1268 power-domains = <&rpmhpd SC7180_CX>; 1269 operating-points-v2 = <&qup_opp_table>; 1270 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1271 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1272 interconnect-names = "qup-core", "qup-config"; 1273 status = "disabled"; 1274 }; 1275 1276 i2c8: i2c@a88000 { 1277 compatible = "qcom,geni-i2c"; 1278 reg = <0 0x00a88000 0 0x4000>; 1279 clock-names = "se"; 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1281 pinctrl-names = "default"; 1282 pinctrl-0 = <&qup_i2c8_default>; 1283 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1287 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1288 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1289 interconnect-names = "qup-core", "qup-config", 1290 "qup-memory"; 1291 power-domains = <&rpmhpd SC7180_CX>; 1292 required-opps = <&rpmhpd_opp_low_svs>; 1293 status = "disabled"; 1294 }; 1295 1296 spi8: spi@a88000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0 0x00a88000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1303 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 power-domains = <&rpmhpd SC7180_CX>; 1307 operating-points-v2 = <&qup_opp_table>; 1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1309 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1310 interconnect-names = "qup-core", "qup-config"; 1311 status = "disabled"; 1312 }; 1313 1314 uart8: serial@a88000 { 1315 compatible = "qcom,geni-debug-uart"; 1316 reg = <0 0x00a88000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_uart8_default>; 1321 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1322 power-domains = <&rpmhpd SC7180_CX>; 1323 operating-points-v2 = <&qup_opp_table>; 1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1326 interconnect-names = "qup-core", "qup-config"; 1327 status = "disabled"; 1328 }; 1329 1330 i2c9: i2c@a8c000 { 1331 compatible = "qcom,geni-i2c"; 1332 reg = <0 0x00a8c000 0 0x4000>; 1333 clock-names = "se"; 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&qup_i2c9_default>; 1337 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1341 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1342 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1343 interconnect-names = "qup-core", "qup-config", 1344 "qup-memory"; 1345 power-domains = <&rpmhpd SC7180_CX>; 1346 required-opps = <&rpmhpd_opp_low_svs>; 1347 status = "disabled"; 1348 }; 1349 1350 uart9: serial@a8c000 { 1351 compatible = "qcom,geni-uart"; 1352 reg = <0 0x00a8c000 0 0x4000>; 1353 clock-names = "se"; 1354 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&qup_uart9_default>; 1357 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1358 power-domains = <&rpmhpd SC7180_CX>; 1359 operating-points-v2 = <&qup_opp_table>; 1360 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1361 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1362 interconnect-names = "qup-core", "qup-config"; 1363 status = "disabled"; 1364 }; 1365 1366 i2c10: i2c@a90000 { 1367 compatible = "qcom,geni-i2c"; 1368 reg = <0 0x00a90000 0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1371 pinctrl-names = "default"; 1372 pinctrl-0 = <&qup_i2c10_default>; 1373 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1377 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1378 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1379 interconnect-names = "qup-core", "qup-config", 1380 "qup-memory"; 1381 power-domains = <&rpmhpd SC7180_CX>; 1382 required-opps = <&rpmhpd_opp_low_svs>; 1383 status = "disabled"; 1384 }; 1385 1386 spi10: spi@a90000 { 1387 compatible = "qcom,geni-spi"; 1388 reg = <0 0x00a90000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1393 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 power-domains = <&rpmhpd SC7180_CX>; 1397 operating-points-v2 = <&qup_opp_table>; 1398 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1399 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1400 interconnect-names = "qup-core", "qup-config"; 1401 status = "disabled"; 1402 }; 1403 1404 uart10: serial@a90000 { 1405 compatible = "qcom,geni-uart"; 1406 reg = <0 0x00a90000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_uart10_default>; 1411 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1412 power-domains = <&rpmhpd SC7180_CX>; 1413 operating-points-v2 = <&qup_opp_table>; 1414 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1415 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1416 interconnect-names = "qup-core", "qup-config"; 1417 status = "disabled"; 1418 }; 1419 1420 i2c11: i2c@a94000 { 1421 compatible = "qcom,geni-i2c"; 1422 reg = <0 0x00a94000 0 0x4000>; 1423 clock-names = "se"; 1424 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&qup_i2c11_default>; 1427 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1431 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1432 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1433 interconnect-names = "qup-core", "qup-config", 1434 "qup-memory"; 1435 power-domains = <&rpmhpd SC7180_CX>; 1436 required-opps = <&rpmhpd_opp_low_svs>; 1437 status = "disabled"; 1438 }; 1439 1440 spi11: spi@a94000 { 1441 compatible = "qcom,geni-spi"; 1442 reg = <0 0x00a94000 0 0x4000>; 1443 clock-names = "se"; 1444 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1445 pinctrl-names = "default"; 1446 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1447 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 power-domains = <&rpmhpd SC7180_CX>; 1451 operating-points-v2 = <&qup_opp_table>; 1452 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1453 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1454 interconnect-names = "qup-core", "qup-config"; 1455 status = "disabled"; 1456 }; 1457 1458 uart11: serial@a94000 { 1459 compatible = "qcom,geni-uart"; 1460 reg = <0 0x00a94000 0 0x4000>; 1461 clock-names = "se"; 1462 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_uart11_default>; 1465 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1466 power-domains = <&rpmhpd SC7180_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1469 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 status = "disabled"; 1472 }; 1473 }; 1474 1475 config_noc: interconnect@1500000 { 1476 compatible = "qcom,sc7180-config-noc"; 1477 reg = <0 0x01500000 0 0x28000>; 1478 #interconnect-cells = <2>; 1479 qcom,bcm-voters = <&apps_bcm_voter>; 1480 }; 1481 1482 system_noc: interconnect@1620000 { 1483 compatible = "qcom,sc7180-system-noc"; 1484 reg = <0 0x01620000 0 0x17080>; 1485 #interconnect-cells = <2>; 1486 qcom,bcm-voters = <&apps_bcm_voter>; 1487 }; 1488 1489 mc_virt: interconnect@1638000 { 1490 compatible = "qcom,sc7180-mc-virt"; 1491 reg = <0 0x01638000 0 0x1000>; 1492 #interconnect-cells = <2>; 1493 qcom,bcm-voters = <&apps_bcm_voter>; 1494 }; 1495 1496 qup_virt: interconnect@1650000 { 1497 compatible = "qcom,sc7180-qup-virt"; 1498 reg = <0 0x01650000 0 0x1000>; 1499 #interconnect-cells = <2>; 1500 qcom,bcm-voters = <&apps_bcm_voter>; 1501 }; 1502 1503 aggre1_noc: interconnect@16e0000 { 1504 compatible = "qcom,sc7180-aggre1-noc"; 1505 reg = <0 0x016e0000 0 0x15080>; 1506 #interconnect-cells = <2>; 1507 qcom,bcm-voters = <&apps_bcm_voter>; 1508 }; 1509 1510 aggre2_noc: interconnect@1705000 { 1511 compatible = "qcom,sc7180-aggre2-noc"; 1512 reg = <0 0x01705000 0 0x9000>; 1513 #interconnect-cells = <2>; 1514 qcom,bcm-voters = <&apps_bcm_voter>; 1515 }; 1516 1517 compute_noc: interconnect@170e000 { 1518 compatible = "qcom,sc7180-compute-noc"; 1519 reg = <0 0x0170e000 0 0x6000>; 1520 #interconnect-cells = <2>; 1521 qcom,bcm-voters = <&apps_bcm_voter>; 1522 }; 1523 1524 mmss_noc: interconnect@1740000 { 1525 compatible = "qcom,sc7180-mmss-noc"; 1526 reg = <0 0x01740000 0 0x1c100>; 1527 #interconnect-cells = <2>; 1528 qcom,bcm-voters = <&apps_bcm_voter>; 1529 }; 1530 1531 ipa: ipa@1e40000 { 1532 compatible = "qcom,sc7180-ipa"; 1533 1534 iommus = <&apps_smmu 0x440 0x0>, 1535 <&apps_smmu 0x442 0x0>; 1536 reg = <0 0x01e40000 0 0x7000>, 1537 <0 0x01e47000 0 0x2000>, 1538 <0 0x01e04000 0 0x2c000>; 1539 reg-names = "ipa-reg", 1540 "ipa-shared", 1541 "gsi"; 1542 1543 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1544 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1545 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1546 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1547 interrupt-names = "ipa", 1548 "gsi", 1549 "ipa-clock-query", 1550 "ipa-setup-ready"; 1551 1552 clocks = <&rpmhcc RPMH_IPA_CLK>; 1553 clock-names = "core"; 1554 1555 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1556 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1557 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1558 interconnect-names = "memory", 1559 "imem", 1560 "config"; 1561 1562 qcom,qmp = <&aoss_qmp>; 1563 1564 qcom,smem-states = <&ipa_smp2p_out 0>, 1565 <&ipa_smp2p_out 1>; 1566 qcom,smem-state-names = "ipa-clock-enabled-valid", 1567 "ipa-clock-enabled"; 1568 1569 status = "disabled"; 1570 }; 1571 1572 tcsr_mutex: hwlock@1f40000 { 1573 compatible = "qcom,tcsr-mutex"; 1574 reg = <0 0x01f40000 0 0x20000>; 1575 #hwlock-cells = <1>; 1576 }; 1577 1578 tcsr_regs_1: syscon@1f60000 { 1579 compatible = "qcom,sc7180-tcsr", "syscon"; 1580 reg = <0 0x01f60000 0 0x20000>; 1581 }; 1582 1583 tcsr_regs_2: syscon@1fc0000 { 1584 compatible = "qcom,sc7180-tcsr", "syscon"; 1585 reg = <0 0x01fc0000 0 0x40000>; 1586 }; 1587 1588 tlmm: pinctrl@3500000 { 1589 compatible = "qcom,sc7180-pinctrl"; 1590 reg = <0 0x03500000 0 0x300000>, 1591 <0 0x03900000 0 0x300000>, 1592 <0 0x03d00000 0 0x300000>; 1593 reg-names = "west", "north", "south"; 1594 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1595 gpio-controller; 1596 #gpio-cells = <2>; 1597 interrupt-controller; 1598 #interrupt-cells = <2>; 1599 gpio-ranges = <&tlmm 0 0 120>; 1600 wakeup-parent = <&pdc>; 1601 1602 dp_hot_plug_det: dp-hot-plug-det-state { 1603 pins = "gpio117"; 1604 function = "dp_hot"; 1605 }; 1606 1607 qspi_clk: qspi-clk-state { 1608 pins = "gpio63"; 1609 function = "qspi_clk"; 1610 }; 1611 1612 qspi_cs0: qspi-cs0-state { 1613 pins = "gpio68"; 1614 function = "qspi_cs"; 1615 }; 1616 1617 qspi_cs1: qspi-cs1-state { 1618 pins = "gpio72"; 1619 function = "qspi_cs"; 1620 }; 1621 1622 qspi_data0: qspi-data0-state { 1623 pins = "gpio64"; 1624 function = "qspi_data"; 1625 }; 1626 1627 qspi_data1: qspi-data1-state { 1628 pins = "gpio65"; 1629 function = "qspi_data"; 1630 }; 1631 1632 qspi_data23: qspi-data23-state { 1633 pins = "gpio66", "gpio67"; 1634 function = "qspi_data"; 1635 }; 1636 1637 qup_i2c0_default: qup-i2c0-default-state { 1638 pins = "gpio34", "gpio35"; 1639 function = "qup00"; 1640 }; 1641 1642 qup_i2c1_default: qup-i2c1-default-state { 1643 pins = "gpio0", "gpio1"; 1644 function = "qup01"; 1645 }; 1646 1647 qup_i2c2_default: qup-i2c2-default-state { 1648 pins = "gpio15", "gpio16"; 1649 function = "qup02_i2c"; 1650 }; 1651 1652 qup_i2c3_default: qup-i2c3-default-state { 1653 pins = "gpio38", "gpio39"; 1654 function = "qup03"; 1655 }; 1656 1657 qup_i2c4_default: qup-i2c4-default-state { 1658 pins = "gpio115", "gpio116"; 1659 function = "qup04_i2c"; 1660 }; 1661 1662 qup_i2c5_default: qup-i2c5-default-state { 1663 pins = "gpio25", "gpio26"; 1664 function = "qup05"; 1665 }; 1666 1667 qup_i2c6_default: qup-i2c6-default-state { 1668 pins = "gpio59", "gpio60"; 1669 function = "qup10"; 1670 }; 1671 1672 qup_i2c7_default: qup-i2c7-default-state { 1673 pins = "gpio6", "gpio7"; 1674 function = "qup11_i2c"; 1675 }; 1676 1677 qup_i2c8_default: qup-i2c8-default-state { 1678 pins = "gpio42", "gpio43"; 1679 function = "qup12"; 1680 }; 1681 1682 qup_i2c9_default: qup-i2c9-default-state { 1683 pins = "gpio46", "gpio47"; 1684 function = "qup13_i2c"; 1685 }; 1686 1687 qup_i2c10_default: qup-i2c10-default-state { 1688 pins = "gpio86", "gpio87"; 1689 function = "qup14"; 1690 }; 1691 1692 qup_i2c11_default: qup-i2c11-default-state { 1693 pins = "gpio53", "gpio54"; 1694 function = "qup15"; 1695 }; 1696 1697 qup_spi0_spi: qup-spi0-spi-state { 1698 pins = "gpio34", "gpio35", "gpio36"; 1699 function = "qup00"; 1700 }; 1701 1702 qup_spi0_cs: qup-spi0-cs-state { 1703 pins = "gpio37"; 1704 function = "qup00"; 1705 }; 1706 1707 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1708 pins = "gpio37"; 1709 function = "gpio"; 1710 }; 1711 1712 qup_spi1_spi: qup-spi1-spi-state { 1713 pins = "gpio0", "gpio1", "gpio2"; 1714 function = "qup01"; 1715 }; 1716 1717 qup_spi1_cs: qup-spi1-cs-state { 1718 pins = "gpio3"; 1719 function = "qup01"; 1720 }; 1721 1722 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1723 pins = "gpio3"; 1724 function = "gpio"; 1725 }; 1726 1727 qup_spi3_spi: qup-spi3-spi-state { 1728 pins = "gpio38", "gpio39", "gpio40"; 1729 function = "qup03"; 1730 }; 1731 1732 qup_spi3_cs: qup-spi3-cs-state { 1733 pins = "gpio41"; 1734 function = "qup03"; 1735 }; 1736 1737 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1738 pins = "gpio41"; 1739 function = "gpio"; 1740 }; 1741 1742 qup_spi5_spi: qup-spi5-spi-state { 1743 pins = "gpio25", "gpio26", "gpio27"; 1744 function = "qup05"; 1745 }; 1746 1747 qup_spi5_cs: qup-spi5-cs-state { 1748 pins = "gpio28"; 1749 function = "qup05"; 1750 }; 1751 1752 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1753 pins = "gpio28"; 1754 function = "gpio"; 1755 }; 1756 1757 qup_spi6_spi: qup-spi6-spi-state { 1758 pins = "gpio59", "gpio60", "gpio61"; 1759 function = "qup10"; 1760 }; 1761 1762 qup_spi6_cs: qup-spi6-cs-state { 1763 pins = "gpio62"; 1764 function = "qup10"; 1765 }; 1766 1767 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1768 pins = "gpio62"; 1769 function = "gpio"; 1770 }; 1771 1772 qup_spi8_spi: qup-spi8-spi-state { 1773 pins = "gpio42", "gpio43", "gpio44"; 1774 function = "qup12"; 1775 }; 1776 1777 qup_spi8_cs: qup-spi8-cs-state { 1778 pins = "gpio45"; 1779 function = "qup12"; 1780 }; 1781 1782 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1783 pins = "gpio45"; 1784 function = "gpio"; 1785 }; 1786 1787 qup_spi10_spi: qup-spi10-spi-state { 1788 pins = "gpio86", "gpio87", "gpio88"; 1789 function = "qup14"; 1790 }; 1791 1792 qup_spi10_cs: qup-spi10-cs-state { 1793 pins = "gpio89"; 1794 function = "qup14"; 1795 }; 1796 1797 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1798 pins = "gpio89"; 1799 function = "gpio"; 1800 }; 1801 1802 qup_spi11_spi: qup-spi11-spi-state { 1803 pins = "gpio53", "gpio54", "gpio55"; 1804 function = "qup15"; 1805 }; 1806 1807 qup_spi11_cs: qup-spi11-cs-state { 1808 pins = "gpio56"; 1809 function = "qup15"; 1810 }; 1811 1812 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1813 pins = "gpio56"; 1814 function = "gpio"; 1815 }; 1816 1817 qup_uart0_default: qup-uart0-default-state { 1818 qup_uart0_cts: cts-pins { 1819 pins = "gpio34"; 1820 function = "qup00"; 1821 }; 1822 1823 qup_uart0_rts: rts-pins { 1824 pins = "gpio35"; 1825 function = "qup00"; 1826 }; 1827 1828 qup_uart0_tx: tx-pins { 1829 pins = "gpio36"; 1830 function = "qup00"; 1831 }; 1832 1833 qup_uart0_rx: rx-pins { 1834 pins = "gpio37"; 1835 function = "qup00"; 1836 }; 1837 }; 1838 1839 qup_uart1_default: qup-uart1-default-state { 1840 qup_uart1_cts: cts-pins { 1841 pins = "gpio0"; 1842 function = "qup01"; 1843 }; 1844 1845 qup_uart1_rts: rts-pins { 1846 pins = "gpio1"; 1847 function = "qup01"; 1848 }; 1849 1850 qup_uart1_tx: tx-pins { 1851 pins = "gpio2"; 1852 function = "qup01"; 1853 }; 1854 1855 qup_uart1_rx: rx-pins { 1856 pins = "gpio3"; 1857 function = "qup01"; 1858 }; 1859 }; 1860 1861 qup_uart2_default: qup-uart2-default-state { 1862 qup_uart2_tx: tx-pins { 1863 pins = "gpio15"; 1864 function = "qup02_uart"; 1865 }; 1866 1867 qup_uart2_rx: rx-pins { 1868 pins = "gpio16"; 1869 function = "qup02_uart"; 1870 }; 1871 }; 1872 1873 qup_uart3_default: qup-uart3-default-state { 1874 qup_uart3_cts: cts-pins { 1875 pins = "gpio38"; 1876 function = "qup03"; 1877 }; 1878 1879 qup_uart3_rts: rts-pins { 1880 pins = "gpio39"; 1881 function = "qup03"; 1882 }; 1883 1884 qup_uart3_tx: tx-pins { 1885 pins = "gpio40"; 1886 function = "qup03"; 1887 }; 1888 1889 qup_uart3_rx: rx-pins { 1890 pins = "gpio41"; 1891 function = "qup03"; 1892 }; 1893 }; 1894 1895 qup_uart4_default: qup-uart4-default-state { 1896 qup_uart4_tx: tx-pins { 1897 pins = "gpio115"; 1898 function = "qup04_uart"; 1899 }; 1900 1901 qup_uart4_rx: rx-pins { 1902 pins = "gpio116"; 1903 function = "qup04_uart"; 1904 }; 1905 }; 1906 1907 qup_uart5_default: qup-uart5-default-state { 1908 qup_uart5_cts: cts-pins { 1909 pins = "gpio25"; 1910 function = "qup05"; 1911 }; 1912 1913 qup_uart5_rts: rts-pins { 1914 pins = "gpio26"; 1915 function = "qup05"; 1916 }; 1917 1918 qup_uart5_tx: tx-pins { 1919 pins = "gpio27"; 1920 function = "qup05"; 1921 }; 1922 1923 qup_uart5_rx: rx-pins { 1924 pins = "gpio28"; 1925 function = "qup05"; 1926 }; 1927 }; 1928 1929 qup_uart6_default: qup-uart6-default-state { 1930 qup_uart6_cts: cts-pins { 1931 pins = "gpio59"; 1932 function = "qup10"; 1933 }; 1934 1935 qup_uart6_rts: rts-pins { 1936 pins = "gpio60"; 1937 function = "qup10"; 1938 }; 1939 1940 qup_uart6_tx: tx-pins { 1941 pins = "gpio61"; 1942 function = "qup10"; 1943 }; 1944 1945 qup_uart6_rx: rx-pins { 1946 pins = "gpio62"; 1947 function = "qup10"; 1948 }; 1949 }; 1950 1951 qup_uart7_default: qup-uart7-default-state { 1952 qup_uart7_tx: tx-pins { 1953 pins = "gpio6"; 1954 function = "qup11_uart"; 1955 }; 1956 1957 qup_uart7_rx: rx-pins { 1958 pins = "gpio7"; 1959 function = "qup11_uart"; 1960 }; 1961 }; 1962 1963 qup_uart8_default: qup-uart8-default-state { 1964 qup_uart8_tx: tx-pins { 1965 pins = "gpio44"; 1966 function = "qup12"; 1967 }; 1968 1969 qup_uart8_rx: rx-pins { 1970 pins = "gpio45"; 1971 function = "qup12"; 1972 }; 1973 }; 1974 1975 qup_uart9_default: qup-uart9-default-state { 1976 qup_uart9_tx: tx-pins { 1977 pins = "gpio46"; 1978 function = "qup13_uart"; 1979 }; 1980 1981 qup_uart9_rx: rx-pins { 1982 pins = "gpio47"; 1983 function = "qup13_uart"; 1984 }; 1985 }; 1986 1987 qup_uart10_default: qup-uart10-default-state { 1988 qup_uart10_cts: cts-pins { 1989 pins = "gpio86"; 1990 function = "qup14"; 1991 }; 1992 1993 qup_uart10_rts: rts-pins { 1994 pins = "gpio87"; 1995 function = "qup14"; 1996 }; 1997 1998 qup_uart10_tx: tx-pins { 1999 pins = "gpio88"; 2000 function = "qup14"; 2001 }; 2002 2003 qup_uart10_rx: rx-pins { 2004 pins = "gpio89"; 2005 function = "qup14"; 2006 }; 2007 }; 2008 2009 qup_uart11_default: qup-uart11-default-state { 2010 qup_uart11_cts: cts-pins { 2011 pins = "gpio53"; 2012 function = "qup15"; 2013 }; 2014 2015 qup_uart11_rts: rts-pins { 2016 pins = "gpio54"; 2017 function = "qup15"; 2018 }; 2019 2020 qup_uart11_tx: tx-pins { 2021 pins = "gpio55"; 2022 function = "qup15"; 2023 }; 2024 2025 qup_uart11_rx: rx-pins { 2026 pins = "gpio56"; 2027 function = "qup15"; 2028 }; 2029 }; 2030 2031 sec_mi2s_active: sec-mi2s-active-state { 2032 pins = "gpio49", "gpio50", "gpio51"; 2033 function = "mi2s_1"; 2034 }; 2035 2036 pri_mi2s_active: pri-mi2s-active-state { 2037 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 2038 function = "mi2s_0"; 2039 }; 2040 2041 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 2042 pins = "gpio57"; 2043 function = "lpass_ext"; 2044 }; 2045 }; 2046 2047 remoteproc_mpss: remoteproc@4080000 { 2048 compatible = "qcom,sc7180-mpss-pas"; 2049 reg = <0 0x04080000 0 0x4040>; 2050 2051 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2052 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2053 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2054 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2055 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2056 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2057 interrupt-names = "wdog", "fatal", "ready", "handover", 2058 "stop-ack", "shutdown-ack"; 2059 2060 clocks = <&rpmhcc RPMH_CXO_CLK>; 2061 clock-names = "xo"; 2062 2063 power-domains = <&rpmhpd SC7180_CX>, 2064 <&rpmhpd SC7180_MX>, 2065 <&rpmhpd SC7180_MSS>; 2066 power-domain-names = "cx", "mx", "mss"; 2067 2068 memory-region = <&mpss_mem>; 2069 2070 qcom,qmp = <&aoss_qmp>; 2071 2072 qcom,smem-states = <&modem_smp2p_out 0>; 2073 qcom,smem-state-names = "stop"; 2074 2075 status = "disabled"; 2076 2077 glink-edge { 2078 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2079 label = "modem"; 2080 qcom,remote-pid = <1>; 2081 mboxes = <&apss_shared 12>; 2082 }; 2083 }; 2084 2085 gpu: gpu@5000000 { 2086 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2087 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2088 <0 0x05061000 0 0x800>; 2089 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2090 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2091 iommus = <&adreno_smmu 0>; 2092 operating-points-v2 = <&gpu_opp_table>; 2093 qcom,gmu = <&gmu>; 2094 2095 #cooling-cells = <2>; 2096 2097 nvmem-cells = <&gpu_speed_bin>; 2098 nvmem-cell-names = "speed_bin"; 2099 2100 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2101 interconnect-names = "gfx-mem"; 2102 2103 gpu_opp_table: opp-table { 2104 compatible = "operating-points-v2"; 2105 2106 opp-825000000 { 2107 opp-hz = /bits/ 64 <825000000>; 2108 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2109 opp-peak-kBps = <8532000>; 2110 opp-supported-hw = <0x04>; 2111 }; 2112 2113 opp-800000000 { 2114 opp-hz = /bits/ 64 <800000000>; 2115 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2116 opp-peak-kBps = <8532000>; 2117 opp-supported-hw = <0x07>; 2118 }; 2119 2120 opp-650000000 { 2121 opp-hz = /bits/ 64 <650000000>; 2122 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2123 opp-peak-kBps = <7216000>; 2124 opp-supported-hw = <0x07>; 2125 }; 2126 2127 opp-565000000 { 2128 opp-hz = /bits/ 64 <565000000>; 2129 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2130 opp-peak-kBps = <5412000>; 2131 opp-supported-hw = <0x07>; 2132 }; 2133 2134 opp-430000000 { 2135 opp-hz = /bits/ 64 <430000000>; 2136 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2137 opp-peak-kBps = <5412000>; 2138 opp-supported-hw = <0x07>; 2139 }; 2140 2141 opp-355000000 { 2142 opp-hz = /bits/ 64 <355000000>; 2143 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2144 opp-peak-kBps = <3072000>; 2145 opp-supported-hw = <0x07>; 2146 }; 2147 2148 opp-267000000 { 2149 opp-hz = /bits/ 64 <267000000>; 2150 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2151 opp-peak-kBps = <3072000>; 2152 opp-supported-hw = <0x07>; 2153 }; 2154 2155 opp-180000000 { 2156 opp-hz = /bits/ 64 <180000000>; 2157 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2158 opp-peak-kBps = <1804000>; 2159 opp-supported-hw = <0x07>; 2160 }; 2161 }; 2162 }; 2163 2164 adreno_smmu: iommu@5040000 { 2165 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2166 reg = <0 0x05040000 0 0x10000>; 2167 #iommu-cells = <1>; 2168 #global-interrupts = <2>; 2169 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2179 2180 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2181 <&gcc GCC_GPU_CFG_AHB_CLK>; 2182 clock-names = "bus", "iface"; 2183 2184 power-domains = <&gpucc CX_GDSC>; 2185 }; 2186 2187 gmu: gmu@506a000 { 2188 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2189 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2190 <0 0x0b490000 0 0x10000>; 2191 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2192 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2194 interrupt-names = "hfi", "gmu"; 2195 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2196 <&gpucc GPU_CC_CXO_CLK>, 2197 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2198 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2199 clock-names = "gmu", "cxo", "axi", "memnoc"; 2200 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2201 power-domain-names = "cx", "gx"; 2202 iommus = <&adreno_smmu 5>; 2203 operating-points-v2 = <&gmu_opp_table>; 2204 2205 gmu_opp_table: opp-table { 2206 compatible = "operating-points-v2"; 2207 2208 opp-200000000 { 2209 opp-hz = /bits/ 64 <200000000>; 2210 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2211 }; 2212 }; 2213 }; 2214 2215 gpucc: clock-controller@5090000 { 2216 compatible = "qcom,sc7180-gpucc"; 2217 reg = <0 0x05090000 0 0x9000>; 2218 clocks = <&rpmhcc RPMH_CXO_CLK>, 2219 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2220 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2221 clock-names = "bi_tcxo", 2222 "gcc_gpu_gpll0_clk_src", 2223 "gcc_gpu_gpll0_div_clk_src"; 2224 #clock-cells = <1>; 2225 #reset-cells = <1>; 2226 #power-domain-cells = <1>; 2227 }; 2228 2229 dma@10a2000 { 2230 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2231 reg = <0x0 0x010a2000 0x0 0x1000>, 2232 <0x0 0x010ae000 0x0 0x2000>; 2233 }; 2234 2235 stm@6002000 { 2236 compatible = "arm,coresight-stm", "arm,primecell"; 2237 reg = <0 0x06002000 0 0x1000>, 2238 <0 0x16280000 0 0x180000>; 2239 reg-names = "stm-base", "stm-stimulus-base"; 2240 2241 clocks = <&aoss_qmp>; 2242 clock-names = "apb_pclk"; 2243 2244 out-ports { 2245 port { 2246 stm_out: endpoint { 2247 remote-endpoint = <&funnel0_in7>; 2248 }; 2249 }; 2250 }; 2251 }; 2252 2253 funnel@6041000 { 2254 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2255 reg = <0 0x06041000 0 0x1000>; 2256 2257 clocks = <&aoss_qmp>; 2258 clock-names = "apb_pclk"; 2259 2260 out-ports { 2261 port { 2262 funnel0_out: endpoint { 2263 remote-endpoint = <&merge_funnel_in0>; 2264 }; 2265 }; 2266 }; 2267 2268 in-ports { 2269 #address-cells = <1>; 2270 #size-cells = <0>; 2271 2272 port@7 { 2273 reg = <7>; 2274 funnel0_in7: endpoint { 2275 remote-endpoint = <&stm_out>; 2276 }; 2277 }; 2278 }; 2279 }; 2280 2281 funnel@6042000 { 2282 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2283 reg = <0 0x06042000 0 0x1000>; 2284 2285 clocks = <&aoss_qmp>; 2286 clock-names = "apb_pclk"; 2287 2288 out-ports { 2289 port { 2290 funnel1_out: endpoint { 2291 remote-endpoint = <&merge_funnel_in1>; 2292 }; 2293 }; 2294 }; 2295 2296 in-ports { 2297 #address-cells = <1>; 2298 #size-cells = <0>; 2299 2300 port@4 { 2301 reg = <4>; 2302 funnel1_in4: endpoint { 2303 remote-endpoint = <&apss_merge_funnel_out>; 2304 }; 2305 }; 2306 }; 2307 }; 2308 2309 funnel@6045000 { 2310 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2311 reg = <0 0x06045000 0 0x1000>; 2312 2313 clocks = <&aoss_qmp>; 2314 clock-names = "apb_pclk"; 2315 2316 out-ports { 2317 port { 2318 merge_funnel_out: endpoint { 2319 remote-endpoint = <&swao_funnel_in>; 2320 }; 2321 }; 2322 }; 2323 2324 in-ports { 2325 #address-cells = <1>; 2326 #size-cells = <0>; 2327 2328 port@0 { 2329 reg = <0>; 2330 merge_funnel_in0: endpoint { 2331 remote-endpoint = <&funnel0_out>; 2332 }; 2333 }; 2334 2335 port@1 { 2336 reg = <1>; 2337 merge_funnel_in1: endpoint { 2338 remote-endpoint = <&funnel1_out>; 2339 }; 2340 }; 2341 }; 2342 }; 2343 2344 replicator@6046000 { 2345 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2346 reg = <0 0x06046000 0 0x1000>; 2347 2348 clocks = <&aoss_qmp>; 2349 clock-names = "apb_pclk"; 2350 2351 out-ports { 2352 port { 2353 replicator_out: endpoint { 2354 remote-endpoint = <&etr_in>; 2355 }; 2356 }; 2357 }; 2358 2359 in-ports { 2360 port { 2361 replicator_in: endpoint { 2362 remote-endpoint = <&swao_replicator_out>; 2363 }; 2364 }; 2365 }; 2366 }; 2367 2368 etr@6048000 { 2369 compatible = "arm,coresight-tmc", "arm,primecell"; 2370 reg = <0 0x06048000 0 0x1000>; 2371 iommus = <&apps_smmu 0x04a0 0x20>; 2372 2373 clocks = <&aoss_qmp>; 2374 clock-names = "apb_pclk"; 2375 arm,scatter-gather; 2376 2377 in-ports { 2378 port { 2379 etr_in: endpoint { 2380 remote-endpoint = <&replicator_out>; 2381 }; 2382 }; 2383 }; 2384 }; 2385 2386 funnel@6b04000 { 2387 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2388 reg = <0 0x06b04000 0 0x1000>; 2389 2390 clocks = <&aoss_qmp>; 2391 clock-names = "apb_pclk"; 2392 2393 out-ports { 2394 port { 2395 swao_funnel_out: endpoint { 2396 remote-endpoint = <&etf_in>; 2397 }; 2398 }; 2399 }; 2400 2401 in-ports { 2402 #address-cells = <1>; 2403 #size-cells = <0>; 2404 2405 port@7 { 2406 reg = <7>; 2407 swao_funnel_in: endpoint { 2408 remote-endpoint = <&merge_funnel_out>; 2409 }; 2410 }; 2411 }; 2412 }; 2413 2414 etf@6b05000 { 2415 compatible = "arm,coresight-tmc", "arm,primecell"; 2416 reg = <0 0x06b05000 0 0x1000>; 2417 2418 clocks = <&aoss_qmp>; 2419 clock-names = "apb_pclk"; 2420 2421 out-ports { 2422 port { 2423 etf_out: endpoint { 2424 remote-endpoint = <&swao_replicator_in>; 2425 }; 2426 }; 2427 }; 2428 2429 in-ports { 2430 port { 2431 etf_in: endpoint { 2432 remote-endpoint = <&swao_funnel_out>; 2433 }; 2434 }; 2435 }; 2436 }; 2437 2438 replicator@6b06000 { 2439 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2440 reg = <0 0x06b06000 0 0x1000>; 2441 2442 clocks = <&aoss_qmp>; 2443 clock-names = "apb_pclk"; 2444 qcom,replicator-loses-context; 2445 2446 out-ports { 2447 port { 2448 swao_replicator_out: endpoint { 2449 remote-endpoint = <&replicator_in>; 2450 }; 2451 }; 2452 }; 2453 2454 in-ports { 2455 port { 2456 swao_replicator_in: endpoint { 2457 remote-endpoint = <&etf_out>; 2458 }; 2459 }; 2460 }; 2461 }; 2462 2463 etm@7040000 { 2464 compatible = "arm,coresight-etm4x", "arm,primecell"; 2465 reg = <0 0x07040000 0 0x1000>; 2466 2467 cpu = <&CPU0>; 2468 2469 clocks = <&aoss_qmp>; 2470 clock-names = "apb_pclk"; 2471 arm,coresight-loses-context-with-cpu; 2472 qcom,skip-power-up; 2473 2474 out-ports { 2475 port { 2476 etm0_out: endpoint { 2477 remote-endpoint = <&apss_funnel_in0>; 2478 }; 2479 }; 2480 }; 2481 }; 2482 2483 etm@7140000 { 2484 compatible = "arm,coresight-etm4x", "arm,primecell"; 2485 reg = <0 0x07140000 0 0x1000>; 2486 2487 cpu = <&CPU1>; 2488 2489 clocks = <&aoss_qmp>; 2490 clock-names = "apb_pclk"; 2491 arm,coresight-loses-context-with-cpu; 2492 qcom,skip-power-up; 2493 2494 out-ports { 2495 port { 2496 etm1_out: endpoint { 2497 remote-endpoint = <&apss_funnel_in1>; 2498 }; 2499 }; 2500 }; 2501 }; 2502 2503 etm@7240000 { 2504 compatible = "arm,coresight-etm4x", "arm,primecell"; 2505 reg = <0 0x07240000 0 0x1000>; 2506 2507 cpu = <&CPU2>; 2508 2509 clocks = <&aoss_qmp>; 2510 clock-names = "apb_pclk"; 2511 arm,coresight-loses-context-with-cpu; 2512 qcom,skip-power-up; 2513 2514 out-ports { 2515 port { 2516 etm2_out: endpoint { 2517 remote-endpoint = <&apss_funnel_in2>; 2518 }; 2519 }; 2520 }; 2521 }; 2522 2523 etm@7340000 { 2524 compatible = "arm,coresight-etm4x", "arm,primecell"; 2525 reg = <0 0x07340000 0 0x1000>; 2526 2527 cpu = <&CPU3>; 2528 2529 clocks = <&aoss_qmp>; 2530 clock-names = "apb_pclk"; 2531 arm,coresight-loses-context-with-cpu; 2532 qcom,skip-power-up; 2533 2534 out-ports { 2535 port { 2536 etm3_out: endpoint { 2537 remote-endpoint = <&apss_funnel_in3>; 2538 }; 2539 }; 2540 }; 2541 }; 2542 2543 etm@7440000 { 2544 compatible = "arm,coresight-etm4x", "arm,primecell"; 2545 reg = <0 0x07440000 0 0x1000>; 2546 2547 cpu = <&CPU4>; 2548 2549 clocks = <&aoss_qmp>; 2550 clock-names = "apb_pclk"; 2551 arm,coresight-loses-context-with-cpu; 2552 qcom,skip-power-up; 2553 2554 out-ports { 2555 port { 2556 etm4_out: endpoint { 2557 remote-endpoint = <&apss_funnel_in4>; 2558 }; 2559 }; 2560 }; 2561 }; 2562 2563 etm@7540000 { 2564 compatible = "arm,coresight-etm4x", "arm,primecell"; 2565 reg = <0 0x07540000 0 0x1000>; 2566 2567 cpu = <&CPU5>; 2568 2569 clocks = <&aoss_qmp>; 2570 clock-names = "apb_pclk"; 2571 arm,coresight-loses-context-with-cpu; 2572 qcom,skip-power-up; 2573 2574 out-ports { 2575 port { 2576 etm5_out: endpoint { 2577 remote-endpoint = <&apss_funnel_in5>; 2578 }; 2579 }; 2580 }; 2581 }; 2582 2583 etm@7640000 { 2584 compatible = "arm,coresight-etm4x", "arm,primecell"; 2585 reg = <0 0x07640000 0 0x1000>; 2586 2587 cpu = <&CPU6>; 2588 2589 clocks = <&aoss_qmp>; 2590 clock-names = "apb_pclk"; 2591 arm,coresight-loses-context-with-cpu; 2592 qcom,skip-power-up; 2593 2594 out-ports { 2595 port { 2596 etm6_out: endpoint { 2597 remote-endpoint = <&apss_funnel_in6>; 2598 }; 2599 }; 2600 }; 2601 }; 2602 2603 etm@7740000 { 2604 compatible = "arm,coresight-etm4x", "arm,primecell"; 2605 reg = <0 0x07740000 0 0x1000>; 2606 2607 cpu = <&CPU7>; 2608 2609 clocks = <&aoss_qmp>; 2610 clock-names = "apb_pclk"; 2611 arm,coresight-loses-context-with-cpu; 2612 qcom,skip-power-up; 2613 2614 out-ports { 2615 port { 2616 etm7_out: endpoint { 2617 remote-endpoint = <&apss_funnel_in7>; 2618 }; 2619 }; 2620 }; 2621 }; 2622 2623 funnel@7800000 { /* APSS Funnel */ 2624 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2625 reg = <0 0x07800000 0 0x1000>; 2626 2627 clocks = <&aoss_qmp>; 2628 clock-names = "apb_pclk"; 2629 2630 out-ports { 2631 port { 2632 apss_funnel_out: endpoint { 2633 remote-endpoint = <&apss_merge_funnel_in>; 2634 }; 2635 }; 2636 }; 2637 2638 in-ports { 2639 #address-cells = <1>; 2640 #size-cells = <0>; 2641 2642 port@0 { 2643 reg = <0>; 2644 apss_funnel_in0: endpoint { 2645 remote-endpoint = <&etm0_out>; 2646 }; 2647 }; 2648 2649 port@1 { 2650 reg = <1>; 2651 apss_funnel_in1: endpoint { 2652 remote-endpoint = <&etm1_out>; 2653 }; 2654 }; 2655 2656 port@2 { 2657 reg = <2>; 2658 apss_funnel_in2: endpoint { 2659 remote-endpoint = <&etm2_out>; 2660 }; 2661 }; 2662 2663 port@3 { 2664 reg = <3>; 2665 apss_funnel_in3: endpoint { 2666 remote-endpoint = <&etm3_out>; 2667 }; 2668 }; 2669 2670 port@4 { 2671 reg = <4>; 2672 apss_funnel_in4: endpoint { 2673 remote-endpoint = <&etm4_out>; 2674 }; 2675 }; 2676 2677 port@5 { 2678 reg = <5>; 2679 apss_funnel_in5: endpoint { 2680 remote-endpoint = <&etm5_out>; 2681 }; 2682 }; 2683 2684 port@6 { 2685 reg = <6>; 2686 apss_funnel_in6: endpoint { 2687 remote-endpoint = <&etm6_out>; 2688 }; 2689 }; 2690 2691 port@7 { 2692 reg = <7>; 2693 apss_funnel_in7: endpoint { 2694 remote-endpoint = <&etm7_out>; 2695 }; 2696 }; 2697 }; 2698 }; 2699 2700 funnel@7810000 { 2701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2702 reg = <0 0x07810000 0 0x1000>; 2703 2704 clocks = <&aoss_qmp>; 2705 clock-names = "apb_pclk"; 2706 2707 out-ports { 2708 port { 2709 apss_merge_funnel_out: endpoint { 2710 remote-endpoint = <&funnel1_in4>; 2711 }; 2712 }; 2713 }; 2714 2715 in-ports { 2716 port { 2717 apss_merge_funnel_in: endpoint { 2718 remote-endpoint = <&apss_funnel_out>; 2719 }; 2720 }; 2721 }; 2722 }; 2723 2724 sdhc_2: mmc@8804000 { 2725 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2726 reg = <0 0x08804000 0 0x1000>; 2727 2728 iommus = <&apps_smmu 0x80 0>; 2729 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2730 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2731 interrupt-names = "hc_irq", "pwr_irq"; 2732 2733 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2734 <&gcc GCC_SDCC2_APPS_CLK>, 2735 <&rpmhcc RPMH_CXO_CLK>; 2736 clock-names = "iface", "core", "xo"; 2737 2738 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2739 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2740 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2741 power-domains = <&rpmhpd SC7180_CX>; 2742 operating-points-v2 = <&sdhc2_opp_table>; 2743 2744 bus-width = <4>; 2745 2746 status = "disabled"; 2747 2748 sdhc2_opp_table: opp-table { 2749 compatible = "operating-points-v2"; 2750 2751 opp-100000000 { 2752 opp-hz = /bits/ 64 <100000000>; 2753 required-opps = <&rpmhpd_opp_low_svs>; 2754 opp-peak-kBps = <1800000 600000>; 2755 opp-avg-kBps = <100000 0>; 2756 }; 2757 2758 opp-202000000 { 2759 opp-hz = /bits/ 64 <202000000>; 2760 required-opps = <&rpmhpd_opp_nom>; 2761 opp-peak-kBps = <5400000 1600000>; 2762 opp-avg-kBps = <200000 0>; 2763 }; 2764 }; 2765 }; 2766 2767 qspi: spi@88dc000 { 2768 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2769 reg = <0 0x088dc000 0 0x600>; 2770 iommus = <&apps_smmu 0x20 0x0>; 2771 #address-cells = <1>; 2772 #size-cells = <0>; 2773 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2774 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2775 <&gcc GCC_QSPI_CORE_CLK>; 2776 clock-names = "iface", "core"; 2777 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2778 &config_noc SLAVE_QSPI_0 0>; 2779 interconnect-names = "qspi-config"; 2780 power-domains = <&rpmhpd SC7180_CX>; 2781 operating-points-v2 = <&qspi_opp_table>; 2782 status = "disabled"; 2783 }; 2784 2785 usb_1_hsphy: phy@88e3000 { 2786 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2787 reg = <0 0x088e3000 0 0x400>; 2788 status = "disabled"; 2789 #phy-cells = <0>; 2790 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2791 <&rpmhcc RPMH_CXO_CLK>; 2792 clock-names = "cfg_ahb", "ref"; 2793 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2794 2795 nvmem-cells = <&qusb2p_hstx_trim>; 2796 }; 2797 2798 usb_1_qmpphy: phy-wrapper@88e9000 { 2799 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2800 reg = <0 0x088e9000 0 0x18c>, 2801 <0 0x088e8000 0 0x3c>, 2802 <0 0x088ea000 0 0x18c>; 2803 status = "disabled"; 2804 #address-cells = <2>; 2805 #size-cells = <2>; 2806 ranges; 2807 2808 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2809 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2810 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2811 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2812 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2813 2814 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2815 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2816 reset-names = "phy", "common"; 2817 2818 usb_1_ssphy: usb3-phy@88e9200 { 2819 reg = <0 0x088e9200 0 0x128>, 2820 <0 0x088e9400 0 0x200>, 2821 <0 0x088e9c00 0 0x218>, 2822 <0 0x088e9600 0 0x128>, 2823 <0 0x088e9800 0 0x200>, 2824 <0 0x088e9a00 0 0x18>; 2825 #clock-cells = <0>; 2826 #phy-cells = <0>; 2827 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2828 clock-names = "pipe0"; 2829 clock-output-names = "usb3_phy_pipe_clk_src"; 2830 }; 2831 2832 dp_phy: dp-phy@88ea200 { 2833 reg = <0 0x088ea200 0 0x200>, 2834 <0 0x088ea400 0 0x200>, 2835 <0 0x088eaa00 0 0x200>, 2836 <0 0x088ea600 0 0x200>, 2837 <0 0x088ea800 0 0x200>; 2838 #clock-cells = <1>; 2839 #phy-cells = <0>; 2840 }; 2841 }; 2842 2843 pmu@90b6300 { 2844 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon"; 2845 reg = <0 0x090b6300 0 0x600>; 2846 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2847 2848 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2849 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 2850 operating-points-v2 = <&cpu_bwmon_opp_table>; 2851 2852 cpu_bwmon_opp_table: opp-table { 2853 compatible = "operating-points-v2"; 2854 2855 opp-0 { 2856 opp-peak-kBps = <2288000>; 2857 }; 2858 2859 opp-1 { 2860 opp-peak-kBps = <4577000>; 2861 }; 2862 2863 opp-2 { 2864 opp-peak-kBps = <7110000>; 2865 }; 2866 2867 opp-3 { 2868 opp-peak-kBps = <9155000>; 2869 }; 2870 2871 opp-4 { 2872 opp-peak-kBps = <12298000>; 2873 }; 2874 2875 opp-5 { 2876 opp-peak-kBps = <14236000>; 2877 }; 2878 }; 2879 }; 2880 2881 pmu@90cd000 { 2882 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2883 reg = <0 0x090cd000 0 0x1000>; 2884 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 2885 2886 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 2887 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2888 operating-points-v2 = <&llcc_bwmon_opp_table>; 2889 2890 llcc_bwmon_opp_table: opp-table { 2891 compatible = "operating-points-v2"; 2892 2893 opp-0 { 2894 opp-peak-kBps = <1144000>; 2895 }; 2896 2897 opp-1 { 2898 opp-peak-kBps = <1720000>; 2899 }; 2900 2901 opp-2 { 2902 opp-peak-kBps = <2086000>; 2903 }; 2904 2905 opp-3 { 2906 opp-peak-kBps = <2929000>; 2907 }; 2908 2909 opp-4 { 2910 opp-peak-kBps = <3879000>; 2911 }; 2912 2913 opp-5 { 2914 opp-peak-kBps = <5931000>; 2915 }; 2916 2917 opp-6 { 2918 opp-peak-kBps = <6881000>; 2919 }; 2920 2921 opp-7 { 2922 opp-peak-kBps = <8137000>; 2923 }; 2924 }; 2925 }; 2926 2927 dc_noc: interconnect@9160000 { 2928 compatible = "qcom,sc7180-dc-noc"; 2929 reg = <0 0x09160000 0 0x03200>; 2930 #interconnect-cells = <2>; 2931 qcom,bcm-voters = <&apps_bcm_voter>; 2932 }; 2933 2934 system-cache-controller@9200000 { 2935 compatible = "qcom,sc7180-llcc"; 2936 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2937 reg-names = "llcc0_base", "llcc_broadcast_base"; 2938 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2939 }; 2940 2941 gem_noc: interconnect@9680000 { 2942 compatible = "qcom,sc7180-gem-noc"; 2943 reg = <0 0x09680000 0 0x3e200>; 2944 #interconnect-cells = <2>; 2945 qcom,bcm-voters = <&apps_bcm_voter>; 2946 }; 2947 2948 npu_noc: interconnect@9990000 { 2949 compatible = "qcom,sc7180-npu-noc"; 2950 reg = <0 0x09990000 0 0x1600>; 2951 #interconnect-cells = <2>; 2952 qcom,bcm-voters = <&apps_bcm_voter>; 2953 }; 2954 2955 usb_1: usb@a6f8800 { 2956 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2957 reg = <0 0x0a6f8800 0 0x400>; 2958 status = "disabled"; 2959 #address-cells = <2>; 2960 #size-cells = <2>; 2961 ranges; 2962 dma-ranges; 2963 2964 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2965 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2966 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2967 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2968 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2969 clock-names = "cfg_noc", 2970 "core", 2971 "iface", 2972 "sleep", 2973 "mock_utmi"; 2974 2975 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2976 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2977 assigned-clock-rates = <19200000>, <150000000>; 2978 2979 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2980 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2981 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2982 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2983 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2984 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2985 2986 power-domains = <&gcc USB30_PRIM_GDSC>; 2987 required-opps = <&rpmhpd_opp_nom>; 2988 2989 resets = <&gcc GCC_USB30_PRIM_BCR>; 2990 2991 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2992 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2993 interconnect-names = "usb-ddr", "apps-usb"; 2994 2995 wakeup-source; 2996 2997 usb_1_dwc3: usb@a600000 { 2998 compatible = "snps,dwc3"; 2999 reg = <0 0x0a600000 0 0xe000>; 3000 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3001 iommus = <&apps_smmu 0x540 0>; 3002 snps,dis_u2_susphy_quirk; 3003 snps,dis_enblslpm_quirk; 3004 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3005 phy-names = "usb2-phy", "usb3-phy"; 3006 maximum-speed = "super-speed"; 3007 }; 3008 }; 3009 3010 venus: video-codec@aa00000 { 3011 compatible = "qcom,sc7180-venus"; 3012 reg = <0 0x0aa00000 0 0xff000>; 3013 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3014 power-domains = <&videocc VENUS_GDSC>, 3015 <&videocc VCODEC0_GDSC>, 3016 <&rpmhpd SC7180_CX>; 3017 power-domain-names = "venus", "vcodec0", "cx"; 3018 operating-points-v2 = <&venus_opp_table>; 3019 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3020 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3021 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3022 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3023 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3024 clock-names = "core", "iface", "bus", 3025 "vcodec0_core", "vcodec0_bus"; 3026 iommus = <&apps_smmu 0x0c00 0x60>; 3027 memory-region = <&venus_mem>; 3028 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 3029 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3030 interconnect-names = "video-mem", "cpu-cfg"; 3031 3032 video-decoder { 3033 compatible = "venus-decoder"; 3034 }; 3035 3036 video-encoder { 3037 compatible = "venus-encoder"; 3038 }; 3039 3040 venus_opp_table: opp-table { 3041 compatible = "operating-points-v2"; 3042 3043 opp-150000000 { 3044 opp-hz = /bits/ 64 <150000000>; 3045 required-opps = <&rpmhpd_opp_low_svs>; 3046 }; 3047 3048 opp-270000000 { 3049 opp-hz = /bits/ 64 <270000000>; 3050 required-opps = <&rpmhpd_opp_svs>; 3051 }; 3052 3053 opp-340000000 { 3054 opp-hz = /bits/ 64 <340000000>; 3055 required-opps = <&rpmhpd_opp_svs_l1>; 3056 }; 3057 3058 opp-434000000 { 3059 opp-hz = /bits/ 64 <434000000>; 3060 required-opps = <&rpmhpd_opp_nom>; 3061 }; 3062 3063 opp-500000097 { 3064 opp-hz = /bits/ 64 <500000097>; 3065 required-opps = <&rpmhpd_opp_turbo>; 3066 }; 3067 }; 3068 }; 3069 3070 videocc: clock-controller@ab00000 { 3071 compatible = "qcom,sc7180-videocc"; 3072 reg = <0 0x0ab00000 0 0x10000>; 3073 clocks = <&rpmhcc RPMH_CXO_CLK>; 3074 clock-names = "bi_tcxo"; 3075 #clock-cells = <1>; 3076 #reset-cells = <1>; 3077 #power-domain-cells = <1>; 3078 }; 3079 3080 camnoc_virt: interconnect@ac00000 { 3081 compatible = "qcom,sc7180-camnoc-virt"; 3082 reg = <0 0x0ac00000 0 0x1000>; 3083 #interconnect-cells = <2>; 3084 qcom,bcm-voters = <&apps_bcm_voter>; 3085 }; 3086 3087 camcc: clock-controller@ad00000 { 3088 compatible = "qcom,sc7180-camcc"; 3089 reg = <0 0x0ad00000 0 0x10000>; 3090 clocks = <&rpmhcc RPMH_CXO_CLK>, 3091 <&gcc GCC_CAMERA_AHB_CLK>, 3092 <&gcc GCC_CAMERA_XO_CLK>; 3093 clock-names = "bi_tcxo", "iface", "xo"; 3094 #clock-cells = <1>; 3095 #reset-cells = <1>; 3096 #power-domain-cells = <1>; 3097 }; 3098 3099 mdss: display-subsystem@ae00000 { 3100 compatible = "qcom,sc7180-mdss"; 3101 reg = <0 0x0ae00000 0 0x1000>; 3102 reg-names = "mdss"; 3103 3104 power-domains = <&dispcc MDSS_GDSC>; 3105 3106 clocks = <&gcc GCC_DISP_AHB_CLK>, 3107 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3108 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3109 clock-names = "iface", "ahb", "core"; 3110 3111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3112 interrupt-controller; 3113 #interrupt-cells = <1>; 3114 3115 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3116 interconnect-names = "mdp0-mem"; 3117 3118 iommus = <&apps_smmu 0x800 0x2>; 3119 3120 #address-cells = <2>; 3121 #size-cells = <2>; 3122 ranges; 3123 3124 status = "disabled"; 3125 3126 mdp: display-controller@ae01000 { 3127 compatible = "qcom,sc7180-dpu"; 3128 reg = <0 0x0ae01000 0 0x8f000>, 3129 <0 0x0aeb0000 0 0x2008>; 3130 reg-names = "mdp", "vbif"; 3131 3132 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3133 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3134 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3135 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3136 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3137 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3138 clock-names = "bus", "iface", "rot", "lut", "core", 3139 "vsync"; 3140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3141 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3142 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3143 assigned-clock-rates = <19200000>, 3144 <19200000>, 3145 <19200000>; 3146 operating-points-v2 = <&mdp_opp_table>; 3147 power-domains = <&rpmhpd SC7180_CX>; 3148 3149 interrupt-parent = <&mdss>; 3150 interrupts = <0>; 3151 3152 ports { 3153 #address-cells = <1>; 3154 #size-cells = <0>; 3155 3156 port@0 { 3157 reg = <0>; 3158 dpu_intf1_out: endpoint { 3159 remote-endpoint = <&mdss_dsi0_in>; 3160 }; 3161 }; 3162 3163 port@2 { 3164 reg = <2>; 3165 dpu_intf0_out: endpoint { 3166 remote-endpoint = <&dp_in>; 3167 }; 3168 }; 3169 }; 3170 3171 mdp_opp_table: opp-table { 3172 compatible = "operating-points-v2"; 3173 3174 opp-200000000 { 3175 opp-hz = /bits/ 64 <200000000>; 3176 required-opps = <&rpmhpd_opp_low_svs>; 3177 }; 3178 3179 opp-300000000 { 3180 opp-hz = /bits/ 64 <300000000>; 3181 required-opps = <&rpmhpd_opp_svs>; 3182 }; 3183 3184 opp-345000000 { 3185 opp-hz = /bits/ 64 <345000000>; 3186 required-opps = <&rpmhpd_opp_svs_l1>; 3187 }; 3188 3189 opp-460000000 { 3190 opp-hz = /bits/ 64 <460000000>; 3191 required-opps = <&rpmhpd_opp_nom>; 3192 }; 3193 }; 3194 }; 3195 3196 mdss_dsi0: dsi@ae94000 { 3197 compatible = "qcom,sc7180-dsi-ctrl", 3198 "qcom,mdss-dsi-ctrl"; 3199 reg = <0 0x0ae94000 0 0x400>; 3200 reg-names = "dsi_ctrl"; 3201 3202 interrupt-parent = <&mdss>; 3203 interrupts = <4>; 3204 3205 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3206 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3207 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3208 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3209 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3210 <&gcc GCC_DISP_HF_AXI_CLK>; 3211 clock-names = "byte", 3212 "byte_intf", 3213 "pixel", 3214 "core", 3215 "iface", 3216 "bus"; 3217 3218 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3219 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3220 3221 operating-points-v2 = <&dsi_opp_table>; 3222 power-domains = <&rpmhpd SC7180_CX>; 3223 3224 phys = <&mdss_dsi0_phy>; 3225 3226 #address-cells = <1>; 3227 #size-cells = <0>; 3228 3229 status = "disabled"; 3230 3231 ports { 3232 #address-cells = <1>; 3233 #size-cells = <0>; 3234 3235 port@0 { 3236 reg = <0>; 3237 mdss_dsi0_in: endpoint { 3238 remote-endpoint = <&dpu_intf1_out>; 3239 }; 3240 }; 3241 3242 port@1 { 3243 reg = <1>; 3244 mdss_dsi0_out: endpoint { 3245 }; 3246 }; 3247 }; 3248 3249 dsi_opp_table: opp-table { 3250 compatible = "operating-points-v2"; 3251 3252 opp-187500000 { 3253 opp-hz = /bits/ 64 <187500000>; 3254 required-opps = <&rpmhpd_opp_low_svs>; 3255 }; 3256 3257 opp-300000000 { 3258 opp-hz = /bits/ 64 <300000000>; 3259 required-opps = <&rpmhpd_opp_svs>; 3260 }; 3261 3262 opp-358000000 { 3263 opp-hz = /bits/ 64 <358000000>; 3264 required-opps = <&rpmhpd_opp_svs_l1>; 3265 }; 3266 }; 3267 }; 3268 3269 mdss_dsi0_phy: phy@ae94400 { 3270 compatible = "qcom,dsi-phy-10nm"; 3271 reg = <0 0x0ae94400 0 0x200>, 3272 <0 0x0ae94600 0 0x280>, 3273 <0 0x0ae94a00 0 0x1e0>; 3274 reg-names = "dsi_phy", 3275 "dsi_phy_lane", 3276 "dsi_pll"; 3277 3278 #clock-cells = <1>; 3279 #phy-cells = <0>; 3280 3281 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3282 <&rpmhcc RPMH_CXO_CLK>; 3283 clock-names = "iface", "ref"; 3284 3285 status = "disabled"; 3286 }; 3287 3288 mdss_dp: displayport-controller@ae90000 { 3289 compatible = "qcom,sc7180-dp"; 3290 status = "disabled"; 3291 3292 reg = <0 0x0ae90000 0 0x200>, 3293 <0 0x0ae90200 0 0x200>, 3294 <0 0x0ae90400 0 0xc00>, 3295 <0 0x0ae91000 0 0x400>, 3296 <0 0x0ae91400 0 0x400>; 3297 3298 interrupt-parent = <&mdss>; 3299 interrupts = <12>; 3300 3301 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3302 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3303 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3304 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3305 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3306 clock-names = "core_iface", "core_aux", "ctrl_link", 3307 "ctrl_link_iface", "stream_pixel"; 3308 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3309 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3310 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3311 phys = <&dp_phy>; 3312 phy-names = "dp"; 3313 3314 operating-points-v2 = <&dp_opp_table>; 3315 power-domains = <&rpmhpd SC7180_CX>; 3316 3317 #sound-dai-cells = <0>; 3318 3319 ports { 3320 #address-cells = <1>; 3321 #size-cells = <0>; 3322 port@0 { 3323 reg = <0>; 3324 dp_in: endpoint { 3325 remote-endpoint = <&dpu_intf0_out>; 3326 }; 3327 }; 3328 3329 port@1 { 3330 reg = <1>; 3331 mdss_dp_out: endpoint { }; 3332 }; 3333 }; 3334 3335 dp_opp_table: opp-table { 3336 compatible = "operating-points-v2"; 3337 3338 opp-160000000 { 3339 opp-hz = /bits/ 64 <160000000>; 3340 required-opps = <&rpmhpd_opp_low_svs>; 3341 }; 3342 3343 opp-270000000 { 3344 opp-hz = /bits/ 64 <270000000>; 3345 required-opps = <&rpmhpd_opp_svs>; 3346 }; 3347 3348 opp-540000000 { 3349 opp-hz = /bits/ 64 <540000000>; 3350 required-opps = <&rpmhpd_opp_svs_l1>; 3351 }; 3352 3353 opp-810000000 { 3354 opp-hz = /bits/ 64 <810000000>; 3355 required-opps = <&rpmhpd_opp_nom>; 3356 }; 3357 }; 3358 }; 3359 }; 3360 3361 dispcc: clock-controller@af00000 { 3362 compatible = "qcom,sc7180-dispcc"; 3363 reg = <0 0x0af00000 0 0x200000>; 3364 clocks = <&rpmhcc RPMH_CXO_CLK>, 3365 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3366 <&mdss_dsi0_phy 0>, 3367 <&mdss_dsi0_phy 1>, 3368 <&dp_phy 0>, 3369 <&dp_phy 1>; 3370 clock-names = "bi_tcxo", 3371 "gcc_disp_gpll0_clk_src", 3372 "dsi0_phy_pll_out_byteclk", 3373 "dsi0_phy_pll_out_dsiclk", 3374 "dp_phy_pll_link_clk", 3375 "dp_phy_pll_vco_div_clk"; 3376 #clock-cells = <1>; 3377 #reset-cells = <1>; 3378 #power-domain-cells = <1>; 3379 }; 3380 3381 pdc: interrupt-controller@b220000 { 3382 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3383 reg = <0 0x0b220000 0 0x30000>; 3384 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3385 #interrupt-cells = <2>; 3386 interrupt-parent = <&intc>; 3387 interrupt-controller; 3388 }; 3389 3390 pdc_reset: reset-controller@b2e0000 { 3391 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3392 reg = <0 0x0b2e0000 0 0x20000>; 3393 #reset-cells = <1>; 3394 }; 3395 3396 tsens0: thermal-sensor@c263000 { 3397 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3398 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3399 <0 0x0c222000 0 0x1ff>; /* SROT */ 3400 #qcom,sensors = <15>; 3401 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3403 interrupt-names = "uplow","critical"; 3404 #thermal-sensor-cells = <1>; 3405 }; 3406 3407 tsens1: thermal-sensor@c265000 { 3408 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3409 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3410 <0 0x0c223000 0 0x1ff>; /* SROT */ 3411 #qcom,sensors = <10>; 3412 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3414 interrupt-names = "uplow","critical"; 3415 #thermal-sensor-cells = <1>; 3416 }; 3417 3418 aoss_reset: reset-controller@c2a0000 { 3419 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3420 reg = <0 0x0c2a0000 0 0x31000>; 3421 #reset-cells = <1>; 3422 }; 3423 3424 aoss_qmp: power-management@c300000 { 3425 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3426 reg = <0 0x0c300000 0 0x400>; 3427 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3428 mboxes = <&apss_shared 0>; 3429 3430 #clock-cells = <0>; 3431 }; 3432 3433 sram@c3f0000 { 3434 compatible = "qcom,rpmh-stats"; 3435 reg = <0 0x0c3f0000 0 0x400>; 3436 }; 3437 3438 spmi_bus: spmi@c440000 { 3439 compatible = "qcom,spmi-pmic-arb"; 3440 reg = <0 0x0c440000 0 0x1100>, 3441 <0 0x0c600000 0 0x2000000>, 3442 <0 0x0e600000 0 0x100000>, 3443 <0 0x0e700000 0 0xa0000>, 3444 <0 0x0c40a000 0 0x26000>; 3445 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3446 interrupt-names = "periph_irq"; 3447 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3448 qcom,ee = <0>; 3449 qcom,channel = <0>; 3450 #address-cells = <2>; 3451 #size-cells = <0>; 3452 interrupt-controller; 3453 #interrupt-cells = <4>; 3454 }; 3455 3456 sram@146aa000 { 3457 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3458 reg = <0 0x146aa000 0 0x2000>; 3459 3460 #address-cells = <1>; 3461 #size-cells = <1>; 3462 3463 ranges = <0 0 0x146aa000 0x2000>; 3464 3465 pil-reloc@94c { 3466 compatible = "qcom,pil-reloc-info"; 3467 reg = <0x94c 0xc8>; 3468 }; 3469 }; 3470 3471 apps_smmu: iommu@15000000 { 3472 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3473 reg = <0 0x15000000 0 0x100000>; 3474 #iommu-cells = <2>; 3475 #global-interrupts = <1>; 3476 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3553 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3557 }; 3558 3559 intc: interrupt-controller@17a00000 { 3560 compatible = "arm,gic-v3"; 3561 #address-cells = <2>; 3562 #size-cells = <2>; 3563 ranges; 3564 #interrupt-cells = <3>; 3565 interrupt-controller; 3566 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3567 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3568 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3569 3570 msi-controller@17a40000 { 3571 compatible = "arm,gic-v3-its"; 3572 msi-controller; 3573 #msi-cells = <1>; 3574 reg = <0 0x17a40000 0 0x20000>; 3575 status = "disabled"; 3576 }; 3577 }; 3578 3579 apss_shared: mailbox@17c00000 { 3580 compatible = "qcom,sc7180-apss-shared", 3581 "qcom,sdm845-apss-shared"; 3582 reg = <0 0x17c00000 0 0x10000>; 3583 #mbox-cells = <1>; 3584 }; 3585 3586 watchdog@17c10000 { 3587 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3588 reg = <0 0x17c10000 0 0x1000>; 3589 clocks = <&sleep_clk>; 3590 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3591 }; 3592 3593 timer@17c20000 { 3594 #address-cells = <1>; 3595 #size-cells = <1>; 3596 ranges = <0 0 0 0x20000000>; 3597 compatible = "arm,armv7-timer-mem"; 3598 reg = <0 0x17c20000 0 0x1000>; 3599 3600 frame@17c21000 { 3601 frame-number = <0>; 3602 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3604 reg = <0x17c21000 0x1000>, 3605 <0x17c22000 0x1000>; 3606 }; 3607 3608 frame@17c23000 { 3609 frame-number = <1>; 3610 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3611 reg = <0x17c23000 0x1000>; 3612 status = "disabled"; 3613 }; 3614 3615 frame@17c25000 { 3616 frame-number = <2>; 3617 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3618 reg = <0x17c25000 0x1000>; 3619 status = "disabled"; 3620 }; 3621 3622 frame@17c27000 { 3623 frame-number = <3>; 3624 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3625 reg = <0x17c27000 0x1000>; 3626 status = "disabled"; 3627 }; 3628 3629 frame@17c29000 { 3630 frame-number = <4>; 3631 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3632 reg = <0x17c29000 0x1000>; 3633 status = "disabled"; 3634 }; 3635 3636 frame@17c2b000 { 3637 frame-number = <5>; 3638 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3639 reg = <0x17c2b000 0x1000>; 3640 status = "disabled"; 3641 }; 3642 3643 frame@17c2d000 { 3644 frame-number = <6>; 3645 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3646 reg = <0x17c2d000 0x1000>; 3647 status = "disabled"; 3648 }; 3649 }; 3650 3651 apps_rsc: rsc@18200000 { 3652 compatible = "qcom,rpmh-rsc"; 3653 reg = <0 0x18200000 0 0x10000>, 3654 <0 0x18210000 0 0x10000>, 3655 <0 0x18220000 0 0x10000>; 3656 reg-names = "drv-0", "drv-1", "drv-2"; 3657 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3660 qcom,tcs-offset = <0xd00>; 3661 qcom,drv-id = <2>; 3662 qcom,tcs-config = <ACTIVE_TCS 2>, 3663 <SLEEP_TCS 3>, 3664 <WAKE_TCS 3>, 3665 <CONTROL_TCS 1>; 3666 power-domains = <&CLUSTER_PD>; 3667 3668 rpmhcc: clock-controller { 3669 compatible = "qcom,sc7180-rpmh-clk"; 3670 clocks = <&xo_board>; 3671 clock-names = "xo"; 3672 #clock-cells = <1>; 3673 }; 3674 3675 rpmhpd: power-controller { 3676 compatible = "qcom,sc7180-rpmhpd"; 3677 #power-domain-cells = <1>; 3678 operating-points-v2 = <&rpmhpd_opp_table>; 3679 3680 rpmhpd_opp_table: opp-table { 3681 compatible = "operating-points-v2"; 3682 3683 rpmhpd_opp_ret: opp1 { 3684 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3685 }; 3686 3687 rpmhpd_opp_min_svs: opp2 { 3688 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3689 }; 3690 3691 rpmhpd_opp_low_svs: opp3 { 3692 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3693 }; 3694 3695 rpmhpd_opp_svs: opp4 { 3696 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3697 }; 3698 3699 rpmhpd_opp_svs_l1: opp5 { 3700 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3701 }; 3702 3703 rpmhpd_opp_svs_l2: opp6 { 3704 opp-level = <224>; 3705 }; 3706 3707 rpmhpd_opp_nom: opp7 { 3708 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3709 }; 3710 3711 rpmhpd_opp_nom_l1: opp8 { 3712 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3713 }; 3714 3715 rpmhpd_opp_nom_l2: opp9 { 3716 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3717 }; 3718 3719 rpmhpd_opp_turbo: opp10 { 3720 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3721 }; 3722 3723 rpmhpd_opp_turbo_l1: opp11 { 3724 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3725 }; 3726 }; 3727 }; 3728 3729 apps_bcm_voter: bcm-voter { 3730 compatible = "qcom,bcm-voter"; 3731 }; 3732 }; 3733 3734 osm_l3: interconnect@18321000 { 3735 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3736 reg = <0 0x18321000 0 0x1400>; 3737 3738 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3739 clock-names = "xo", "alternate"; 3740 3741 #interconnect-cells = <1>; 3742 }; 3743 3744 cpufreq_hw: cpufreq@18323000 { 3745 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; 3746 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3747 reg-names = "freq-domain0", "freq-domain1"; 3748 3749 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3750 clock-names = "xo", "alternate"; 3751 3752 #freq-domain-cells = <1>; 3753 #clock-cells = <1>; 3754 }; 3755 3756 wifi: wifi@18800000 { 3757 compatible = "qcom,wcn3990-wifi"; 3758 reg = <0 0x18800000 0 0x800000>; 3759 reg-names = "membase"; 3760 iommus = <&apps_smmu 0xc0 0x1>; 3761 interrupts = 3762 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3763 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3764 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3765 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3766 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3767 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3768 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3769 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3770 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3771 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3772 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3773 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3774 memory-region = <&wlan_mem>; 3775 qcom,msa-fixed-perm; 3776 status = "disabled"; 3777 }; 3778 3779 lpasscc: clock-controller@62d00000 { 3780 compatible = "qcom,sc7180-lpasscorecc"; 3781 reg = <0 0x62d00000 0 0x50000>, 3782 <0 0x62780000 0 0x30000>; 3783 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3784 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3785 <&rpmhcc RPMH_CXO_CLK>; 3786 clock-names = "iface", "bi_tcxo"; 3787 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3788 #clock-cells = <1>; 3789 #power-domain-cells = <1>; 3790 3791 status = "reserved"; /* Controlled by ADSP */ 3792 }; 3793 3794 lpass_cpu: lpass@62d87000 { 3795 compatible = "qcom,sc7180-lpass-cpu"; 3796 3797 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3798 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3799 3800 iommus = <&apps_smmu 0x1020 0>, 3801 <&apps_smmu 0x1021 0>, 3802 <&apps_smmu 0x1032 0>; 3803 3804 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3805 required-opps = <&rpmhpd_opp_nom>; 3806 3807 status = "disabled"; 3808 3809 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3810 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3811 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3812 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3813 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3814 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3815 3816 clock-names = "pcnoc-sway-clk", "audio-core", 3817 "mclk0", "pcnoc-mport-clk", 3818 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3819 3820 3821 #sound-dai-cells = <1>; 3822 #address-cells = <1>; 3823 #size-cells = <0>; 3824 3825 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3827 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3828 }; 3829 3830 lpass_hm: clock-controller@63000000 { 3831 compatible = "qcom,sc7180-lpasshm"; 3832 reg = <0 0x63000000 0 0x28>; 3833 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3834 <&rpmhcc RPMH_CXO_CLK>; 3835 clock-names = "iface", "bi_tcxo"; 3836 power-domains = <&rpmhpd SC7180_CX>; 3837 3838 #clock-cells = <1>; 3839 #power-domain-cells = <1>; 3840 3841 status = "reserved"; /* Controlled by ADSP */ 3842 }; 3843 }; 3844 3845 thermal-zones { 3846 cpu0_thermal: cpu0-thermal { 3847 polling-delay-passive = <250>; 3848 polling-delay = <0>; 3849 3850 thermal-sensors = <&tsens0 1>; 3851 sustainable-power = <1052>; 3852 3853 trips { 3854 cpu0_alert0: trip-point0 { 3855 temperature = <90000>; 3856 hysteresis = <2000>; 3857 type = "passive"; 3858 }; 3859 3860 cpu0_alert1: trip-point1 { 3861 temperature = <95000>; 3862 hysteresis = <2000>; 3863 type = "passive"; 3864 }; 3865 3866 cpu0_crit: cpu-crit { 3867 temperature = <110000>; 3868 hysteresis = <1000>; 3869 type = "critical"; 3870 }; 3871 }; 3872 3873 cooling-maps { 3874 map0 { 3875 trip = <&cpu0_alert0>; 3876 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3877 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3878 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3882 }; 3883 map1 { 3884 trip = <&cpu0_alert1>; 3885 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3886 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3887 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3889 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3890 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3891 }; 3892 }; 3893 }; 3894 3895 cpu1_thermal: cpu1-thermal { 3896 polling-delay-passive = <250>; 3897 polling-delay = <0>; 3898 3899 thermal-sensors = <&tsens0 2>; 3900 sustainable-power = <1052>; 3901 3902 trips { 3903 cpu1_alert0: trip-point0 { 3904 temperature = <90000>; 3905 hysteresis = <2000>; 3906 type = "passive"; 3907 }; 3908 3909 cpu1_alert1: trip-point1 { 3910 temperature = <95000>; 3911 hysteresis = <2000>; 3912 type = "passive"; 3913 }; 3914 3915 cpu1_crit: cpu-crit { 3916 temperature = <110000>; 3917 hysteresis = <1000>; 3918 type = "critical"; 3919 }; 3920 }; 3921 3922 cooling-maps { 3923 map0 { 3924 trip = <&cpu1_alert0>; 3925 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3926 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3927 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3928 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3929 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3931 }; 3932 map1 { 3933 trip = <&cpu1_alert1>; 3934 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3935 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3936 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3940 }; 3941 }; 3942 }; 3943 3944 cpu2_thermal: cpu2-thermal { 3945 polling-delay-passive = <250>; 3946 polling-delay = <0>; 3947 3948 thermal-sensors = <&tsens0 3>; 3949 sustainable-power = <1052>; 3950 3951 trips { 3952 cpu2_alert0: trip-point0 { 3953 temperature = <90000>; 3954 hysteresis = <2000>; 3955 type = "passive"; 3956 }; 3957 3958 cpu2_alert1: trip-point1 { 3959 temperature = <95000>; 3960 hysteresis = <2000>; 3961 type = "passive"; 3962 }; 3963 3964 cpu2_crit: cpu-crit { 3965 temperature = <110000>; 3966 hysteresis = <1000>; 3967 type = "critical"; 3968 }; 3969 }; 3970 3971 cooling-maps { 3972 map0 { 3973 trip = <&cpu2_alert0>; 3974 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3975 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3976 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3977 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3978 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3979 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3980 }; 3981 map1 { 3982 trip = <&cpu2_alert1>; 3983 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3984 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3985 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3986 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3988 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3989 }; 3990 }; 3991 }; 3992 3993 cpu3_thermal: cpu3-thermal { 3994 polling-delay-passive = <250>; 3995 polling-delay = <0>; 3996 3997 thermal-sensors = <&tsens0 4>; 3998 sustainable-power = <1052>; 3999 4000 trips { 4001 cpu3_alert0: trip-point0 { 4002 temperature = <90000>; 4003 hysteresis = <2000>; 4004 type = "passive"; 4005 }; 4006 4007 cpu3_alert1: trip-point1 { 4008 temperature = <95000>; 4009 hysteresis = <2000>; 4010 type = "passive"; 4011 }; 4012 4013 cpu3_crit: cpu-crit { 4014 temperature = <110000>; 4015 hysteresis = <1000>; 4016 type = "critical"; 4017 }; 4018 }; 4019 4020 cooling-maps { 4021 map0 { 4022 trip = <&cpu3_alert0>; 4023 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4024 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4027 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4028 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4029 }; 4030 map1 { 4031 trip = <&cpu3_alert1>; 4032 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4034 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4036 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4037 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4038 }; 4039 }; 4040 }; 4041 4042 cpu4_thermal: cpu4-thermal { 4043 polling-delay-passive = <250>; 4044 polling-delay = <0>; 4045 4046 thermal-sensors = <&tsens0 5>; 4047 sustainable-power = <1052>; 4048 4049 trips { 4050 cpu4_alert0: trip-point0 { 4051 temperature = <90000>; 4052 hysteresis = <2000>; 4053 type = "passive"; 4054 }; 4055 4056 cpu4_alert1: trip-point1 { 4057 temperature = <95000>; 4058 hysteresis = <2000>; 4059 type = "passive"; 4060 }; 4061 4062 cpu4_crit: cpu-crit { 4063 temperature = <110000>; 4064 hysteresis = <1000>; 4065 type = "critical"; 4066 }; 4067 }; 4068 4069 cooling-maps { 4070 map0 { 4071 trip = <&cpu4_alert0>; 4072 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4073 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4074 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4078 }; 4079 map1 { 4080 trip = <&cpu4_alert1>; 4081 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4082 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4083 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4084 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4085 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4086 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4087 }; 4088 }; 4089 }; 4090 4091 cpu5_thermal: cpu5-thermal { 4092 polling-delay-passive = <250>; 4093 polling-delay = <0>; 4094 4095 thermal-sensors = <&tsens0 6>; 4096 sustainable-power = <1052>; 4097 4098 trips { 4099 cpu5_alert0: trip-point0 { 4100 temperature = <90000>; 4101 hysteresis = <2000>; 4102 type = "passive"; 4103 }; 4104 4105 cpu5_alert1: trip-point1 { 4106 temperature = <95000>; 4107 hysteresis = <2000>; 4108 type = "passive"; 4109 }; 4110 4111 cpu5_crit: cpu-crit { 4112 temperature = <110000>; 4113 hysteresis = <1000>; 4114 type = "critical"; 4115 }; 4116 }; 4117 4118 cooling-maps { 4119 map0 { 4120 trip = <&cpu5_alert0>; 4121 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4125 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4126 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4127 }; 4128 map1 { 4129 trip = <&cpu5_alert1>; 4130 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4133 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4134 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4135 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4136 }; 4137 }; 4138 }; 4139 4140 cpu6_thermal: cpu6-thermal { 4141 polling-delay-passive = <250>; 4142 polling-delay = <0>; 4143 4144 thermal-sensors = <&tsens0 9>; 4145 sustainable-power = <1425>; 4146 4147 trips { 4148 cpu6_alert0: trip-point0 { 4149 temperature = <90000>; 4150 hysteresis = <2000>; 4151 type = "passive"; 4152 }; 4153 4154 cpu6_alert1: trip-point1 { 4155 temperature = <95000>; 4156 hysteresis = <2000>; 4157 type = "passive"; 4158 }; 4159 4160 cpu6_crit: cpu-crit { 4161 temperature = <110000>; 4162 hysteresis = <1000>; 4163 type = "critical"; 4164 }; 4165 }; 4166 4167 cooling-maps { 4168 map0 { 4169 trip = <&cpu6_alert0>; 4170 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4171 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4172 }; 4173 map1 { 4174 trip = <&cpu6_alert1>; 4175 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4176 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4177 }; 4178 }; 4179 }; 4180 4181 cpu7_thermal: cpu7-thermal { 4182 polling-delay-passive = <250>; 4183 polling-delay = <0>; 4184 4185 thermal-sensors = <&tsens0 10>; 4186 sustainable-power = <1425>; 4187 4188 trips { 4189 cpu7_alert0: trip-point0 { 4190 temperature = <90000>; 4191 hysteresis = <2000>; 4192 type = "passive"; 4193 }; 4194 4195 cpu7_alert1: trip-point1 { 4196 temperature = <95000>; 4197 hysteresis = <2000>; 4198 type = "passive"; 4199 }; 4200 4201 cpu7_crit: cpu-crit { 4202 temperature = <110000>; 4203 hysteresis = <1000>; 4204 type = "critical"; 4205 }; 4206 }; 4207 4208 cooling-maps { 4209 map0 { 4210 trip = <&cpu7_alert0>; 4211 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4213 }; 4214 map1 { 4215 trip = <&cpu7_alert1>; 4216 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4217 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4218 }; 4219 }; 4220 }; 4221 4222 cpu8_thermal: cpu8-thermal { 4223 polling-delay-passive = <250>; 4224 polling-delay = <0>; 4225 4226 thermal-sensors = <&tsens0 11>; 4227 sustainable-power = <1425>; 4228 4229 trips { 4230 cpu8_alert0: trip-point0 { 4231 temperature = <90000>; 4232 hysteresis = <2000>; 4233 type = "passive"; 4234 }; 4235 4236 cpu8_alert1: trip-point1 { 4237 temperature = <95000>; 4238 hysteresis = <2000>; 4239 type = "passive"; 4240 }; 4241 4242 cpu8_crit: cpu-crit { 4243 temperature = <110000>; 4244 hysteresis = <1000>; 4245 type = "critical"; 4246 }; 4247 }; 4248 4249 cooling-maps { 4250 map0 { 4251 trip = <&cpu8_alert0>; 4252 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4253 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4254 }; 4255 map1 { 4256 trip = <&cpu8_alert1>; 4257 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4258 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4259 }; 4260 }; 4261 }; 4262 4263 cpu9_thermal: cpu9-thermal { 4264 polling-delay-passive = <250>; 4265 polling-delay = <0>; 4266 4267 thermal-sensors = <&tsens0 12>; 4268 sustainable-power = <1425>; 4269 4270 trips { 4271 cpu9_alert0: trip-point0 { 4272 temperature = <90000>; 4273 hysteresis = <2000>; 4274 type = "passive"; 4275 }; 4276 4277 cpu9_alert1: trip-point1 { 4278 temperature = <95000>; 4279 hysteresis = <2000>; 4280 type = "passive"; 4281 }; 4282 4283 cpu9_crit: cpu-crit { 4284 temperature = <110000>; 4285 hysteresis = <1000>; 4286 type = "critical"; 4287 }; 4288 }; 4289 4290 cooling-maps { 4291 map0 { 4292 trip = <&cpu9_alert0>; 4293 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4294 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4295 }; 4296 map1 { 4297 trip = <&cpu9_alert1>; 4298 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4299 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4300 }; 4301 }; 4302 }; 4303 4304 aoss0-thermal { 4305 polling-delay-passive = <250>; 4306 polling-delay = <0>; 4307 4308 thermal-sensors = <&tsens0 0>; 4309 4310 trips { 4311 aoss0_alert0: trip-point0 { 4312 temperature = <90000>; 4313 hysteresis = <2000>; 4314 type = "hot"; 4315 }; 4316 4317 aoss0_crit: aoss0-crit { 4318 temperature = <110000>; 4319 hysteresis = <2000>; 4320 type = "critical"; 4321 }; 4322 }; 4323 }; 4324 4325 cpuss0-thermal { 4326 polling-delay-passive = <250>; 4327 polling-delay = <0>; 4328 4329 thermal-sensors = <&tsens0 7>; 4330 4331 trips { 4332 cpuss0_alert0: trip-point0 { 4333 temperature = <90000>; 4334 hysteresis = <2000>; 4335 type = "hot"; 4336 }; 4337 cpuss0_crit: cluster0-crit { 4338 temperature = <110000>; 4339 hysteresis = <2000>; 4340 type = "critical"; 4341 }; 4342 }; 4343 }; 4344 4345 cpuss1-thermal { 4346 polling-delay-passive = <250>; 4347 polling-delay = <0>; 4348 4349 thermal-sensors = <&tsens0 8>; 4350 4351 trips { 4352 cpuss1_alert0: trip-point0 { 4353 temperature = <90000>; 4354 hysteresis = <2000>; 4355 type = "hot"; 4356 }; 4357 cpuss1_crit: cluster0-crit { 4358 temperature = <110000>; 4359 hysteresis = <2000>; 4360 type = "critical"; 4361 }; 4362 }; 4363 }; 4364 4365 gpuss0-thermal { 4366 polling-delay-passive = <250>; 4367 polling-delay = <0>; 4368 4369 thermal-sensors = <&tsens0 13>; 4370 4371 trips { 4372 gpuss0_alert0: trip-point0 { 4373 temperature = <95000>; 4374 hysteresis = <2000>; 4375 type = "passive"; 4376 }; 4377 4378 gpuss0_crit: gpuss0-crit { 4379 temperature = <110000>; 4380 hysteresis = <2000>; 4381 type = "critical"; 4382 }; 4383 }; 4384 4385 cooling-maps { 4386 map0 { 4387 trip = <&gpuss0_alert0>; 4388 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4389 }; 4390 }; 4391 }; 4392 4393 gpuss1-thermal { 4394 polling-delay-passive = <250>; 4395 polling-delay = <0>; 4396 4397 thermal-sensors = <&tsens0 14>; 4398 4399 trips { 4400 gpuss1_alert0: trip-point0 { 4401 temperature = <95000>; 4402 hysteresis = <2000>; 4403 type = "passive"; 4404 }; 4405 4406 gpuss1_crit: gpuss1-crit { 4407 temperature = <110000>; 4408 hysteresis = <2000>; 4409 type = "critical"; 4410 }; 4411 }; 4412 4413 cooling-maps { 4414 map0 { 4415 trip = <&gpuss1_alert0>; 4416 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4417 }; 4418 }; 4419 }; 4420 4421 aoss1-thermal { 4422 polling-delay-passive = <250>; 4423 polling-delay = <0>; 4424 4425 thermal-sensors = <&tsens1 0>; 4426 4427 trips { 4428 aoss1_alert0: trip-point0 { 4429 temperature = <90000>; 4430 hysteresis = <2000>; 4431 type = "hot"; 4432 }; 4433 4434 aoss1_crit: aoss1-crit { 4435 temperature = <110000>; 4436 hysteresis = <2000>; 4437 type = "critical"; 4438 }; 4439 }; 4440 }; 4441 4442 cwlan-thermal { 4443 polling-delay-passive = <250>; 4444 polling-delay = <0>; 4445 4446 thermal-sensors = <&tsens1 1>; 4447 4448 trips { 4449 cwlan_alert0: trip-point0 { 4450 temperature = <90000>; 4451 hysteresis = <2000>; 4452 type = "hot"; 4453 }; 4454 4455 cwlan_crit: cwlan-crit { 4456 temperature = <110000>; 4457 hysteresis = <2000>; 4458 type = "critical"; 4459 }; 4460 }; 4461 }; 4462 4463 audio-thermal { 4464 polling-delay-passive = <250>; 4465 polling-delay = <0>; 4466 4467 thermal-sensors = <&tsens1 2>; 4468 4469 trips { 4470 audio_alert0: trip-point0 { 4471 temperature = <90000>; 4472 hysteresis = <2000>; 4473 type = "hot"; 4474 }; 4475 4476 audio_crit: audio-crit { 4477 temperature = <110000>; 4478 hysteresis = <2000>; 4479 type = "critical"; 4480 }; 4481 }; 4482 }; 4483 4484 ddr-thermal { 4485 polling-delay-passive = <250>; 4486 polling-delay = <0>; 4487 4488 thermal-sensors = <&tsens1 3>; 4489 4490 trips { 4491 ddr_alert0: trip-point0 { 4492 temperature = <90000>; 4493 hysteresis = <2000>; 4494 type = "hot"; 4495 }; 4496 4497 ddr_crit: ddr-crit { 4498 temperature = <110000>; 4499 hysteresis = <2000>; 4500 type = "critical"; 4501 }; 4502 }; 4503 }; 4504 4505 q6-hvx-thermal { 4506 polling-delay-passive = <250>; 4507 polling-delay = <0>; 4508 4509 thermal-sensors = <&tsens1 4>; 4510 4511 trips { 4512 q6_hvx_alert0: trip-point0 { 4513 temperature = <90000>; 4514 hysteresis = <2000>; 4515 type = "hot"; 4516 }; 4517 4518 q6_hvx_crit: q6-hvx-crit { 4519 temperature = <110000>; 4520 hysteresis = <2000>; 4521 type = "critical"; 4522 }; 4523 }; 4524 }; 4525 4526 camera-thermal { 4527 polling-delay-passive = <250>; 4528 polling-delay = <0>; 4529 4530 thermal-sensors = <&tsens1 5>; 4531 4532 trips { 4533 camera_alert0: trip-point0 { 4534 temperature = <90000>; 4535 hysteresis = <2000>; 4536 type = "hot"; 4537 }; 4538 4539 camera_crit: camera-crit { 4540 temperature = <110000>; 4541 hysteresis = <2000>; 4542 type = "critical"; 4543 }; 4544 }; 4545 }; 4546 4547 mdm-core-thermal { 4548 polling-delay-passive = <250>; 4549 polling-delay = <0>; 4550 4551 thermal-sensors = <&tsens1 6>; 4552 4553 trips { 4554 mdm_alert0: trip-point0 { 4555 temperature = <90000>; 4556 hysteresis = <2000>; 4557 type = "hot"; 4558 }; 4559 4560 mdm_crit: mdm-crit { 4561 temperature = <110000>; 4562 hysteresis = <2000>; 4563 type = "critical"; 4564 }; 4565 }; 4566 }; 4567 4568 mdm-dsp-thermal { 4569 polling-delay-passive = <250>; 4570 polling-delay = <0>; 4571 4572 thermal-sensors = <&tsens1 7>; 4573 4574 trips { 4575 mdm_dsp_alert0: trip-point0 { 4576 temperature = <90000>; 4577 hysteresis = <2000>; 4578 type = "hot"; 4579 }; 4580 4581 mdm_dsp_crit: mdm-dsp-crit { 4582 temperature = <110000>; 4583 hysteresis = <2000>; 4584 type = "critical"; 4585 }; 4586 }; 4587 }; 4588 4589 npu-thermal { 4590 polling-delay-passive = <250>; 4591 polling-delay = <0>; 4592 4593 thermal-sensors = <&tsens1 8>; 4594 4595 trips { 4596 npu_alert0: trip-point0 { 4597 temperature = <90000>; 4598 hysteresis = <2000>; 4599 type = "hot"; 4600 }; 4601 4602 npu_crit: npu-crit { 4603 temperature = <110000>; 4604 hysteresis = <2000>; 4605 type = "critical"; 4606 }; 4607 }; 4608 }; 4609 4610 video-thermal { 4611 polling-delay-passive = <250>; 4612 polling-delay = <0>; 4613 4614 thermal-sensors = <&tsens1 9>; 4615 4616 trips { 4617 video_alert0: trip-point0 { 4618 temperature = <90000>; 4619 hysteresis = <2000>; 4620 type = "hot"; 4621 }; 4622 4623 video_crit: video-crit { 4624 temperature = <110000>; 4625 hysteresis = <2000>; 4626 type = "critical"; 4627 }; 4628 }; 4629 }; 4630 }; 4631 4632 timer { 4633 compatible = "arm,armv8-timer"; 4634 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4635 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4636 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4637 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4638 }; 4639}; 4640