1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 mmc1 = &sdhc_1; 32 mmc2 = &sdhc_2; 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi3 = &spi3; 48 spi5 = &spi5; 49 spi6 = &spi6; 50 spi8 = &spi8; 51 spi10 = &spi10; 52 spi11 = &spi11; 53 }; 54 55 chosen { }; 56 57 clocks { 58 xo_board: xo-board { 59 compatible = "fixed-clock"; 60 clock-frequency = <38400000>; 61 #clock-cells = <0>; 62 }; 63 64 sleep_clk: sleep-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <32764>; 67 #clock-cells = <0>; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <2>; 73 #size-cells = <0>; 74 75 CPU0: cpu@0 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo468"; 78 reg = <0x0 0x0>; 79 clocks = <&cpufreq_hw 0>; 80 enable-method = "psci"; 81 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 82 &LITTLE_CPU_SLEEP_1 83 &CLUSTER_SLEEP_0>; 84 capacity-dmips-mhz = <415>; 85 dynamic-power-coefficient = <137>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 89 next-level-cache = <&L2_0>; 90 #cooling-cells = <2>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 L2_0: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 next-level-cache = <&L3_0>; 96 L3_0: l3-cache { 97 compatible = "cache"; 98 cache-level = <3>; 99 }; 100 }; 101 }; 102 103 CPU1: cpu@100 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo468"; 106 reg = <0x0 0x100>; 107 clocks = <&cpufreq_hw 0>; 108 enable-method = "psci"; 109 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 110 &LITTLE_CPU_SLEEP_1 111 &CLUSTER_SLEEP_0>; 112 capacity-dmips-mhz = <415>; 113 dynamic-power-coefficient = <137>; 114 next-level-cache = <&L2_100>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 117 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 118 #cooling-cells = <2>; 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 L2_100: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU2: cpu@200 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo468"; 130 reg = <0x0 0x200>; 131 clocks = <&cpufreq_hw 0>; 132 enable-method = "psci"; 133 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 134 &LITTLE_CPU_SLEEP_1 135 &CLUSTER_SLEEP_0>; 136 capacity-dmips-mhz = <415>; 137 dynamic-power-coefficient = <137>; 138 next-level-cache = <&L2_200>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 141 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 142 #cooling-cells = <2>; 143 qcom,freq-domain = <&cpufreq_hw 0>; 144 L2_200: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU3: cpu@300 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo468"; 154 reg = <0x0 0x300>; 155 clocks = <&cpufreq_hw 0>; 156 enable-method = "psci"; 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 158 &LITTLE_CPU_SLEEP_1 159 &CLUSTER_SLEEP_0>; 160 capacity-dmips-mhz = <415>; 161 dynamic-power-coefficient = <137>; 162 next-level-cache = <&L2_300>; 163 operating-points-v2 = <&cpu0_opp_table>; 164 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 #cooling-cells = <2>; 167 qcom,freq-domain = <&cpufreq_hw 0>; 168 L2_300: l2-cache { 169 compatible = "cache"; 170 cache-level = <2>; 171 next-level-cache = <&L3_0>; 172 }; 173 }; 174 175 CPU4: cpu@400 { 176 device_type = "cpu"; 177 compatible = "qcom,kryo468"; 178 reg = <0x0 0x400>; 179 clocks = <&cpufreq_hw 0>; 180 enable-method = "psci"; 181 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 182 &LITTLE_CPU_SLEEP_1 183 &CLUSTER_SLEEP_0>; 184 capacity-dmips-mhz = <415>; 185 dynamic-power-coefficient = <137>; 186 next-level-cache = <&L2_400>; 187 operating-points-v2 = <&cpu0_opp_table>; 188 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 189 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 190 #cooling-cells = <2>; 191 qcom,freq-domain = <&cpufreq_hw 0>; 192 L2_400: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 next-level-cache = <&L3_0>; 196 }; 197 }; 198 199 CPU5: cpu@500 { 200 device_type = "cpu"; 201 compatible = "qcom,kryo468"; 202 reg = <0x0 0x500>; 203 clocks = <&cpufreq_hw 0>; 204 enable-method = "psci"; 205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 206 &LITTLE_CPU_SLEEP_1 207 &CLUSTER_SLEEP_0>; 208 capacity-dmips-mhz = <415>; 209 dynamic-power-coefficient = <137>; 210 next-level-cache = <&L2_500>; 211 operating-points-v2 = <&cpu0_opp_table>; 212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 #cooling-cells = <2>; 215 qcom,freq-domain = <&cpufreq_hw 0>; 216 L2_500: l2-cache { 217 compatible = "cache"; 218 cache-level = <2>; 219 next-level-cache = <&L3_0>; 220 }; 221 }; 222 223 CPU6: cpu@600 { 224 device_type = "cpu"; 225 compatible = "qcom,kryo468"; 226 reg = <0x0 0x600>; 227 clocks = <&cpufreq_hw 1>; 228 enable-method = "psci"; 229 cpu-idle-states = <&BIG_CPU_SLEEP_0 230 &BIG_CPU_SLEEP_1 231 &CLUSTER_SLEEP_0>; 232 capacity-dmips-mhz = <1024>; 233 dynamic-power-coefficient = <480>; 234 next-level-cache = <&L2_600>; 235 operating-points-v2 = <&cpu6_opp_table>; 236 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 237 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 238 #cooling-cells = <2>; 239 qcom,freq-domain = <&cpufreq_hw 1>; 240 L2_600: l2-cache { 241 compatible = "cache"; 242 cache-level = <2>; 243 next-level-cache = <&L3_0>; 244 }; 245 }; 246 247 CPU7: cpu@700 { 248 device_type = "cpu"; 249 compatible = "qcom,kryo468"; 250 reg = <0x0 0x700>; 251 clocks = <&cpufreq_hw 1>; 252 enable-method = "psci"; 253 cpu-idle-states = <&BIG_CPU_SLEEP_0 254 &BIG_CPU_SLEEP_1 255 &CLUSTER_SLEEP_0>; 256 capacity-dmips-mhz = <1024>; 257 dynamic-power-coefficient = <480>; 258 next-level-cache = <&L2_700>; 259 operating-points-v2 = <&cpu6_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 262 #cooling-cells = <2>; 263 qcom,freq-domain = <&cpufreq_hw 1>; 264 L2_700: l2-cache { 265 compatible = "cache"; 266 cache-level = <2>; 267 next-level-cache = <&L3_0>; 268 }; 269 }; 270 271 cpu-map { 272 cluster0 { 273 core0 { 274 cpu = <&CPU0>; 275 }; 276 277 core1 { 278 cpu = <&CPU1>; 279 }; 280 281 core2 { 282 cpu = <&CPU2>; 283 }; 284 285 core3 { 286 cpu = <&CPU3>; 287 }; 288 289 core4 { 290 cpu = <&CPU4>; 291 }; 292 293 core5 { 294 cpu = <&CPU5>; 295 }; 296 297 core6 { 298 cpu = <&CPU6>; 299 }; 300 301 core7 { 302 cpu = <&CPU7>; 303 }; 304 }; 305 }; 306 307 idle-states { 308 entry-method = "psci"; 309 310 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 311 compatible = "arm,idle-state"; 312 idle-state-name = "little-power-down"; 313 arm,psci-suspend-param = <0x40000003>; 314 entry-latency-us = <549>; 315 exit-latency-us = <901>; 316 min-residency-us = <1774>; 317 local-timer-stop; 318 }; 319 320 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 321 compatible = "arm,idle-state"; 322 idle-state-name = "little-rail-power-down"; 323 arm,psci-suspend-param = <0x40000004>; 324 entry-latency-us = <702>; 325 exit-latency-us = <915>; 326 min-residency-us = <4001>; 327 local-timer-stop; 328 }; 329 330 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 331 compatible = "arm,idle-state"; 332 idle-state-name = "big-power-down"; 333 arm,psci-suspend-param = <0x40000003>; 334 entry-latency-us = <523>; 335 exit-latency-us = <1244>; 336 min-residency-us = <2207>; 337 local-timer-stop; 338 }; 339 340 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 341 compatible = "arm,idle-state"; 342 idle-state-name = "big-rail-power-down"; 343 arm,psci-suspend-param = <0x40000004>; 344 entry-latency-us = <526>; 345 exit-latency-us = <1854>; 346 min-residency-us = <5555>; 347 local-timer-stop; 348 }; 349 350 CLUSTER_SLEEP_0: cluster-sleep-0 { 351 compatible = "arm,idle-state"; 352 idle-state-name = "cluster-power-down"; 353 arm,psci-suspend-param = <0x40003444>; 354 entry-latency-us = <3263>; 355 exit-latency-us = <6562>; 356 min-residency-us = <9926>; 357 local-timer-stop; 358 }; 359 }; 360 }; 361 362 firmware { 363 scm { 364 compatible = "qcom,scm-sc7180", "qcom,scm"; 365 }; 366 }; 367 368 memory@80000000 { 369 device_type = "memory"; 370 /* We expect the bootloader to fill in the size */ 371 reg = <0 0x80000000 0 0>; 372 }; 373 374 cpu0_opp_table: opp-table-cpu0 { 375 compatible = "operating-points-v2"; 376 opp-shared; 377 378 cpu0_opp1: opp-300000000 { 379 opp-hz = /bits/ 64 <300000000>; 380 opp-peak-kBps = <1200000 4800000>; 381 }; 382 383 cpu0_opp2: opp-576000000 { 384 opp-hz = /bits/ 64 <576000000>; 385 opp-peak-kBps = <1200000 4800000>; 386 }; 387 388 cpu0_opp3: opp-768000000 { 389 opp-hz = /bits/ 64 <768000000>; 390 opp-peak-kBps = <1200000 4800000>; 391 }; 392 393 cpu0_opp4: opp-1017600000 { 394 opp-hz = /bits/ 64 <1017600000>; 395 opp-peak-kBps = <1804000 8908800>; 396 }; 397 398 cpu0_opp5: opp-1248000000 { 399 opp-hz = /bits/ 64 <1248000000>; 400 opp-peak-kBps = <2188000 12902400>; 401 }; 402 403 cpu0_opp6: opp-1324800000 { 404 opp-hz = /bits/ 64 <1324800000>; 405 opp-peak-kBps = <2188000 12902400>; 406 }; 407 408 cpu0_opp7: opp-1516800000 { 409 opp-hz = /bits/ 64 <1516800000>; 410 opp-peak-kBps = <3072000 15052800>; 411 }; 412 413 cpu0_opp8: opp-1612800000 { 414 opp-hz = /bits/ 64 <1612800000>; 415 opp-peak-kBps = <3072000 15052800>; 416 }; 417 418 cpu0_opp9: opp-1708800000 { 419 opp-hz = /bits/ 64 <1708800000>; 420 opp-peak-kBps = <3072000 15052800>; 421 }; 422 423 cpu0_opp10: opp-1804800000 { 424 opp-hz = /bits/ 64 <1804800000>; 425 opp-peak-kBps = <4068000 22425600>; 426 }; 427 }; 428 429 cpu6_opp_table: opp-table-cpu6 { 430 compatible = "operating-points-v2"; 431 opp-shared; 432 433 cpu6_opp1: opp-300000000 { 434 opp-hz = /bits/ 64 <300000000>; 435 opp-peak-kBps = <2188000 8908800>; 436 }; 437 438 cpu6_opp2: opp-652800000 { 439 opp-hz = /bits/ 64 <652800000>; 440 opp-peak-kBps = <2188000 8908800>; 441 }; 442 443 cpu6_opp3: opp-825600000 { 444 opp-hz = /bits/ 64 <825600000>; 445 opp-peak-kBps = <2188000 8908800>; 446 }; 447 448 cpu6_opp4: opp-979200000 { 449 opp-hz = /bits/ 64 <979200000>; 450 opp-peak-kBps = <2188000 8908800>; 451 }; 452 453 cpu6_opp5: opp-1113600000 { 454 opp-hz = /bits/ 64 <1113600000>; 455 opp-peak-kBps = <2188000 8908800>; 456 }; 457 458 cpu6_opp6: opp-1267200000 { 459 opp-hz = /bits/ 64 <1267200000>; 460 opp-peak-kBps = <4068000 12902400>; 461 }; 462 463 cpu6_opp7: opp-1555200000 { 464 opp-hz = /bits/ 64 <1555200000>; 465 opp-peak-kBps = <4068000 15052800>; 466 }; 467 468 cpu6_opp8: opp-1708800000 { 469 opp-hz = /bits/ 64 <1708800000>; 470 opp-peak-kBps = <6220000 19353600>; 471 }; 472 473 cpu6_opp9: opp-1843200000 { 474 opp-hz = /bits/ 64 <1843200000>; 475 opp-peak-kBps = <6220000 19353600>; 476 }; 477 478 cpu6_opp10: opp-1900800000 { 479 opp-hz = /bits/ 64 <1900800000>; 480 opp-peak-kBps = <6220000 22425600>; 481 }; 482 483 cpu6_opp11: opp-1996800000 { 484 opp-hz = /bits/ 64 <1996800000>; 485 opp-peak-kBps = <6220000 22425600>; 486 }; 487 488 cpu6_opp12: opp-2112000000 { 489 opp-hz = /bits/ 64 <2112000000>; 490 opp-peak-kBps = <6220000 22425600>; 491 }; 492 493 cpu6_opp13: opp-2208000000 { 494 opp-hz = /bits/ 64 <2208000000>; 495 opp-peak-kBps = <7216000 22425600>; 496 }; 497 498 cpu6_opp14: opp-2323200000 { 499 opp-hz = /bits/ 64 <2323200000>; 500 opp-peak-kBps = <7216000 22425600>; 501 }; 502 503 cpu6_opp15: opp-2400000000 { 504 opp-hz = /bits/ 64 <2400000000>; 505 opp-peak-kBps = <8532000 23347200>; 506 }; 507 508 cpu6_opp16: opp-2553600000 { 509 opp-hz = /bits/ 64 <2553600000>; 510 opp-peak-kBps = <8532000 23347200>; 511 }; 512 }; 513 514 qspi_opp_table: opp-table-qspi { 515 compatible = "operating-points-v2"; 516 517 opp-75000000 { 518 opp-hz = /bits/ 64 <75000000>; 519 required-opps = <&rpmhpd_opp_low_svs>; 520 }; 521 522 opp-150000000 { 523 opp-hz = /bits/ 64 <150000000>; 524 required-opps = <&rpmhpd_opp_svs>; 525 }; 526 527 opp-300000000 { 528 opp-hz = /bits/ 64 <300000000>; 529 required-opps = <&rpmhpd_opp_nom>; 530 }; 531 }; 532 533 qup_opp_table: opp-table-qup { 534 compatible = "operating-points-v2"; 535 536 opp-75000000 { 537 opp-hz = /bits/ 64 <75000000>; 538 required-opps = <&rpmhpd_opp_low_svs>; 539 }; 540 541 opp-100000000 { 542 opp-hz = /bits/ 64 <100000000>; 543 required-opps = <&rpmhpd_opp_svs>; 544 }; 545 546 opp-128000000 { 547 opp-hz = /bits/ 64 <128000000>; 548 required-opps = <&rpmhpd_opp_nom>; 549 }; 550 }; 551 552 pmu { 553 compatible = "arm,armv8-pmuv3"; 554 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 555 }; 556 557 psci { 558 compatible = "arm,psci-1.0"; 559 method = "smc"; 560 }; 561 562 reserved_memory: reserved-memory { 563 #address-cells = <2>; 564 #size-cells = <2>; 565 ranges; 566 567 hyp_mem: memory@80000000 { 568 reg = <0x0 0x80000000 0x0 0x600000>; 569 no-map; 570 }; 571 572 xbl_mem: memory@80600000 { 573 reg = <0x0 0x80600000 0x0 0x200000>; 574 no-map; 575 }; 576 577 aop_mem: memory@80800000 { 578 reg = <0x0 0x80800000 0x0 0x20000>; 579 no-map; 580 }; 581 582 aop_cmd_db_mem: memory@80820000 { 583 reg = <0x0 0x80820000 0x0 0x20000>; 584 compatible = "qcom,cmd-db"; 585 no-map; 586 }; 587 588 sec_apps_mem: memory@808ff000 { 589 reg = <0x0 0x808ff000 0x0 0x1000>; 590 no-map; 591 }; 592 593 smem_mem: memory@80900000 { 594 reg = <0x0 0x80900000 0x0 0x200000>; 595 no-map; 596 }; 597 598 tz_mem: memory@80b00000 { 599 reg = <0x0 0x80b00000 0x0 0x3900000>; 600 no-map; 601 }; 602 603 ipa_fw_mem: memory@8b700000 { 604 reg = <0 0x8b700000 0 0x10000>; 605 no-map; 606 }; 607 608 rmtfs_mem: memory@94600000 { 609 compatible = "qcom,rmtfs-mem"; 610 reg = <0x0 0x94600000 0x0 0x200000>; 611 no-map; 612 613 qcom,client-id = <1>; 614 qcom,vmid = <15>; 615 }; 616 }; 617 618 smem { 619 compatible = "qcom,smem"; 620 memory-region = <&smem_mem>; 621 hwlocks = <&tcsr_mutex 3>; 622 }; 623 624 smp2p-cdsp { 625 compatible = "qcom,smp2p"; 626 qcom,smem = <94>, <432>; 627 628 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 629 630 mboxes = <&apss_shared 6>; 631 632 qcom,local-pid = <0>; 633 qcom,remote-pid = <5>; 634 635 cdsp_smp2p_out: master-kernel { 636 qcom,entry-name = "master-kernel"; 637 #qcom,smem-state-cells = <1>; 638 }; 639 640 cdsp_smp2p_in: slave-kernel { 641 qcom,entry-name = "slave-kernel"; 642 643 interrupt-controller; 644 #interrupt-cells = <2>; 645 }; 646 }; 647 648 smp2p-lpass { 649 compatible = "qcom,smp2p"; 650 qcom,smem = <443>, <429>; 651 652 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 653 654 mboxes = <&apss_shared 10>; 655 656 qcom,local-pid = <0>; 657 qcom,remote-pid = <2>; 658 659 adsp_smp2p_out: master-kernel { 660 qcom,entry-name = "master-kernel"; 661 #qcom,smem-state-cells = <1>; 662 }; 663 664 adsp_smp2p_in: slave-kernel { 665 qcom,entry-name = "slave-kernel"; 666 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 }; 670 }; 671 672 smp2p-mpss { 673 compatible = "qcom,smp2p"; 674 qcom,smem = <435>, <428>; 675 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 676 mboxes = <&apss_shared 14>; 677 qcom,local-pid = <0>; 678 qcom,remote-pid = <1>; 679 680 modem_smp2p_out: master-kernel { 681 qcom,entry-name = "master-kernel"; 682 #qcom,smem-state-cells = <1>; 683 }; 684 685 modem_smp2p_in: slave-kernel { 686 qcom,entry-name = "slave-kernel"; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 }; 690 691 ipa_smp2p_out: ipa-ap-to-modem { 692 qcom,entry-name = "ipa"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 ipa_smp2p_in: ipa-modem-to-ap { 697 qcom,entry-name = "ipa"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 }; 702 703 soc: soc@0 { 704 #address-cells = <2>; 705 #size-cells = <2>; 706 ranges = <0 0 0 0 0x10 0>; 707 dma-ranges = <0 0 0 0 0x10 0>; 708 compatible = "simple-bus"; 709 710 gcc: clock-controller@100000 { 711 compatible = "qcom,gcc-sc7180"; 712 reg = <0 0x00100000 0 0x1f0000>; 713 clocks = <&rpmhcc RPMH_CXO_CLK>, 714 <&rpmhcc RPMH_CXO_CLK_A>, 715 <&sleep_clk>; 716 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 717 #clock-cells = <1>; 718 #reset-cells = <1>; 719 #power-domain-cells = <1>; 720 power-domains = <&rpmhpd SC7180_CX>; 721 }; 722 723 qfprom: efuse@784000 { 724 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 725 reg = <0 0x00784000 0 0x7a0>, 726 <0 0x00780000 0 0x7a0>, 727 <0 0x00782000 0 0x100>, 728 <0 0x00786000 0 0x1fff>; 729 730 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 731 clock-names = "core"; 732 #address-cells = <1>; 733 #size-cells = <1>; 734 735 qusb2p_hstx_trim: hstx-trim-primary@25b { 736 reg = <0x25b 0x1>; 737 bits = <1 3>; 738 }; 739 740 gpu_speed_bin: gpu_speed_bin@1d2 { 741 reg = <0x1d2 0x2>; 742 bits = <5 8>; 743 }; 744 }; 745 746 sdhc_1: mmc@7c4000 { 747 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 748 reg = <0 0x007c4000 0 0x1000>, 749 <0 0x007c5000 0 0x1000>; 750 reg-names = "hc", "cqhci"; 751 752 iommus = <&apps_smmu 0x60 0x0>; 753 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 755 interrupt-names = "hc_irq", "pwr_irq"; 756 757 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 758 <&gcc GCC_SDCC1_APPS_CLK>, 759 <&rpmhcc RPMH_CXO_CLK>; 760 clock-names = "iface", "core", "xo"; 761 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 762 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 763 interconnect-names = "sdhc-ddr","cpu-sdhc"; 764 power-domains = <&rpmhpd SC7180_CX>; 765 operating-points-v2 = <&sdhc1_opp_table>; 766 767 bus-width = <8>; 768 non-removable; 769 supports-cqe; 770 771 mmc-ddr-1_8v; 772 mmc-hs200-1_8v; 773 mmc-hs400-1_8v; 774 mmc-hs400-enhanced-strobe; 775 776 status = "disabled"; 777 778 sdhc1_opp_table: opp-table { 779 compatible = "operating-points-v2"; 780 781 opp-100000000 { 782 opp-hz = /bits/ 64 <100000000>; 783 required-opps = <&rpmhpd_opp_low_svs>; 784 opp-peak-kBps = <1800000 600000>; 785 opp-avg-kBps = <100000 0>; 786 }; 787 788 opp-384000000 { 789 opp-hz = /bits/ 64 <384000000>; 790 required-opps = <&rpmhpd_opp_nom>; 791 opp-peak-kBps = <5400000 1600000>; 792 opp-avg-kBps = <390000 0>; 793 }; 794 }; 795 }; 796 797 qupv3_id_0: geniqup@8c0000 { 798 compatible = "qcom,geni-se-qup"; 799 reg = <0 0x008c0000 0 0x6000>; 800 clock-names = "m-ahb", "s-ahb"; 801 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 802 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 803 #address-cells = <2>; 804 #size-cells = <2>; 805 ranges; 806 iommus = <&apps_smmu 0x43 0x0>; 807 status = "disabled"; 808 809 i2c0: i2c@880000 { 810 compatible = "qcom,geni-i2c"; 811 reg = <0 0x00880000 0 0x4000>; 812 clock-names = "se"; 813 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 814 pinctrl-names = "default"; 815 pinctrl-0 = <&qup_i2c0_default>; 816 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 820 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 821 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 822 interconnect-names = "qup-core", "qup-config", 823 "qup-memory"; 824 power-domains = <&rpmhpd SC7180_CX>; 825 required-opps = <&rpmhpd_opp_low_svs>; 826 status = "disabled"; 827 }; 828 829 spi0: spi@880000 { 830 compatible = "qcom,geni-spi"; 831 reg = <0 0x00880000 0 0x4000>; 832 clock-names = "se"; 833 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 836 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 power-domains = <&rpmhpd SC7180_CX>; 840 operating-points-v2 = <&qup_opp_table>; 841 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 842 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 843 interconnect-names = "qup-core", "qup-config"; 844 status = "disabled"; 845 }; 846 847 uart0: serial@880000 { 848 compatible = "qcom,geni-uart"; 849 reg = <0 0x00880000 0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&qup_uart0_default>; 854 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 855 power-domains = <&rpmhpd SC7180_CX>; 856 operating-points-v2 = <&qup_opp_table>; 857 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 858 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 859 interconnect-names = "qup-core", "qup-config"; 860 status = "disabled"; 861 }; 862 863 i2c1: i2c@884000 { 864 compatible = "qcom,geni-i2c"; 865 reg = <0 0x00884000 0 0x4000>; 866 clock-names = "se"; 867 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&qup_i2c1_default>; 870 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 874 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 875 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 876 interconnect-names = "qup-core", "qup-config", 877 "qup-memory"; 878 power-domains = <&rpmhpd SC7180_CX>; 879 required-opps = <&rpmhpd_opp_low_svs>; 880 status = "disabled"; 881 }; 882 883 spi1: spi@884000 { 884 compatible = "qcom,geni-spi"; 885 reg = <0 0x00884000 0 0x4000>; 886 clock-names = "se"; 887 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 890 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 power-domains = <&rpmhpd SC7180_CX>; 894 operating-points-v2 = <&qup_opp_table>; 895 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 897 interconnect-names = "qup-core", "qup-config"; 898 status = "disabled"; 899 }; 900 901 uart1: serial@884000 { 902 compatible = "qcom,geni-uart"; 903 reg = <0 0x00884000 0 0x4000>; 904 clock-names = "se"; 905 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_uart1_default>; 908 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 909 power-domains = <&rpmhpd SC7180_CX>; 910 operating-points-v2 = <&qup_opp_table>; 911 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 913 interconnect-names = "qup-core", "qup-config"; 914 status = "disabled"; 915 }; 916 917 i2c2: i2c@888000 { 918 compatible = "qcom,geni-i2c"; 919 reg = <0 0x00888000 0 0x4000>; 920 clock-names = "se"; 921 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&qup_i2c2_default>; 924 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 928 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 929 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 930 interconnect-names = "qup-core", "qup-config", 931 "qup-memory"; 932 power-domains = <&rpmhpd SC7180_CX>; 933 required-opps = <&rpmhpd_opp_low_svs>; 934 status = "disabled"; 935 }; 936 937 uart2: serial@888000 { 938 compatible = "qcom,geni-uart"; 939 reg = <0 0x00888000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_uart2_default>; 944 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 945 power-domains = <&rpmhpd SC7180_CX>; 946 operating-points-v2 = <&qup_opp_table>; 947 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 948 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 949 interconnect-names = "qup-core", "qup-config"; 950 status = "disabled"; 951 }; 952 953 i2c3: i2c@88c000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0 0x0088c000 0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_i2c3_default>; 960 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 964 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 965 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", 967 "qup-memory"; 968 power-domains = <&rpmhpd SC7180_CX>; 969 required-opps = <&rpmhpd_opp_low_svs>; 970 status = "disabled"; 971 }; 972 973 spi3: spi@88c000 { 974 compatible = "qcom,geni-spi"; 975 reg = <0 0x0088c000 0 0x4000>; 976 clock-names = "se"; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 980 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 power-domains = <&rpmhpd SC7180_CX>; 984 operating-points-v2 = <&qup_opp_table>; 985 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 986 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 987 interconnect-names = "qup-core", "qup-config"; 988 status = "disabled"; 989 }; 990 991 uart3: serial@88c000 { 992 compatible = "qcom,geni-uart"; 993 reg = <0 0x0088c000 0 0x4000>; 994 clock-names = "se"; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&qup_uart3_default>; 998 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 999 power-domains = <&rpmhpd SC7180_CX>; 1000 operating-points-v2 = <&qup_opp_table>; 1001 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1003 interconnect-names = "qup-core", "qup-config"; 1004 status = "disabled"; 1005 }; 1006 1007 i2c4: i2c@890000 { 1008 compatible = "qcom,geni-i2c"; 1009 reg = <0 0x00890000 0 0x4000>; 1010 clock-names = "se"; 1011 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&qup_i2c4_default>; 1014 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1018 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1019 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1020 interconnect-names = "qup-core", "qup-config", 1021 "qup-memory"; 1022 power-domains = <&rpmhpd SC7180_CX>; 1023 required-opps = <&rpmhpd_opp_low_svs>; 1024 status = "disabled"; 1025 }; 1026 1027 uart4: serial@890000 { 1028 compatible = "qcom,geni-uart"; 1029 reg = <0 0x00890000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_uart4_default>; 1034 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1035 power-domains = <&rpmhpd SC7180_CX>; 1036 operating-points-v2 = <&qup_opp_table>; 1037 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1038 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1039 interconnect-names = "qup-core", "qup-config"; 1040 status = "disabled"; 1041 }; 1042 1043 i2c5: i2c@894000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0 0x00894000 0 0x4000>; 1046 clock-names = "se"; 1047 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1048 pinctrl-names = "default"; 1049 pinctrl-0 = <&qup_i2c5_default>; 1050 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1055 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1056 interconnect-names = "qup-core", "qup-config", 1057 "qup-memory"; 1058 power-domains = <&rpmhpd SC7180_CX>; 1059 required-opps = <&rpmhpd_opp_low_svs>; 1060 status = "disabled"; 1061 }; 1062 1063 spi5: spi@894000 { 1064 compatible = "qcom,geni-spi"; 1065 reg = <0 0x00894000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1070 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 power-domains = <&rpmhpd SC7180_CX>; 1074 operating-points-v2 = <&qup_opp_table>; 1075 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1076 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1077 interconnect-names = "qup-core", "qup-config"; 1078 status = "disabled"; 1079 }; 1080 1081 uart5: serial@894000 { 1082 compatible = "qcom,geni-uart"; 1083 reg = <0 0x00894000 0 0x4000>; 1084 clock-names = "se"; 1085 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1086 pinctrl-names = "default"; 1087 pinctrl-0 = <&qup_uart5_default>; 1088 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1089 power-domains = <&rpmhpd SC7180_CX>; 1090 operating-points-v2 = <&qup_opp_table>; 1091 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1093 interconnect-names = "qup-core", "qup-config"; 1094 status = "disabled"; 1095 }; 1096 }; 1097 1098 qupv3_id_1: geniqup@ac0000 { 1099 compatible = "qcom,geni-se-qup"; 1100 reg = <0 0x00ac0000 0 0x6000>; 1101 clock-names = "m-ahb", "s-ahb"; 1102 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1103 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1104 #address-cells = <2>; 1105 #size-cells = <2>; 1106 ranges; 1107 iommus = <&apps_smmu 0x4c3 0x0>; 1108 status = "disabled"; 1109 1110 i2c6: i2c@a80000 { 1111 compatible = "qcom,geni-i2c"; 1112 reg = <0 0x00a80000 0 0x4000>; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_i2c6_default>; 1117 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1121 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1122 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1123 interconnect-names = "qup-core", "qup-config", 1124 "qup-memory"; 1125 power-domains = <&rpmhpd SC7180_CX>; 1126 required-opps = <&rpmhpd_opp_low_svs>; 1127 status = "disabled"; 1128 }; 1129 1130 spi6: spi@a80000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00a80000 0 0x4000>; 1133 clock-names = "se"; 1134 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1137 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 power-domains = <&rpmhpd SC7180_CX>; 1141 operating-points-v2 = <&qup_opp_table>; 1142 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1143 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1144 interconnect-names = "qup-core", "qup-config"; 1145 status = "disabled"; 1146 }; 1147 1148 uart6: serial@a80000 { 1149 compatible = "qcom,geni-uart"; 1150 reg = <0 0x00a80000 0 0x4000>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_uart6_default>; 1155 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1156 power-domains = <&rpmhpd SC7180_CX>; 1157 operating-points-v2 = <&qup_opp_table>; 1158 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1159 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1160 interconnect-names = "qup-core", "qup-config"; 1161 status = "disabled"; 1162 }; 1163 1164 i2c7: i2c@a84000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00a84000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c7_default>; 1171 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1175 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1176 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1177 interconnect-names = "qup-core", "qup-config", 1178 "qup-memory"; 1179 power-domains = <&rpmhpd SC7180_CX>; 1180 required-opps = <&rpmhpd_opp_low_svs>; 1181 status = "disabled"; 1182 }; 1183 1184 uart7: serial@a84000 { 1185 compatible = "qcom,geni-uart"; 1186 reg = <0 0x00a84000 0 0x4000>; 1187 clock-names = "se"; 1188 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_uart7_default>; 1191 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1192 power-domains = <&rpmhpd SC7180_CX>; 1193 operating-points-v2 = <&qup_opp_table>; 1194 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1196 interconnect-names = "qup-core", "qup-config"; 1197 status = "disabled"; 1198 }; 1199 1200 i2c8: i2c@a88000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0 0x00a88000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_i2c8_default>; 1207 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1212 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1213 interconnect-names = "qup-core", "qup-config", 1214 "qup-memory"; 1215 power-domains = <&rpmhpd SC7180_CX>; 1216 required-opps = <&rpmhpd_opp_low_svs>; 1217 status = "disabled"; 1218 }; 1219 1220 spi8: spi@a88000 { 1221 compatible = "qcom,geni-spi"; 1222 reg = <0 0x00a88000 0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1227 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 power-domains = <&rpmhpd SC7180_CX>; 1231 operating-points-v2 = <&qup_opp_table>; 1232 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1233 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1234 interconnect-names = "qup-core", "qup-config"; 1235 status = "disabled"; 1236 }; 1237 1238 uart8: serial@a88000 { 1239 compatible = "qcom,geni-debug-uart"; 1240 reg = <0 0x00a88000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_uart8_default>; 1245 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1246 power-domains = <&rpmhpd SC7180_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1249 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1250 interconnect-names = "qup-core", "qup-config"; 1251 status = "disabled"; 1252 }; 1253 1254 i2c9: i2c@a8c000 { 1255 compatible = "qcom,geni-i2c"; 1256 reg = <0 0x00a8c000 0 0x4000>; 1257 clock-names = "se"; 1258 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&qup_i2c9_default>; 1261 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1265 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1266 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1267 interconnect-names = "qup-core", "qup-config", 1268 "qup-memory"; 1269 power-domains = <&rpmhpd SC7180_CX>; 1270 required-opps = <&rpmhpd_opp_low_svs>; 1271 status = "disabled"; 1272 }; 1273 1274 uart9: serial@a8c000 { 1275 compatible = "qcom,geni-uart"; 1276 reg = <0 0x00a8c000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_uart9_default>; 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd SC7180_CX>; 1283 operating-points-v2 = <&qup_opp_table>; 1284 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1285 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1286 interconnect-names = "qup-core", "qup-config"; 1287 status = "disabled"; 1288 }; 1289 1290 i2c10: i2c@a90000 { 1291 compatible = "qcom,geni-i2c"; 1292 reg = <0 0x00a90000 0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&qup_i2c10_default>; 1297 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1301 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1302 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1303 interconnect-names = "qup-core", "qup-config", 1304 "qup-memory"; 1305 power-domains = <&rpmhpd SC7180_CX>; 1306 required-opps = <&rpmhpd_opp_low_svs>; 1307 status = "disabled"; 1308 }; 1309 1310 spi10: spi@a90000 { 1311 compatible = "qcom,geni-spi"; 1312 reg = <0 0x00a90000 0 0x4000>; 1313 clock-names = "se"; 1314 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1317 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 power-domains = <&rpmhpd SC7180_CX>; 1321 operating-points-v2 = <&qup_opp_table>; 1322 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1323 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1324 interconnect-names = "qup-core", "qup-config"; 1325 status = "disabled"; 1326 }; 1327 1328 uart10: serial@a90000 { 1329 compatible = "qcom,geni-uart"; 1330 reg = <0 0x00a90000 0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_uart10_default>; 1335 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1336 power-domains = <&rpmhpd SC7180_CX>; 1337 operating-points-v2 = <&qup_opp_table>; 1338 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1339 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 status = "disabled"; 1342 }; 1343 1344 i2c11: i2c@a94000 { 1345 compatible = "qcom,geni-i2c"; 1346 reg = <0 0x00a94000 0 0x4000>; 1347 clock-names = "se"; 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_i2c11_default>; 1351 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1355 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1356 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1357 interconnect-names = "qup-core", "qup-config", 1358 "qup-memory"; 1359 power-domains = <&rpmhpd SC7180_CX>; 1360 required-opps = <&rpmhpd_opp_low_svs>; 1361 status = "disabled"; 1362 }; 1363 1364 spi11: spi@a94000 { 1365 compatible = "qcom,geni-spi"; 1366 reg = <0 0x00a94000 0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1371 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 power-domains = <&rpmhpd SC7180_CX>; 1375 operating-points-v2 = <&qup_opp_table>; 1376 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1377 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1378 interconnect-names = "qup-core", "qup-config"; 1379 status = "disabled"; 1380 }; 1381 1382 uart11: serial@a94000 { 1383 compatible = "qcom,geni-uart"; 1384 reg = <0 0x00a94000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_uart11_default>; 1389 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1390 power-domains = <&rpmhpd SC7180_CX>; 1391 operating-points-v2 = <&qup_opp_table>; 1392 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1393 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1394 interconnect-names = "qup-core", "qup-config"; 1395 status = "disabled"; 1396 }; 1397 }; 1398 1399 config_noc: interconnect@1500000 { 1400 compatible = "qcom,sc7180-config-noc"; 1401 reg = <0 0x01500000 0 0x28000>; 1402 #interconnect-cells = <2>; 1403 qcom,bcm-voters = <&apps_bcm_voter>; 1404 }; 1405 1406 system_noc: interconnect@1620000 { 1407 compatible = "qcom,sc7180-system-noc"; 1408 reg = <0 0x01620000 0 0x17080>; 1409 #interconnect-cells = <2>; 1410 qcom,bcm-voters = <&apps_bcm_voter>; 1411 }; 1412 1413 mc_virt: interconnect@1638000 { 1414 compatible = "qcom,sc7180-mc-virt"; 1415 reg = <0 0x01638000 0 0x1000>; 1416 #interconnect-cells = <2>; 1417 qcom,bcm-voters = <&apps_bcm_voter>; 1418 }; 1419 1420 qup_virt: interconnect@1650000 { 1421 compatible = "qcom,sc7180-qup-virt"; 1422 reg = <0 0x01650000 0 0x1000>; 1423 #interconnect-cells = <2>; 1424 qcom,bcm-voters = <&apps_bcm_voter>; 1425 }; 1426 1427 aggre1_noc: interconnect@16e0000 { 1428 compatible = "qcom,sc7180-aggre1-noc"; 1429 reg = <0 0x016e0000 0 0x15080>; 1430 #interconnect-cells = <2>; 1431 qcom,bcm-voters = <&apps_bcm_voter>; 1432 }; 1433 1434 aggre2_noc: interconnect@1705000 { 1435 compatible = "qcom,sc7180-aggre2-noc"; 1436 reg = <0 0x01705000 0 0x9000>; 1437 #interconnect-cells = <2>; 1438 qcom,bcm-voters = <&apps_bcm_voter>; 1439 }; 1440 1441 compute_noc: interconnect@170e000 { 1442 compatible = "qcom,sc7180-compute-noc"; 1443 reg = <0 0x0170e000 0 0x6000>; 1444 #interconnect-cells = <2>; 1445 qcom,bcm-voters = <&apps_bcm_voter>; 1446 }; 1447 1448 mmss_noc: interconnect@1740000 { 1449 compatible = "qcom,sc7180-mmss-noc"; 1450 reg = <0 0x01740000 0 0x1c100>; 1451 #interconnect-cells = <2>; 1452 qcom,bcm-voters = <&apps_bcm_voter>; 1453 }; 1454 1455 ipa: ipa@1e40000 { 1456 compatible = "qcom,sc7180-ipa"; 1457 1458 iommus = <&apps_smmu 0x440 0x0>, 1459 <&apps_smmu 0x442 0x0>; 1460 reg = <0 0x01e40000 0 0x7000>, 1461 <0 0x01e47000 0 0x2000>, 1462 <0 0x01e04000 0 0x2c000>; 1463 reg-names = "ipa-reg", 1464 "ipa-shared", 1465 "gsi"; 1466 1467 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1468 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1469 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1470 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1471 interrupt-names = "ipa", 1472 "gsi", 1473 "ipa-clock-query", 1474 "ipa-setup-ready"; 1475 1476 clocks = <&rpmhcc RPMH_IPA_CLK>; 1477 clock-names = "core"; 1478 1479 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1480 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1481 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1482 interconnect-names = "memory", 1483 "imem", 1484 "config"; 1485 1486 qcom,qmp = <&aoss_qmp>; 1487 1488 qcom,smem-states = <&ipa_smp2p_out 0>, 1489 <&ipa_smp2p_out 1>; 1490 qcom,smem-state-names = "ipa-clock-enabled-valid", 1491 "ipa-clock-enabled"; 1492 1493 status = "disabled"; 1494 }; 1495 1496 tcsr_mutex: hwlock@1f40000 { 1497 compatible = "qcom,tcsr-mutex"; 1498 reg = <0 0x01f40000 0 0x20000>; 1499 #hwlock-cells = <1>; 1500 }; 1501 1502 tcsr_regs_1: syscon@1f60000 { 1503 compatible = "qcom,sc7180-tcsr", "syscon"; 1504 reg = <0 0x01f60000 0 0x20000>; 1505 }; 1506 1507 tcsr_regs_2: syscon@1fc0000 { 1508 compatible = "qcom,sc7180-tcsr", "syscon"; 1509 reg = <0 0x01fc0000 0 0x40000>; 1510 }; 1511 1512 tlmm: pinctrl@3500000 { 1513 compatible = "qcom,sc7180-pinctrl"; 1514 reg = <0 0x03500000 0 0x300000>, 1515 <0 0x03900000 0 0x300000>, 1516 <0 0x03d00000 0 0x300000>; 1517 reg-names = "west", "north", "south"; 1518 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1519 gpio-controller; 1520 #gpio-cells = <2>; 1521 interrupt-controller; 1522 #interrupt-cells = <2>; 1523 gpio-ranges = <&tlmm 0 0 120>; 1524 wakeup-parent = <&pdc>; 1525 1526 dp_hot_plug_det: dp-hot-plug-det-state { 1527 pins = "gpio117"; 1528 function = "dp_hot"; 1529 }; 1530 1531 qspi_clk: qspi-clk-state { 1532 pins = "gpio63"; 1533 function = "qspi_clk"; 1534 }; 1535 1536 qspi_cs0: qspi-cs0-state { 1537 pins = "gpio68"; 1538 function = "qspi_cs"; 1539 }; 1540 1541 qspi_cs1: qspi-cs1-state { 1542 pins = "gpio72"; 1543 function = "qspi_cs"; 1544 }; 1545 1546 qspi_data0: qspi-data0-state { 1547 pins = "gpio64"; 1548 function = "qspi_data"; 1549 }; 1550 1551 qspi_data1: qspi-data1-state { 1552 pins = "gpio65"; 1553 function = "qspi_data"; 1554 }; 1555 1556 qspi_data23: qspi-data23-state { 1557 pins = "gpio66", "gpio67"; 1558 function = "qspi_data"; 1559 }; 1560 1561 qup_i2c0_default: qup-i2c0-default-state { 1562 pins = "gpio34", "gpio35"; 1563 function = "qup00"; 1564 }; 1565 1566 qup_i2c1_default: qup-i2c1-default-state { 1567 pins = "gpio0", "gpio1"; 1568 function = "qup01"; 1569 }; 1570 1571 qup_i2c2_default: qup-i2c2-default-state { 1572 pins = "gpio15", "gpio16"; 1573 function = "qup02_i2c"; 1574 }; 1575 1576 qup_i2c3_default: qup-i2c3-default-state { 1577 pins = "gpio38", "gpio39"; 1578 function = "qup03"; 1579 }; 1580 1581 qup_i2c4_default: qup-i2c4-default-state { 1582 pins = "gpio115", "gpio116"; 1583 function = "qup04_i2c"; 1584 }; 1585 1586 qup_i2c5_default: qup-i2c5-default-state { 1587 pins = "gpio25", "gpio26"; 1588 function = "qup05"; 1589 }; 1590 1591 qup_i2c6_default: qup-i2c6-default-state { 1592 pins = "gpio59", "gpio60"; 1593 function = "qup10"; 1594 }; 1595 1596 qup_i2c7_default: qup-i2c7-default-state { 1597 pins = "gpio6", "gpio7"; 1598 function = "qup11_i2c"; 1599 }; 1600 1601 qup_i2c8_default: qup-i2c8-default-state { 1602 pins = "gpio42", "gpio43"; 1603 function = "qup12"; 1604 }; 1605 1606 qup_i2c9_default: qup-i2c9-default-state { 1607 pins = "gpio46", "gpio47"; 1608 function = "qup13_i2c"; 1609 }; 1610 1611 qup_i2c10_default: qup-i2c10-default-state { 1612 pins = "gpio86", "gpio87"; 1613 function = "qup14"; 1614 }; 1615 1616 qup_i2c11_default: qup-i2c11-default-state { 1617 pins = "gpio53", "gpio54"; 1618 function = "qup15"; 1619 }; 1620 1621 qup_spi0_spi: qup-spi0-spi-state { 1622 pins = "gpio34", "gpio35", "gpio36"; 1623 function = "qup00"; 1624 }; 1625 1626 qup_spi0_cs: qup-spi0-cs-state { 1627 pins = "gpio37"; 1628 function = "qup00"; 1629 }; 1630 1631 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1632 pins = "gpio37"; 1633 function = "gpio"; 1634 }; 1635 1636 qup_spi1_spi: qup-spi1-spi-state { 1637 pins = "gpio0", "gpio1", "gpio2"; 1638 function = "qup01"; 1639 }; 1640 1641 qup_spi1_cs: qup-spi1-cs-state { 1642 pins = "gpio3"; 1643 function = "qup01"; 1644 }; 1645 1646 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1647 pins = "gpio3"; 1648 function = "gpio"; 1649 }; 1650 1651 qup_spi3_spi: qup-spi3-spi-state { 1652 pins = "gpio38", "gpio39", "gpio40"; 1653 function = "qup03"; 1654 }; 1655 1656 qup_spi3_cs: qup-spi3-cs-state { 1657 pins = "gpio41"; 1658 function = "qup03"; 1659 }; 1660 1661 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1662 pins = "gpio41"; 1663 function = "gpio"; 1664 }; 1665 1666 qup_spi5_spi: qup-spi5-spi-state { 1667 pins = "gpio25", "gpio26", "gpio27"; 1668 function = "qup05"; 1669 }; 1670 1671 qup_spi5_cs: qup-spi5-cs-state { 1672 pins = "gpio28"; 1673 function = "qup05"; 1674 }; 1675 1676 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1677 pins = "gpio28"; 1678 function = "gpio"; 1679 }; 1680 1681 qup_spi6_spi: qup-spi6-spi-state { 1682 pins = "gpio59", "gpio60", "gpio61"; 1683 function = "qup10"; 1684 }; 1685 1686 qup_spi6_cs: qup-spi6-cs-state { 1687 pins = "gpio62"; 1688 function = "qup10"; 1689 }; 1690 1691 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1692 pins = "gpio62"; 1693 function = "gpio"; 1694 }; 1695 1696 qup_spi8_spi: qup-spi8-spi-state { 1697 pins = "gpio42", "gpio43", "gpio44"; 1698 function = "qup12"; 1699 }; 1700 1701 qup_spi8_cs: qup-spi8-cs-state { 1702 pins = "gpio45"; 1703 function = "qup12"; 1704 }; 1705 1706 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1707 pins = "gpio45"; 1708 function = "gpio"; 1709 }; 1710 1711 qup_spi10_spi: qup-spi10-spi-state { 1712 pins = "gpio86", "gpio87", "gpio88"; 1713 function = "qup14"; 1714 }; 1715 1716 qup_spi10_cs: qup-spi10-cs-state { 1717 pins = "gpio89"; 1718 function = "qup14"; 1719 }; 1720 1721 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1722 pins = "gpio89"; 1723 function = "gpio"; 1724 }; 1725 1726 qup_spi11_spi: qup-spi11-spi-state { 1727 pins = "gpio53", "gpio54", "gpio55"; 1728 function = "qup15"; 1729 }; 1730 1731 qup_spi11_cs: qup-spi11-cs-state { 1732 pins = "gpio56"; 1733 function = "qup15"; 1734 }; 1735 1736 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1737 pins = "gpio56"; 1738 function = "gpio"; 1739 }; 1740 1741 qup_uart0_default: qup-uart0-default-state { 1742 qup_uart0_cts: cts-pins { 1743 pins = "gpio34"; 1744 function = "qup00"; 1745 }; 1746 1747 qup_uart0_rts: rts-pins { 1748 pins = "gpio35"; 1749 function = "qup00"; 1750 }; 1751 1752 qup_uart0_tx: tx-pins { 1753 pins = "gpio36"; 1754 function = "qup00"; 1755 }; 1756 1757 qup_uart0_rx: rx-pins { 1758 pins = "gpio37"; 1759 function = "qup00"; 1760 }; 1761 }; 1762 1763 qup_uart1_default: qup-uart1-default-state { 1764 qup_uart1_cts: cts-pins { 1765 pins = "gpio0"; 1766 function = "qup01"; 1767 }; 1768 1769 qup_uart1_rts: rts-pins { 1770 pins = "gpio1"; 1771 function = "qup01"; 1772 }; 1773 1774 qup_uart1_tx: tx-pins { 1775 pins = "gpio2"; 1776 function = "qup01"; 1777 }; 1778 1779 qup_uart1_rx: rx-pins { 1780 pins = "gpio3"; 1781 function = "qup01"; 1782 }; 1783 }; 1784 1785 qup_uart2_default: qup-uart2-default-state { 1786 qup_uart2_tx: tx-pins { 1787 pins = "gpio15"; 1788 function = "qup02_uart"; 1789 }; 1790 1791 qup_uart2_rx: rx-pins { 1792 pins = "gpio16"; 1793 function = "qup02_uart"; 1794 }; 1795 }; 1796 1797 qup_uart3_default: qup-uart3-default-state { 1798 qup_uart3_cts: cts-pins { 1799 pins = "gpio38"; 1800 function = "qup03"; 1801 }; 1802 1803 qup_uart3_rts: rts-pins { 1804 pins = "gpio39"; 1805 function = "qup03"; 1806 }; 1807 1808 qup_uart3_tx: tx-pins { 1809 pins = "gpio40"; 1810 function = "qup03"; 1811 }; 1812 1813 qup_uart3_rx: rx-pins { 1814 pins = "gpio41"; 1815 function = "qup03"; 1816 }; 1817 }; 1818 1819 qup_uart4_default: qup-uart4-default-state { 1820 qup_uart4_tx: tx-pins { 1821 pins = "gpio115"; 1822 function = "qup04_uart"; 1823 }; 1824 1825 qup_uart4_rx: rx-pins { 1826 pins = "gpio116"; 1827 function = "qup04_uart"; 1828 }; 1829 }; 1830 1831 qup_uart5_default: qup-uart5-default-state { 1832 qup_uart5_cts: cts-pins { 1833 pins = "gpio25"; 1834 function = "qup05"; 1835 }; 1836 1837 qup_uart5_rts: rts-pins { 1838 pins = "gpio26"; 1839 function = "qup05"; 1840 }; 1841 1842 qup_uart5_tx: tx-pins { 1843 pins = "gpio27"; 1844 function = "qup05"; 1845 }; 1846 1847 qup_uart5_rx: rx-pins { 1848 pins = "gpio28"; 1849 function = "qup05"; 1850 }; 1851 }; 1852 1853 qup_uart6_default: qup-uart6-default-state { 1854 qup_uart6_cts: cts-pins { 1855 pins = "gpio59"; 1856 function = "qup10"; 1857 }; 1858 1859 qup_uart6_rts: rts-pins { 1860 pins = "gpio60"; 1861 function = "qup10"; 1862 }; 1863 1864 qup_uart6_tx: tx-pins { 1865 pins = "gpio61"; 1866 function = "qup10"; 1867 }; 1868 1869 qup_uart6_rx: rx-pins { 1870 pins = "gpio62"; 1871 function = "qup10"; 1872 }; 1873 }; 1874 1875 qup_uart7_default: qup-uart7-default-state { 1876 qup_uart7_tx: tx-pins { 1877 pins = "gpio6"; 1878 function = "qup11_uart"; 1879 }; 1880 1881 qup_uart7_rx: rx-pins { 1882 pins = "gpio7"; 1883 function = "qup11_uart"; 1884 }; 1885 }; 1886 1887 qup_uart8_default: qup-uart8-default-state { 1888 qup_uart8_tx: tx-pins { 1889 pins = "gpio44"; 1890 function = "qup12"; 1891 }; 1892 1893 qup_uart8_rx: rx-pins { 1894 pins = "gpio45"; 1895 function = "qup12"; 1896 }; 1897 }; 1898 1899 qup_uart9_default: qup-uart9-default-state { 1900 qup_uart9_tx: tx-pins { 1901 pins = "gpio46"; 1902 function = "qup13_uart"; 1903 }; 1904 1905 qup_uart9_rx: rx-pins { 1906 pins = "gpio47"; 1907 function = "qup13_uart"; 1908 }; 1909 }; 1910 1911 qup_uart10_default: qup-uart10-default-state { 1912 qup_uart10_cts: cts-pins { 1913 pins = "gpio86"; 1914 function = "qup14"; 1915 }; 1916 1917 qup_uart10_rts: rts-pins { 1918 pins = "gpio87"; 1919 function = "qup14"; 1920 }; 1921 1922 qup_uart10_tx: tx-pins { 1923 pins = "gpio88"; 1924 function = "qup14"; 1925 }; 1926 1927 qup_uart10_rx: rx-pins { 1928 pins = "gpio89"; 1929 function = "qup14"; 1930 }; 1931 }; 1932 1933 qup_uart11_default: qup-uart11-default-state { 1934 qup_uart11_cts: cts-pins { 1935 pins = "gpio53"; 1936 function = "qup15"; 1937 }; 1938 1939 qup_uart11_rts: rts-pins { 1940 pins = "gpio54"; 1941 function = "qup15"; 1942 }; 1943 1944 qup_uart11_tx: tx-pins { 1945 pins = "gpio55"; 1946 function = "qup15"; 1947 }; 1948 1949 qup_uart11_rx: rx-pins { 1950 pins = "gpio56"; 1951 function = "qup15"; 1952 }; 1953 }; 1954 1955 sec_mi2s_active: sec-mi2s-active-state { 1956 pins = "gpio49", "gpio50", "gpio51"; 1957 function = "mi2s_1"; 1958 }; 1959 1960 pri_mi2s_active: pri-mi2s-active-state { 1961 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1962 function = "mi2s_0"; 1963 }; 1964 1965 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 1966 pins = "gpio57"; 1967 function = "lpass_ext"; 1968 }; 1969 }; 1970 1971 remoteproc_mpss: remoteproc@4080000 { 1972 compatible = "qcom,sc7180-mpss-pas"; 1973 reg = <0 0x04080000 0 0x4040>; 1974 1975 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1976 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1977 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1978 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1979 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1980 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1981 interrupt-names = "wdog", "fatal", "ready", "handover", 1982 "stop-ack", "shutdown-ack"; 1983 1984 clocks = <&rpmhcc RPMH_CXO_CLK>; 1985 clock-names = "xo"; 1986 1987 power-domains = <&rpmhpd SC7180_CX>, 1988 <&rpmhpd SC7180_MX>, 1989 <&rpmhpd SC7180_MSS>; 1990 power-domain-names = "cx", "mx", "mss"; 1991 1992 memory-region = <&mpss_mem>; 1993 1994 qcom,qmp = <&aoss_qmp>; 1995 1996 qcom,smem-states = <&modem_smp2p_out 0>; 1997 qcom,smem-state-names = "stop"; 1998 1999 status = "disabled"; 2000 2001 glink-edge { 2002 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2003 label = "modem"; 2004 qcom,remote-pid = <1>; 2005 mboxes = <&apss_shared 12>; 2006 }; 2007 }; 2008 2009 gpu: gpu@5000000 { 2010 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2011 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2012 <0 0x05061000 0 0x800>; 2013 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2014 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2015 iommus = <&adreno_smmu 0>; 2016 operating-points-v2 = <&gpu_opp_table>; 2017 qcom,gmu = <&gmu>; 2018 2019 #cooling-cells = <2>; 2020 2021 nvmem-cells = <&gpu_speed_bin>; 2022 nvmem-cell-names = "speed_bin"; 2023 2024 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2025 interconnect-names = "gfx-mem"; 2026 2027 gpu_opp_table: opp-table { 2028 compatible = "operating-points-v2"; 2029 2030 opp-825000000 { 2031 opp-hz = /bits/ 64 <825000000>; 2032 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2033 opp-peak-kBps = <8532000>; 2034 opp-supported-hw = <0x04>; 2035 }; 2036 2037 opp-800000000 { 2038 opp-hz = /bits/ 64 <800000000>; 2039 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2040 opp-peak-kBps = <8532000>; 2041 opp-supported-hw = <0x07>; 2042 }; 2043 2044 opp-650000000 { 2045 opp-hz = /bits/ 64 <650000000>; 2046 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2047 opp-peak-kBps = <7216000>; 2048 opp-supported-hw = <0x07>; 2049 }; 2050 2051 opp-565000000 { 2052 opp-hz = /bits/ 64 <565000000>; 2053 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2054 opp-peak-kBps = <5412000>; 2055 opp-supported-hw = <0x07>; 2056 }; 2057 2058 opp-430000000 { 2059 opp-hz = /bits/ 64 <430000000>; 2060 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2061 opp-peak-kBps = <5412000>; 2062 opp-supported-hw = <0x07>; 2063 }; 2064 2065 opp-355000000 { 2066 opp-hz = /bits/ 64 <355000000>; 2067 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2068 opp-peak-kBps = <3072000>; 2069 opp-supported-hw = <0x07>; 2070 }; 2071 2072 opp-267000000 { 2073 opp-hz = /bits/ 64 <267000000>; 2074 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2075 opp-peak-kBps = <3072000>; 2076 opp-supported-hw = <0x07>; 2077 }; 2078 2079 opp-180000000 { 2080 opp-hz = /bits/ 64 <180000000>; 2081 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2082 opp-peak-kBps = <1804000>; 2083 opp-supported-hw = <0x07>; 2084 }; 2085 }; 2086 }; 2087 2088 adreno_smmu: iommu@5040000 { 2089 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2090 reg = <0 0x05040000 0 0x10000>; 2091 #iommu-cells = <1>; 2092 #global-interrupts = <2>; 2093 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2096 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2097 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2098 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2099 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2100 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2101 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2102 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2103 2104 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2105 <&gcc GCC_GPU_CFG_AHB_CLK>; 2106 clock-names = "bus", "iface"; 2107 2108 power-domains = <&gpucc CX_GDSC>; 2109 }; 2110 2111 gmu: gmu@506a000 { 2112 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2113 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2114 <0 0x0b490000 0 0x10000>; 2115 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2116 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2118 interrupt-names = "hfi", "gmu"; 2119 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2120 <&gpucc GPU_CC_CXO_CLK>, 2121 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2122 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2123 clock-names = "gmu", "cxo", "axi", "memnoc"; 2124 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2125 power-domain-names = "cx", "gx"; 2126 iommus = <&adreno_smmu 5>; 2127 operating-points-v2 = <&gmu_opp_table>; 2128 2129 gmu_opp_table: opp-table { 2130 compatible = "operating-points-v2"; 2131 2132 opp-200000000 { 2133 opp-hz = /bits/ 64 <200000000>; 2134 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2135 }; 2136 }; 2137 }; 2138 2139 gpucc: clock-controller@5090000 { 2140 compatible = "qcom,sc7180-gpucc"; 2141 reg = <0 0x05090000 0 0x9000>; 2142 clocks = <&rpmhcc RPMH_CXO_CLK>, 2143 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2144 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2145 clock-names = "bi_tcxo", 2146 "gcc_gpu_gpll0_clk_src", 2147 "gcc_gpu_gpll0_div_clk_src"; 2148 #clock-cells = <1>; 2149 #reset-cells = <1>; 2150 #power-domain-cells = <1>; 2151 }; 2152 2153 dma@10a2000 { 2154 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2155 reg = <0x0 0x010a2000 0x0 0x1000>, 2156 <0x0 0x010ae000 0x0 0x2000>; 2157 }; 2158 2159 stm@6002000 { 2160 compatible = "arm,coresight-stm", "arm,primecell"; 2161 reg = <0 0x06002000 0 0x1000>, 2162 <0 0x16280000 0 0x180000>; 2163 reg-names = "stm-base", "stm-stimulus-base"; 2164 2165 clocks = <&aoss_qmp>; 2166 clock-names = "apb_pclk"; 2167 2168 out-ports { 2169 port { 2170 stm_out: endpoint { 2171 remote-endpoint = <&funnel0_in7>; 2172 }; 2173 }; 2174 }; 2175 }; 2176 2177 funnel@6041000 { 2178 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2179 reg = <0 0x06041000 0 0x1000>; 2180 2181 clocks = <&aoss_qmp>; 2182 clock-names = "apb_pclk"; 2183 2184 out-ports { 2185 port { 2186 funnel0_out: endpoint { 2187 remote-endpoint = <&merge_funnel_in0>; 2188 }; 2189 }; 2190 }; 2191 2192 in-ports { 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 2196 port@7 { 2197 reg = <7>; 2198 funnel0_in7: endpoint { 2199 remote-endpoint = <&stm_out>; 2200 }; 2201 }; 2202 }; 2203 }; 2204 2205 funnel@6042000 { 2206 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2207 reg = <0 0x06042000 0 0x1000>; 2208 2209 clocks = <&aoss_qmp>; 2210 clock-names = "apb_pclk"; 2211 2212 out-ports { 2213 port { 2214 funnel1_out: endpoint { 2215 remote-endpoint = <&merge_funnel_in1>; 2216 }; 2217 }; 2218 }; 2219 2220 in-ports { 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 2224 port@4 { 2225 reg = <4>; 2226 funnel1_in4: endpoint { 2227 remote-endpoint = <&apss_merge_funnel_out>; 2228 }; 2229 }; 2230 }; 2231 }; 2232 2233 funnel@6045000 { 2234 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2235 reg = <0 0x06045000 0 0x1000>; 2236 2237 clocks = <&aoss_qmp>; 2238 clock-names = "apb_pclk"; 2239 2240 out-ports { 2241 port { 2242 merge_funnel_out: endpoint { 2243 remote-endpoint = <&swao_funnel_in>; 2244 }; 2245 }; 2246 }; 2247 2248 in-ports { 2249 #address-cells = <1>; 2250 #size-cells = <0>; 2251 2252 port@0 { 2253 reg = <0>; 2254 merge_funnel_in0: endpoint { 2255 remote-endpoint = <&funnel0_out>; 2256 }; 2257 }; 2258 2259 port@1 { 2260 reg = <1>; 2261 merge_funnel_in1: endpoint { 2262 remote-endpoint = <&funnel1_out>; 2263 }; 2264 }; 2265 }; 2266 }; 2267 2268 replicator@6046000 { 2269 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2270 reg = <0 0x06046000 0 0x1000>; 2271 2272 clocks = <&aoss_qmp>; 2273 clock-names = "apb_pclk"; 2274 2275 out-ports { 2276 port { 2277 replicator_out: endpoint { 2278 remote-endpoint = <&etr_in>; 2279 }; 2280 }; 2281 }; 2282 2283 in-ports { 2284 port { 2285 replicator_in: endpoint { 2286 remote-endpoint = <&swao_replicator_out>; 2287 }; 2288 }; 2289 }; 2290 }; 2291 2292 etr@6048000 { 2293 compatible = "arm,coresight-tmc", "arm,primecell"; 2294 reg = <0 0x06048000 0 0x1000>; 2295 iommus = <&apps_smmu 0x04a0 0x20>; 2296 2297 clocks = <&aoss_qmp>; 2298 clock-names = "apb_pclk"; 2299 arm,scatter-gather; 2300 2301 in-ports { 2302 port { 2303 etr_in: endpoint { 2304 remote-endpoint = <&replicator_out>; 2305 }; 2306 }; 2307 }; 2308 }; 2309 2310 funnel@6b04000 { 2311 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2312 reg = <0 0x06b04000 0 0x1000>; 2313 2314 clocks = <&aoss_qmp>; 2315 clock-names = "apb_pclk"; 2316 2317 out-ports { 2318 port { 2319 swao_funnel_out: endpoint { 2320 remote-endpoint = <&etf_in>; 2321 }; 2322 }; 2323 }; 2324 2325 in-ports { 2326 #address-cells = <1>; 2327 #size-cells = <0>; 2328 2329 port@7 { 2330 reg = <7>; 2331 swao_funnel_in: endpoint { 2332 remote-endpoint = <&merge_funnel_out>; 2333 }; 2334 }; 2335 }; 2336 }; 2337 2338 etf@6b05000 { 2339 compatible = "arm,coresight-tmc", "arm,primecell"; 2340 reg = <0 0x06b05000 0 0x1000>; 2341 2342 clocks = <&aoss_qmp>; 2343 clock-names = "apb_pclk"; 2344 2345 out-ports { 2346 port { 2347 etf_out: endpoint { 2348 remote-endpoint = <&swao_replicator_in>; 2349 }; 2350 }; 2351 }; 2352 2353 in-ports { 2354 port { 2355 etf_in: endpoint { 2356 remote-endpoint = <&swao_funnel_out>; 2357 }; 2358 }; 2359 }; 2360 }; 2361 2362 replicator@6b06000 { 2363 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2364 reg = <0 0x06b06000 0 0x1000>; 2365 2366 clocks = <&aoss_qmp>; 2367 clock-names = "apb_pclk"; 2368 qcom,replicator-loses-context; 2369 2370 out-ports { 2371 port { 2372 swao_replicator_out: endpoint { 2373 remote-endpoint = <&replicator_in>; 2374 }; 2375 }; 2376 }; 2377 2378 in-ports { 2379 port { 2380 swao_replicator_in: endpoint { 2381 remote-endpoint = <&etf_out>; 2382 }; 2383 }; 2384 }; 2385 }; 2386 2387 etm@7040000 { 2388 compatible = "arm,coresight-etm4x", "arm,primecell"; 2389 reg = <0 0x07040000 0 0x1000>; 2390 2391 cpu = <&CPU0>; 2392 2393 clocks = <&aoss_qmp>; 2394 clock-names = "apb_pclk"; 2395 arm,coresight-loses-context-with-cpu; 2396 qcom,skip-power-up; 2397 2398 out-ports { 2399 port { 2400 etm0_out: endpoint { 2401 remote-endpoint = <&apss_funnel_in0>; 2402 }; 2403 }; 2404 }; 2405 }; 2406 2407 etm@7140000 { 2408 compatible = "arm,coresight-etm4x", "arm,primecell"; 2409 reg = <0 0x07140000 0 0x1000>; 2410 2411 cpu = <&CPU1>; 2412 2413 clocks = <&aoss_qmp>; 2414 clock-names = "apb_pclk"; 2415 arm,coresight-loses-context-with-cpu; 2416 qcom,skip-power-up; 2417 2418 out-ports { 2419 port { 2420 etm1_out: endpoint { 2421 remote-endpoint = <&apss_funnel_in1>; 2422 }; 2423 }; 2424 }; 2425 }; 2426 2427 etm@7240000 { 2428 compatible = "arm,coresight-etm4x", "arm,primecell"; 2429 reg = <0 0x07240000 0 0x1000>; 2430 2431 cpu = <&CPU2>; 2432 2433 clocks = <&aoss_qmp>; 2434 clock-names = "apb_pclk"; 2435 arm,coresight-loses-context-with-cpu; 2436 qcom,skip-power-up; 2437 2438 out-ports { 2439 port { 2440 etm2_out: endpoint { 2441 remote-endpoint = <&apss_funnel_in2>; 2442 }; 2443 }; 2444 }; 2445 }; 2446 2447 etm@7340000 { 2448 compatible = "arm,coresight-etm4x", "arm,primecell"; 2449 reg = <0 0x07340000 0 0x1000>; 2450 2451 cpu = <&CPU3>; 2452 2453 clocks = <&aoss_qmp>; 2454 clock-names = "apb_pclk"; 2455 arm,coresight-loses-context-with-cpu; 2456 qcom,skip-power-up; 2457 2458 out-ports { 2459 port { 2460 etm3_out: endpoint { 2461 remote-endpoint = <&apss_funnel_in3>; 2462 }; 2463 }; 2464 }; 2465 }; 2466 2467 etm@7440000 { 2468 compatible = "arm,coresight-etm4x", "arm,primecell"; 2469 reg = <0 0x07440000 0 0x1000>; 2470 2471 cpu = <&CPU4>; 2472 2473 clocks = <&aoss_qmp>; 2474 clock-names = "apb_pclk"; 2475 arm,coresight-loses-context-with-cpu; 2476 qcom,skip-power-up; 2477 2478 out-ports { 2479 port { 2480 etm4_out: endpoint { 2481 remote-endpoint = <&apss_funnel_in4>; 2482 }; 2483 }; 2484 }; 2485 }; 2486 2487 etm@7540000 { 2488 compatible = "arm,coresight-etm4x", "arm,primecell"; 2489 reg = <0 0x07540000 0 0x1000>; 2490 2491 cpu = <&CPU5>; 2492 2493 clocks = <&aoss_qmp>; 2494 clock-names = "apb_pclk"; 2495 arm,coresight-loses-context-with-cpu; 2496 qcom,skip-power-up; 2497 2498 out-ports { 2499 port { 2500 etm5_out: endpoint { 2501 remote-endpoint = <&apss_funnel_in5>; 2502 }; 2503 }; 2504 }; 2505 }; 2506 2507 etm@7640000 { 2508 compatible = "arm,coresight-etm4x", "arm,primecell"; 2509 reg = <0 0x07640000 0 0x1000>; 2510 2511 cpu = <&CPU6>; 2512 2513 clocks = <&aoss_qmp>; 2514 clock-names = "apb_pclk"; 2515 arm,coresight-loses-context-with-cpu; 2516 qcom,skip-power-up; 2517 2518 out-ports { 2519 port { 2520 etm6_out: endpoint { 2521 remote-endpoint = <&apss_funnel_in6>; 2522 }; 2523 }; 2524 }; 2525 }; 2526 2527 etm@7740000 { 2528 compatible = "arm,coresight-etm4x", "arm,primecell"; 2529 reg = <0 0x07740000 0 0x1000>; 2530 2531 cpu = <&CPU7>; 2532 2533 clocks = <&aoss_qmp>; 2534 clock-names = "apb_pclk"; 2535 arm,coresight-loses-context-with-cpu; 2536 qcom,skip-power-up; 2537 2538 out-ports { 2539 port { 2540 etm7_out: endpoint { 2541 remote-endpoint = <&apss_funnel_in7>; 2542 }; 2543 }; 2544 }; 2545 }; 2546 2547 funnel@7800000 { /* APSS Funnel */ 2548 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2549 reg = <0 0x07800000 0 0x1000>; 2550 2551 clocks = <&aoss_qmp>; 2552 clock-names = "apb_pclk"; 2553 2554 out-ports { 2555 port { 2556 apss_funnel_out: endpoint { 2557 remote-endpoint = <&apss_merge_funnel_in>; 2558 }; 2559 }; 2560 }; 2561 2562 in-ports { 2563 #address-cells = <1>; 2564 #size-cells = <0>; 2565 2566 port@0 { 2567 reg = <0>; 2568 apss_funnel_in0: endpoint { 2569 remote-endpoint = <&etm0_out>; 2570 }; 2571 }; 2572 2573 port@1 { 2574 reg = <1>; 2575 apss_funnel_in1: endpoint { 2576 remote-endpoint = <&etm1_out>; 2577 }; 2578 }; 2579 2580 port@2 { 2581 reg = <2>; 2582 apss_funnel_in2: endpoint { 2583 remote-endpoint = <&etm2_out>; 2584 }; 2585 }; 2586 2587 port@3 { 2588 reg = <3>; 2589 apss_funnel_in3: endpoint { 2590 remote-endpoint = <&etm3_out>; 2591 }; 2592 }; 2593 2594 port@4 { 2595 reg = <4>; 2596 apss_funnel_in4: endpoint { 2597 remote-endpoint = <&etm4_out>; 2598 }; 2599 }; 2600 2601 port@5 { 2602 reg = <5>; 2603 apss_funnel_in5: endpoint { 2604 remote-endpoint = <&etm5_out>; 2605 }; 2606 }; 2607 2608 port@6 { 2609 reg = <6>; 2610 apss_funnel_in6: endpoint { 2611 remote-endpoint = <&etm6_out>; 2612 }; 2613 }; 2614 2615 port@7 { 2616 reg = <7>; 2617 apss_funnel_in7: endpoint { 2618 remote-endpoint = <&etm7_out>; 2619 }; 2620 }; 2621 }; 2622 }; 2623 2624 funnel@7810000 { 2625 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2626 reg = <0 0x07810000 0 0x1000>; 2627 2628 clocks = <&aoss_qmp>; 2629 clock-names = "apb_pclk"; 2630 2631 out-ports { 2632 port { 2633 apss_merge_funnel_out: endpoint { 2634 remote-endpoint = <&funnel1_in4>; 2635 }; 2636 }; 2637 }; 2638 2639 in-ports { 2640 port { 2641 apss_merge_funnel_in: endpoint { 2642 remote-endpoint = <&apss_funnel_out>; 2643 }; 2644 }; 2645 }; 2646 }; 2647 2648 sdhc_2: mmc@8804000 { 2649 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2650 reg = <0 0x08804000 0 0x1000>; 2651 2652 iommus = <&apps_smmu 0x80 0>; 2653 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2654 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2655 interrupt-names = "hc_irq", "pwr_irq"; 2656 2657 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2658 <&gcc GCC_SDCC2_APPS_CLK>, 2659 <&rpmhcc RPMH_CXO_CLK>; 2660 clock-names = "iface", "core", "xo"; 2661 2662 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2663 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2664 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2665 power-domains = <&rpmhpd SC7180_CX>; 2666 operating-points-v2 = <&sdhc2_opp_table>; 2667 2668 bus-width = <4>; 2669 2670 status = "disabled"; 2671 2672 sdhc2_opp_table: opp-table { 2673 compatible = "operating-points-v2"; 2674 2675 opp-100000000 { 2676 opp-hz = /bits/ 64 <100000000>; 2677 required-opps = <&rpmhpd_opp_low_svs>; 2678 opp-peak-kBps = <1800000 600000>; 2679 opp-avg-kBps = <100000 0>; 2680 }; 2681 2682 opp-202000000 { 2683 opp-hz = /bits/ 64 <202000000>; 2684 required-opps = <&rpmhpd_opp_nom>; 2685 opp-peak-kBps = <5400000 1600000>; 2686 opp-avg-kBps = <200000 0>; 2687 }; 2688 }; 2689 }; 2690 2691 qspi: spi@88dc000 { 2692 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2693 reg = <0 0x088dc000 0 0x600>; 2694 iommus = <&apps_smmu 0x20 0x0>; 2695 #address-cells = <1>; 2696 #size-cells = <0>; 2697 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2698 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2699 <&gcc GCC_QSPI_CORE_CLK>; 2700 clock-names = "iface", "core"; 2701 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2702 &config_noc SLAVE_QSPI_0 0>; 2703 interconnect-names = "qspi-config"; 2704 power-domains = <&rpmhpd SC7180_CX>; 2705 operating-points-v2 = <&qspi_opp_table>; 2706 status = "disabled"; 2707 }; 2708 2709 usb_1_hsphy: phy@88e3000 { 2710 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2711 reg = <0 0x088e3000 0 0x400>; 2712 status = "disabled"; 2713 #phy-cells = <0>; 2714 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2715 <&rpmhcc RPMH_CXO_CLK>; 2716 clock-names = "cfg_ahb", "ref"; 2717 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2718 2719 nvmem-cells = <&qusb2p_hstx_trim>; 2720 }; 2721 2722 usb_1_qmpphy: phy-wrapper@88e9000 { 2723 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2724 reg = <0 0x088e9000 0 0x18c>, 2725 <0 0x088e8000 0 0x3c>, 2726 <0 0x088ea000 0 0x18c>; 2727 status = "disabled"; 2728 #address-cells = <2>; 2729 #size-cells = <2>; 2730 ranges; 2731 2732 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2733 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2734 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2735 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2736 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2737 2738 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2739 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2740 reset-names = "phy", "common"; 2741 2742 usb_1_ssphy: usb3-phy@88e9200 { 2743 reg = <0 0x088e9200 0 0x128>, 2744 <0 0x088e9400 0 0x200>, 2745 <0 0x088e9c00 0 0x218>, 2746 <0 0x088e9600 0 0x128>, 2747 <0 0x088e9800 0 0x200>, 2748 <0 0x088e9a00 0 0x18>; 2749 #clock-cells = <0>; 2750 #phy-cells = <0>; 2751 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2752 clock-names = "pipe0"; 2753 clock-output-names = "usb3_phy_pipe_clk_src"; 2754 }; 2755 2756 dp_phy: dp-phy@88ea200 { 2757 reg = <0 0x088ea200 0 0x200>, 2758 <0 0x088ea400 0 0x200>, 2759 <0 0x088eaa00 0 0x200>, 2760 <0 0x088ea600 0 0x200>, 2761 <0 0x088ea800 0 0x200>; 2762 #clock-cells = <1>; 2763 #phy-cells = <0>; 2764 }; 2765 }; 2766 2767 dc_noc: interconnect@9160000 { 2768 compatible = "qcom,sc7180-dc-noc"; 2769 reg = <0 0x09160000 0 0x03200>; 2770 #interconnect-cells = <2>; 2771 qcom,bcm-voters = <&apps_bcm_voter>; 2772 }; 2773 2774 system-cache-controller@9200000 { 2775 compatible = "qcom,sc7180-llcc"; 2776 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2777 reg-names = "llcc0_base", "llcc_broadcast_base"; 2778 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2779 }; 2780 2781 gem_noc: interconnect@9680000 { 2782 compatible = "qcom,sc7180-gem-noc"; 2783 reg = <0 0x09680000 0 0x3e200>; 2784 #interconnect-cells = <2>; 2785 qcom,bcm-voters = <&apps_bcm_voter>; 2786 }; 2787 2788 npu_noc: interconnect@9990000 { 2789 compatible = "qcom,sc7180-npu-noc"; 2790 reg = <0 0x09990000 0 0x1600>; 2791 #interconnect-cells = <2>; 2792 qcom,bcm-voters = <&apps_bcm_voter>; 2793 }; 2794 2795 usb_1: usb@a6f8800 { 2796 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2797 reg = <0 0x0a6f8800 0 0x400>; 2798 status = "disabled"; 2799 #address-cells = <2>; 2800 #size-cells = <2>; 2801 ranges; 2802 dma-ranges; 2803 2804 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2805 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2806 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2807 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2808 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2809 clock-names = "cfg_noc", 2810 "core", 2811 "iface", 2812 "sleep", 2813 "mock_utmi"; 2814 2815 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2816 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2817 assigned-clock-rates = <19200000>, <150000000>; 2818 2819 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2820 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2821 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2822 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2823 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2824 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2825 2826 power-domains = <&gcc USB30_PRIM_GDSC>; 2827 required-opps = <&rpmhpd_opp_nom>; 2828 2829 resets = <&gcc GCC_USB30_PRIM_BCR>; 2830 2831 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2832 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2833 interconnect-names = "usb-ddr", "apps-usb"; 2834 2835 wakeup-source; 2836 2837 usb_1_dwc3: usb@a600000 { 2838 compatible = "snps,dwc3"; 2839 reg = <0 0x0a600000 0 0xe000>; 2840 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2841 iommus = <&apps_smmu 0x540 0>; 2842 snps,dis_u2_susphy_quirk; 2843 snps,dis_enblslpm_quirk; 2844 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2845 phy-names = "usb2-phy", "usb3-phy"; 2846 maximum-speed = "super-speed"; 2847 }; 2848 }; 2849 2850 venus: video-codec@aa00000 { 2851 compatible = "qcom,sc7180-venus"; 2852 reg = <0 0x0aa00000 0 0xff000>; 2853 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2854 power-domains = <&videocc VENUS_GDSC>, 2855 <&videocc VCODEC0_GDSC>, 2856 <&rpmhpd SC7180_CX>; 2857 power-domain-names = "venus", "vcodec0", "cx"; 2858 operating-points-v2 = <&venus_opp_table>; 2859 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2860 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2861 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2862 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2863 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2864 clock-names = "core", "iface", "bus", 2865 "vcodec0_core", "vcodec0_bus"; 2866 iommus = <&apps_smmu 0x0c00 0x60>; 2867 memory-region = <&venus_mem>; 2868 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2870 interconnect-names = "video-mem", "cpu-cfg"; 2871 2872 video-decoder { 2873 compatible = "venus-decoder"; 2874 }; 2875 2876 video-encoder { 2877 compatible = "venus-encoder"; 2878 }; 2879 2880 venus_opp_table: opp-table { 2881 compatible = "operating-points-v2"; 2882 2883 opp-150000000 { 2884 opp-hz = /bits/ 64 <150000000>; 2885 required-opps = <&rpmhpd_opp_low_svs>; 2886 }; 2887 2888 opp-270000000 { 2889 opp-hz = /bits/ 64 <270000000>; 2890 required-opps = <&rpmhpd_opp_svs>; 2891 }; 2892 2893 opp-340000000 { 2894 opp-hz = /bits/ 64 <340000000>; 2895 required-opps = <&rpmhpd_opp_svs_l1>; 2896 }; 2897 2898 opp-434000000 { 2899 opp-hz = /bits/ 64 <434000000>; 2900 required-opps = <&rpmhpd_opp_nom>; 2901 }; 2902 2903 opp-500000097 { 2904 opp-hz = /bits/ 64 <500000097>; 2905 required-opps = <&rpmhpd_opp_turbo>; 2906 }; 2907 }; 2908 }; 2909 2910 videocc: clock-controller@ab00000 { 2911 compatible = "qcom,sc7180-videocc"; 2912 reg = <0 0x0ab00000 0 0x10000>; 2913 clocks = <&rpmhcc RPMH_CXO_CLK>; 2914 clock-names = "bi_tcxo"; 2915 #clock-cells = <1>; 2916 #reset-cells = <1>; 2917 #power-domain-cells = <1>; 2918 }; 2919 2920 camnoc_virt: interconnect@ac00000 { 2921 compatible = "qcom,sc7180-camnoc-virt"; 2922 reg = <0 0x0ac00000 0 0x1000>; 2923 #interconnect-cells = <2>; 2924 qcom,bcm-voters = <&apps_bcm_voter>; 2925 }; 2926 2927 camcc: clock-controller@ad00000 { 2928 compatible = "qcom,sc7180-camcc"; 2929 reg = <0 0x0ad00000 0 0x10000>; 2930 clocks = <&rpmhcc RPMH_CXO_CLK>, 2931 <&gcc GCC_CAMERA_AHB_CLK>, 2932 <&gcc GCC_CAMERA_XO_CLK>; 2933 clock-names = "bi_tcxo", "iface", "xo"; 2934 #clock-cells = <1>; 2935 #reset-cells = <1>; 2936 #power-domain-cells = <1>; 2937 }; 2938 2939 mdss: display-subsystem@ae00000 { 2940 compatible = "qcom,sc7180-mdss"; 2941 reg = <0 0x0ae00000 0 0x1000>; 2942 reg-names = "mdss"; 2943 2944 power-domains = <&dispcc MDSS_GDSC>; 2945 2946 clocks = <&gcc GCC_DISP_AHB_CLK>, 2947 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2948 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2949 clock-names = "iface", "ahb", "core"; 2950 2951 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2952 interrupt-controller; 2953 #interrupt-cells = <1>; 2954 2955 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2956 interconnect-names = "mdp0-mem"; 2957 2958 iommus = <&apps_smmu 0x800 0x2>; 2959 2960 #address-cells = <2>; 2961 #size-cells = <2>; 2962 ranges; 2963 2964 status = "disabled"; 2965 2966 mdp: display-controller@ae01000 { 2967 compatible = "qcom,sc7180-dpu"; 2968 reg = <0 0x0ae01000 0 0x8f000>, 2969 <0 0x0aeb0000 0 0x2008>; 2970 reg-names = "mdp", "vbif"; 2971 2972 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2973 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2974 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2975 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2976 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2977 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2978 clock-names = "bus", "iface", "rot", "lut", "core", 2979 "vsync"; 2980 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2981 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2982 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2983 assigned-clock-rates = <19200000>, 2984 <19200000>, 2985 <19200000>; 2986 operating-points-v2 = <&mdp_opp_table>; 2987 power-domains = <&rpmhpd SC7180_CX>; 2988 2989 interrupt-parent = <&mdss>; 2990 interrupts = <0>; 2991 2992 ports { 2993 #address-cells = <1>; 2994 #size-cells = <0>; 2995 2996 port@0 { 2997 reg = <0>; 2998 dpu_intf1_out: endpoint { 2999 remote-endpoint = <&dsi0_in>; 3000 }; 3001 }; 3002 3003 port@2 { 3004 reg = <2>; 3005 dpu_intf0_out: endpoint { 3006 remote-endpoint = <&dp_in>; 3007 }; 3008 }; 3009 }; 3010 3011 mdp_opp_table: opp-table { 3012 compatible = "operating-points-v2"; 3013 3014 opp-200000000 { 3015 opp-hz = /bits/ 64 <200000000>; 3016 required-opps = <&rpmhpd_opp_low_svs>; 3017 }; 3018 3019 opp-300000000 { 3020 opp-hz = /bits/ 64 <300000000>; 3021 required-opps = <&rpmhpd_opp_svs>; 3022 }; 3023 3024 opp-345000000 { 3025 opp-hz = /bits/ 64 <345000000>; 3026 required-opps = <&rpmhpd_opp_svs_l1>; 3027 }; 3028 3029 opp-460000000 { 3030 opp-hz = /bits/ 64 <460000000>; 3031 required-opps = <&rpmhpd_opp_nom>; 3032 }; 3033 }; 3034 }; 3035 3036 dsi0: dsi@ae94000 { 3037 compatible = "qcom,sc7180-dsi-ctrl", 3038 "qcom,mdss-dsi-ctrl"; 3039 reg = <0 0x0ae94000 0 0x400>; 3040 reg-names = "dsi_ctrl"; 3041 3042 interrupt-parent = <&mdss>; 3043 interrupts = <4>; 3044 3045 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3046 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3047 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3048 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3049 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3050 <&gcc GCC_DISP_HF_AXI_CLK>; 3051 clock-names = "byte", 3052 "byte_intf", 3053 "pixel", 3054 "core", 3055 "iface", 3056 "bus"; 3057 3058 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3059 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 3060 3061 operating-points-v2 = <&dsi_opp_table>; 3062 power-domains = <&rpmhpd SC7180_CX>; 3063 3064 phys = <&dsi_phy>; 3065 3066 #address-cells = <1>; 3067 #size-cells = <0>; 3068 3069 status = "disabled"; 3070 3071 ports { 3072 #address-cells = <1>; 3073 #size-cells = <0>; 3074 3075 port@0 { 3076 reg = <0>; 3077 dsi0_in: endpoint { 3078 remote-endpoint = <&dpu_intf1_out>; 3079 }; 3080 }; 3081 3082 port@1 { 3083 reg = <1>; 3084 dsi0_out: endpoint { 3085 }; 3086 }; 3087 }; 3088 3089 dsi_opp_table: opp-table { 3090 compatible = "operating-points-v2"; 3091 3092 opp-187500000 { 3093 opp-hz = /bits/ 64 <187500000>; 3094 required-opps = <&rpmhpd_opp_low_svs>; 3095 }; 3096 3097 opp-300000000 { 3098 opp-hz = /bits/ 64 <300000000>; 3099 required-opps = <&rpmhpd_opp_svs>; 3100 }; 3101 3102 opp-358000000 { 3103 opp-hz = /bits/ 64 <358000000>; 3104 required-opps = <&rpmhpd_opp_svs_l1>; 3105 }; 3106 }; 3107 }; 3108 3109 dsi_phy: phy@ae94400 { 3110 compatible = "qcom,dsi-phy-10nm"; 3111 reg = <0 0x0ae94400 0 0x200>, 3112 <0 0x0ae94600 0 0x280>, 3113 <0 0x0ae94a00 0 0x1e0>; 3114 reg-names = "dsi_phy", 3115 "dsi_phy_lane", 3116 "dsi_pll"; 3117 3118 #clock-cells = <1>; 3119 #phy-cells = <0>; 3120 3121 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3122 <&rpmhcc RPMH_CXO_CLK>; 3123 clock-names = "iface", "ref"; 3124 3125 status = "disabled"; 3126 }; 3127 3128 mdss_dp: displayport-controller@ae90000 { 3129 compatible = "qcom,sc7180-dp"; 3130 status = "disabled"; 3131 3132 reg = <0 0x0ae90000 0 0x200>, 3133 <0 0x0ae90200 0 0x200>, 3134 <0 0x0ae90400 0 0xc00>, 3135 <0 0x0ae91000 0 0x400>, 3136 <0 0x0ae91400 0 0x400>; 3137 3138 interrupt-parent = <&mdss>; 3139 interrupts = <12>; 3140 3141 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3142 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3143 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3144 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3145 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3146 clock-names = "core_iface", "core_aux", "ctrl_link", 3147 "ctrl_link_iface", "stream_pixel"; 3148 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3149 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3150 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3151 phys = <&dp_phy>; 3152 phy-names = "dp"; 3153 3154 operating-points-v2 = <&dp_opp_table>; 3155 power-domains = <&rpmhpd SC7180_CX>; 3156 3157 #sound-dai-cells = <0>; 3158 3159 ports { 3160 #address-cells = <1>; 3161 #size-cells = <0>; 3162 port@0 { 3163 reg = <0>; 3164 dp_in: endpoint { 3165 remote-endpoint = <&dpu_intf0_out>; 3166 }; 3167 }; 3168 3169 port@1 { 3170 reg = <1>; 3171 mdss_dp_out: endpoint { }; 3172 }; 3173 }; 3174 3175 dp_opp_table: opp-table { 3176 compatible = "operating-points-v2"; 3177 3178 opp-160000000 { 3179 opp-hz = /bits/ 64 <160000000>; 3180 required-opps = <&rpmhpd_opp_low_svs>; 3181 }; 3182 3183 opp-270000000 { 3184 opp-hz = /bits/ 64 <270000000>; 3185 required-opps = <&rpmhpd_opp_svs>; 3186 }; 3187 3188 opp-540000000 { 3189 opp-hz = /bits/ 64 <540000000>; 3190 required-opps = <&rpmhpd_opp_svs_l1>; 3191 }; 3192 3193 opp-810000000 { 3194 opp-hz = /bits/ 64 <810000000>; 3195 required-opps = <&rpmhpd_opp_nom>; 3196 }; 3197 }; 3198 }; 3199 }; 3200 3201 dispcc: clock-controller@af00000 { 3202 compatible = "qcom,sc7180-dispcc"; 3203 reg = <0 0x0af00000 0 0x200000>; 3204 clocks = <&rpmhcc RPMH_CXO_CLK>, 3205 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3206 <&dsi_phy 0>, 3207 <&dsi_phy 1>, 3208 <&dp_phy 0>, 3209 <&dp_phy 1>; 3210 clock-names = "bi_tcxo", 3211 "gcc_disp_gpll0_clk_src", 3212 "dsi0_phy_pll_out_byteclk", 3213 "dsi0_phy_pll_out_dsiclk", 3214 "dp_phy_pll_link_clk", 3215 "dp_phy_pll_vco_div_clk"; 3216 #clock-cells = <1>; 3217 #reset-cells = <1>; 3218 #power-domain-cells = <1>; 3219 }; 3220 3221 pdc: interrupt-controller@b220000 { 3222 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3223 reg = <0 0x0b220000 0 0x30000>; 3224 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3225 #interrupt-cells = <2>; 3226 interrupt-parent = <&intc>; 3227 interrupt-controller; 3228 }; 3229 3230 pdc_reset: reset-controller@b2e0000 { 3231 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3232 reg = <0 0x0b2e0000 0 0x20000>; 3233 #reset-cells = <1>; 3234 }; 3235 3236 tsens0: thermal-sensor@c263000 { 3237 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3238 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3239 <0 0x0c222000 0 0x1ff>; /* SROT */ 3240 #qcom,sensors = <15>; 3241 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3243 interrupt-names = "uplow","critical"; 3244 #thermal-sensor-cells = <1>; 3245 }; 3246 3247 tsens1: thermal-sensor@c265000 { 3248 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3249 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3250 <0 0x0c223000 0 0x1ff>; /* SROT */ 3251 #qcom,sensors = <10>; 3252 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3254 interrupt-names = "uplow","critical"; 3255 #thermal-sensor-cells = <1>; 3256 }; 3257 3258 aoss_reset: reset-controller@c2a0000 { 3259 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3260 reg = <0 0x0c2a0000 0 0x31000>; 3261 #reset-cells = <1>; 3262 }; 3263 3264 aoss_qmp: power-management@c300000 { 3265 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3266 reg = <0 0x0c300000 0 0x400>; 3267 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3268 mboxes = <&apss_shared 0>; 3269 3270 #clock-cells = <0>; 3271 }; 3272 3273 sram@c3f0000 { 3274 compatible = "qcom,rpmh-stats"; 3275 reg = <0 0x0c3f0000 0 0x400>; 3276 }; 3277 3278 spmi_bus: spmi@c440000 { 3279 compatible = "qcom,spmi-pmic-arb"; 3280 reg = <0 0x0c440000 0 0x1100>, 3281 <0 0x0c600000 0 0x2000000>, 3282 <0 0x0e600000 0 0x100000>, 3283 <0 0x0e700000 0 0xa0000>, 3284 <0 0x0c40a000 0 0x26000>; 3285 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3286 interrupt-names = "periph_irq"; 3287 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3288 qcom,ee = <0>; 3289 qcom,channel = <0>; 3290 #address-cells = <2>; 3291 #size-cells = <0>; 3292 interrupt-controller; 3293 #interrupt-cells = <4>; 3294 }; 3295 3296 sram@146aa000 { 3297 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3298 reg = <0 0x146aa000 0 0x2000>; 3299 3300 #address-cells = <1>; 3301 #size-cells = <1>; 3302 3303 ranges = <0 0 0x146aa000 0x2000>; 3304 3305 pil-reloc@94c { 3306 compatible = "qcom,pil-reloc-info"; 3307 reg = <0x94c 0xc8>; 3308 }; 3309 }; 3310 3311 apps_smmu: iommu@15000000 { 3312 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3313 reg = <0 0x15000000 0 0x100000>; 3314 #iommu-cells = <2>; 3315 #global-interrupts = <1>; 3316 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3397 }; 3398 3399 intc: interrupt-controller@17a00000 { 3400 compatible = "arm,gic-v3"; 3401 #address-cells = <2>; 3402 #size-cells = <2>; 3403 ranges; 3404 #interrupt-cells = <3>; 3405 interrupt-controller; 3406 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3407 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3408 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3409 3410 msi-controller@17a40000 { 3411 compatible = "arm,gic-v3-its"; 3412 msi-controller; 3413 #msi-cells = <1>; 3414 reg = <0 0x17a40000 0 0x20000>; 3415 status = "disabled"; 3416 }; 3417 }; 3418 3419 apss_shared: mailbox@17c00000 { 3420 compatible = "qcom,sc7180-apss-shared", 3421 "qcom,sdm845-apss-shared"; 3422 reg = <0 0x17c00000 0 0x10000>; 3423 #mbox-cells = <1>; 3424 }; 3425 3426 watchdog@17c10000 { 3427 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3428 reg = <0 0x17c10000 0 0x1000>; 3429 clocks = <&sleep_clk>; 3430 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3431 }; 3432 3433 timer@17c20000 { 3434 #address-cells = <1>; 3435 #size-cells = <1>; 3436 ranges = <0 0 0 0x20000000>; 3437 compatible = "arm,armv7-timer-mem"; 3438 reg = <0 0x17c20000 0 0x1000>; 3439 3440 frame@17c21000 { 3441 frame-number = <0>; 3442 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3444 reg = <0x17c21000 0x1000>, 3445 <0x17c22000 0x1000>; 3446 }; 3447 3448 frame@17c23000 { 3449 frame-number = <1>; 3450 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3451 reg = <0x17c23000 0x1000>; 3452 status = "disabled"; 3453 }; 3454 3455 frame@17c25000 { 3456 frame-number = <2>; 3457 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3458 reg = <0x17c25000 0x1000>; 3459 status = "disabled"; 3460 }; 3461 3462 frame@17c27000 { 3463 frame-number = <3>; 3464 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3465 reg = <0x17c27000 0x1000>; 3466 status = "disabled"; 3467 }; 3468 3469 frame@17c29000 { 3470 frame-number = <4>; 3471 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3472 reg = <0x17c29000 0x1000>; 3473 status = "disabled"; 3474 }; 3475 3476 frame@17c2b000 { 3477 frame-number = <5>; 3478 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3479 reg = <0x17c2b000 0x1000>; 3480 status = "disabled"; 3481 }; 3482 3483 frame@17c2d000 { 3484 frame-number = <6>; 3485 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3486 reg = <0x17c2d000 0x1000>; 3487 status = "disabled"; 3488 }; 3489 }; 3490 3491 apps_rsc: rsc@18200000 { 3492 compatible = "qcom,rpmh-rsc"; 3493 reg = <0 0x18200000 0 0x10000>, 3494 <0 0x18210000 0 0x10000>, 3495 <0 0x18220000 0 0x10000>; 3496 reg-names = "drv-0", "drv-1", "drv-2"; 3497 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3500 qcom,tcs-offset = <0xd00>; 3501 qcom,drv-id = <2>; 3502 qcom,tcs-config = <ACTIVE_TCS 2>, 3503 <SLEEP_TCS 3>, 3504 <WAKE_TCS 3>, 3505 <CONTROL_TCS 1>; 3506 3507 rpmhcc: clock-controller { 3508 compatible = "qcom,sc7180-rpmh-clk"; 3509 clocks = <&xo_board>; 3510 clock-names = "xo"; 3511 #clock-cells = <1>; 3512 }; 3513 3514 rpmhpd: power-controller { 3515 compatible = "qcom,sc7180-rpmhpd"; 3516 #power-domain-cells = <1>; 3517 operating-points-v2 = <&rpmhpd_opp_table>; 3518 3519 rpmhpd_opp_table: opp-table { 3520 compatible = "operating-points-v2"; 3521 3522 rpmhpd_opp_ret: opp1 { 3523 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3524 }; 3525 3526 rpmhpd_opp_min_svs: opp2 { 3527 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3528 }; 3529 3530 rpmhpd_opp_low_svs: opp3 { 3531 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3532 }; 3533 3534 rpmhpd_opp_svs: opp4 { 3535 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3536 }; 3537 3538 rpmhpd_opp_svs_l1: opp5 { 3539 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3540 }; 3541 3542 rpmhpd_opp_svs_l2: opp6 { 3543 opp-level = <224>; 3544 }; 3545 3546 rpmhpd_opp_nom: opp7 { 3547 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3548 }; 3549 3550 rpmhpd_opp_nom_l1: opp8 { 3551 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3552 }; 3553 3554 rpmhpd_opp_nom_l2: opp9 { 3555 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3556 }; 3557 3558 rpmhpd_opp_turbo: opp10 { 3559 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3560 }; 3561 3562 rpmhpd_opp_turbo_l1: opp11 { 3563 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3564 }; 3565 }; 3566 }; 3567 3568 apps_bcm_voter: bcm-voter { 3569 compatible = "qcom,bcm-voter"; 3570 }; 3571 }; 3572 3573 osm_l3: interconnect@18321000 { 3574 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3575 reg = <0 0x18321000 0 0x1400>; 3576 3577 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3578 clock-names = "xo", "alternate"; 3579 3580 #interconnect-cells = <1>; 3581 }; 3582 3583 cpufreq_hw: cpufreq@18323000 { 3584 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; 3585 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3586 reg-names = "freq-domain0", "freq-domain1"; 3587 3588 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3589 clock-names = "xo", "alternate"; 3590 3591 #freq-domain-cells = <1>; 3592 #clock-cells = <1>; 3593 }; 3594 3595 wifi: wifi@18800000 { 3596 compatible = "qcom,wcn3990-wifi"; 3597 reg = <0 0x18800000 0 0x800000>; 3598 reg-names = "membase"; 3599 iommus = <&apps_smmu 0xc0 0x1>; 3600 interrupts = 3601 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3602 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3603 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3604 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3605 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3606 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3607 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3608 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3609 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3610 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3611 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3612 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3613 memory-region = <&wlan_mem>; 3614 qcom,msa-fixed-perm; 3615 status = "disabled"; 3616 }; 3617 3618 lpasscc: clock-controller@62d00000 { 3619 compatible = "qcom,sc7180-lpasscorecc"; 3620 reg = <0 0x62d00000 0 0x50000>, 3621 <0 0x62780000 0 0x30000>; 3622 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3623 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3624 <&rpmhcc RPMH_CXO_CLK>; 3625 clock-names = "iface", "bi_tcxo"; 3626 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3627 #clock-cells = <1>; 3628 #power-domain-cells = <1>; 3629 3630 status = "reserved"; /* Controlled by ADSP */ 3631 }; 3632 3633 lpass_cpu: lpass@62d87000 { 3634 compatible = "qcom,sc7180-lpass-cpu"; 3635 3636 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3637 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3638 3639 iommus = <&apps_smmu 0x1020 0>, 3640 <&apps_smmu 0x1021 0>, 3641 <&apps_smmu 0x1032 0>; 3642 3643 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3644 required-opps = <&rpmhpd_opp_nom>; 3645 3646 status = "disabled"; 3647 3648 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3649 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3650 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3651 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3652 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3653 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3654 3655 clock-names = "pcnoc-sway-clk", "audio-core", 3656 "mclk0", "pcnoc-mport-clk", 3657 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3658 3659 3660 #sound-dai-cells = <1>; 3661 #address-cells = <1>; 3662 #size-cells = <0>; 3663 3664 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3666 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3667 }; 3668 3669 lpass_hm: clock-controller@63000000 { 3670 compatible = "qcom,sc7180-lpasshm"; 3671 reg = <0 0x63000000 0 0x28>; 3672 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3673 <&rpmhcc RPMH_CXO_CLK>; 3674 clock-names = "iface", "bi_tcxo"; 3675 power-domains = <&rpmhpd SC7180_CX>; 3676 3677 #clock-cells = <1>; 3678 #power-domain-cells = <1>; 3679 3680 status = "reserved"; /* Controlled by ADSP */ 3681 }; 3682 }; 3683 3684 thermal-zones { 3685 cpu0_thermal: cpu0-thermal { 3686 polling-delay-passive = <250>; 3687 polling-delay = <0>; 3688 3689 thermal-sensors = <&tsens0 1>; 3690 sustainable-power = <1052>; 3691 3692 trips { 3693 cpu0_alert0: trip-point0 { 3694 temperature = <90000>; 3695 hysteresis = <2000>; 3696 type = "passive"; 3697 }; 3698 3699 cpu0_alert1: trip-point1 { 3700 temperature = <95000>; 3701 hysteresis = <2000>; 3702 type = "passive"; 3703 }; 3704 3705 cpu0_crit: cpu-crit { 3706 temperature = <110000>; 3707 hysteresis = <1000>; 3708 type = "critical"; 3709 }; 3710 }; 3711 3712 cooling-maps { 3713 map0 { 3714 trip = <&cpu0_alert0>; 3715 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3716 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3717 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3718 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3719 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3720 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3721 }; 3722 map1 { 3723 trip = <&cpu0_alert1>; 3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3728 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3730 }; 3731 }; 3732 }; 3733 3734 cpu1_thermal: cpu1-thermal { 3735 polling-delay-passive = <250>; 3736 polling-delay = <0>; 3737 3738 thermal-sensors = <&tsens0 2>; 3739 sustainable-power = <1052>; 3740 3741 trips { 3742 cpu1_alert0: trip-point0 { 3743 temperature = <90000>; 3744 hysteresis = <2000>; 3745 type = "passive"; 3746 }; 3747 3748 cpu1_alert1: trip-point1 { 3749 temperature = <95000>; 3750 hysteresis = <2000>; 3751 type = "passive"; 3752 }; 3753 3754 cpu1_crit: cpu-crit { 3755 temperature = <110000>; 3756 hysteresis = <1000>; 3757 type = "critical"; 3758 }; 3759 }; 3760 3761 cooling-maps { 3762 map0 { 3763 trip = <&cpu1_alert0>; 3764 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3765 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3767 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3768 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3769 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3770 }; 3771 map1 { 3772 trip = <&cpu1_alert1>; 3773 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3774 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3776 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3777 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3778 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3779 }; 3780 }; 3781 }; 3782 3783 cpu2_thermal: cpu2-thermal { 3784 polling-delay-passive = <250>; 3785 polling-delay = <0>; 3786 3787 thermal-sensors = <&tsens0 3>; 3788 sustainable-power = <1052>; 3789 3790 trips { 3791 cpu2_alert0: trip-point0 { 3792 temperature = <90000>; 3793 hysteresis = <2000>; 3794 type = "passive"; 3795 }; 3796 3797 cpu2_alert1: trip-point1 { 3798 temperature = <95000>; 3799 hysteresis = <2000>; 3800 type = "passive"; 3801 }; 3802 3803 cpu2_crit: cpu-crit { 3804 temperature = <110000>; 3805 hysteresis = <1000>; 3806 type = "critical"; 3807 }; 3808 }; 3809 3810 cooling-maps { 3811 map0 { 3812 trip = <&cpu2_alert0>; 3813 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3816 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3817 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3818 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3819 }; 3820 map1 { 3821 trip = <&cpu2_alert1>; 3822 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3826 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3827 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3828 }; 3829 }; 3830 }; 3831 3832 cpu3_thermal: cpu3-thermal { 3833 polling-delay-passive = <250>; 3834 polling-delay = <0>; 3835 3836 thermal-sensors = <&tsens0 4>; 3837 sustainable-power = <1052>; 3838 3839 trips { 3840 cpu3_alert0: trip-point0 { 3841 temperature = <90000>; 3842 hysteresis = <2000>; 3843 type = "passive"; 3844 }; 3845 3846 cpu3_alert1: trip-point1 { 3847 temperature = <95000>; 3848 hysteresis = <2000>; 3849 type = "passive"; 3850 }; 3851 3852 cpu3_crit: cpu-crit { 3853 temperature = <110000>; 3854 hysteresis = <1000>; 3855 type = "critical"; 3856 }; 3857 }; 3858 3859 cooling-maps { 3860 map0 { 3861 trip = <&cpu3_alert0>; 3862 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3863 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3864 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3865 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3868 }; 3869 map1 { 3870 trip = <&cpu3_alert1>; 3871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3875 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3876 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3877 }; 3878 }; 3879 }; 3880 3881 cpu4_thermal: cpu4-thermal { 3882 polling-delay-passive = <250>; 3883 polling-delay = <0>; 3884 3885 thermal-sensors = <&tsens0 5>; 3886 sustainable-power = <1052>; 3887 3888 trips { 3889 cpu4_alert0: trip-point0 { 3890 temperature = <90000>; 3891 hysteresis = <2000>; 3892 type = "passive"; 3893 }; 3894 3895 cpu4_alert1: trip-point1 { 3896 temperature = <95000>; 3897 hysteresis = <2000>; 3898 type = "passive"; 3899 }; 3900 3901 cpu4_crit: cpu-crit { 3902 temperature = <110000>; 3903 hysteresis = <1000>; 3904 type = "critical"; 3905 }; 3906 }; 3907 3908 cooling-maps { 3909 map0 { 3910 trip = <&cpu4_alert0>; 3911 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3914 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3915 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3916 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3917 }; 3918 map1 { 3919 trip = <&cpu4_alert1>; 3920 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3923 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3926 }; 3927 }; 3928 }; 3929 3930 cpu5_thermal: cpu5-thermal { 3931 polling-delay-passive = <250>; 3932 polling-delay = <0>; 3933 3934 thermal-sensors = <&tsens0 6>; 3935 sustainable-power = <1052>; 3936 3937 trips { 3938 cpu5_alert0: trip-point0 { 3939 temperature = <90000>; 3940 hysteresis = <2000>; 3941 type = "passive"; 3942 }; 3943 3944 cpu5_alert1: trip-point1 { 3945 temperature = <95000>; 3946 hysteresis = <2000>; 3947 type = "passive"; 3948 }; 3949 3950 cpu5_crit: cpu-crit { 3951 temperature = <110000>; 3952 hysteresis = <1000>; 3953 type = "critical"; 3954 }; 3955 }; 3956 3957 cooling-maps { 3958 map0 { 3959 trip = <&cpu5_alert0>; 3960 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3964 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3965 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3966 }; 3967 map1 { 3968 trip = <&cpu5_alert1>; 3969 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3970 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3971 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3972 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3973 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3975 }; 3976 }; 3977 }; 3978 3979 cpu6_thermal: cpu6-thermal { 3980 polling-delay-passive = <250>; 3981 polling-delay = <0>; 3982 3983 thermal-sensors = <&tsens0 9>; 3984 sustainable-power = <1425>; 3985 3986 trips { 3987 cpu6_alert0: trip-point0 { 3988 temperature = <90000>; 3989 hysteresis = <2000>; 3990 type = "passive"; 3991 }; 3992 3993 cpu6_alert1: trip-point1 { 3994 temperature = <95000>; 3995 hysteresis = <2000>; 3996 type = "passive"; 3997 }; 3998 3999 cpu6_crit: cpu-crit { 4000 temperature = <110000>; 4001 hysteresis = <1000>; 4002 type = "critical"; 4003 }; 4004 }; 4005 4006 cooling-maps { 4007 map0 { 4008 trip = <&cpu6_alert0>; 4009 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4010 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4011 }; 4012 map1 { 4013 trip = <&cpu6_alert1>; 4014 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4015 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4016 }; 4017 }; 4018 }; 4019 4020 cpu7_thermal: cpu7-thermal { 4021 polling-delay-passive = <250>; 4022 polling-delay = <0>; 4023 4024 thermal-sensors = <&tsens0 10>; 4025 sustainable-power = <1425>; 4026 4027 trips { 4028 cpu7_alert0: trip-point0 { 4029 temperature = <90000>; 4030 hysteresis = <2000>; 4031 type = "passive"; 4032 }; 4033 4034 cpu7_alert1: trip-point1 { 4035 temperature = <95000>; 4036 hysteresis = <2000>; 4037 type = "passive"; 4038 }; 4039 4040 cpu7_crit: cpu-crit { 4041 temperature = <110000>; 4042 hysteresis = <1000>; 4043 type = "critical"; 4044 }; 4045 }; 4046 4047 cooling-maps { 4048 map0 { 4049 trip = <&cpu7_alert0>; 4050 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4051 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4052 }; 4053 map1 { 4054 trip = <&cpu7_alert1>; 4055 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4056 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4057 }; 4058 }; 4059 }; 4060 4061 cpu8_thermal: cpu8-thermal { 4062 polling-delay-passive = <250>; 4063 polling-delay = <0>; 4064 4065 thermal-sensors = <&tsens0 11>; 4066 sustainable-power = <1425>; 4067 4068 trips { 4069 cpu8_alert0: trip-point0 { 4070 temperature = <90000>; 4071 hysteresis = <2000>; 4072 type = "passive"; 4073 }; 4074 4075 cpu8_alert1: trip-point1 { 4076 temperature = <95000>; 4077 hysteresis = <2000>; 4078 type = "passive"; 4079 }; 4080 4081 cpu8_crit: cpu-crit { 4082 temperature = <110000>; 4083 hysteresis = <1000>; 4084 type = "critical"; 4085 }; 4086 }; 4087 4088 cooling-maps { 4089 map0 { 4090 trip = <&cpu8_alert0>; 4091 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4092 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4093 }; 4094 map1 { 4095 trip = <&cpu8_alert1>; 4096 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4097 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4098 }; 4099 }; 4100 }; 4101 4102 cpu9_thermal: cpu9-thermal { 4103 polling-delay-passive = <250>; 4104 polling-delay = <0>; 4105 4106 thermal-sensors = <&tsens0 12>; 4107 sustainable-power = <1425>; 4108 4109 trips { 4110 cpu9_alert0: trip-point0 { 4111 temperature = <90000>; 4112 hysteresis = <2000>; 4113 type = "passive"; 4114 }; 4115 4116 cpu9_alert1: trip-point1 { 4117 temperature = <95000>; 4118 hysteresis = <2000>; 4119 type = "passive"; 4120 }; 4121 4122 cpu9_crit: cpu-crit { 4123 temperature = <110000>; 4124 hysteresis = <1000>; 4125 type = "critical"; 4126 }; 4127 }; 4128 4129 cooling-maps { 4130 map0 { 4131 trip = <&cpu9_alert0>; 4132 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4133 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4134 }; 4135 map1 { 4136 trip = <&cpu9_alert1>; 4137 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4139 }; 4140 }; 4141 }; 4142 4143 aoss0-thermal { 4144 polling-delay-passive = <250>; 4145 polling-delay = <0>; 4146 4147 thermal-sensors = <&tsens0 0>; 4148 4149 trips { 4150 aoss0_alert0: trip-point0 { 4151 temperature = <90000>; 4152 hysteresis = <2000>; 4153 type = "hot"; 4154 }; 4155 4156 aoss0_crit: aoss0-crit { 4157 temperature = <110000>; 4158 hysteresis = <2000>; 4159 type = "critical"; 4160 }; 4161 }; 4162 }; 4163 4164 cpuss0-thermal { 4165 polling-delay-passive = <250>; 4166 polling-delay = <0>; 4167 4168 thermal-sensors = <&tsens0 7>; 4169 4170 trips { 4171 cpuss0_alert0: trip-point0 { 4172 temperature = <90000>; 4173 hysteresis = <2000>; 4174 type = "hot"; 4175 }; 4176 cpuss0_crit: cluster0-crit { 4177 temperature = <110000>; 4178 hysteresis = <2000>; 4179 type = "critical"; 4180 }; 4181 }; 4182 }; 4183 4184 cpuss1-thermal { 4185 polling-delay-passive = <250>; 4186 polling-delay = <0>; 4187 4188 thermal-sensors = <&tsens0 8>; 4189 4190 trips { 4191 cpuss1_alert0: trip-point0 { 4192 temperature = <90000>; 4193 hysteresis = <2000>; 4194 type = "hot"; 4195 }; 4196 cpuss1_crit: cluster0-crit { 4197 temperature = <110000>; 4198 hysteresis = <2000>; 4199 type = "critical"; 4200 }; 4201 }; 4202 }; 4203 4204 gpuss0-thermal { 4205 polling-delay-passive = <250>; 4206 polling-delay = <0>; 4207 4208 thermal-sensors = <&tsens0 13>; 4209 4210 trips { 4211 gpuss0_alert0: trip-point0 { 4212 temperature = <95000>; 4213 hysteresis = <2000>; 4214 type = "passive"; 4215 }; 4216 4217 gpuss0_crit: gpuss0-crit { 4218 temperature = <110000>; 4219 hysteresis = <2000>; 4220 type = "critical"; 4221 }; 4222 }; 4223 4224 cooling-maps { 4225 map0 { 4226 trip = <&gpuss0_alert0>; 4227 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4228 }; 4229 }; 4230 }; 4231 4232 gpuss1-thermal { 4233 polling-delay-passive = <250>; 4234 polling-delay = <0>; 4235 4236 thermal-sensors = <&tsens0 14>; 4237 4238 trips { 4239 gpuss1_alert0: trip-point0 { 4240 temperature = <95000>; 4241 hysteresis = <2000>; 4242 type = "passive"; 4243 }; 4244 4245 gpuss1_crit: gpuss1-crit { 4246 temperature = <110000>; 4247 hysteresis = <2000>; 4248 type = "critical"; 4249 }; 4250 }; 4251 4252 cooling-maps { 4253 map0 { 4254 trip = <&gpuss1_alert0>; 4255 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4256 }; 4257 }; 4258 }; 4259 4260 aoss1-thermal { 4261 polling-delay-passive = <250>; 4262 polling-delay = <0>; 4263 4264 thermal-sensors = <&tsens1 0>; 4265 4266 trips { 4267 aoss1_alert0: trip-point0 { 4268 temperature = <90000>; 4269 hysteresis = <2000>; 4270 type = "hot"; 4271 }; 4272 4273 aoss1_crit: aoss1-crit { 4274 temperature = <110000>; 4275 hysteresis = <2000>; 4276 type = "critical"; 4277 }; 4278 }; 4279 }; 4280 4281 cwlan-thermal { 4282 polling-delay-passive = <250>; 4283 polling-delay = <0>; 4284 4285 thermal-sensors = <&tsens1 1>; 4286 4287 trips { 4288 cwlan_alert0: trip-point0 { 4289 temperature = <90000>; 4290 hysteresis = <2000>; 4291 type = "hot"; 4292 }; 4293 4294 cwlan_crit: cwlan-crit { 4295 temperature = <110000>; 4296 hysteresis = <2000>; 4297 type = "critical"; 4298 }; 4299 }; 4300 }; 4301 4302 audio-thermal { 4303 polling-delay-passive = <250>; 4304 polling-delay = <0>; 4305 4306 thermal-sensors = <&tsens1 2>; 4307 4308 trips { 4309 audio_alert0: trip-point0 { 4310 temperature = <90000>; 4311 hysteresis = <2000>; 4312 type = "hot"; 4313 }; 4314 4315 audio_crit: audio-crit { 4316 temperature = <110000>; 4317 hysteresis = <2000>; 4318 type = "critical"; 4319 }; 4320 }; 4321 }; 4322 4323 ddr-thermal { 4324 polling-delay-passive = <250>; 4325 polling-delay = <0>; 4326 4327 thermal-sensors = <&tsens1 3>; 4328 4329 trips { 4330 ddr_alert0: trip-point0 { 4331 temperature = <90000>; 4332 hysteresis = <2000>; 4333 type = "hot"; 4334 }; 4335 4336 ddr_crit: ddr-crit { 4337 temperature = <110000>; 4338 hysteresis = <2000>; 4339 type = "critical"; 4340 }; 4341 }; 4342 }; 4343 4344 q6-hvx-thermal { 4345 polling-delay-passive = <250>; 4346 polling-delay = <0>; 4347 4348 thermal-sensors = <&tsens1 4>; 4349 4350 trips { 4351 q6_hvx_alert0: trip-point0 { 4352 temperature = <90000>; 4353 hysteresis = <2000>; 4354 type = "hot"; 4355 }; 4356 4357 q6_hvx_crit: q6-hvx-crit { 4358 temperature = <110000>; 4359 hysteresis = <2000>; 4360 type = "critical"; 4361 }; 4362 }; 4363 }; 4364 4365 camera-thermal { 4366 polling-delay-passive = <250>; 4367 polling-delay = <0>; 4368 4369 thermal-sensors = <&tsens1 5>; 4370 4371 trips { 4372 camera_alert0: trip-point0 { 4373 temperature = <90000>; 4374 hysteresis = <2000>; 4375 type = "hot"; 4376 }; 4377 4378 camera_crit: camera-crit { 4379 temperature = <110000>; 4380 hysteresis = <2000>; 4381 type = "critical"; 4382 }; 4383 }; 4384 }; 4385 4386 mdm-core-thermal { 4387 polling-delay-passive = <250>; 4388 polling-delay = <0>; 4389 4390 thermal-sensors = <&tsens1 6>; 4391 4392 trips { 4393 mdm_alert0: trip-point0 { 4394 temperature = <90000>; 4395 hysteresis = <2000>; 4396 type = "hot"; 4397 }; 4398 4399 mdm_crit: mdm-crit { 4400 temperature = <110000>; 4401 hysteresis = <2000>; 4402 type = "critical"; 4403 }; 4404 }; 4405 }; 4406 4407 mdm-dsp-thermal { 4408 polling-delay-passive = <250>; 4409 polling-delay = <0>; 4410 4411 thermal-sensors = <&tsens1 7>; 4412 4413 trips { 4414 mdm_dsp_alert0: trip-point0 { 4415 temperature = <90000>; 4416 hysteresis = <2000>; 4417 type = "hot"; 4418 }; 4419 4420 mdm_dsp_crit: mdm-dsp-crit { 4421 temperature = <110000>; 4422 hysteresis = <2000>; 4423 type = "critical"; 4424 }; 4425 }; 4426 }; 4427 4428 npu-thermal { 4429 polling-delay-passive = <250>; 4430 polling-delay = <0>; 4431 4432 thermal-sensors = <&tsens1 8>; 4433 4434 trips { 4435 npu_alert0: trip-point0 { 4436 temperature = <90000>; 4437 hysteresis = <2000>; 4438 type = "hot"; 4439 }; 4440 4441 npu_crit: npu-crit { 4442 temperature = <110000>; 4443 hysteresis = <2000>; 4444 type = "critical"; 4445 }; 4446 }; 4447 }; 4448 4449 video-thermal { 4450 polling-delay-passive = <250>; 4451 polling-delay = <0>; 4452 4453 thermal-sensors = <&tsens1 9>; 4454 4455 trips { 4456 video_alert0: trip-point0 { 4457 temperature = <90000>; 4458 hysteresis = <2000>; 4459 type = "hot"; 4460 }; 4461 4462 video_crit: video-crit { 4463 temperature = <110000>; 4464 hysteresis = <2000>; 4465 type = "critical"; 4466 }; 4467 }; 4468 }; 4469 }; 4470 4471 timer { 4472 compatible = "arm,armv8-timer"; 4473 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4474 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4475 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4476 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4477 }; 4478}; 4479