1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7180.h> 13#include <dt-bindings/interconnect/qcom,sc7180.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/phy/phy-qcom-qusb2.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 aliases { 32 i2c0 = &i2c0; 33 i2c1 = &i2c1; 34 i2c2 = &i2c2; 35 i2c3 = &i2c3; 36 i2c4 = &i2c4; 37 i2c5 = &i2c5; 38 i2c6 = &i2c6; 39 i2c7 = &i2c7; 40 i2c8 = &i2c8; 41 i2c9 = &i2c9; 42 i2c10 = &i2c10; 43 i2c11 = &i2c11; 44 spi0 = &spi0; 45 spi1 = &spi1; 46 spi3 = &spi3; 47 spi5 = &spi5; 48 spi6 = &spi6; 49 spi8 = &spi8; 50 spi10 = &spi10; 51 spi11 = &spi11; 52 }; 53 54 clocks { 55 xo_board: xo-board { 56 compatible = "fixed-clock"; 57 clock-frequency = <38400000>; 58 #clock-cells = <0>; 59 }; 60 61 sleep_clk: sleep-clk { 62 compatible = "fixed-clock"; 63 clock-frequency = <32764>; 64 #clock-cells = <0>; 65 }; 66 }; 67 68 reserved_memory: reserved-memory { 69 #address-cells = <2>; 70 #size-cells = <2>; 71 ranges; 72 73 hyp_mem: memory@80000000 { 74 reg = <0x0 0x80000000 0x0 0x600000>; 75 no-map; 76 }; 77 78 xbl_mem: memory@80600000 { 79 reg = <0x0 0x80600000 0x0 0x200000>; 80 no-map; 81 }; 82 83 aop_mem: memory@80800000 { 84 reg = <0x0 0x80800000 0x0 0x20000>; 85 no-map; 86 }; 87 88 aop_cmd_db_mem: memory@80820000 { 89 reg = <0x0 0x80820000 0x0 0x20000>; 90 compatible = "qcom,cmd-db"; 91 no-map; 92 }; 93 94 sec_apps_mem: memory@808ff000 { 95 reg = <0x0 0x808ff000 0x0 0x1000>; 96 no-map; 97 }; 98 99 smem_mem: memory@80900000 { 100 reg = <0x0 0x80900000 0x0 0x200000>; 101 no-map; 102 }; 103 104 tz_mem: memory@80b00000 { 105 reg = <0x0 0x80b00000 0x0 0x3900000>; 106 no-map; 107 }; 108 109 rmtfs_mem: memory@84400000 { 110 compatible = "qcom,rmtfs-mem"; 111 reg = <0x0 0x84400000 0x0 0x200000>; 112 no-map; 113 114 qcom,client-id = <1>; 115 qcom,vmid = <15>; 116 }; 117 }; 118 119 cpus { 120 #address-cells = <2>; 121 #size-cells = <0>; 122 123 CPU0: cpu@0 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo468"; 126 reg = <0x0 0x0>; 127 enable-method = "psci"; 128 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 129 &LITTLE_CPU_SLEEP_1 130 &CLUSTER_SLEEP_0>; 131 capacity-dmips-mhz = <1024>; 132 dynamic-power-coefficient = <100>; 133 next-level-cache = <&L2_0>; 134 #cooling-cells = <2>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 L2_0: l2-cache { 137 compatible = "cache"; 138 next-level-cache = <&L3_0>; 139 L3_0: l3-cache { 140 compatible = "cache"; 141 }; 142 }; 143 }; 144 145 CPU1: cpu@100 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo468"; 148 reg = <0x0 0x100>; 149 enable-method = "psci"; 150 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 151 &LITTLE_CPU_SLEEP_1 152 &CLUSTER_SLEEP_0>; 153 capacity-dmips-mhz = <1024>; 154 dynamic-power-coefficient = <100>; 155 next-level-cache = <&L2_100>; 156 #cooling-cells = <2>; 157 qcom,freq-domain = <&cpufreq_hw 0>; 158 L2_100: l2-cache { 159 compatible = "cache"; 160 next-level-cache = <&L3_0>; 161 }; 162 }; 163 164 CPU2: cpu@200 { 165 device_type = "cpu"; 166 compatible = "qcom,kryo468"; 167 reg = <0x0 0x200>; 168 enable-method = "psci"; 169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 170 &LITTLE_CPU_SLEEP_1 171 &CLUSTER_SLEEP_0>; 172 capacity-dmips-mhz = <1024>; 173 dynamic-power-coefficient = <100>; 174 next-level-cache = <&L2_200>; 175 #cooling-cells = <2>; 176 qcom,freq-domain = <&cpufreq_hw 0>; 177 L2_200: l2-cache { 178 compatible = "cache"; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU3: cpu@300 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo468"; 186 reg = <0x0 0x300>; 187 enable-method = "psci"; 188 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 189 &LITTLE_CPU_SLEEP_1 190 &CLUSTER_SLEEP_0>; 191 capacity-dmips-mhz = <1024>; 192 dynamic-power-coefficient = <100>; 193 next-level-cache = <&L2_300>; 194 #cooling-cells = <2>; 195 qcom,freq-domain = <&cpufreq_hw 0>; 196 L2_300: l2-cache { 197 compatible = "cache"; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU4: cpu@400 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo468"; 205 reg = <0x0 0x400>; 206 enable-method = "psci"; 207 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 208 &LITTLE_CPU_SLEEP_1 209 &CLUSTER_SLEEP_0>; 210 capacity-dmips-mhz = <1024>; 211 dynamic-power-coefficient = <100>; 212 next-level-cache = <&L2_400>; 213 #cooling-cells = <2>; 214 qcom,freq-domain = <&cpufreq_hw 0>; 215 L2_400: l2-cache { 216 compatible = "cache"; 217 next-level-cache = <&L3_0>; 218 }; 219 }; 220 221 CPU5: cpu@500 { 222 device_type = "cpu"; 223 compatible = "qcom,kryo468"; 224 reg = <0x0 0x500>; 225 enable-method = "psci"; 226 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 227 &LITTLE_CPU_SLEEP_1 228 &CLUSTER_SLEEP_0>; 229 capacity-dmips-mhz = <1024>; 230 dynamic-power-coefficient = <100>; 231 next-level-cache = <&L2_500>; 232 #cooling-cells = <2>; 233 qcom,freq-domain = <&cpufreq_hw 0>; 234 L2_500: l2-cache { 235 compatible = "cache"; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU6: cpu@600 { 241 device_type = "cpu"; 242 compatible = "qcom,kryo468"; 243 reg = <0x0 0x600>; 244 enable-method = "psci"; 245 cpu-idle-states = <&BIG_CPU_SLEEP_0 246 &BIG_CPU_SLEEP_1 247 &CLUSTER_SLEEP_0>; 248 capacity-dmips-mhz = <1740>; 249 dynamic-power-coefficient = <405>; 250 next-level-cache = <&L2_600>; 251 #cooling-cells = <2>; 252 qcom,freq-domain = <&cpufreq_hw 1>; 253 L2_600: l2-cache { 254 compatible = "cache"; 255 next-level-cache = <&L3_0>; 256 }; 257 }; 258 259 CPU7: cpu@700 { 260 device_type = "cpu"; 261 compatible = "qcom,kryo468"; 262 reg = <0x0 0x700>; 263 enable-method = "psci"; 264 cpu-idle-states = <&BIG_CPU_SLEEP_0 265 &BIG_CPU_SLEEP_1 266 &CLUSTER_SLEEP_0>; 267 capacity-dmips-mhz = <1740>; 268 dynamic-power-coefficient = <405>; 269 next-level-cache = <&L2_700>; 270 #cooling-cells = <2>; 271 qcom,freq-domain = <&cpufreq_hw 1>; 272 L2_700: l2-cache { 273 compatible = "cache"; 274 next-level-cache = <&L3_0>; 275 }; 276 }; 277 278 cpu-map { 279 cluster0 { 280 core0 { 281 cpu = <&CPU0>; 282 }; 283 284 core1 { 285 cpu = <&CPU1>; 286 }; 287 288 core2 { 289 cpu = <&CPU2>; 290 }; 291 292 core3 { 293 cpu = <&CPU3>; 294 }; 295 296 core4 { 297 cpu = <&CPU4>; 298 }; 299 300 core5 { 301 cpu = <&CPU5>; 302 }; 303 304 core6 { 305 cpu = <&CPU6>; 306 }; 307 308 core7 { 309 cpu = <&CPU7>; 310 }; 311 }; 312 }; 313 314 idle-states { 315 entry-method = "psci"; 316 317 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "little-power-down"; 320 arm,psci-suspend-param = <0x40000003>; 321 entry-latency-us = <549>; 322 exit-latency-us = <901>; 323 min-residency-us = <1774>; 324 local-timer-stop; 325 }; 326 327 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 328 compatible = "arm,idle-state"; 329 idle-state-name = "little-rail-power-down"; 330 arm,psci-suspend-param = <0x40000004>; 331 entry-latency-us = <702>; 332 exit-latency-us = <915>; 333 min-residency-us = <4001>; 334 local-timer-stop; 335 }; 336 337 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 338 compatible = "arm,idle-state"; 339 idle-state-name = "big-power-down"; 340 arm,psci-suspend-param = <0x40000003>; 341 entry-latency-us = <523>; 342 exit-latency-us = <1244>; 343 min-residency-us = <2207>; 344 local-timer-stop; 345 }; 346 347 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 348 compatible = "arm,idle-state"; 349 idle-state-name = "big-rail-power-down"; 350 arm,psci-suspend-param = <0x40000004>; 351 entry-latency-us = <526>; 352 exit-latency-us = <1854>; 353 min-residency-us = <5555>; 354 local-timer-stop; 355 }; 356 357 CLUSTER_SLEEP_0: cluster-sleep-0 { 358 compatible = "arm,idle-state"; 359 idle-state-name = "cluster-power-down"; 360 arm,psci-suspend-param = <0x40003444>; 361 entry-latency-us = <3263>; 362 exit-latency-us = <6562>; 363 min-residency-us = <9926>; 364 local-timer-stop; 365 }; 366 }; 367 }; 368 369 memory@80000000 { 370 device_type = "memory"; 371 /* We expect the bootloader to fill in the size */ 372 reg = <0 0x80000000 0 0>; 373 }; 374 375 pmu { 376 compatible = "arm,armv8-pmuv3"; 377 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 378 }; 379 380 firmware { 381 scm { 382 compatible = "qcom,scm-sc7180", "qcom,scm"; 383 }; 384 }; 385 386 tcsr_mutex: hwlock { 387 compatible = "qcom,tcsr-mutex"; 388 syscon = <&tcsr_mutex_regs 0 0x1000>; 389 #hwlock-cells = <1>; 390 }; 391 392 smem { 393 compatible = "qcom,smem"; 394 memory-region = <&smem_mem>; 395 hwlocks = <&tcsr_mutex 3>; 396 }; 397 398 smp2p-cdsp { 399 compatible = "qcom,smp2p"; 400 qcom,smem = <94>, <432>; 401 402 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 403 404 mboxes = <&apss_shared 6>; 405 406 qcom,local-pid = <0>; 407 qcom,remote-pid = <5>; 408 409 cdsp_smp2p_out: master-kernel { 410 qcom,entry-name = "master-kernel"; 411 #qcom,smem-state-cells = <1>; 412 }; 413 414 cdsp_smp2p_in: slave-kernel { 415 qcom,entry-name = "slave-kernel"; 416 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 }; 420 }; 421 422 smp2p-lpass { 423 compatible = "qcom,smp2p"; 424 qcom,smem = <443>, <429>; 425 426 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 427 428 mboxes = <&apss_shared 10>; 429 430 qcom,local-pid = <0>; 431 qcom,remote-pid = <2>; 432 433 adsp_smp2p_out: master-kernel { 434 qcom,entry-name = "master-kernel"; 435 #qcom,smem-state-cells = <1>; 436 }; 437 438 adsp_smp2p_in: slave-kernel { 439 qcom,entry-name = "slave-kernel"; 440 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 }; 444 }; 445 446 smp2p-mpss { 447 compatible = "qcom,smp2p"; 448 qcom,smem = <435>, <428>; 449 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 450 mboxes = <&apss_shared 14>; 451 qcom,local-pid = <0>; 452 qcom,remote-pid = <1>; 453 454 modem_smp2p_out: master-kernel { 455 qcom,entry-name = "master-kernel"; 456 #qcom,smem-state-cells = <1>; 457 }; 458 459 modem_smp2p_in: slave-kernel { 460 qcom,entry-name = "slave-kernel"; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 }; 464 465 ipa_smp2p_out: ipa-ap-to-modem { 466 qcom,entry-name = "ipa"; 467 #qcom,smem-state-cells = <1>; 468 }; 469 470 ipa_smp2p_in: ipa-modem-to-ap { 471 qcom,entry-name = "ipa"; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 }; 475 }; 476 477 psci { 478 compatible = "arm,psci-1.0"; 479 method = "smc"; 480 }; 481 482 soc: soc@0 { 483 #address-cells = <2>; 484 #size-cells = <2>; 485 ranges = <0 0 0 0 0x10 0>; 486 dma-ranges = <0 0 0 0 0x10 0>; 487 compatible = "simple-bus"; 488 489 gcc: clock-controller@100000 { 490 compatible = "qcom,gcc-sc7180"; 491 reg = <0 0x00100000 0 0x1f0000>; 492 clocks = <&rpmhcc RPMH_CXO_CLK>, 493 <&rpmhcc RPMH_CXO_CLK_A>, 494 <&sleep_clk>; 495 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 496 #clock-cells = <1>; 497 #reset-cells = <1>; 498 #power-domain-cells = <1>; 499 }; 500 501 qfprom@784000 { 502 compatible = "qcom,qfprom"; 503 reg = <0 0x00784000 0 0x8ff>; 504 #address-cells = <1>; 505 #size-cells = <1>; 506 507 qusb2p_hstx_trim: hstx-trim-primary@25b { 508 reg = <0x25b 0x1>; 509 bits = <1 3>; 510 }; 511 }; 512 513 sdhc_1: sdhci@7c4000 { 514 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 515 reg = <0 0x7c4000 0 0x1000>, 516 <0 0x07c5000 0 0x1000>; 517 reg-names = "hc", "cqhci"; 518 519 iommus = <&apps_smmu 0x60 0x0>; 520 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "hc_irq", "pwr_irq"; 523 524 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 525 <&gcc GCC_SDCC1_AHB_CLK>; 526 clock-names = "core", "iface"; 527 528 bus-width = <8>; 529 non-removable; 530 supports-cqe; 531 532 mmc-ddr-1_8v; 533 mmc-hs200-1_8v; 534 mmc-hs400-1_8v; 535 mmc-hs400-enhanced-strobe; 536 537 status = "disabled"; 538 }; 539 540 qupv3_id_0: geniqup@8c0000 { 541 compatible = "qcom,geni-se-qup"; 542 reg = <0 0x008c0000 0 0x6000>; 543 clock-names = "m-ahb", "s-ahb"; 544 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 545 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 546 #address-cells = <2>; 547 #size-cells = <2>; 548 ranges; 549 iommus = <&apps_smmu 0x43 0x0>; 550 status = "disabled"; 551 552 i2c0: i2c@880000 { 553 compatible = "qcom,geni-i2c"; 554 reg = <0 0x00880000 0 0x4000>; 555 clock-names = "se"; 556 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&qup_i2c0_default>; 559 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 status = "disabled"; 563 }; 564 565 spi0: spi@880000 { 566 compatible = "qcom,geni-spi"; 567 reg = <0 0x00880000 0 0x4000>; 568 clock-names = "se"; 569 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&qup_spi0_default>; 572 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 uart0: serial@880000 { 579 compatible = "qcom,geni-uart"; 580 reg = <0 0x00880000 0 0x4000>; 581 clock-names = "se"; 582 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&qup_uart0_default>; 585 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 586 status = "disabled"; 587 }; 588 589 i2c1: i2c@884000 { 590 compatible = "qcom,geni-i2c"; 591 reg = <0 0x00884000 0 0x4000>; 592 clock-names = "se"; 593 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&qup_i2c1_default>; 596 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 spi1: spi@884000 { 603 compatible = "qcom,geni-spi"; 604 reg = <0 0x00884000 0 0x4000>; 605 clock-names = "se"; 606 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&qup_spi1_default>; 609 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 status = "disabled"; 613 }; 614 615 uart1: serial@884000 { 616 compatible = "qcom,geni-uart"; 617 reg = <0 0x00884000 0 0x4000>; 618 clock-names = "se"; 619 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&qup_uart1_default>; 622 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 623 status = "disabled"; 624 }; 625 626 i2c2: i2c@888000 { 627 compatible = "qcom,geni-i2c"; 628 reg = <0 0x00888000 0 0x4000>; 629 clock-names = "se"; 630 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&qup_i2c2_default>; 633 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 status = "disabled"; 637 }; 638 639 uart2: serial@888000 { 640 compatible = "qcom,geni-uart"; 641 reg = <0 0x00888000 0 0x4000>; 642 clock-names = "se"; 643 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&qup_uart2_default>; 646 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 647 status = "disabled"; 648 }; 649 650 i2c3: i2c@88c000 { 651 compatible = "qcom,geni-i2c"; 652 reg = <0 0x0088c000 0 0x4000>; 653 clock-names = "se"; 654 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&qup_i2c3_default>; 657 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 663 spi3: spi@88c000 { 664 compatible = "qcom,geni-spi"; 665 reg = <0 0x0088c000 0 0x4000>; 666 clock-names = "se"; 667 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&qup_spi3_default>; 670 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 status = "disabled"; 674 }; 675 676 uart3: serial@88c000 { 677 compatible = "qcom,geni-uart"; 678 reg = <0 0x0088c000 0 0x4000>; 679 clock-names = "se"; 680 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_uart3_default>; 683 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 684 status = "disabled"; 685 }; 686 687 i2c4: i2c@890000 { 688 compatible = "qcom,geni-i2c"; 689 reg = <0 0x00890000 0 0x4000>; 690 clock-names = "se"; 691 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&qup_i2c4_default>; 694 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 status = "disabled"; 698 }; 699 700 uart4: serial@890000 { 701 compatible = "qcom,geni-uart"; 702 reg = <0 0x00890000 0 0x4000>; 703 clock-names = "se"; 704 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&qup_uart4_default>; 707 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 708 status = "disabled"; 709 }; 710 711 i2c5: i2c@894000 { 712 compatible = "qcom,geni-i2c"; 713 reg = <0 0x00894000 0 0x4000>; 714 clock-names = "se"; 715 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&qup_i2c5_default>; 718 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 status = "disabled"; 722 }; 723 724 spi5: spi@894000 { 725 compatible = "qcom,geni-spi"; 726 reg = <0 0x00894000 0 0x4000>; 727 clock-names = "se"; 728 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&qup_spi5_default>; 731 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 }; 736 737 uart5: serial@894000 { 738 compatible = "qcom,geni-uart"; 739 reg = <0 0x00894000 0 0x4000>; 740 clock-names = "se"; 741 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&qup_uart5_default>; 744 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 745 status = "disabled"; 746 }; 747 }; 748 749 qupv3_id_1: geniqup@ac0000 { 750 compatible = "qcom,geni-se-qup"; 751 reg = <0 0x00ac0000 0 0x6000>; 752 clock-names = "m-ahb", "s-ahb"; 753 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 754 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 755 #address-cells = <2>; 756 #size-cells = <2>; 757 ranges; 758 iommus = <&apps_smmu 0x4c3 0x0>; 759 status = "disabled"; 760 761 i2c6: i2c@a80000 { 762 compatible = "qcom,geni-i2c"; 763 reg = <0 0x00a80000 0 0x4000>; 764 clock-names = "se"; 765 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&qup_i2c6_default>; 768 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 spi6: spi@a80000 { 775 compatible = "qcom,geni-spi"; 776 reg = <0 0x00a80000 0 0x4000>; 777 clock-names = "se"; 778 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&qup_spi6_default>; 781 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 status = "disabled"; 785 }; 786 787 uart6: serial@a80000 { 788 compatible = "qcom,geni-uart"; 789 reg = <0 0x00a80000 0 0x4000>; 790 clock-names = "se"; 791 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&qup_uart6_default>; 794 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 795 status = "disabled"; 796 }; 797 798 i2c7: i2c@a84000 { 799 compatible = "qcom,geni-i2c"; 800 reg = <0 0x00a84000 0 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_i2c7_default>; 805 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 uart7: serial@a84000 { 812 compatible = "qcom,geni-uart"; 813 reg = <0 0x00a84000 0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&qup_uart7_default>; 818 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 819 status = "disabled"; 820 }; 821 822 i2c8: i2c@a88000 { 823 compatible = "qcom,geni-i2c"; 824 reg = <0 0x00a88000 0 0x4000>; 825 clock-names = "se"; 826 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&qup_i2c8_default>; 829 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 status = "disabled"; 833 }; 834 835 spi8: spi@a88000 { 836 compatible = "qcom,geni-spi"; 837 reg = <0 0x00a88000 0 0x4000>; 838 clock-names = "se"; 839 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 840 pinctrl-names = "default"; 841 pinctrl-0 = <&qup_spi8_default>; 842 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 status = "disabled"; 846 }; 847 848 uart8: serial@a88000 { 849 compatible = "qcom,geni-debug-uart"; 850 reg = <0 0x00a88000 0 0x4000>; 851 clock-names = "se"; 852 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&qup_uart8_default>; 855 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 856 status = "disabled"; 857 }; 858 859 i2c9: i2c@a8c000 { 860 compatible = "qcom,geni-i2c"; 861 reg = <0 0x00a8c000 0 0x4000>; 862 clock-names = "se"; 863 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&qup_i2c9_default>; 866 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 uart9: serial@a8c000 { 873 compatible = "qcom,geni-uart"; 874 reg = <0 0x00a8c000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&qup_uart9_default>; 879 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 880 status = "disabled"; 881 }; 882 883 i2c10: i2c@a90000 { 884 compatible = "qcom,geni-i2c"; 885 reg = <0 0x00a90000 0 0x4000>; 886 clock-names = "se"; 887 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&qup_i2c10_default>; 890 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 status = "disabled"; 894 }; 895 896 spi10: spi@a90000 { 897 compatible = "qcom,geni-spi"; 898 reg = <0 0x00a90000 0 0x4000>; 899 clock-names = "se"; 900 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 901 pinctrl-names = "default"; 902 pinctrl-0 = <&qup_spi10_default>; 903 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 status = "disabled"; 907 }; 908 909 uart10: serial@a90000 { 910 compatible = "qcom,geni-uart"; 911 reg = <0 0x00a90000 0 0x4000>; 912 clock-names = "se"; 913 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&qup_uart10_default>; 916 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 917 status = "disabled"; 918 }; 919 920 i2c11: i2c@a94000 { 921 compatible = "qcom,geni-i2c"; 922 reg = <0 0x00a94000 0 0x4000>; 923 clock-names = "se"; 924 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&qup_i2c11_default>; 927 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 933 spi11: spi@a94000 { 934 compatible = "qcom,geni-spi"; 935 reg = <0 0x00a94000 0 0x4000>; 936 clock-names = "se"; 937 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&qup_spi11_default>; 940 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 }; 945 946 uart11: serial@a94000 { 947 compatible = "qcom,geni-uart"; 948 reg = <0 0x00a94000 0 0x4000>; 949 clock-names = "se"; 950 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_uart11_default>; 953 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 954 status = "disabled"; 955 }; 956 }; 957 958 config_noc: interconnect@1500000 { 959 compatible = "qcom,sc7180-config-noc"; 960 reg = <0 0x01500000 0 0x28000>; 961 #interconnect-cells = <1>; 962 qcom,bcm-voters = <&apps_bcm_voter>; 963 }; 964 965 system_noc: interconnect@1620000 { 966 compatible = "qcom,sc7180-system-noc"; 967 reg = <0 0x01620000 0 0x17080>; 968 #interconnect-cells = <1>; 969 qcom,bcm-voters = <&apps_bcm_voter>; 970 }; 971 972 mc_virt: interconnect@1638000 { 973 compatible = "qcom,sc7180-mc-virt"; 974 reg = <0 0x01638000 0 0x1000>; 975 #interconnect-cells = <1>; 976 qcom,bcm-voters = <&apps_bcm_voter>; 977 }; 978 979 qup_virt: interconnect@1650000 { 980 compatible = "qcom,sc7180-qup-virt"; 981 reg = <0 0x01650000 0 0x1000>; 982 #interconnect-cells = <1>; 983 qcom,bcm-voters = <&apps_bcm_voter>; 984 }; 985 986 aggre1_noc: interconnect@16e0000 { 987 compatible = "qcom,sc7180-aggre1-noc"; 988 reg = <0 0x016e0000 0 0x15080>; 989 #interconnect-cells = <1>; 990 qcom,bcm-voters = <&apps_bcm_voter>; 991 }; 992 993 aggre2_noc: interconnect@1705000 { 994 compatible = "qcom,sc7180-aggre2-noc"; 995 reg = <0 0x01705000 0 0x9000>; 996 #interconnect-cells = <1>; 997 qcom,bcm-voters = <&apps_bcm_voter>; 998 }; 999 1000 compute_noc: interconnect@170e000 { 1001 compatible = "qcom,sc7180-compute-noc"; 1002 reg = <0 0x0170e000 0 0x6000>; 1003 #interconnect-cells = <1>; 1004 qcom,bcm-voters = <&apps_bcm_voter>; 1005 }; 1006 1007 mmss_noc: interconnect@1740000 { 1008 compatible = "qcom,sc7180-mmss-noc"; 1009 reg = <0 0x01740000 0 0x1c100>; 1010 #interconnect-cells = <1>; 1011 qcom,bcm-voters = <&apps_bcm_voter>; 1012 }; 1013 1014 ipa_virt: interconnect@1e00000 { 1015 compatible = "qcom,sc7180-ipa-virt"; 1016 reg = <0 0x01e00000 0 0x1000>; 1017 #interconnect-cells = <1>; 1018 qcom,bcm-voters = <&apps_bcm_voter>; 1019 }; 1020 1021 ipa: ipa@1e40000 { 1022 compatible = "qcom,sc7180-ipa"; 1023 1024 iommus = <&apps_smmu 0x440 0x3>; 1025 reg = <0 0x1e40000 0 0x7000>, 1026 <0 0x1e47000 0 0x2000>, 1027 <0 0x1e04000 0 0x2c000>; 1028 reg-names = "ipa-reg", 1029 "ipa-shared", 1030 "gsi"; 1031 1032 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 1033 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 1034 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1035 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1036 interrupt-names = "ipa", 1037 "gsi", 1038 "ipa-clock-query", 1039 "ipa-setup-ready"; 1040 1041 clocks = <&rpmhcc RPMH_IPA_CLK>; 1042 clock-names = "core"; 1043 1044 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 1045 <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, 1046 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 1047 interconnect-names = "memory", 1048 "imem", 1049 "config"; 1050 1051 qcom,smem-states = <&ipa_smp2p_out 0>, 1052 <&ipa_smp2p_out 1>; 1053 qcom,smem-state-names = "ipa-clock-enabled-valid", 1054 "ipa-clock-enabled"; 1055 1056 modem-remoteproc = <&remoteproc_mpss>; 1057 1058 status = "disabled"; 1059 }; 1060 1061 tcsr_mutex_regs: syscon@1f40000 { 1062 compatible = "syscon"; 1063 reg = <0 0x01f40000 0 0x40000>; 1064 }; 1065 1066 tcsr_regs: syscon@1fc0000 { 1067 compatible = "syscon"; 1068 reg = <0 0x01fc0000 0 0x40000>; 1069 }; 1070 1071 tlmm: pinctrl@3500000 { 1072 compatible = "qcom,sc7180-pinctrl"; 1073 reg = <0 0x03500000 0 0x300000>, 1074 <0 0x03900000 0 0x300000>, 1075 <0 0x03d00000 0 0x300000>; 1076 reg-names = "west", "north", "south"; 1077 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1078 gpio-controller; 1079 #gpio-cells = <2>; 1080 interrupt-controller; 1081 #interrupt-cells = <2>; 1082 gpio-ranges = <&tlmm 0 0 120>; 1083 wakeup-parent = <&pdc>; 1084 1085 qspi_clk: qspi-clk { 1086 pinmux { 1087 pins = "gpio63"; 1088 function = "qspi_clk"; 1089 }; 1090 }; 1091 1092 qspi_cs0: qspi-cs0 { 1093 pinmux { 1094 pins = "gpio68"; 1095 function = "qspi_cs"; 1096 }; 1097 }; 1098 1099 qspi_cs1: qspi-cs1 { 1100 pinmux { 1101 pins = "gpio72"; 1102 function = "qspi_cs"; 1103 }; 1104 }; 1105 1106 qspi_data01: qspi-data01 { 1107 pinmux-data { 1108 pins = "gpio64", "gpio65"; 1109 function = "qspi_data"; 1110 }; 1111 }; 1112 1113 qspi_data12: qspi-data12 { 1114 pinmux-data { 1115 pins = "gpio66", "gpio67"; 1116 function = "qspi_data"; 1117 }; 1118 }; 1119 1120 qup_i2c0_default: qup-i2c0-default { 1121 pinmux { 1122 pins = "gpio34", "gpio35"; 1123 function = "qup00"; 1124 }; 1125 }; 1126 1127 qup_i2c1_default: qup-i2c1-default { 1128 pinmux { 1129 pins = "gpio0", "gpio1"; 1130 function = "qup01"; 1131 }; 1132 }; 1133 1134 qup_i2c2_default: qup-i2c2-default { 1135 pinmux { 1136 pins = "gpio15", "gpio16"; 1137 function = "qup02_i2c"; 1138 }; 1139 }; 1140 1141 qup_i2c3_default: qup-i2c3-default { 1142 pinmux { 1143 pins = "gpio38", "gpio39"; 1144 function = "qup03"; 1145 }; 1146 }; 1147 1148 qup_i2c4_default: qup-i2c4-default { 1149 pinmux { 1150 pins = "gpio115", "gpio116"; 1151 function = "qup04_i2c"; 1152 }; 1153 }; 1154 1155 qup_i2c5_default: qup-i2c5-default { 1156 pinmux { 1157 pins = "gpio25", "gpio26"; 1158 function = "qup05"; 1159 }; 1160 }; 1161 1162 qup_i2c6_default: qup-i2c6-default { 1163 pinmux { 1164 pins = "gpio59", "gpio60"; 1165 function = "qup10"; 1166 }; 1167 }; 1168 1169 qup_i2c7_default: qup-i2c7-default { 1170 pinmux { 1171 pins = "gpio6", "gpio7"; 1172 function = "qup11_i2c"; 1173 }; 1174 }; 1175 1176 qup_i2c8_default: qup-i2c8-default { 1177 pinmux { 1178 pins = "gpio42", "gpio43"; 1179 function = "qup12"; 1180 }; 1181 }; 1182 1183 qup_i2c9_default: qup-i2c9-default { 1184 pinmux { 1185 pins = "gpio46", "gpio47"; 1186 function = "qup13_i2c"; 1187 }; 1188 }; 1189 1190 qup_i2c10_default: qup-i2c10-default { 1191 pinmux { 1192 pins = "gpio86", "gpio87"; 1193 function = "qup14"; 1194 }; 1195 }; 1196 1197 qup_i2c11_default: qup-i2c11-default { 1198 pinmux { 1199 pins = "gpio53", "gpio54"; 1200 function = "qup15"; 1201 }; 1202 }; 1203 1204 qup_spi0_default: qup-spi0-default { 1205 pinmux { 1206 pins = "gpio34", "gpio35", 1207 "gpio36", "gpio37"; 1208 function = "qup00"; 1209 }; 1210 }; 1211 1212 qup_spi1_default: qup-spi1-default { 1213 pinmux { 1214 pins = "gpio0", "gpio1", 1215 "gpio2", "gpio3"; 1216 function = "qup01"; 1217 }; 1218 }; 1219 1220 qup_spi3_default: qup-spi3-default { 1221 pinmux { 1222 pins = "gpio38", "gpio39", 1223 "gpio40", "gpio41"; 1224 function = "qup03"; 1225 }; 1226 }; 1227 1228 qup_spi5_default: qup-spi5-default { 1229 pinmux { 1230 pins = "gpio25", "gpio26", 1231 "gpio27", "gpio28"; 1232 function = "qup05"; 1233 }; 1234 }; 1235 1236 qup_spi6_default: qup-spi6-default { 1237 pinmux { 1238 pins = "gpio59", "gpio60", 1239 "gpio61", "gpio62"; 1240 function = "qup10"; 1241 }; 1242 }; 1243 1244 qup_spi8_default: qup-spi8-default { 1245 pinmux { 1246 pins = "gpio42", "gpio43", 1247 "gpio44", "gpio45"; 1248 function = "qup12"; 1249 }; 1250 }; 1251 1252 qup_spi10_default: qup-spi10-default { 1253 pinmux { 1254 pins = "gpio86", "gpio87", 1255 "gpio88", "gpio89"; 1256 function = "qup14"; 1257 }; 1258 }; 1259 1260 qup_spi11_default: qup-spi11-default { 1261 pinmux { 1262 pins = "gpio53", "gpio54", 1263 "gpio55", "gpio56"; 1264 function = "qup15"; 1265 }; 1266 }; 1267 1268 qup_uart0_default: qup-uart0-default { 1269 pinmux { 1270 pins = "gpio34", "gpio35", 1271 "gpio36", "gpio37"; 1272 function = "qup00"; 1273 }; 1274 }; 1275 1276 qup_uart1_default: qup-uart1-default { 1277 pinmux { 1278 pins = "gpio0", "gpio1", 1279 "gpio2", "gpio3"; 1280 function = "qup01"; 1281 }; 1282 }; 1283 1284 qup_uart2_default: qup-uart2-default { 1285 pinmux { 1286 pins = "gpio15", "gpio16"; 1287 function = "qup02_uart"; 1288 }; 1289 }; 1290 1291 qup_uart3_default: qup-uart3-default { 1292 pinmux { 1293 pins = "gpio38", "gpio39", 1294 "gpio40", "gpio41"; 1295 function = "qup03"; 1296 }; 1297 }; 1298 1299 qup_uart4_default: qup-uart4-default { 1300 pinmux { 1301 pins = "gpio115", "gpio116"; 1302 function = "qup04_uart"; 1303 }; 1304 }; 1305 1306 qup_uart5_default: qup-uart5-default { 1307 pinmux { 1308 pins = "gpio25", "gpio26", 1309 "gpio27", "gpio28"; 1310 function = "qup05"; 1311 }; 1312 }; 1313 1314 qup_uart6_default: qup-uart6-default { 1315 pinmux { 1316 pins = "gpio59", "gpio60", 1317 "gpio61", "gpio62"; 1318 function = "qup10"; 1319 }; 1320 }; 1321 1322 qup_uart7_default: qup-uart7-default { 1323 pinmux { 1324 pins = "gpio6", "gpio7"; 1325 function = "qup11_uart"; 1326 }; 1327 }; 1328 1329 qup_uart8_default: qup-uart8-default { 1330 pinmux { 1331 pins = "gpio44", "gpio45"; 1332 function = "qup12"; 1333 }; 1334 }; 1335 1336 qup_uart9_default: qup-uart9-default { 1337 pinmux { 1338 pins = "gpio46", "gpio47"; 1339 function = "qup13_uart"; 1340 }; 1341 }; 1342 1343 qup_uart10_default: qup-uart10-default { 1344 pinmux { 1345 pins = "gpio86", "gpio87", 1346 "gpio88", "gpio89"; 1347 function = "qup14"; 1348 }; 1349 }; 1350 1351 qup_uart11_default: qup-uart11-default { 1352 pinmux { 1353 pins = "gpio53", "gpio54", 1354 "gpio55", "gpio56"; 1355 function = "qup15"; 1356 }; 1357 }; 1358 1359 sdc1_on: sdc1-on { 1360 pinconf-clk { 1361 pins = "sdc1_clk"; 1362 bias-disable; 1363 drive-strength = <16>; 1364 }; 1365 1366 pinconf-cmd { 1367 pins = "sdc1_cmd"; 1368 bias-pull-up; 1369 drive-strength = <10>; 1370 }; 1371 1372 pinconf-data { 1373 pins = "sdc1_data"; 1374 bias-pull-up; 1375 drive-strength = <10>; 1376 }; 1377 1378 pinconf-rclk { 1379 pins = "sdc1_rclk"; 1380 bias-pull-down; 1381 }; 1382 }; 1383 1384 sdc1_off: sdc1-off { 1385 pinconf-clk { 1386 pins = "sdc1_clk"; 1387 bias-disable; 1388 drive-strength = <2>; 1389 }; 1390 1391 pinconf-cmd { 1392 pins = "sdc1_cmd"; 1393 bias-pull-up; 1394 drive-strength = <2>; 1395 }; 1396 1397 pinconf-data { 1398 pins = "sdc1_data"; 1399 bias-pull-up; 1400 drive-strength = <2>; 1401 }; 1402 1403 pinconf-rclk { 1404 pins = "sdc1_rclk"; 1405 bias-pull-down; 1406 }; 1407 }; 1408 1409 sdc2_on: sdc2-on { 1410 pinconf-clk { 1411 pins = "sdc2_clk"; 1412 bias-disable; 1413 drive-strength = <16>; 1414 }; 1415 1416 pinconf-cmd { 1417 pins = "sdc2_cmd"; 1418 bias-pull-up; 1419 drive-strength = <10>; 1420 }; 1421 1422 pinconf-data { 1423 pins = "sdc2_data"; 1424 bias-pull-up; 1425 drive-strength = <10>; 1426 }; 1427 1428 pinconf-sd-cd { 1429 pins = "gpio69"; 1430 bias-pull-up; 1431 drive-strength = <2>; 1432 }; 1433 }; 1434 1435 sdc2_off: sdc2-off { 1436 pinconf-clk { 1437 pins = "sdc2_clk"; 1438 bias-disable; 1439 drive-strength = <2>; 1440 }; 1441 1442 pinconf-cmd { 1443 pins = "sdc2_cmd"; 1444 bias-pull-up; 1445 drive-strength = <2>; 1446 }; 1447 1448 pinconf-data { 1449 pins = "sdc2_data"; 1450 bias-pull-up; 1451 drive-strength = <2>; 1452 }; 1453 1454 pinconf-sd-cd { 1455 pins = "gpio69"; 1456 bias-disable; 1457 drive-strength = <2>; 1458 }; 1459 }; 1460 }; 1461 1462 gpu: gpu@5000000 { 1463 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1464 #stream-id-cells = <16>; 1465 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1466 <0 0x05061000 0 0x800>; 1467 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1468 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1469 iommus = <&adreno_smmu 0>; 1470 operating-points-v2 = <&gpu_opp_table>; 1471 qcom,gmu = <&gmu>; 1472 1473 gpu_opp_table: opp-table { 1474 compatible = "operating-points-v2"; 1475 1476 opp-800000000 { 1477 opp-hz = /bits/ 64 <800000000>; 1478 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1479 }; 1480 1481 opp-650000000 { 1482 opp-hz = /bits/ 64 <650000000>; 1483 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1484 }; 1485 1486 opp-565000000 { 1487 opp-hz = /bits/ 64 <565000000>; 1488 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1489 }; 1490 1491 opp-430000000 { 1492 opp-hz = /bits/ 64 <430000000>; 1493 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1494 }; 1495 1496 opp-355000000 { 1497 opp-hz = /bits/ 64 <355000000>; 1498 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1499 }; 1500 1501 opp-267000000 { 1502 opp-hz = /bits/ 64 <267000000>; 1503 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1504 }; 1505 1506 opp-180000000 { 1507 opp-hz = /bits/ 64 <180000000>; 1508 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1509 }; 1510 }; 1511 }; 1512 1513 adreno_smmu: iommu@5040000 { 1514 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; 1515 reg = <0 0x05040000 0 0x10000>; 1516 #iommu-cells = <1>; 1517 #global-interrupts = <2>; 1518 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 1521 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 1522 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 1523 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 1524 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 1525 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 1526 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 1527 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 1528 1529 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1530 <&gcc GCC_GPU_CFG_AHB_CLK>; 1531 clock-names = "bus", "iface"; 1532 1533 power-domains = <&gpucc CX_GDSC>; 1534 }; 1535 1536 gmu: gmu@506a000 { 1537 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 1538 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 1539 <0 0x0b490000 0 0x10000>; 1540 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1541 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1543 interrupt-names = "hfi", "gmu"; 1544 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1545 <&gpucc GPU_CC_CXO_CLK>, 1546 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1547 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1548 clock-names = "gmu", "cxo", "axi", "memnoc"; 1549 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 1550 power-domain-names = "cx", "gx"; 1551 iommus = <&adreno_smmu 5>; 1552 operating-points-v2 = <&gmu_opp_table>; 1553 1554 gmu_opp_table: opp-table { 1555 compatible = "operating-points-v2"; 1556 1557 opp-200000000 { 1558 opp-hz = /bits/ 64 <200000000>; 1559 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1560 }; 1561 }; 1562 }; 1563 1564 gpucc: clock-controller@5090000 { 1565 compatible = "qcom,sc7180-gpucc"; 1566 reg = <0 0x05090000 0 0x9000>; 1567 clocks = <&rpmhcc RPMH_CXO_CLK>, 1568 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1569 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1570 clock-names = "bi_tcxo", 1571 "gcc_gpu_gpll0_clk_src", 1572 "gcc_gpu_gpll0_div_clk_src"; 1573 #clock-cells = <1>; 1574 #reset-cells = <1>; 1575 #power-domain-cells = <1>; 1576 }; 1577 1578 stm@6002000 { 1579 compatible = "arm,coresight-stm", "arm,primecell"; 1580 reg = <0 0x06002000 0 0x1000>, 1581 <0 0x16280000 0 0x180000>; 1582 reg-names = "stm-base", "stm-stimulus-base"; 1583 1584 clocks = <&aoss_qmp>; 1585 clock-names = "apb_pclk"; 1586 1587 out-ports { 1588 port { 1589 stm_out: endpoint { 1590 remote-endpoint = <&funnel0_in7>; 1591 }; 1592 }; 1593 }; 1594 }; 1595 1596 funnel@6041000 { 1597 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1598 reg = <0 0x06041000 0 0x1000>; 1599 1600 clocks = <&aoss_qmp>; 1601 clock-names = "apb_pclk"; 1602 1603 out-ports { 1604 port { 1605 funnel0_out: endpoint { 1606 remote-endpoint = <&merge_funnel_in0>; 1607 }; 1608 }; 1609 }; 1610 1611 in-ports { 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 1615 port@7 { 1616 reg = <7>; 1617 funnel0_in7: endpoint { 1618 remote-endpoint = <&stm_out>; 1619 }; 1620 }; 1621 }; 1622 }; 1623 1624 funnel@6042000 { 1625 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1626 reg = <0 0x06042000 0 0x1000>; 1627 1628 clocks = <&aoss_qmp>; 1629 clock-names = "apb_pclk"; 1630 1631 out-ports { 1632 port { 1633 funnel1_out: endpoint { 1634 remote-endpoint = <&merge_funnel_in1>; 1635 }; 1636 }; 1637 }; 1638 1639 in-ports { 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 1643 port@4 { 1644 reg = <4>; 1645 funnel1_in4: endpoint { 1646 remote-endpoint = <&apss_merge_funnel_out>; 1647 }; 1648 }; 1649 }; 1650 }; 1651 1652 funnel@6045000 { 1653 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1654 reg = <0 0x06045000 0 0x1000>; 1655 1656 clocks = <&aoss_qmp>; 1657 clock-names = "apb_pclk"; 1658 1659 out-ports { 1660 port { 1661 merge_funnel_out: endpoint { 1662 remote-endpoint = <&swao_funnel_in>; 1663 }; 1664 }; 1665 }; 1666 1667 in-ports { 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 1671 port@0 { 1672 reg = <0>; 1673 merge_funnel_in0: endpoint { 1674 remote-endpoint = <&funnel0_out>; 1675 }; 1676 }; 1677 1678 port@1 { 1679 reg = <1>; 1680 merge_funnel_in1: endpoint { 1681 remote-endpoint = <&funnel1_out>; 1682 }; 1683 }; 1684 }; 1685 }; 1686 1687 replicator@6046000 { 1688 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1689 reg = <0 0x06046000 0 0x1000>; 1690 1691 clocks = <&aoss_qmp>; 1692 clock-names = "apb_pclk"; 1693 1694 out-ports { 1695 port { 1696 replicator_out: endpoint { 1697 remote-endpoint = <&etr_in>; 1698 }; 1699 }; 1700 }; 1701 1702 in-ports { 1703 port { 1704 replicator_in: endpoint { 1705 remote-endpoint = <&swao_replicator_out>; 1706 }; 1707 }; 1708 }; 1709 }; 1710 1711 etr@6048000 { 1712 compatible = "arm,coresight-tmc", "arm,primecell"; 1713 reg = <0 0x06048000 0 0x1000>; 1714 1715 clocks = <&aoss_qmp>; 1716 clock-names = "apb_pclk"; 1717 arm,scatter-gather; 1718 1719 in-ports { 1720 port { 1721 etr_in: endpoint { 1722 remote-endpoint = <&replicator_out>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 funnel@6b04000 { 1729 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1730 reg = <0 0x06b04000 0 0x1000>; 1731 1732 clocks = <&aoss_qmp>; 1733 clock-names = "apb_pclk"; 1734 1735 out-ports { 1736 port { 1737 swao_funnel_out: endpoint { 1738 remote-endpoint = <&etf_in>; 1739 }; 1740 }; 1741 }; 1742 1743 in-ports { 1744 #address-cells = <1>; 1745 #size-cells = <0>; 1746 1747 port@7 { 1748 reg = <7>; 1749 swao_funnel_in: endpoint { 1750 remote-endpoint = <&merge_funnel_out>; 1751 }; 1752 }; 1753 }; 1754 }; 1755 1756 etf@6b05000 { 1757 compatible = "arm,coresight-tmc", "arm,primecell"; 1758 reg = <0 0x06b05000 0 0x1000>; 1759 1760 clocks = <&aoss_qmp>; 1761 clock-names = "apb_pclk"; 1762 1763 out-ports { 1764 port { 1765 etf_out: endpoint { 1766 remote-endpoint = <&swao_replicator_in>; 1767 }; 1768 }; 1769 }; 1770 1771 in-ports { 1772 port { 1773 etf_in: endpoint { 1774 remote-endpoint = <&swao_funnel_out>; 1775 }; 1776 }; 1777 }; 1778 }; 1779 1780 replicator@6b06000 { 1781 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1782 reg = <0 0x06b06000 0 0x1000>; 1783 1784 clocks = <&aoss_qmp>; 1785 clock-names = "apb_pclk"; 1786 1787 out-ports { 1788 port { 1789 swao_replicator_out: endpoint { 1790 remote-endpoint = <&replicator_in>; 1791 }; 1792 }; 1793 }; 1794 1795 in-ports { 1796 port { 1797 swao_replicator_in: endpoint { 1798 remote-endpoint = <&etf_out>; 1799 }; 1800 }; 1801 }; 1802 }; 1803 1804 etm@7040000 { 1805 compatible = "arm,coresight-etm4x", "arm,primecell"; 1806 reg = <0 0x07040000 0 0x1000>; 1807 1808 cpu = <&CPU0>; 1809 1810 clocks = <&aoss_qmp>; 1811 clock-names = "apb_pclk"; 1812 arm,coresight-loses-context-with-cpu; 1813 1814 out-ports { 1815 port { 1816 etm0_out: endpoint { 1817 remote-endpoint = <&apss_funnel_in0>; 1818 }; 1819 }; 1820 }; 1821 }; 1822 1823 etm@7140000 { 1824 compatible = "arm,coresight-etm4x", "arm,primecell"; 1825 reg = <0 0x07140000 0 0x1000>; 1826 1827 cpu = <&CPU1>; 1828 1829 clocks = <&aoss_qmp>; 1830 clock-names = "apb_pclk"; 1831 arm,coresight-loses-context-with-cpu; 1832 1833 out-ports { 1834 port { 1835 etm1_out: endpoint { 1836 remote-endpoint = <&apss_funnel_in1>; 1837 }; 1838 }; 1839 }; 1840 }; 1841 1842 etm@7240000 { 1843 compatible = "arm,coresight-etm4x", "arm,primecell"; 1844 reg = <0 0x07240000 0 0x1000>; 1845 1846 cpu = <&CPU2>; 1847 1848 clocks = <&aoss_qmp>; 1849 clock-names = "apb_pclk"; 1850 arm,coresight-loses-context-with-cpu; 1851 1852 out-ports { 1853 port { 1854 etm2_out: endpoint { 1855 remote-endpoint = <&apss_funnel_in2>; 1856 }; 1857 }; 1858 }; 1859 }; 1860 1861 etm@7340000 { 1862 compatible = "arm,coresight-etm4x", "arm,primecell"; 1863 reg = <0 0x07340000 0 0x1000>; 1864 1865 cpu = <&CPU3>; 1866 1867 clocks = <&aoss_qmp>; 1868 clock-names = "apb_pclk"; 1869 arm,coresight-loses-context-with-cpu; 1870 1871 out-ports { 1872 port { 1873 etm3_out: endpoint { 1874 remote-endpoint = <&apss_funnel_in3>; 1875 }; 1876 }; 1877 }; 1878 }; 1879 1880 etm@7440000 { 1881 compatible = "arm,coresight-etm4x", "arm,primecell"; 1882 reg = <0 0x07440000 0 0x1000>; 1883 1884 cpu = <&CPU4>; 1885 1886 clocks = <&aoss_qmp>; 1887 clock-names = "apb_pclk"; 1888 arm,coresight-loses-context-with-cpu; 1889 1890 out-ports { 1891 port { 1892 etm4_out: endpoint { 1893 remote-endpoint = <&apss_funnel_in4>; 1894 }; 1895 }; 1896 }; 1897 }; 1898 1899 etm@7540000 { 1900 compatible = "arm,coresight-etm4x", "arm,primecell"; 1901 reg = <0 0x07540000 0 0x1000>; 1902 1903 cpu = <&CPU5>; 1904 1905 clocks = <&aoss_qmp>; 1906 clock-names = "apb_pclk"; 1907 arm,coresight-loses-context-with-cpu; 1908 1909 out-ports { 1910 port { 1911 etm5_out: endpoint { 1912 remote-endpoint = <&apss_funnel_in5>; 1913 }; 1914 }; 1915 }; 1916 }; 1917 1918 etm@7640000 { 1919 compatible = "arm,coresight-etm4x", "arm,primecell"; 1920 reg = <0 0x07640000 0 0x1000>; 1921 1922 cpu = <&CPU6>; 1923 1924 clocks = <&aoss_qmp>; 1925 clock-names = "apb_pclk"; 1926 arm,coresight-loses-context-with-cpu; 1927 1928 out-ports { 1929 port { 1930 etm6_out: endpoint { 1931 remote-endpoint = <&apss_funnel_in6>; 1932 }; 1933 }; 1934 }; 1935 }; 1936 1937 etm@7740000 { 1938 compatible = "arm,coresight-etm4x", "arm,primecell"; 1939 reg = <0 0x07740000 0 0x1000>; 1940 1941 cpu = <&CPU7>; 1942 1943 clocks = <&aoss_qmp>; 1944 clock-names = "apb_pclk"; 1945 arm,coresight-loses-context-with-cpu; 1946 1947 out-ports { 1948 port { 1949 etm7_out: endpoint { 1950 remote-endpoint = <&apss_funnel_in7>; 1951 }; 1952 }; 1953 }; 1954 }; 1955 1956 funnel@7800000 { /* APSS Funnel */ 1957 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1958 reg = <0 0x07800000 0 0x1000>; 1959 1960 clocks = <&aoss_qmp>; 1961 clock-names = "apb_pclk"; 1962 1963 out-ports { 1964 port { 1965 apss_funnel_out: endpoint { 1966 remote-endpoint = <&apss_merge_funnel_in>; 1967 }; 1968 }; 1969 }; 1970 1971 in-ports { 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 port@0 { 1976 reg = <0>; 1977 apss_funnel_in0: endpoint { 1978 remote-endpoint = <&etm0_out>; 1979 }; 1980 }; 1981 1982 port@1 { 1983 reg = <1>; 1984 apss_funnel_in1: endpoint { 1985 remote-endpoint = <&etm1_out>; 1986 }; 1987 }; 1988 1989 port@2 { 1990 reg = <2>; 1991 apss_funnel_in2: endpoint { 1992 remote-endpoint = <&etm2_out>; 1993 }; 1994 }; 1995 1996 port@3 { 1997 reg = <3>; 1998 apss_funnel_in3: endpoint { 1999 remote-endpoint = <&etm3_out>; 2000 }; 2001 }; 2002 2003 port@4 { 2004 reg = <4>; 2005 apss_funnel_in4: endpoint { 2006 remote-endpoint = <&etm4_out>; 2007 }; 2008 }; 2009 2010 port@5 { 2011 reg = <5>; 2012 apss_funnel_in5: endpoint { 2013 remote-endpoint = <&etm5_out>; 2014 }; 2015 }; 2016 2017 port@6 { 2018 reg = <6>; 2019 apss_funnel_in6: endpoint { 2020 remote-endpoint = <&etm6_out>; 2021 }; 2022 }; 2023 2024 port@7 { 2025 reg = <7>; 2026 apss_funnel_in7: endpoint { 2027 remote-endpoint = <&etm7_out>; 2028 }; 2029 }; 2030 }; 2031 }; 2032 2033 funnel@7810000 { 2034 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2035 reg = <0 0x07810000 0 0x1000>; 2036 2037 clocks = <&aoss_qmp>; 2038 clock-names = "apb_pclk"; 2039 2040 out-ports { 2041 port { 2042 apss_merge_funnel_out: endpoint { 2043 remote-endpoint = <&funnel1_in4>; 2044 }; 2045 }; 2046 }; 2047 2048 in-ports { 2049 port { 2050 apss_merge_funnel_in: endpoint { 2051 remote-endpoint = <&apss_funnel_out>; 2052 }; 2053 }; 2054 }; 2055 }; 2056 2057 remoteproc_mpss: remoteproc@4080000 { 2058 compatible = "qcom,sc7180-mpss-pas"; 2059 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 2060 reg-names = "qdsp6", "rmb"; 2061 2062 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2063 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2064 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2065 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2066 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2067 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2068 interrupt-names = "wdog", "fatal", "ready", "handover", 2069 "stop-ack", "shutdown-ack"; 2070 2071 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2072 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2073 <&gcc GCC_MSS_NAV_AXI_CLK>, 2074 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2075 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2076 <&rpmhcc RPMH_CXO_CLK>; 2077 clock-names = "iface", "bus", "nav", "snoc_axi", 2078 "mnoc_axi", "xo"; 2079 2080 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 2081 <&rpmhpd SC7180_CX>, 2082 <&rpmhpd SC7180_MX>, 2083 <&rpmhpd SC7180_MSS>; 2084 power-domain-names = "load_state", "cx", "mx", "mss"; 2085 2086 memory-region = <&mpss_mem>; 2087 2088 qcom,smem-states = <&modem_smp2p_out 0>; 2089 qcom,smem-state-names = "stop"; 2090 2091 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2092 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2093 reset-names = "mss_restart", "pdc_reset"; 2094 2095 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2096 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 2097 2098 status = "disabled"; 2099 2100 glink-edge { 2101 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2102 label = "modem"; 2103 qcom,remote-pid = <1>; 2104 mboxes = <&apss_shared 12>; 2105 }; 2106 }; 2107 2108 sdhc_2: sdhci@8804000 { 2109 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2110 reg = <0 0x08804000 0 0x1000>; 2111 2112 iommus = <&apps_smmu 0x80 0>; 2113 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2115 interrupt-names = "hc_irq", "pwr_irq"; 2116 2117 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2118 <&gcc GCC_SDCC2_AHB_CLK>; 2119 clock-names = "core", "iface"; 2120 2121 bus-width = <4>; 2122 2123 status = "disabled"; 2124 }; 2125 2126 qspi: spi@88dc000 { 2127 compatible = "qcom,qspi-v1"; 2128 reg = <0 0x088dc000 0 0x600>; 2129 #address-cells = <1>; 2130 #size-cells = <0>; 2131 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2132 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2133 <&gcc GCC_QSPI_CORE_CLK>; 2134 clock-names = "iface", "core"; 2135 status = "disabled"; 2136 }; 2137 2138 usb_1_hsphy: phy@88e3000 { 2139 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2140 reg = <0 0x088e3000 0 0x400>; 2141 status = "disabled"; 2142 #phy-cells = <0>; 2143 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2144 <&rpmhcc RPMH_CXO_CLK>; 2145 clock-names = "cfg_ahb", "ref"; 2146 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2147 2148 nvmem-cells = <&qusb2p_hstx_trim>; 2149 }; 2150 2151 usb_1_qmpphy: phy-wrapper@88e9000 { 2152 compatible = "qcom,sc7180-qmp-usb3-phy"; 2153 reg = <0 0x088e9000 0 0x18c>, 2154 <0 0x088e8000 0 0x38>; 2155 reg-names = "reg-base", "dp_com"; 2156 status = "disabled"; 2157 #clock-cells = <1>; 2158 #address-cells = <2>; 2159 #size-cells = <2>; 2160 ranges; 2161 2162 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2163 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2164 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2165 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2166 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2167 2168 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2169 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2170 reset-names = "phy", "common"; 2171 2172 usb_1_ssphy: phy@88e9200 { 2173 reg = <0 0x088e9200 0 0x128>, 2174 <0 0x088e9400 0 0x200>, 2175 <0 0x088e9c00 0 0x218>, 2176 <0 0x088e9600 0 0x128>, 2177 <0 0x088e9800 0 0x200>, 2178 <0 0x088e9a00 0 0x18>; 2179 #clock-cells = <0>; 2180 #phy-cells = <0>; 2181 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2182 clock-names = "pipe0"; 2183 clock-output-names = "usb3_phy_pipe_clk_src"; 2184 }; 2185 }; 2186 2187 dc_noc: interconnect@9160000 { 2188 compatible = "qcom,sc7180-dc-noc"; 2189 reg = <0 0x09160000 0 0x03200>; 2190 #interconnect-cells = <1>; 2191 qcom,bcm-voters = <&apps_bcm_voter>; 2192 }; 2193 2194 system-cache-controller@9200000 { 2195 compatible = "qcom,sc7180-llcc"; 2196 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 2197 reg-names = "llcc_base", "llcc_broadcast_base"; 2198 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2199 }; 2200 2201 gem_noc: interconnect@9680000 { 2202 compatible = "qcom,sc7180-gem-noc"; 2203 reg = <0 0x09680000 0 0x3e200>; 2204 #interconnect-cells = <1>; 2205 qcom,bcm-voters = <&apps_bcm_voter>; 2206 }; 2207 2208 npu_noc: interconnect@9990000 { 2209 compatible = "qcom,sc7180-npu-noc"; 2210 reg = <0 0x09990000 0 0x1600>; 2211 #interconnect-cells = <1>; 2212 qcom,bcm-voters = <&apps_bcm_voter>; 2213 }; 2214 2215 usb_1: usb@a6f8800 { 2216 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2217 reg = <0 0x0a6f8800 0 0x400>; 2218 status = "disabled"; 2219 #address-cells = <2>; 2220 #size-cells = <2>; 2221 ranges; 2222 dma-ranges; 2223 2224 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2225 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2226 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2227 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2228 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2229 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2230 "sleep"; 2231 2232 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2233 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2234 assigned-clock-rates = <19200000>, <150000000>; 2235 2236 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2240 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2241 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2242 2243 power-domains = <&gcc USB30_PRIM_GDSC>; 2244 2245 resets = <&gcc GCC_USB30_PRIM_BCR>; 2246 2247 interconnects = <&aggre2_noc MASTER_USB3 &mc_virt SLAVE_EBI1>, 2248 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>; 2249 interconnect-names = "usb-ddr", "apps-usb"; 2250 2251 usb_1_dwc3: dwc3@a600000 { 2252 compatible = "snps,dwc3"; 2253 reg = <0 0x0a600000 0 0xe000>; 2254 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2255 iommus = <&apps_smmu 0x540 0>; 2256 snps,dis_u2_susphy_quirk; 2257 snps,dis_enblslpm_quirk; 2258 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2259 phy-names = "usb2-phy", "usb3-phy"; 2260 }; 2261 }; 2262 2263 venus: video-codec@aa00000 { 2264 compatible = "qcom,sc7180-venus"; 2265 reg = <0 0x0aa00000 0 0xff000>; 2266 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2267 power-domains = <&videocc VENUS_GDSC>, 2268 <&videocc VCODEC0_GDSC>; 2269 power-domain-names = "venus", "vcodec0"; 2270 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2271 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2272 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2273 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2274 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2275 clock-names = "core", "iface", "bus", 2276 "vcodec0_core", "vcodec0_bus"; 2277 iommus = <&apps_smmu 0x0c00 0x60>; 2278 memory-region = <&venus_mem>; 2279 interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>, 2280 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; 2281 interconnect-names = "video-mem", "cpu-cfg"; 2282 2283 video-decoder { 2284 compatible = "venus-decoder"; 2285 }; 2286 2287 video-encoder { 2288 compatible = "venus-encoder"; 2289 }; 2290 }; 2291 2292 videocc: clock-controller@ab00000 { 2293 compatible = "qcom,sc7180-videocc"; 2294 reg = <0 0x0ab00000 0 0x10000>; 2295 clocks = <&rpmhcc RPMH_CXO_CLK>; 2296 clock-names = "bi_tcxo"; 2297 #clock-cells = <1>; 2298 #reset-cells = <1>; 2299 #power-domain-cells = <1>; 2300 }; 2301 2302 camnoc_virt: interconnect@ac00000 { 2303 compatible = "qcom,sc7180-camnoc-virt"; 2304 reg = <0 0x0ac00000 0 0x1000>; 2305 #interconnect-cells = <1>; 2306 qcom,bcm-voters = <&apps_bcm_voter>; 2307 }; 2308 2309 mdss: mdss@ae00000 { 2310 compatible = "qcom,sc7180-mdss"; 2311 reg = <0 0x0ae00000 0 0x1000>; 2312 reg-names = "mdss"; 2313 2314 power-domains = <&dispcc MDSS_GDSC>; 2315 2316 clocks = <&gcc GCC_DISP_AHB_CLK>, 2317 <&gcc GCC_DISP_HF_AXI_CLK>, 2318 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2319 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2320 clock-names = "iface", "bus", "ahb", "core"; 2321 2322 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2323 assigned-clock-rates = <300000000>; 2324 2325 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2326 interrupt-controller; 2327 #interrupt-cells = <1>; 2328 2329 iommus = <&apps_smmu 0x800 0x2>; 2330 2331 #address-cells = <2>; 2332 #size-cells = <2>; 2333 ranges; 2334 2335 status = "disabled"; 2336 2337 mdp: mdp@ae01000 { 2338 compatible = "qcom,sc7180-dpu"; 2339 reg = <0 0x0ae01000 0 0x8f000>, 2340 <0 0x0aeb0000 0 0x2008>; 2341 reg-names = "mdp", "vbif"; 2342 2343 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2344 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2345 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2346 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2347 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2348 clock-names = "iface", "rot", "lut", "core", 2349 "vsync"; 2350 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2351 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2352 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2353 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2354 assigned-clock-rates = <300000000>, 2355 <19200000>, 2356 <19200000>, 2357 <19200000>; 2358 2359 interrupt-parent = <&mdss>; 2360 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2361 2362 status = "disabled"; 2363 2364 ports { 2365 #address-cells = <1>; 2366 #size-cells = <0>; 2367 2368 port@0 { 2369 reg = <0>; 2370 dpu_intf1_out: endpoint { 2371 remote-endpoint = <&dsi0_in>; 2372 }; 2373 }; 2374 }; 2375 }; 2376 2377 dsi0: dsi@ae94000 { 2378 compatible = "qcom,mdss-dsi-ctrl"; 2379 reg = <0 0x0ae94000 0 0x400>; 2380 reg-names = "dsi_ctrl"; 2381 2382 interrupt-parent = <&mdss>; 2383 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2384 2385 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2386 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2387 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2388 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2389 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2390 <&gcc GCC_DISP_HF_AXI_CLK>; 2391 clock-names = "byte", 2392 "byte_intf", 2393 "pixel", 2394 "core", 2395 "iface", 2396 "bus"; 2397 2398 phys = <&dsi_phy>; 2399 phy-names = "dsi"; 2400 2401 #address-cells = <1>; 2402 #size-cells = <0>; 2403 2404 status = "disabled"; 2405 2406 ports { 2407 #address-cells = <1>; 2408 #size-cells = <0>; 2409 2410 port@0 { 2411 reg = <0>; 2412 dsi0_in: endpoint { 2413 remote-endpoint = <&dpu_intf1_out>; 2414 }; 2415 }; 2416 2417 port@1 { 2418 reg = <1>; 2419 dsi0_out: endpoint { 2420 }; 2421 }; 2422 }; 2423 }; 2424 2425 dsi_phy: dsi-phy@ae94400 { 2426 compatible = "qcom,dsi-phy-10nm"; 2427 reg = <0 0x0ae94400 0 0x200>, 2428 <0 0x0ae94600 0 0x280>, 2429 <0 0x0ae94a00 0 0x1e0>; 2430 reg-names = "dsi_phy", 2431 "dsi_phy_lane", 2432 "dsi_pll"; 2433 2434 #clock-cells = <1>; 2435 #phy-cells = <0>; 2436 2437 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2438 <&rpmhcc RPMH_CXO_CLK>; 2439 clock-names = "iface", "ref"; 2440 2441 status = "disabled"; 2442 }; 2443 }; 2444 2445 dispcc: clock-controller@af00000 { 2446 compatible = "qcom,sc7180-dispcc"; 2447 reg = <0 0x0af00000 0 0x200000>; 2448 clocks = <&rpmhcc RPMH_CXO_CLK>, 2449 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2450 <&dsi_phy 0>, 2451 <&dsi_phy 1>, 2452 <0>, 2453 <0>; 2454 clock-names = "bi_tcxo", 2455 "gcc_disp_gpll0_clk_src", 2456 "dsi0_phy_pll_out_byteclk", 2457 "dsi0_phy_pll_out_dsiclk", 2458 "dp_phy_pll_link_clk", 2459 "dp_phy_pll_vco_div_clk"; 2460 #clock-cells = <1>; 2461 #reset-cells = <1>; 2462 #power-domain-cells = <1>; 2463 }; 2464 2465 pdc: interrupt-controller@b220000 { 2466 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 2467 reg = <0 0x0b220000 0 0x30000>; 2468 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 2469 #interrupt-cells = <2>; 2470 interrupt-parent = <&intc>; 2471 interrupt-controller; 2472 }; 2473 2474 pdc_reset: reset-controller@b2e0000 { 2475 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 2476 reg = <0 0x0b2e0000 0 0x20000>; 2477 #reset-cells = <1>; 2478 }; 2479 2480 tsens0: thermal-sensor@c263000 { 2481 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 2482 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2483 <0 0x0c222000 0 0x1ff>; /* SROT */ 2484 #qcom,sensors = <15>; 2485 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2487 interrupt-names = "uplow","critical"; 2488 #thermal-sensor-cells = <1>; 2489 }; 2490 2491 tsens1: thermal-sensor@c265000 { 2492 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 2493 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2494 <0 0x0c223000 0 0x1ff>; /* SROT */ 2495 #qcom,sensors = <10>; 2496 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2498 interrupt-names = "uplow","critical"; 2499 #thermal-sensor-cells = <1>; 2500 }; 2501 2502 aoss_reset: reset-controller@c2a0000 { 2503 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 2504 reg = <0 0x0c2a0000 0 0x31000>; 2505 #reset-cells = <1>; 2506 }; 2507 2508 aoss_qmp: qmp@c300000 { 2509 compatible = "qcom,sc7180-aoss-qmp"; 2510 reg = <0 0x0c300000 0 0x100000>; 2511 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 2512 mboxes = <&apss_shared 0>; 2513 2514 #clock-cells = <0>; 2515 #power-domain-cells = <1>; 2516 }; 2517 2518 spmi_bus: spmi@c440000 { 2519 compatible = "qcom,spmi-pmic-arb"; 2520 reg = <0 0x0c440000 0 0x1100>, 2521 <0 0x0c600000 0 0x2000000>, 2522 <0 0x0e600000 0 0x100000>, 2523 <0 0x0e700000 0 0xa0000>, 2524 <0 0x0c40a000 0 0x26000>; 2525 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2526 interrupt-names = "periph_irq"; 2527 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2528 qcom,ee = <0>; 2529 qcom,channel = <0>; 2530 #address-cells = <1>; 2531 #size-cells = <1>; 2532 interrupt-controller; 2533 #interrupt-cells = <4>; 2534 cell-index = <0>; 2535 }; 2536 2537 apps_smmu: iommu@15000000 { 2538 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 2539 reg = <0 0x15000000 0 0x100000>; 2540 #iommu-cells = <2>; 2541 #global-interrupts = <1>; 2542 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2547 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2548 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2549 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2550 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2553 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2554 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2555 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2556 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2557 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2558 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2559 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2560 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2561 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2562 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2563 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2564 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2566 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2567 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2568 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2569 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2570 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2571 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2572 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2573 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2574 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2575 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2576 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2577 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2578 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2579 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2596 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2611 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2612 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2614 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2615 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2616 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2618 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2619 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2620 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2621 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2622 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 2623 }; 2624 2625 intc: interrupt-controller@17a00000 { 2626 compatible = "arm,gic-v3"; 2627 #address-cells = <2>; 2628 #size-cells = <2>; 2629 ranges; 2630 #interrupt-cells = <3>; 2631 interrupt-controller; 2632 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2633 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2634 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2635 2636 msi-controller@17a40000 { 2637 compatible = "arm,gic-v3-its"; 2638 msi-controller; 2639 #msi-cells = <1>; 2640 reg = <0 0x17a40000 0 0x20000>; 2641 status = "disabled"; 2642 }; 2643 }; 2644 2645 apss_shared: mailbox@17c00000 { 2646 compatible = "qcom,sc7180-apss-shared"; 2647 reg = <0 0x17c00000 0 0x10000>; 2648 #mbox-cells = <1>; 2649 }; 2650 2651 watchdog@17c10000 { 2652 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 2653 reg = <0 0x17c10000 0 0x1000>; 2654 clocks = <&sleep_clk>; 2655 }; 2656 2657 timer@17c20000{ 2658 #address-cells = <2>; 2659 #size-cells = <2>; 2660 ranges; 2661 compatible = "arm,armv7-timer-mem"; 2662 reg = <0 0x17c20000 0 0x1000>; 2663 2664 frame@17c21000 { 2665 frame-number = <0>; 2666 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2668 reg = <0 0x17c21000 0 0x1000>, 2669 <0 0x17c22000 0 0x1000>; 2670 }; 2671 2672 frame@17c23000 { 2673 frame-number = <1>; 2674 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2675 reg = <0 0x17c23000 0 0x1000>; 2676 status = "disabled"; 2677 }; 2678 2679 frame@17c25000 { 2680 frame-number = <2>; 2681 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2682 reg = <0 0x17c25000 0 0x1000>; 2683 status = "disabled"; 2684 }; 2685 2686 frame@17c27000 { 2687 frame-number = <3>; 2688 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2689 reg = <0 0x17c27000 0 0x1000>; 2690 status = "disabled"; 2691 }; 2692 2693 frame@17c29000 { 2694 frame-number = <4>; 2695 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2696 reg = <0 0x17c29000 0 0x1000>; 2697 status = "disabled"; 2698 }; 2699 2700 frame@17c2b000 { 2701 frame-number = <5>; 2702 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2703 reg = <0 0x17c2b000 0 0x1000>; 2704 status = "disabled"; 2705 }; 2706 2707 frame@17c2d000 { 2708 frame-number = <6>; 2709 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2710 reg = <0 0x17c2d000 0 0x1000>; 2711 status = "disabled"; 2712 }; 2713 }; 2714 2715 apps_rsc: rsc@18200000 { 2716 compatible = "qcom,rpmh-rsc"; 2717 reg = <0 0x18200000 0 0x10000>, 2718 <0 0x18210000 0 0x10000>, 2719 <0 0x18220000 0 0x10000>; 2720 reg-names = "drv-0", "drv-1", "drv-2"; 2721 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2724 qcom,tcs-offset = <0xd00>; 2725 qcom,drv-id = <2>; 2726 qcom,tcs-config = <ACTIVE_TCS 2>, 2727 <SLEEP_TCS 3>, 2728 <WAKE_TCS 3>, 2729 <CONTROL_TCS 1>; 2730 2731 rpmhcc: clock-controller { 2732 compatible = "qcom,sc7180-rpmh-clk"; 2733 clocks = <&xo_board>; 2734 clock-names = "xo"; 2735 #clock-cells = <1>; 2736 }; 2737 2738 rpmhpd: power-controller { 2739 compatible = "qcom,sc7180-rpmhpd"; 2740 #power-domain-cells = <1>; 2741 operating-points-v2 = <&rpmhpd_opp_table>; 2742 2743 rpmhpd_opp_table: opp-table { 2744 compatible = "operating-points-v2"; 2745 2746 rpmhpd_opp_ret: opp1 { 2747 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2748 }; 2749 2750 rpmhpd_opp_min_svs: opp2 { 2751 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2752 }; 2753 2754 rpmhpd_opp_low_svs: opp3 { 2755 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2756 }; 2757 2758 rpmhpd_opp_svs: opp4 { 2759 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2760 }; 2761 2762 rpmhpd_opp_svs_l1: opp5 { 2763 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2764 }; 2765 2766 rpmhpd_opp_svs_l2: opp6 { 2767 opp-level = <224>; 2768 }; 2769 2770 rpmhpd_opp_nom: opp7 { 2771 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2772 }; 2773 2774 rpmhpd_opp_nom_l1: opp8 { 2775 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2776 }; 2777 2778 rpmhpd_opp_nom_l2: opp9 { 2779 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2780 }; 2781 2782 rpmhpd_opp_turbo: opp10 { 2783 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2784 }; 2785 2786 rpmhpd_opp_turbo_l1: opp11 { 2787 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2788 }; 2789 }; 2790 }; 2791 2792 apps_bcm_voter: bcm_voter { 2793 compatible = "qcom,bcm-voter"; 2794 }; 2795 }; 2796 2797 osm_l3: interconnect@18321000 { 2798 compatible = "qcom,sc7180-osm-l3"; 2799 reg = <0 0x18321000 0 0x1400>; 2800 2801 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2802 clock-names = "xo", "alternate"; 2803 2804 #interconnect-cells = <1>; 2805 }; 2806 2807 cpufreq_hw: cpufreq@18323000 { 2808 compatible = "qcom,cpufreq-hw"; 2809 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 2810 reg-names = "freq-domain0", "freq-domain1"; 2811 2812 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2813 clock-names = "xo", "alternate"; 2814 2815 #freq-domain-cells = <1>; 2816 }; 2817 }; 2818 2819 thermal-zones { 2820 cpu0-thermal { 2821 polling-delay-passive = <0>; 2822 polling-delay = <0>; 2823 2824 thermal-sensors = <&tsens0 1>; 2825 2826 trips { 2827 cpu0_alert0: trip-point0 { 2828 temperature = <90000>; 2829 hysteresis = <2000>; 2830 type = "passive"; 2831 }; 2832 2833 cpu0_alert1: trip-point1 { 2834 temperature = <95000>; 2835 hysteresis = <2000>; 2836 type = "passive"; 2837 }; 2838 2839 cpu0_crit: cpu_crit { 2840 temperature = <110000>; 2841 hysteresis = <1000>; 2842 type = "critical"; 2843 }; 2844 }; 2845 2846 cooling-maps { 2847 map0 { 2848 trip = <&cpu0_alert0>; 2849 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2850 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2851 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2852 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2853 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2855 }; 2856 map1 { 2857 trip = <&cpu0_alert1>; 2858 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2859 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2860 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2861 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2862 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2863 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2864 }; 2865 }; 2866 }; 2867 2868 cpu1-thermal { 2869 polling-delay-passive = <0>; 2870 polling-delay = <0>; 2871 2872 thermal-sensors = <&tsens0 2>; 2873 2874 trips { 2875 cpu1_alert0: trip-point0 { 2876 temperature = <90000>; 2877 hysteresis = <2000>; 2878 type = "passive"; 2879 }; 2880 2881 cpu1_alert1: trip-point1 { 2882 temperature = <95000>; 2883 hysteresis = <2000>; 2884 type = "passive"; 2885 }; 2886 2887 cpu1_crit: cpu_crit { 2888 temperature = <110000>; 2889 hysteresis = <1000>; 2890 type = "critical"; 2891 }; 2892 }; 2893 2894 cooling-maps { 2895 map0 { 2896 trip = <&cpu1_alert0>; 2897 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2898 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2899 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2900 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2901 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2902 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2903 }; 2904 map1 { 2905 trip = <&cpu1_alert1>; 2906 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2907 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2908 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2909 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2910 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2911 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2912 }; 2913 }; 2914 }; 2915 2916 cpu2-thermal { 2917 polling-delay-passive = <0>; 2918 polling-delay = <0>; 2919 2920 thermal-sensors = <&tsens0 3>; 2921 2922 trips { 2923 cpu2_alert0: trip-point0 { 2924 temperature = <90000>; 2925 hysteresis = <2000>; 2926 type = "passive"; 2927 }; 2928 2929 cpu2_alert1: trip-point1 { 2930 temperature = <95000>; 2931 hysteresis = <2000>; 2932 type = "passive"; 2933 }; 2934 2935 cpu2_crit: cpu_crit { 2936 temperature = <110000>; 2937 hysteresis = <1000>; 2938 type = "critical"; 2939 }; 2940 }; 2941 2942 cooling-maps { 2943 map0 { 2944 trip = <&cpu2_alert0>; 2945 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2946 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2947 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2948 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2949 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2950 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2951 }; 2952 map1 { 2953 trip = <&cpu2_alert1>; 2954 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2955 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2956 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2957 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2958 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2959 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2960 }; 2961 }; 2962 }; 2963 2964 cpu3-thermal { 2965 polling-delay-passive = <0>; 2966 polling-delay = <0>; 2967 2968 thermal-sensors = <&tsens0 4>; 2969 2970 trips { 2971 cpu3_alert0: trip-point0 { 2972 temperature = <90000>; 2973 hysteresis = <2000>; 2974 type = "passive"; 2975 }; 2976 2977 cpu3_alert1: trip-point1 { 2978 temperature = <95000>; 2979 hysteresis = <2000>; 2980 type = "passive"; 2981 }; 2982 2983 cpu3_crit: cpu_crit { 2984 temperature = <110000>; 2985 hysteresis = <1000>; 2986 type = "critical"; 2987 }; 2988 }; 2989 2990 cooling-maps { 2991 map0 { 2992 trip = <&cpu3_alert0>; 2993 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2994 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2995 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2996 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2997 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2998 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2999 }; 3000 map1 { 3001 trip = <&cpu3_alert1>; 3002 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3003 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3004 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3005 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3006 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3007 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3008 }; 3009 }; 3010 }; 3011 3012 cpu4-thermal { 3013 polling-delay-passive = <0>; 3014 polling-delay = <0>; 3015 3016 thermal-sensors = <&tsens0 5>; 3017 3018 trips { 3019 cpu4_alert0: trip-point0 { 3020 temperature = <90000>; 3021 hysteresis = <2000>; 3022 type = "passive"; 3023 }; 3024 3025 cpu4_alert1: trip-point1 { 3026 temperature = <95000>; 3027 hysteresis = <2000>; 3028 type = "passive"; 3029 }; 3030 3031 cpu4_crit: cpu_crit { 3032 temperature = <110000>; 3033 hysteresis = <1000>; 3034 type = "critical"; 3035 }; 3036 }; 3037 3038 cooling-maps { 3039 map0 { 3040 trip = <&cpu4_alert0>; 3041 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3042 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3043 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3044 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3045 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3046 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3047 }; 3048 map1 { 3049 trip = <&cpu4_alert1>; 3050 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3051 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3052 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3053 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3054 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3055 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3056 }; 3057 }; 3058 }; 3059 3060 cpu5-thermal { 3061 polling-delay-passive = <0>; 3062 polling-delay = <0>; 3063 3064 thermal-sensors = <&tsens0 6>; 3065 3066 trips { 3067 cpu5_alert0: trip-point0 { 3068 temperature = <90000>; 3069 hysteresis = <2000>; 3070 type = "passive"; 3071 }; 3072 3073 cpu5_alert1: trip-point1 { 3074 temperature = <95000>; 3075 hysteresis = <2000>; 3076 type = "passive"; 3077 }; 3078 3079 cpu5_crit: cpu_crit { 3080 temperature = <110000>; 3081 hysteresis = <1000>; 3082 type = "critical"; 3083 }; 3084 }; 3085 3086 cooling-maps { 3087 map0 { 3088 trip = <&cpu5_alert0>; 3089 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3090 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3091 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3092 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3093 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3094 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3095 }; 3096 map1 { 3097 trip = <&cpu5_alert1>; 3098 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3099 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3100 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3101 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3102 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3103 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3104 }; 3105 }; 3106 }; 3107 3108 cpu6-thermal { 3109 polling-delay-passive = <0>; 3110 polling-delay = <0>; 3111 3112 thermal-sensors = <&tsens0 9>; 3113 3114 trips { 3115 cpu6_alert0: trip-point0 { 3116 temperature = <90000>; 3117 hysteresis = <2000>; 3118 type = "passive"; 3119 }; 3120 3121 cpu6_alert1: trip-point1 { 3122 temperature = <95000>; 3123 hysteresis = <2000>; 3124 type = "passive"; 3125 }; 3126 3127 cpu6_crit: cpu_crit { 3128 temperature = <110000>; 3129 hysteresis = <1000>; 3130 type = "critical"; 3131 }; 3132 }; 3133 3134 cooling-maps { 3135 map0 { 3136 trip = <&cpu6_alert0>; 3137 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3139 }; 3140 map1 { 3141 trip = <&cpu6_alert1>; 3142 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3143 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3144 }; 3145 }; 3146 }; 3147 3148 cpu7-thermal { 3149 polling-delay-passive = <0>; 3150 polling-delay = <0>; 3151 3152 thermal-sensors = <&tsens0 10>; 3153 3154 trips { 3155 cpu7_alert0: trip-point0 { 3156 temperature = <90000>; 3157 hysteresis = <2000>; 3158 type = "passive"; 3159 }; 3160 3161 cpu7_alert1: trip-point1 { 3162 temperature = <95000>; 3163 hysteresis = <2000>; 3164 type = "passive"; 3165 }; 3166 3167 cpu7_crit: cpu_crit { 3168 temperature = <110000>; 3169 hysteresis = <1000>; 3170 type = "critical"; 3171 }; 3172 }; 3173 3174 cooling-maps { 3175 map0 { 3176 trip = <&cpu7_alert0>; 3177 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3178 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3179 }; 3180 map1 { 3181 trip = <&cpu7_alert1>; 3182 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3183 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3184 }; 3185 }; 3186 }; 3187 3188 cpu8-thermal { 3189 polling-delay-passive = <0>; 3190 polling-delay = <0>; 3191 3192 thermal-sensors = <&tsens0 11>; 3193 3194 trips { 3195 cpu8_alert0: trip-point0 { 3196 temperature = <90000>; 3197 hysteresis = <2000>; 3198 type = "passive"; 3199 }; 3200 3201 cpu8_alert1: trip-point1 { 3202 temperature = <95000>; 3203 hysteresis = <2000>; 3204 type = "passive"; 3205 }; 3206 3207 cpu8_crit: cpu_crit { 3208 temperature = <110000>; 3209 hysteresis = <1000>; 3210 type = "critical"; 3211 }; 3212 }; 3213 3214 cooling-maps { 3215 map0 { 3216 trip = <&cpu8_alert0>; 3217 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3218 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3219 }; 3220 map1 { 3221 trip = <&cpu8_alert1>; 3222 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3223 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3224 }; 3225 }; 3226 }; 3227 3228 cpu9-thermal { 3229 polling-delay-passive = <0>; 3230 polling-delay = <0>; 3231 3232 thermal-sensors = <&tsens0 12>; 3233 3234 trips { 3235 cpu9_alert0: trip-point0 { 3236 temperature = <90000>; 3237 hysteresis = <2000>; 3238 type = "passive"; 3239 }; 3240 3241 cpu9_alert1: trip-point1 { 3242 temperature = <95000>; 3243 hysteresis = <2000>; 3244 type = "passive"; 3245 }; 3246 3247 cpu9_crit: cpu_crit { 3248 temperature = <110000>; 3249 hysteresis = <1000>; 3250 type = "critical"; 3251 }; 3252 }; 3253 3254 cooling-maps { 3255 map0 { 3256 trip = <&cpu9_alert0>; 3257 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3258 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3259 }; 3260 map1 { 3261 trip = <&cpu9_alert1>; 3262 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3263 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3264 }; 3265 }; 3266 }; 3267 3268 aoss0-thermal { 3269 polling-delay-passive = <0>; 3270 polling-delay = <0>; 3271 3272 thermal-sensors = <&tsens0 0>; 3273 3274 trips { 3275 aoss0_alert0: trip-point0 { 3276 temperature = <90000>; 3277 hysteresis = <2000>; 3278 type = "hot"; 3279 }; 3280 3281 aoss0_crit: aoss0_crit { 3282 temperature = <110000>; 3283 hysteresis = <2000>; 3284 type = "critical"; 3285 }; 3286 }; 3287 }; 3288 3289 cpuss0-thermal { 3290 polling-delay-passive = <0>; 3291 polling-delay = <0>; 3292 3293 thermal-sensors = <&tsens0 7>; 3294 3295 trips { 3296 cpuss0_alert0: trip-point0 { 3297 temperature = <90000>; 3298 hysteresis = <2000>; 3299 type = "hot"; 3300 }; 3301 cpuss0_crit: cluster0_crit { 3302 temperature = <110000>; 3303 hysteresis = <2000>; 3304 type = "critical"; 3305 }; 3306 }; 3307 }; 3308 3309 cpuss1-thermal { 3310 polling-delay-passive = <0>; 3311 polling-delay = <0>; 3312 3313 thermal-sensors = <&tsens0 8>; 3314 3315 trips { 3316 cpuss1_alert0: trip-point0 { 3317 temperature = <90000>; 3318 hysteresis = <2000>; 3319 type = "hot"; 3320 }; 3321 cpuss1_crit: cluster0_crit { 3322 temperature = <110000>; 3323 hysteresis = <2000>; 3324 type = "critical"; 3325 }; 3326 }; 3327 }; 3328 3329 gpuss0-thermal { 3330 polling-delay-passive = <0>; 3331 polling-delay = <0>; 3332 3333 thermal-sensors = <&tsens0 13>; 3334 3335 trips { 3336 gpuss0_alert0: trip-point0 { 3337 temperature = <90000>; 3338 hysteresis = <2000>; 3339 type = "hot"; 3340 }; 3341 3342 gpuss0_crit: gpuss0_crit { 3343 temperature = <110000>; 3344 hysteresis = <2000>; 3345 type = "critical"; 3346 }; 3347 }; 3348 }; 3349 3350 gpuss1-thermal { 3351 polling-delay-passive = <0>; 3352 polling-delay = <0>; 3353 3354 thermal-sensors = <&tsens0 14>; 3355 3356 trips { 3357 gpuss1_alert0: trip-point0 { 3358 temperature = <90000>; 3359 hysteresis = <2000>; 3360 type = "hot"; 3361 }; 3362 3363 gpuss1_crit: gpuss1_crit { 3364 temperature = <110000>; 3365 hysteresis = <2000>; 3366 type = "critical"; 3367 }; 3368 }; 3369 }; 3370 3371 aoss1-thermal { 3372 polling-delay-passive = <0>; 3373 polling-delay = <0>; 3374 3375 thermal-sensors = <&tsens1 0>; 3376 3377 trips { 3378 aoss1_alert0: trip-point0 { 3379 temperature = <90000>; 3380 hysteresis = <2000>; 3381 type = "hot"; 3382 }; 3383 3384 aoss1_crit: aoss1_crit { 3385 temperature = <110000>; 3386 hysteresis = <2000>; 3387 type = "critical"; 3388 }; 3389 }; 3390 }; 3391 3392 cwlan-thermal { 3393 polling-delay-passive = <0>; 3394 polling-delay = <0>; 3395 3396 thermal-sensors = <&tsens1 1>; 3397 3398 trips { 3399 cwlan_alert0: trip-point0 { 3400 temperature = <90000>; 3401 hysteresis = <2000>; 3402 type = "hot"; 3403 }; 3404 3405 cwlan_crit: cwlan_crit { 3406 temperature = <110000>; 3407 hysteresis = <2000>; 3408 type = "critical"; 3409 }; 3410 }; 3411 }; 3412 3413 audio-thermal { 3414 polling-delay-passive = <0>; 3415 polling-delay = <0>; 3416 3417 thermal-sensors = <&tsens1 2>; 3418 3419 trips { 3420 audio_alert0: trip-point0 { 3421 temperature = <90000>; 3422 hysteresis = <2000>; 3423 type = "hot"; 3424 }; 3425 3426 audio_crit: audio_crit { 3427 temperature = <110000>; 3428 hysteresis = <2000>; 3429 type = "critical"; 3430 }; 3431 }; 3432 }; 3433 3434 ddr-thermal { 3435 polling-delay-passive = <0>; 3436 polling-delay = <0>; 3437 3438 thermal-sensors = <&tsens1 3>; 3439 3440 trips { 3441 ddr_alert0: trip-point0 { 3442 temperature = <90000>; 3443 hysteresis = <2000>; 3444 type = "hot"; 3445 }; 3446 3447 ddr_crit: ddr_crit { 3448 temperature = <110000>; 3449 hysteresis = <2000>; 3450 type = "critical"; 3451 }; 3452 }; 3453 }; 3454 3455 q6-hvx-thermal { 3456 polling-delay-passive = <0>; 3457 polling-delay = <0>; 3458 3459 thermal-sensors = <&tsens1 4>; 3460 3461 trips { 3462 q6_hvx_alert0: trip-point0 { 3463 temperature = <90000>; 3464 hysteresis = <2000>; 3465 type = "hot"; 3466 }; 3467 3468 q6_hvx_crit: q6_hvx_crit { 3469 temperature = <110000>; 3470 hysteresis = <2000>; 3471 type = "critical"; 3472 }; 3473 }; 3474 }; 3475 3476 camera-thermal { 3477 polling-delay-passive = <0>; 3478 polling-delay = <0>; 3479 3480 thermal-sensors = <&tsens1 5>; 3481 3482 trips { 3483 camera_alert0: trip-point0 { 3484 temperature = <90000>; 3485 hysteresis = <2000>; 3486 type = "hot"; 3487 }; 3488 3489 camera_crit: camera_crit { 3490 temperature = <110000>; 3491 hysteresis = <2000>; 3492 type = "critical"; 3493 }; 3494 }; 3495 }; 3496 3497 mdm-core-thermal { 3498 polling-delay-passive = <0>; 3499 polling-delay = <0>; 3500 3501 thermal-sensors = <&tsens1 6>; 3502 3503 trips { 3504 mdm_alert0: trip-point0 { 3505 temperature = <90000>; 3506 hysteresis = <2000>; 3507 type = "hot"; 3508 }; 3509 3510 mdm_crit: mdm_crit { 3511 temperature = <110000>; 3512 hysteresis = <2000>; 3513 type = "critical"; 3514 }; 3515 }; 3516 }; 3517 3518 mdm-dsp-thermal { 3519 polling-delay-passive = <0>; 3520 polling-delay = <0>; 3521 3522 thermal-sensors = <&tsens1 7>; 3523 3524 trips { 3525 mdm_dsp_alert0: trip-point0 { 3526 temperature = <90000>; 3527 hysteresis = <2000>; 3528 type = "hot"; 3529 }; 3530 3531 mdm_dsp_crit: mdm_dsp_crit { 3532 temperature = <110000>; 3533 hysteresis = <2000>; 3534 type = "critical"; 3535 }; 3536 }; 3537 }; 3538 3539 npu-thermal { 3540 polling-delay-passive = <0>; 3541 polling-delay = <0>; 3542 3543 thermal-sensors = <&tsens1 8>; 3544 3545 trips { 3546 npu_alert0: trip-point0 { 3547 temperature = <90000>; 3548 hysteresis = <2000>; 3549 type = "hot"; 3550 }; 3551 3552 npu_crit: npu_crit { 3553 temperature = <110000>; 3554 hysteresis = <2000>; 3555 type = "critical"; 3556 }; 3557 }; 3558 }; 3559 3560 video-thermal { 3561 polling-delay-passive = <0>; 3562 polling-delay = <0>; 3563 3564 thermal-sensors = <&tsens1 9>; 3565 3566 trips { 3567 video_alert0: trip-point0 { 3568 temperature = <90000>; 3569 hysteresis = <2000>; 3570 type = "hot"; 3571 }; 3572 3573 video_crit: video_crit { 3574 temperature = <110000>; 3575 hysteresis = <2000>; 3576 type = "critical"; 3577 }; 3578 }; 3579 }; 3580 }; 3581 3582 timer { 3583 compatible = "arm,armv8-timer"; 3584 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3585 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3586 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3587 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3588 }; 3589}; 3590