1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 mmc1 = &sdhc_1; 32 mmc2 = &sdhc_2; 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi3 = &spi3; 48 spi5 = &spi5; 49 spi6 = &spi6; 50 spi8 = &spi8; 51 spi10 = &spi10; 52 spi11 = &spi11; 53 }; 54 55 chosen { }; 56 57 clocks { 58 xo_board: xo-board { 59 compatible = "fixed-clock"; 60 clock-frequency = <38400000>; 61 #clock-cells = <0>; 62 }; 63 64 sleep_clk: sleep-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <32764>; 67 #clock-cells = <0>; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <2>; 73 #size-cells = <0>; 74 75 CPU0: cpu@0 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo468"; 78 reg = <0x0 0x0>; 79 enable-method = "psci"; 80 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 81 &LITTLE_CPU_SLEEP_1 82 &CLUSTER_SLEEP_0>; 83 capacity-dmips-mhz = <415>; 84 dynamic-power-coefficient = <137>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 87 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 88 next-level-cache = <&L2_0>; 89 #cooling-cells = <2>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 L2_0: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 next-level-cache = <&L3_0>; 95 L3_0: l3-cache { 96 compatible = "cache"; 97 cache-level = <3>; 98 }; 99 }; 100 }; 101 102 CPU1: cpu@100 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo468"; 105 reg = <0x0 0x100>; 106 enable-method = "psci"; 107 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 108 &LITTLE_CPU_SLEEP_1 109 &CLUSTER_SLEEP_0>; 110 capacity-dmips-mhz = <415>; 111 dynamic-power-coefficient = <137>; 112 next-level-cache = <&L2_100>; 113 operating-points-v2 = <&cpu0_opp_table>; 114 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 115 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 116 #cooling-cells = <2>; 117 qcom,freq-domain = <&cpufreq_hw 0>; 118 L2_100: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 next-level-cache = <&L3_0>; 122 }; 123 }; 124 125 CPU2: cpu@200 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo468"; 128 reg = <0x0 0x200>; 129 enable-method = "psci"; 130 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 131 &LITTLE_CPU_SLEEP_1 132 &CLUSTER_SLEEP_0>; 133 capacity-dmips-mhz = <415>; 134 dynamic-power-coefficient = <137>; 135 next-level-cache = <&L2_200>; 136 operating-points-v2 = <&cpu0_opp_table>; 137 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 139 #cooling-cells = <2>; 140 qcom,freq-domain = <&cpufreq_hw 0>; 141 L2_200: l2-cache { 142 compatible = "cache"; 143 cache-level = <2>; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU3: cpu@300 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo468"; 151 reg = <0x0 0x300>; 152 enable-method = "psci"; 153 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 154 &LITTLE_CPU_SLEEP_1 155 &CLUSTER_SLEEP_0>; 156 capacity-dmips-mhz = <415>; 157 dynamic-power-coefficient = <137>; 158 next-level-cache = <&L2_300>; 159 operating-points-v2 = <&cpu0_opp_table>; 160 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 161 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 162 #cooling-cells = <2>; 163 qcom,freq-domain = <&cpufreq_hw 0>; 164 L2_300: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU4: cpu@400 { 172 device_type = "cpu"; 173 compatible = "qcom,kryo468"; 174 reg = <0x0 0x400>; 175 enable-method = "psci"; 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 177 &LITTLE_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 capacity-dmips-mhz = <415>; 180 dynamic-power-coefficient = <137>; 181 next-level-cache = <&L2_400>; 182 operating-points-v2 = <&cpu0_opp_table>; 183 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 185 #cooling-cells = <2>; 186 qcom,freq-domain = <&cpufreq_hw 0>; 187 L2_400: l2-cache { 188 compatible = "cache"; 189 cache-level = <2>; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU5: cpu@500 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo468"; 197 reg = <0x0 0x500>; 198 enable-method = "psci"; 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 200 &LITTLE_CPU_SLEEP_1 201 &CLUSTER_SLEEP_0>; 202 capacity-dmips-mhz = <415>; 203 dynamic-power-coefficient = <137>; 204 next-level-cache = <&L2_500>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 208 #cooling-cells = <2>; 209 qcom,freq-domain = <&cpufreq_hw 0>; 210 L2_500: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 CPU6: cpu@600 { 218 device_type = "cpu"; 219 compatible = "qcom,kryo468"; 220 reg = <0x0 0x600>; 221 enable-method = "psci"; 222 cpu-idle-states = <&BIG_CPU_SLEEP_0 223 &BIG_CPU_SLEEP_1 224 &CLUSTER_SLEEP_0>; 225 capacity-dmips-mhz = <1024>; 226 dynamic-power-coefficient = <480>; 227 next-level-cache = <&L2_600>; 228 operating-points-v2 = <&cpu6_opp_table>; 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 230 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 231 #cooling-cells = <2>; 232 qcom,freq-domain = <&cpufreq_hw 1>; 233 L2_600: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU7: cpu@700 { 241 device_type = "cpu"; 242 compatible = "qcom,kryo468"; 243 reg = <0x0 0x700>; 244 enable-method = "psci"; 245 cpu-idle-states = <&BIG_CPU_SLEEP_0 246 &BIG_CPU_SLEEP_1 247 &CLUSTER_SLEEP_0>; 248 capacity-dmips-mhz = <1024>; 249 dynamic-power-coefficient = <480>; 250 next-level-cache = <&L2_700>; 251 operating-points-v2 = <&cpu6_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 254 #cooling-cells = <2>; 255 qcom,freq-domain = <&cpufreq_hw 1>; 256 L2_700: l2-cache { 257 compatible = "cache"; 258 cache-level = <2>; 259 next-level-cache = <&L3_0>; 260 }; 261 }; 262 263 cpu-map { 264 cluster0 { 265 core0 { 266 cpu = <&CPU0>; 267 }; 268 269 core1 { 270 cpu = <&CPU1>; 271 }; 272 273 core2 { 274 cpu = <&CPU2>; 275 }; 276 277 core3 { 278 cpu = <&CPU3>; 279 }; 280 281 core4 { 282 cpu = <&CPU4>; 283 }; 284 285 core5 { 286 cpu = <&CPU5>; 287 }; 288 289 core6 { 290 cpu = <&CPU6>; 291 }; 292 293 core7 { 294 cpu = <&CPU7>; 295 }; 296 }; 297 }; 298 299 idle-states { 300 entry-method = "psci"; 301 302 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 303 compatible = "arm,idle-state"; 304 idle-state-name = "little-power-down"; 305 arm,psci-suspend-param = <0x40000003>; 306 entry-latency-us = <549>; 307 exit-latency-us = <901>; 308 min-residency-us = <1774>; 309 local-timer-stop; 310 }; 311 312 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 313 compatible = "arm,idle-state"; 314 idle-state-name = "little-rail-power-down"; 315 arm,psci-suspend-param = <0x40000004>; 316 entry-latency-us = <702>; 317 exit-latency-us = <915>; 318 min-residency-us = <4001>; 319 local-timer-stop; 320 }; 321 322 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 323 compatible = "arm,idle-state"; 324 idle-state-name = "big-power-down"; 325 arm,psci-suspend-param = <0x40000003>; 326 entry-latency-us = <523>; 327 exit-latency-us = <1244>; 328 min-residency-us = <2207>; 329 local-timer-stop; 330 }; 331 332 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 333 compatible = "arm,idle-state"; 334 idle-state-name = "big-rail-power-down"; 335 arm,psci-suspend-param = <0x40000004>; 336 entry-latency-us = <526>; 337 exit-latency-us = <1854>; 338 min-residency-us = <5555>; 339 local-timer-stop; 340 }; 341 342 CLUSTER_SLEEP_0: cluster-sleep-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "cluster-power-down"; 345 arm,psci-suspend-param = <0x40003444>; 346 entry-latency-us = <3263>; 347 exit-latency-us = <6562>; 348 min-residency-us = <9926>; 349 local-timer-stop; 350 }; 351 }; 352 }; 353 354 firmware { 355 scm { 356 compatible = "qcom,scm-sc7180", "qcom,scm"; 357 }; 358 }; 359 360 memory@80000000 { 361 device_type = "memory"; 362 /* We expect the bootloader to fill in the size */ 363 reg = <0 0x80000000 0 0>; 364 }; 365 366 cpu0_opp_table: opp-table-cpu0 { 367 compatible = "operating-points-v2"; 368 opp-shared; 369 370 cpu0_opp1: opp-300000000 { 371 opp-hz = /bits/ 64 <300000000>; 372 opp-peak-kBps = <1200000 4800000>; 373 }; 374 375 cpu0_opp2: opp-576000000 { 376 opp-hz = /bits/ 64 <576000000>; 377 opp-peak-kBps = <1200000 4800000>; 378 }; 379 380 cpu0_opp3: opp-768000000 { 381 opp-hz = /bits/ 64 <768000000>; 382 opp-peak-kBps = <1200000 4800000>; 383 }; 384 385 cpu0_opp4: opp-1017600000 { 386 opp-hz = /bits/ 64 <1017600000>; 387 opp-peak-kBps = <1804000 8908800>; 388 }; 389 390 cpu0_opp5: opp-1248000000 { 391 opp-hz = /bits/ 64 <1248000000>; 392 opp-peak-kBps = <2188000 12902400>; 393 }; 394 395 cpu0_opp6: opp-1324800000 { 396 opp-hz = /bits/ 64 <1324800000>; 397 opp-peak-kBps = <2188000 12902400>; 398 }; 399 400 cpu0_opp7: opp-1516800000 { 401 opp-hz = /bits/ 64 <1516800000>; 402 opp-peak-kBps = <3072000 15052800>; 403 }; 404 405 cpu0_opp8: opp-1612800000 { 406 opp-hz = /bits/ 64 <1612800000>; 407 opp-peak-kBps = <3072000 15052800>; 408 }; 409 410 cpu0_opp9: opp-1708800000 { 411 opp-hz = /bits/ 64 <1708800000>; 412 opp-peak-kBps = <3072000 15052800>; 413 }; 414 415 cpu0_opp10: opp-1804800000 { 416 opp-hz = /bits/ 64 <1804800000>; 417 opp-peak-kBps = <4068000 22425600>; 418 }; 419 }; 420 421 cpu6_opp_table: opp-table-cpu6 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu6_opp1: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <2188000 8908800>; 428 }; 429 430 cpu6_opp2: opp-652800000 { 431 opp-hz = /bits/ 64 <652800000>; 432 opp-peak-kBps = <2188000 8908800>; 433 }; 434 435 cpu6_opp3: opp-825600000 { 436 opp-hz = /bits/ 64 <825600000>; 437 opp-peak-kBps = <2188000 8908800>; 438 }; 439 440 cpu6_opp4: opp-979200000 { 441 opp-hz = /bits/ 64 <979200000>; 442 opp-peak-kBps = <2188000 8908800>; 443 }; 444 445 cpu6_opp5: opp-1113600000 { 446 opp-hz = /bits/ 64 <1113600000>; 447 opp-peak-kBps = <2188000 8908800>; 448 }; 449 450 cpu6_opp6: opp-1267200000 { 451 opp-hz = /bits/ 64 <1267200000>; 452 opp-peak-kBps = <4068000 12902400>; 453 }; 454 455 cpu6_opp7: opp-1555200000 { 456 opp-hz = /bits/ 64 <1555200000>; 457 opp-peak-kBps = <4068000 15052800>; 458 }; 459 460 cpu6_opp8: opp-1708800000 { 461 opp-hz = /bits/ 64 <1708800000>; 462 opp-peak-kBps = <6220000 19353600>; 463 }; 464 465 cpu6_opp9: opp-1843200000 { 466 opp-hz = /bits/ 64 <1843200000>; 467 opp-peak-kBps = <6220000 19353600>; 468 }; 469 470 cpu6_opp10: opp-1900800000 { 471 opp-hz = /bits/ 64 <1900800000>; 472 opp-peak-kBps = <6220000 22425600>; 473 }; 474 475 cpu6_opp11: opp-1996800000 { 476 opp-hz = /bits/ 64 <1996800000>; 477 opp-peak-kBps = <6220000 22425600>; 478 }; 479 480 cpu6_opp12: opp-2112000000 { 481 opp-hz = /bits/ 64 <2112000000>; 482 opp-peak-kBps = <6220000 22425600>; 483 }; 484 485 cpu6_opp13: opp-2208000000 { 486 opp-hz = /bits/ 64 <2208000000>; 487 opp-peak-kBps = <7216000 22425600>; 488 }; 489 490 cpu6_opp14: opp-2323200000 { 491 opp-hz = /bits/ 64 <2323200000>; 492 opp-peak-kBps = <7216000 22425600>; 493 }; 494 495 cpu6_opp15: opp-2400000000 { 496 opp-hz = /bits/ 64 <2400000000>; 497 opp-peak-kBps = <8532000 23347200>; 498 }; 499 500 cpu6_opp16: opp-2553600000 { 501 opp-hz = /bits/ 64 <2553600000>; 502 opp-peak-kBps = <8532000 23347200>; 503 }; 504 }; 505 506 qspi_opp_table: opp-table-qspi { 507 compatible = "operating-points-v2"; 508 509 opp-75000000 { 510 opp-hz = /bits/ 64 <75000000>; 511 required-opps = <&rpmhpd_opp_low_svs>; 512 }; 513 514 opp-150000000 { 515 opp-hz = /bits/ 64 <150000000>; 516 required-opps = <&rpmhpd_opp_svs>; 517 }; 518 519 opp-300000000 { 520 opp-hz = /bits/ 64 <300000000>; 521 required-opps = <&rpmhpd_opp_nom>; 522 }; 523 }; 524 525 qup_opp_table: opp-table-qup { 526 compatible = "operating-points-v2"; 527 528 opp-75000000 { 529 opp-hz = /bits/ 64 <75000000>; 530 required-opps = <&rpmhpd_opp_low_svs>; 531 }; 532 533 opp-100000000 { 534 opp-hz = /bits/ 64 <100000000>; 535 required-opps = <&rpmhpd_opp_svs>; 536 }; 537 538 opp-128000000 { 539 opp-hz = /bits/ 64 <128000000>; 540 required-opps = <&rpmhpd_opp_nom>; 541 }; 542 }; 543 544 pmu { 545 compatible = "arm,armv8-pmuv3"; 546 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 547 }; 548 549 psci { 550 compatible = "arm,psci-1.0"; 551 method = "smc"; 552 }; 553 554 reserved_memory: reserved-memory { 555 #address-cells = <2>; 556 #size-cells = <2>; 557 ranges; 558 559 hyp_mem: memory@80000000 { 560 reg = <0x0 0x80000000 0x0 0x600000>; 561 no-map; 562 }; 563 564 xbl_mem: memory@80600000 { 565 reg = <0x0 0x80600000 0x0 0x200000>; 566 no-map; 567 }; 568 569 aop_mem: memory@80800000 { 570 reg = <0x0 0x80800000 0x0 0x20000>; 571 no-map; 572 }; 573 574 aop_cmd_db_mem: memory@80820000 { 575 reg = <0x0 0x80820000 0x0 0x20000>; 576 compatible = "qcom,cmd-db"; 577 no-map; 578 }; 579 580 sec_apps_mem: memory@808ff000 { 581 reg = <0x0 0x808ff000 0x0 0x1000>; 582 no-map; 583 }; 584 585 smem_mem: memory@80900000 { 586 reg = <0x0 0x80900000 0x0 0x200000>; 587 no-map; 588 }; 589 590 tz_mem: memory@80b00000 { 591 reg = <0x0 0x80b00000 0x0 0x3900000>; 592 no-map; 593 }; 594 595 ipa_fw_mem: memory@8b700000 { 596 reg = <0 0x8b700000 0 0x10000>; 597 no-map; 598 }; 599 600 rmtfs_mem: memory@94600000 { 601 compatible = "qcom,rmtfs-mem"; 602 reg = <0x0 0x94600000 0x0 0x200000>; 603 no-map; 604 605 qcom,client-id = <1>; 606 qcom,vmid = <15>; 607 }; 608 }; 609 610 smem { 611 compatible = "qcom,smem"; 612 memory-region = <&smem_mem>; 613 hwlocks = <&tcsr_mutex 3>; 614 }; 615 616 smp2p-cdsp { 617 compatible = "qcom,smp2p"; 618 qcom,smem = <94>, <432>; 619 620 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 621 622 mboxes = <&apss_shared 6>; 623 624 qcom,local-pid = <0>; 625 qcom,remote-pid = <5>; 626 627 cdsp_smp2p_out: master-kernel { 628 qcom,entry-name = "master-kernel"; 629 #qcom,smem-state-cells = <1>; 630 }; 631 632 cdsp_smp2p_in: slave-kernel { 633 qcom,entry-name = "slave-kernel"; 634 635 interrupt-controller; 636 #interrupt-cells = <2>; 637 }; 638 }; 639 640 smp2p-lpass { 641 compatible = "qcom,smp2p"; 642 qcom,smem = <443>, <429>; 643 644 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 645 646 mboxes = <&apss_shared 10>; 647 648 qcom,local-pid = <0>; 649 qcom,remote-pid = <2>; 650 651 adsp_smp2p_out: master-kernel { 652 qcom,entry-name = "master-kernel"; 653 #qcom,smem-state-cells = <1>; 654 }; 655 656 adsp_smp2p_in: slave-kernel { 657 qcom,entry-name = "slave-kernel"; 658 659 interrupt-controller; 660 #interrupt-cells = <2>; 661 }; 662 }; 663 664 smp2p-mpss { 665 compatible = "qcom,smp2p"; 666 qcom,smem = <435>, <428>; 667 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 668 mboxes = <&apss_shared 14>; 669 qcom,local-pid = <0>; 670 qcom,remote-pid = <1>; 671 672 modem_smp2p_out: master-kernel { 673 qcom,entry-name = "master-kernel"; 674 #qcom,smem-state-cells = <1>; 675 }; 676 677 modem_smp2p_in: slave-kernel { 678 qcom,entry-name = "slave-kernel"; 679 interrupt-controller; 680 #interrupt-cells = <2>; 681 }; 682 683 ipa_smp2p_out: ipa-ap-to-modem { 684 qcom,entry-name = "ipa"; 685 #qcom,smem-state-cells = <1>; 686 }; 687 688 ipa_smp2p_in: ipa-modem-to-ap { 689 qcom,entry-name = "ipa"; 690 interrupt-controller; 691 #interrupt-cells = <2>; 692 }; 693 }; 694 695 soc: soc@0 { 696 #address-cells = <2>; 697 #size-cells = <2>; 698 ranges = <0 0 0 0 0x10 0>; 699 dma-ranges = <0 0 0 0 0x10 0>; 700 compatible = "simple-bus"; 701 702 gcc: clock-controller@100000 { 703 compatible = "qcom,gcc-sc7180"; 704 reg = <0 0x00100000 0 0x1f0000>; 705 clocks = <&rpmhcc RPMH_CXO_CLK>, 706 <&rpmhcc RPMH_CXO_CLK_A>, 707 <&sleep_clk>; 708 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 709 #clock-cells = <1>; 710 #reset-cells = <1>; 711 #power-domain-cells = <1>; 712 power-domains = <&rpmhpd SC7180_CX>; 713 }; 714 715 qfprom: efuse@784000 { 716 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 717 reg = <0 0x00784000 0 0x7a0>, 718 <0 0x00780000 0 0x7a0>, 719 <0 0x00782000 0 0x100>, 720 <0 0x00786000 0 0x1fff>; 721 722 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 723 clock-names = "core"; 724 #address-cells = <1>; 725 #size-cells = <1>; 726 727 qusb2p_hstx_trim: hstx-trim-primary@25b { 728 reg = <0x25b 0x1>; 729 bits = <1 3>; 730 }; 731 732 gpu_speed_bin: gpu_speed_bin@1d2 { 733 reg = <0x1d2 0x2>; 734 bits = <5 8>; 735 }; 736 }; 737 738 sdhc_1: mmc@7c4000 { 739 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 740 reg = <0 0x007c4000 0 0x1000>, 741 <0 0x007c5000 0 0x1000>; 742 reg-names = "hc", "cqhci"; 743 744 iommus = <&apps_smmu 0x60 0x0>; 745 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 747 interrupt-names = "hc_irq", "pwr_irq"; 748 749 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 750 <&gcc GCC_SDCC1_APPS_CLK>, 751 <&rpmhcc RPMH_CXO_CLK>; 752 clock-names = "iface", "core", "xo"; 753 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 754 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 755 interconnect-names = "sdhc-ddr","cpu-sdhc"; 756 power-domains = <&rpmhpd SC7180_CX>; 757 operating-points-v2 = <&sdhc1_opp_table>; 758 759 bus-width = <8>; 760 non-removable; 761 supports-cqe; 762 763 mmc-ddr-1_8v; 764 mmc-hs200-1_8v; 765 mmc-hs400-1_8v; 766 mmc-hs400-enhanced-strobe; 767 768 status = "disabled"; 769 770 sdhc1_opp_table: opp-table { 771 compatible = "operating-points-v2"; 772 773 opp-100000000 { 774 opp-hz = /bits/ 64 <100000000>; 775 required-opps = <&rpmhpd_opp_low_svs>; 776 opp-peak-kBps = <1800000 600000>; 777 opp-avg-kBps = <100000 0>; 778 }; 779 780 opp-384000000 { 781 opp-hz = /bits/ 64 <384000000>; 782 required-opps = <&rpmhpd_opp_nom>; 783 opp-peak-kBps = <5400000 1600000>; 784 opp-avg-kBps = <390000 0>; 785 }; 786 }; 787 }; 788 789 qupv3_id_0: geniqup@8c0000 { 790 compatible = "qcom,geni-se-qup"; 791 reg = <0 0x008c0000 0 0x6000>; 792 clock-names = "m-ahb", "s-ahb"; 793 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 794 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 795 #address-cells = <2>; 796 #size-cells = <2>; 797 ranges; 798 iommus = <&apps_smmu 0x43 0x0>; 799 status = "disabled"; 800 801 i2c0: i2c@880000 { 802 compatible = "qcom,geni-i2c"; 803 reg = <0 0x00880000 0 0x4000>; 804 clock-names = "se"; 805 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&qup_i2c0_default>; 808 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 812 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 813 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 814 interconnect-names = "qup-core", "qup-config", 815 "qup-memory"; 816 power-domains = <&rpmhpd SC7180_CX>; 817 required-opps = <&rpmhpd_opp_low_svs>; 818 status = "disabled"; 819 }; 820 821 spi0: spi@880000 { 822 compatible = "qcom,geni-spi"; 823 reg = <0 0x00880000 0 0x4000>; 824 clock-names = "se"; 825 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 828 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 power-domains = <&rpmhpd SC7180_CX>; 832 operating-points-v2 = <&qup_opp_table>; 833 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 834 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 status = "disabled"; 837 }; 838 839 uart0: serial@880000 { 840 compatible = "qcom,geni-uart"; 841 reg = <0 0x00880000 0 0x4000>; 842 clock-names = "se"; 843 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&qup_uart0_default>; 846 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 847 power-domains = <&rpmhpd SC7180_CX>; 848 operating-points-v2 = <&qup_opp_table>; 849 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 850 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 851 interconnect-names = "qup-core", "qup-config"; 852 status = "disabled"; 853 }; 854 855 i2c1: i2c@884000 { 856 compatible = "qcom,geni-i2c"; 857 reg = <0 0x00884000 0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_i2c1_default>; 862 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 866 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 867 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 868 interconnect-names = "qup-core", "qup-config", 869 "qup-memory"; 870 power-domains = <&rpmhpd SC7180_CX>; 871 required-opps = <&rpmhpd_opp_low_svs>; 872 status = "disabled"; 873 }; 874 875 spi1: spi@884000 { 876 compatible = "qcom,geni-spi"; 877 reg = <0 0x00884000 0 0x4000>; 878 clock-names = "se"; 879 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 882 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 power-domains = <&rpmhpd SC7180_CX>; 886 operating-points-v2 = <&qup_opp_table>; 887 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 889 interconnect-names = "qup-core", "qup-config"; 890 status = "disabled"; 891 }; 892 893 uart1: serial@884000 { 894 compatible = "qcom,geni-uart"; 895 reg = <0 0x00884000 0 0x4000>; 896 clock-names = "se"; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_uart1_default>; 900 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 901 power-domains = <&rpmhpd SC7180_CX>; 902 operating-points-v2 = <&qup_opp_table>; 903 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 905 interconnect-names = "qup-core", "qup-config"; 906 status = "disabled"; 907 }; 908 909 i2c2: i2c@888000 { 910 compatible = "qcom,geni-i2c"; 911 reg = <0 0x00888000 0 0x4000>; 912 clock-names = "se"; 913 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&qup_i2c2_default>; 916 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 921 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 922 interconnect-names = "qup-core", "qup-config", 923 "qup-memory"; 924 power-domains = <&rpmhpd SC7180_CX>; 925 required-opps = <&rpmhpd_opp_low_svs>; 926 status = "disabled"; 927 }; 928 929 uart2: serial@888000 { 930 compatible = "qcom,geni-uart"; 931 reg = <0 0x00888000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_uart2_default>; 936 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 937 power-domains = <&rpmhpd SC7180_CX>; 938 operating-points-v2 = <&qup_opp_table>; 939 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 940 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 941 interconnect-names = "qup-core", "qup-config"; 942 status = "disabled"; 943 }; 944 945 i2c3: i2c@88c000 { 946 compatible = "qcom,geni-i2c"; 947 reg = <0 0x0088c000 0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&qup_i2c3_default>; 952 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 956 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 957 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 958 interconnect-names = "qup-core", "qup-config", 959 "qup-memory"; 960 power-domains = <&rpmhpd SC7180_CX>; 961 required-opps = <&rpmhpd_opp_low_svs>; 962 status = "disabled"; 963 }; 964 965 spi3: spi@88c000 { 966 compatible = "qcom,geni-spi"; 967 reg = <0 0x0088c000 0 0x4000>; 968 clock-names = "se"; 969 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 972 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 power-domains = <&rpmhpd SC7180_CX>; 976 operating-points-v2 = <&qup_opp_table>; 977 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 978 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 979 interconnect-names = "qup-core", "qup-config"; 980 status = "disabled"; 981 }; 982 983 uart3: serial@88c000 { 984 compatible = "qcom,geni-uart"; 985 reg = <0 0x0088c000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_uart3_default>; 990 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 991 power-domains = <&rpmhpd SC7180_CX>; 992 operating-points-v2 = <&qup_opp_table>; 993 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 995 interconnect-names = "qup-core", "qup-config"; 996 status = "disabled"; 997 }; 998 999 i2c4: i2c@890000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00890000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&qup_i2c4_default>; 1006 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1010 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1011 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1012 interconnect-names = "qup-core", "qup-config", 1013 "qup-memory"; 1014 power-domains = <&rpmhpd SC7180_CX>; 1015 required-opps = <&rpmhpd_opp_low_svs>; 1016 status = "disabled"; 1017 }; 1018 1019 uart4: serial@890000 { 1020 compatible = "qcom,geni-uart"; 1021 reg = <0 0x00890000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_uart4_default>; 1026 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1027 power-domains = <&rpmhpd SC7180_CX>; 1028 operating-points-v2 = <&qup_opp_table>; 1029 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1031 interconnect-names = "qup-core", "qup-config"; 1032 status = "disabled"; 1033 }; 1034 1035 i2c5: i2c@894000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x00894000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c5_default>; 1042 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1047 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", 1049 "qup-memory"; 1050 power-domains = <&rpmhpd SC7180_CX>; 1051 required-opps = <&rpmhpd_opp_low_svs>; 1052 status = "disabled"; 1053 }; 1054 1055 spi5: spi@894000 { 1056 compatible = "qcom,geni-spi"; 1057 reg = <0 0x00894000 0 0x4000>; 1058 clock-names = "se"; 1059 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1062 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 power-domains = <&rpmhpd SC7180_CX>; 1066 operating-points-v2 = <&qup_opp_table>; 1067 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1069 interconnect-names = "qup-core", "qup-config"; 1070 status = "disabled"; 1071 }; 1072 1073 uart5: serial@894000 { 1074 compatible = "qcom,geni-uart"; 1075 reg = <0 0x00894000 0 0x4000>; 1076 clock-names = "se"; 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1078 pinctrl-names = "default"; 1079 pinctrl-0 = <&qup_uart5_default>; 1080 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1081 power-domains = <&rpmhpd SC7180_CX>; 1082 operating-points-v2 = <&qup_opp_table>; 1083 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1085 interconnect-names = "qup-core", "qup-config"; 1086 status = "disabled"; 1087 }; 1088 }; 1089 1090 qupv3_id_1: geniqup@ac0000 { 1091 compatible = "qcom,geni-se-qup"; 1092 reg = <0 0x00ac0000 0 0x6000>; 1093 clock-names = "m-ahb", "s-ahb"; 1094 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1095 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1096 #address-cells = <2>; 1097 #size-cells = <2>; 1098 ranges; 1099 iommus = <&apps_smmu 0x4c3 0x0>; 1100 status = "disabled"; 1101 1102 i2c6: i2c@a80000 { 1103 compatible = "qcom,geni-i2c"; 1104 reg = <0 0x00a80000 0 0x4000>; 1105 clock-names = "se"; 1106 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&qup_i2c6_default>; 1109 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1114 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1115 interconnect-names = "qup-core", "qup-config", 1116 "qup-memory"; 1117 power-domains = <&rpmhpd SC7180_CX>; 1118 required-opps = <&rpmhpd_opp_low_svs>; 1119 status = "disabled"; 1120 }; 1121 1122 spi6: spi@a80000 { 1123 compatible = "qcom,geni-spi"; 1124 reg = <0 0x00a80000 0 0x4000>; 1125 clock-names = "se"; 1126 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1127 pinctrl-names = "default"; 1128 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1129 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 power-domains = <&rpmhpd SC7180_CX>; 1133 operating-points-v2 = <&qup_opp_table>; 1134 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1136 interconnect-names = "qup-core", "qup-config"; 1137 status = "disabled"; 1138 }; 1139 1140 uart6: serial@a80000 { 1141 compatible = "qcom,geni-uart"; 1142 reg = <0 0x00a80000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_uart6_default>; 1147 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1148 power-domains = <&rpmhpd SC7180_CX>; 1149 operating-points-v2 = <&qup_opp_table>; 1150 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1151 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1152 interconnect-names = "qup-core", "qup-config"; 1153 status = "disabled"; 1154 }; 1155 1156 i2c7: i2c@a84000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x00a84000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_i2c7_default>; 1163 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1167 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1168 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1169 interconnect-names = "qup-core", "qup-config", 1170 "qup-memory"; 1171 power-domains = <&rpmhpd SC7180_CX>; 1172 required-opps = <&rpmhpd_opp_low_svs>; 1173 status = "disabled"; 1174 }; 1175 1176 uart7: serial@a84000 { 1177 compatible = "qcom,geni-uart"; 1178 reg = <0 0x00a84000 0 0x4000>; 1179 clock-names = "se"; 1180 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&qup_uart7_default>; 1183 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1184 power-domains = <&rpmhpd SC7180_CX>; 1185 operating-points-v2 = <&qup_opp_table>; 1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1188 interconnect-names = "qup-core", "qup-config"; 1189 status = "disabled"; 1190 }; 1191 1192 i2c8: i2c@a88000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x00a88000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_i2c8_default>; 1199 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1204 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1205 interconnect-names = "qup-core", "qup-config", 1206 "qup-memory"; 1207 power-domains = <&rpmhpd SC7180_CX>; 1208 required-opps = <&rpmhpd_opp_low_svs>; 1209 status = "disabled"; 1210 }; 1211 1212 spi8: spi@a88000 { 1213 compatible = "qcom,geni-spi"; 1214 reg = <0 0x00a88000 0 0x4000>; 1215 clock-names = "se"; 1216 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1219 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 power-domains = <&rpmhpd SC7180_CX>; 1223 operating-points-v2 = <&qup_opp_table>; 1224 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1225 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1226 interconnect-names = "qup-core", "qup-config"; 1227 status = "disabled"; 1228 }; 1229 1230 uart8: serial@a88000 { 1231 compatible = "qcom,geni-debug-uart"; 1232 reg = <0 0x00a88000 0 0x4000>; 1233 clock-names = "se"; 1234 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1235 pinctrl-names = "default"; 1236 pinctrl-0 = <&qup_uart8_default>; 1237 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1238 power-domains = <&rpmhpd SC7180_CX>; 1239 operating-points-v2 = <&qup_opp_table>; 1240 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1241 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1242 interconnect-names = "qup-core", "qup-config"; 1243 status = "disabled"; 1244 }; 1245 1246 i2c9: i2c@a8c000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0 0x00a8c000 0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c9_default>; 1253 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1257 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1258 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1259 interconnect-names = "qup-core", "qup-config", 1260 "qup-memory"; 1261 power-domains = <&rpmhpd SC7180_CX>; 1262 required-opps = <&rpmhpd_opp_low_svs>; 1263 status = "disabled"; 1264 }; 1265 1266 uart9: serial@a8c000 { 1267 compatible = "qcom,geni-uart"; 1268 reg = <0 0x00a8c000 0 0x4000>; 1269 clock-names = "se"; 1270 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_uart9_default>; 1273 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1274 power-domains = <&rpmhpd SC7180_CX>; 1275 operating-points-v2 = <&qup_opp_table>; 1276 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1278 interconnect-names = "qup-core", "qup-config"; 1279 status = "disabled"; 1280 }; 1281 1282 i2c10: i2c@a90000 { 1283 compatible = "qcom,geni-i2c"; 1284 reg = <0 0x00a90000 0 0x4000>; 1285 clock-names = "se"; 1286 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1287 pinctrl-names = "default"; 1288 pinctrl-0 = <&qup_i2c10_default>; 1289 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1293 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1294 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1295 interconnect-names = "qup-core", "qup-config", 1296 "qup-memory"; 1297 power-domains = <&rpmhpd SC7180_CX>; 1298 required-opps = <&rpmhpd_opp_low_svs>; 1299 status = "disabled"; 1300 }; 1301 1302 spi10: spi@a90000 { 1303 compatible = "qcom,geni-spi"; 1304 reg = <0 0x00a90000 0 0x4000>; 1305 clock-names = "se"; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1309 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 power-domains = <&rpmhpd SC7180_CX>; 1313 operating-points-v2 = <&qup_opp_table>; 1314 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1315 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1316 interconnect-names = "qup-core", "qup-config"; 1317 status = "disabled"; 1318 }; 1319 1320 uart10: serial@a90000 { 1321 compatible = "qcom,geni-uart"; 1322 reg = <0 0x00a90000 0 0x4000>; 1323 clock-names = "se"; 1324 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1325 pinctrl-names = "default"; 1326 pinctrl-0 = <&qup_uart10_default>; 1327 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1328 power-domains = <&rpmhpd SC7180_CX>; 1329 operating-points-v2 = <&qup_opp_table>; 1330 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1332 interconnect-names = "qup-core", "qup-config"; 1333 status = "disabled"; 1334 }; 1335 1336 i2c11: i2c@a94000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0 0x00a94000 0 0x4000>; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_i2c11_default>; 1343 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1348 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", 1350 "qup-memory"; 1351 power-domains = <&rpmhpd SC7180_CX>; 1352 required-opps = <&rpmhpd_opp_low_svs>; 1353 status = "disabled"; 1354 }; 1355 1356 spi11: spi@a94000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0 0x00a94000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1363 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 power-domains = <&rpmhpd SC7180_CX>; 1367 operating-points-v2 = <&qup_opp_table>; 1368 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1369 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1370 interconnect-names = "qup-core", "qup-config"; 1371 status = "disabled"; 1372 }; 1373 1374 uart11: serial@a94000 { 1375 compatible = "qcom,geni-uart"; 1376 reg = <0 0x00a94000 0 0x4000>; 1377 clock-names = "se"; 1378 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&qup_uart11_default>; 1381 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1382 power-domains = <&rpmhpd SC7180_CX>; 1383 operating-points-v2 = <&qup_opp_table>; 1384 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1386 interconnect-names = "qup-core", "qup-config"; 1387 status = "disabled"; 1388 }; 1389 }; 1390 1391 config_noc: interconnect@1500000 { 1392 compatible = "qcom,sc7180-config-noc"; 1393 reg = <0 0x01500000 0 0x28000>; 1394 #interconnect-cells = <2>; 1395 qcom,bcm-voters = <&apps_bcm_voter>; 1396 }; 1397 1398 system_noc: interconnect@1620000 { 1399 compatible = "qcom,sc7180-system-noc"; 1400 reg = <0 0x01620000 0 0x17080>; 1401 #interconnect-cells = <2>; 1402 qcom,bcm-voters = <&apps_bcm_voter>; 1403 }; 1404 1405 mc_virt: interconnect@1638000 { 1406 compatible = "qcom,sc7180-mc-virt"; 1407 reg = <0 0x01638000 0 0x1000>; 1408 #interconnect-cells = <2>; 1409 qcom,bcm-voters = <&apps_bcm_voter>; 1410 }; 1411 1412 qup_virt: interconnect@1650000 { 1413 compatible = "qcom,sc7180-qup-virt"; 1414 reg = <0 0x01650000 0 0x1000>; 1415 #interconnect-cells = <2>; 1416 qcom,bcm-voters = <&apps_bcm_voter>; 1417 }; 1418 1419 aggre1_noc: interconnect@16e0000 { 1420 compatible = "qcom,sc7180-aggre1-noc"; 1421 reg = <0 0x016e0000 0 0x15080>; 1422 #interconnect-cells = <2>; 1423 qcom,bcm-voters = <&apps_bcm_voter>; 1424 }; 1425 1426 aggre2_noc: interconnect@1705000 { 1427 compatible = "qcom,sc7180-aggre2-noc"; 1428 reg = <0 0x01705000 0 0x9000>; 1429 #interconnect-cells = <2>; 1430 qcom,bcm-voters = <&apps_bcm_voter>; 1431 }; 1432 1433 compute_noc: interconnect@170e000 { 1434 compatible = "qcom,sc7180-compute-noc"; 1435 reg = <0 0x0170e000 0 0x6000>; 1436 #interconnect-cells = <2>; 1437 qcom,bcm-voters = <&apps_bcm_voter>; 1438 }; 1439 1440 mmss_noc: interconnect@1740000 { 1441 compatible = "qcom,sc7180-mmss-noc"; 1442 reg = <0 0x01740000 0 0x1c100>; 1443 #interconnect-cells = <2>; 1444 qcom,bcm-voters = <&apps_bcm_voter>; 1445 }; 1446 1447 ipa: ipa@1e40000 { 1448 compatible = "qcom,sc7180-ipa"; 1449 1450 iommus = <&apps_smmu 0x440 0x0>, 1451 <&apps_smmu 0x442 0x0>; 1452 reg = <0 0x01e40000 0 0x7000>, 1453 <0 0x01e47000 0 0x2000>, 1454 <0 0x01e04000 0 0x2c000>; 1455 reg-names = "ipa-reg", 1456 "ipa-shared", 1457 "gsi"; 1458 1459 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1460 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1461 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1462 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1463 interrupt-names = "ipa", 1464 "gsi", 1465 "ipa-clock-query", 1466 "ipa-setup-ready"; 1467 1468 clocks = <&rpmhcc RPMH_IPA_CLK>; 1469 clock-names = "core"; 1470 1471 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1472 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1473 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1474 interconnect-names = "memory", 1475 "imem", 1476 "config"; 1477 1478 qcom,qmp = <&aoss_qmp>; 1479 1480 qcom,smem-states = <&ipa_smp2p_out 0>, 1481 <&ipa_smp2p_out 1>; 1482 qcom,smem-state-names = "ipa-clock-enabled-valid", 1483 "ipa-clock-enabled"; 1484 1485 status = "disabled"; 1486 }; 1487 1488 tcsr_mutex: hwlock@1f40000 { 1489 compatible = "qcom,tcsr-mutex"; 1490 reg = <0 0x01f40000 0 0x20000>; 1491 #hwlock-cells = <1>; 1492 }; 1493 1494 tcsr_regs_1: syscon@1f60000 { 1495 compatible = "qcom,sc7180-tcsr", "syscon"; 1496 reg = <0 0x01f60000 0 0x20000>; 1497 }; 1498 1499 tcsr_regs_2: syscon@1fc0000 { 1500 compatible = "qcom,sc7180-tcsr", "syscon"; 1501 reg = <0 0x01fc0000 0 0x40000>; 1502 }; 1503 1504 tlmm: pinctrl@3500000 { 1505 compatible = "qcom,sc7180-pinctrl"; 1506 reg = <0 0x03500000 0 0x300000>, 1507 <0 0x03900000 0 0x300000>, 1508 <0 0x03d00000 0 0x300000>; 1509 reg-names = "west", "north", "south"; 1510 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1511 gpio-controller; 1512 #gpio-cells = <2>; 1513 interrupt-controller; 1514 #interrupt-cells = <2>; 1515 gpio-ranges = <&tlmm 0 0 120>; 1516 wakeup-parent = <&pdc>; 1517 1518 dp_hot_plug_det: dp-hot-plug-det-state { 1519 pins = "gpio117"; 1520 function = "dp_hot"; 1521 }; 1522 1523 qspi_clk: qspi-clk-state { 1524 pins = "gpio63"; 1525 function = "qspi_clk"; 1526 }; 1527 1528 qspi_cs0: qspi-cs0-state { 1529 pins = "gpio68"; 1530 function = "qspi_cs"; 1531 }; 1532 1533 qspi_cs1: qspi-cs1-state { 1534 pins = "gpio72"; 1535 function = "qspi_cs"; 1536 }; 1537 1538 qspi_data01: qspi-data01-state { 1539 pins = "gpio64", "gpio65"; 1540 function = "qspi_data"; 1541 }; 1542 1543 qspi_data12: qspi-data12-state { 1544 pins = "gpio66", "gpio67"; 1545 function = "qspi_data"; 1546 }; 1547 1548 qup_i2c0_default: qup-i2c0-default-state { 1549 pins = "gpio34", "gpio35"; 1550 function = "qup00"; 1551 }; 1552 1553 qup_i2c1_default: qup-i2c1-default-state { 1554 pins = "gpio0", "gpio1"; 1555 function = "qup01"; 1556 }; 1557 1558 qup_i2c2_default: qup-i2c2-default-state { 1559 pins = "gpio15", "gpio16"; 1560 function = "qup02_i2c"; 1561 }; 1562 1563 qup_i2c3_default: qup-i2c3-default-state { 1564 pins = "gpio38", "gpio39"; 1565 function = "qup03"; 1566 }; 1567 1568 qup_i2c4_default: qup-i2c4-default-state { 1569 pins = "gpio115", "gpio116"; 1570 function = "qup04_i2c"; 1571 }; 1572 1573 qup_i2c5_default: qup-i2c5-default-state { 1574 pins = "gpio25", "gpio26"; 1575 function = "qup05"; 1576 }; 1577 1578 qup_i2c6_default: qup-i2c6-default-state { 1579 pins = "gpio59", "gpio60"; 1580 function = "qup10"; 1581 }; 1582 1583 qup_i2c7_default: qup-i2c7-default-state { 1584 pins = "gpio6", "gpio7"; 1585 function = "qup11_i2c"; 1586 }; 1587 1588 qup_i2c8_default: qup-i2c8-default-state { 1589 pins = "gpio42", "gpio43"; 1590 function = "qup12"; 1591 }; 1592 1593 qup_i2c9_default: qup-i2c9-default-state { 1594 pins = "gpio46", "gpio47"; 1595 function = "qup13_i2c"; 1596 }; 1597 1598 qup_i2c10_default: qup-i2c10-default-state { 1599 pins = "gpio86", "gpio87"; 1600 function = "qup14"; 1601 }; 1602 1603 qup_i2c11_default: qup-i2c11-default-state { 1604 pins = "gpio53", "gpio54"; 1605 function = "qup15"; 1606 }; 1607 1608 qup_spi0_spi: qup-spi0-spi-state { 1609 pins = "gpio34", "gpio35", "gpio36"; 1610 function = "qup00"; 1611 }; 1612 1613 qup_spi0_cs: qup-spi0-cs-state { 1614 pins = "gpio37"; 1615 function = "qup00"; 1616 }; 1617 1618 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1619 pins = "gpio37"; 1620 function = "gpio"; 1621 }; 1622 1623 qup_spi1_spi: qup-spi1-spi-state { 1624 pins = "gpio0", "gpio1", "gpio2"; 1625 function = "qup01"; 1626 }; 1627 1628 qup_spi1_cs: qup-spi1-cs-state { 1629 pins = "gpio3"; 1630 function = "qup01"; 1631 }; 1632 1633 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1634 pins = "gpio3"; 1635 function = "gpio"; 1636 }; 1637 1638 qup_spi3_spi: qup-spi3-spi-state { 1639 pins = "gpio38", "gpio39", "gpio40"; 1640 function = "qup03"; 1641 }; 1642 1643 qup_spi3_cs: qup-spi3-cs-state { 1644 pins = "gpio41"; 1645 function = "qup03"; 1646 }; 1647 1648 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1649 pins = "gpio41"; 1650 function = "gpio"; 1651 }; 1652 1653 qup_spi5_spi: qup-spi5-spi-state { 1654 pins = "gpio25", "gpio26", "gpio27"; 1655 function = "qup05"; 1656 }; 1657 1658 qup_spi5_cs: qup-spi5-cs-state { 1659 pins = "gpio28"; 1660 function = "qup05"; 1661 }; 1662 1663 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1664 pins = "gpio28"; 1665 function = "gpio"; 1666 }; 1667 1668 qup_spi6_spi: qup-spi6-spi-state { 1669 pins = "gpio59", "gpio60", "gpio61"; 1670 function = "qup10"; 1671 }; 1672 1673 qup_spi6_cs: qup-spi6-cs-state { 1674 pins = "gpio62"; 1675 function = "qup10"; 1676 }; 1677 1678 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1679 pins = "gpio62"; 1680 function = "gpio"; 1681 }; 1682 1683 qup_spi8_spi: qup-spi8-spi-state { 1684 pins = "gpio42", "gpio43", "gpio44"; 1685 function = "qup12"; 1686 }; 1687 1688 qup_spi8_cs: qup-spi8-cs-state { 1689 pins = "gpio45"; 1690 function = "qup12"; 1691 }; 1692 1693 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1694 pins = "gpio45"; 1695 function = "gpio"; 1696 }; 1697 1698 qup_spi10_spi: qup-spi10-spi-state { 1699 pins = "gpio86", "gpio87", "gpio88"; 1700 function = "qup14"; 1701 }; 1702 1703 qup_spi10_cs: qup-spi10-cs-state { 1704 pins = "gpio89"; 1705 function = "qup14"; 1706 }; 1707 1708 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1709 pins = "gpio89"; 1710 function = "gpio"; 1711 }; 1712 1713 qup_spi11_spi: qup-spi11-spi-state { 1714 pins = "gpio53", "gpio54", "gpio55"; 1715 function = "qup15"; 1716 }; 1717 1718 qup_spi11_cs: qup-spi11-cs-state { 1719 pins = "gpio56"; 1720 function = "qup15"; 1721 }; 1722 1723 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1724 pins = "gpio56"; 1725 function = "gpio"; 1726 }; 1727 1728 qup_uart0_default: qup-uart0-default-state { 1729 qup_uart0_cts: cts-pins { 1730 pins = "gpio34"; 1731 function = "qup00"; 1732 }; 1733 1734 qup_uart0_rts: rts-pins { 1735 pins = "gpio35"; 1736 function = "qup00"; 1737 }; 1738 1739 qup_uart0_tx: tx-pins { 1740 pins = "gpio36"; 1741 function = "qup00"; 1742 }; 1743 1744 qup_uart0_rx: rx-pins { 1745 pins = "gpio37"; 1746 function = "qup00"; 1747 }; 1748 }; 1749 1750 qup_uart1_default: qup-uart1-default-state { 1751 qup_uart1_cts: cts-pins { 1752 pins = "gpio0"; 1753 function = "qup01"; 1754 }; 1755 1756 qup_uart1_rts: rts-pins { 1757 pins = "gpio1"; 1758 function = "qup01"; 1759 }; 1760 1761 qup_uart1_tx: tx-pins { 1762 pins = "gpio2"; 1763 function = "qup01"; 1764 }; 1765 1766 qup_uart1_rx: rx-pins { 1767 pins = "gpio3"; 1768 function = "qup01"; 1769 }; 1770 }; 1771 1772 qup_uart2_default: qup-uart2-default-state { 1773 qup_uart2_tx: tx-pins { 1774 pins = "gpio15"; 1775 function = "qup02_uart"; 1776 }; 1777 1778 qup_uart2_rx: rx-pins { 1779 pins = "gpio16"; 1780 function = "qup02_uart"; 1781 }; 1782 }; 1783 1784 qup_uart3_default: qup-uart3-default-state { 1785 qup_uart3_cts: cts-pins { 1786 pins = "gpio38"; 1787 function = "qup03"; 1788 }; 1789 1790 qup_uart3_rts: rts-pins { 1791 pins = "gpio39"; 1792 function = "qup03"; 1793 }; 1794 1795 qup_uart3_tx: tx-pins { 1796 pins = "gpio40"; 1797 function = "qup03"; 1798 }; 1799 1800 qup_uart3_rx: rx-pins { 1801 pins = "gpio41"; 1802 function = "qup03"; 1803 }; 1804 }; 1805 1806 qup_uart4_default: qup-uart4-default-state { 1807 qup_uart4_tx: tx-pins { 1808 pins = "gpio115"; 1809 function = "qup04_uart"; 1810 }; 1811 1812 qup_uart4_rx: rx-pins { 1813 pins = "gpio116"; 1814 function = "qup04_uart"; 1815 }; 1816 }; 1817 1818 qup_uart5_default: qup-uart5-default-state { 1819 qup_uart5_cts: cts-pins { 1820 pins = "gpio25"; 1821 function = "qup05"; 1822 }; 1823 1824 qup_uart5_rts: rts-pins { 1825 pins = "gpio26"; 1826 function = "qup05"; 1827 }; 1828 1829 qup_uart5_tx: tx-pins { 1830 pins = "gpio27"; 1831 function = "qup05"; 1832 }; 1833 1834 qup_uart5_rx: rx-pins { 1835 pins = "gpio28"; 1836 function = "qup05"; 1837 }; 1838 }; 1839 1840 qup_uart6_default: qup-uart6-default-state { 1841 qup_uart6_cts: cts-pins { 1842 pins = "gpio59"; 1843 function = "qup10"; 1844 }; 1845 1846 qup_uart6_rts: rts-pins { 1847 pins = "gpio60"; 1848 function = "qup10"; 1849 }; 1850 1851 qup_uart6_tx: tx-pins { 1852 pins = "gpio61"; 1853 function = "qup10"; 1854 }; 1855 1856 qup_uart6_rx: rx-pins { 1857 pins = "gpio62"; 1858 function = "qup10"; 1859 }; 1860 }; 1861 1862 qup_uart7_default: qup-uart7-default-state { 1863 qup_uart7_tx: tx-pins { 1864 pins = "gpio6"; 1865 function = "qup11_uart"; 1866 }; 1867 1868 qup_uart7_rx: rx-pins { 1869 pins = "gpio7"; 1870 function = "qup11_uart"; 1871 }; 1872 }; 1873 1874 qup_uart8_default: qup-uart8-default-state { 1875 qup_uart8_tx: tx-pins { 1876 pins = "gpio44"; 1877 function = "qup12"; 1878 }; 1879 1880 qup_uart8_rx: rx-pins { 1881 pins = "gpio45"; 1882 function = "qup12"; 1883 }; 1884 }; 1885 1886 qup_uart9_default: qup-uart9-default-state { 1887 qup_uart9_tx: tx-pins { 1888 pins = "gpio46"; 1889 function = "qup13_uart"; 1890 }; 1891 1892 qup_uart9_rx: rx-pins { 1893 pins = "gpio47"; 1894 function = "qup13_uart"; 1895 }; 1896 }; 1897 1898 qup_uart10_default: qup-uart10-default-state { 1899 qup_uart10_cts: cts-pins { 1900 pins = "gpio86"; 1901 function = "qup14"; 1902 }; 1903 1904 qup_uart10_rts: rts-pins { 1905 pins = "gpio87"; 1906 function = "qup14"; 1907 }; 1908 1909 qup_uart10_tx: tx-pins { 1910 pins = "gpio88"; 1911 function = "qup14"; 1912 }; 1913 1914 qup_uart10_rx: rx-pins { 1915 pins = "gpio89"; 1916 function = "qup14"; 1917 }; 1918 }; 1919 1920 qup_uart11_default: qup-uart11-default-state { 1921 qup_uart11_cts: cts-pins { 1922 pins = "gpio53"; 1923 function = "qup15"; 1924 }; 1925 1926 qup_uart11_rts: rts-pins { 1927 pins = "gpio54"; 1928 function = "qup15"; 1929 }; 1930 1931 qup_uart11_tx: tx-pins { 1932 pins = "gpio55"; 1933 function = "qup15"; 1934 }; 1935 1936 qup_uart11_rx: rx-pins { 1937 pins = "gpio56"; 1938 function = "qup15"; 1939 }; 1940 }; 1941 1942 sec_mi2s_active: sec-mi2s-active-state { 1943 pins = "gpio49", "gpio50", "gpio51"; 1944 function = "mi2s_1"; 1945 }; 1946 1947 pri_mi2s_active: pri-mi2s-active-state { 1948 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1949 function = "mi2s_0"; 1950 }; 1951 1952 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 1953 pins = "gpio57"; 1954 function = "lpass_ext"; 1955 }; 1956 }; 1957 1958 remoteproc_mpss: remoteproc@4080000 { 1959 compatible = "qcom,sc7180-mpss-pas"; 1960 reg = <0 0x04080000 0 0x4040>; 1961 1962 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1963 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1964 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1965 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1966 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1967 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1968 interrupt-names = "wdog", "fatal", "ready", "handover", 1969 "stop-ack", "shutdown-ack"; 1970 1971 clocks = <&rpmhcc RPMH_CXO_CLK>; 1972 clock-names = "xo"; 1973 1974 power-domains = <&rpmhpd SC7180_CX>, 1975 <&rpmhpd SC7180_MX>, 1976 <&rpmhpd SC7180_MSS>; 1977 power-domain-names = "cx", "mx", "mss"; 1978 1979 memory-region = <&mpss_mem>; 1980 1981 qcom,qmp = <&aoss_qmp>; 1982 1983 qcom,smem-states = <&modem_smp2p_out 0>; 1984 qcom,smem-state-names = "stop"; 1985 1986 status = "disabled"; 1987 1988 glink-edge { 1989 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1990 label = "modem"; 1991 qcom,remote-pid = <1>; 1992 mboxes = <&apss_shared 12>; 1993 }; 1994 }; 1995 1996 gpu: gpu@5000000 { 1997 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1998 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1999 <0 0x05061000 0 0x800>; 2000 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2001 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2002 iommus = <&adreno_smmu 0>; 2003 operating-points-v2 = <&gpu_opp_table>; 2004 qcom,gmu = <&gmu>; 2005 2006 #cooling-cells = <2>; 2007 2008 nvmem-cells = <&gpu_speed_bin>; 2009 nvmem-cell-names = "speed_bin"; 2010 2011 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2012 interconnect-names = "gfx-mem"; 2013 2014 gpu_opp_table: opp-table { 2015 compatible = "operating-points-v2"; 2016 2017 opp-825000000 { 2018 opp-hz = /bits/ 64 <825000000>; 2019 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2020 opp-peak-kBps = <8532000>; 2021 opp-supported-hw = <0x04>; 2022 }; 2023 2024 opp-800000000 { 2025 opp-hz = /bits/ 64 <800000000>; 2026 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2027 opp-peak-kBps = <8532000>; 2028 opp-supported-hw = <0x07>; 2029 }; 2030 2031 opp-650000000 { 2032 opp-hz = /bits/ 64 <650000000>; 2033 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2034 opp-peak-kBps = <7216000>; 2035 opp-supported-hw = <0x07>; 2036 }; 2037 2038 opp-565000000 { 2039 opp-hz = /bits/ 64 <565000000>; 2040 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2041 opp-peak-kBps = <5412000>; 2042 opp-supported-hw = <0x07>; 2043 }; 2044 2045 opp-430000000 { 2046 opp-hz = /bits/ 64 <430000000>; 2047 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2048 opp-peak-kBps = <5412000>; 2049 opp-supported-hw = <0x07>; 2050 }; 2051 2052 opp-355000000 { 2053 opp-hz = /bits/ 64 <355000000>; 2054 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2055 opp-peak-kBps = <3072000>; 2056 opp-supported-hw = <0x07>; 2057 }; 2058 2059 opp-267000000 { 2060 opp-hz = /bits/ 64 <267000000>; 2061 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2062 opp-peak-kBps = <3072000>; 2063 opp-supported-hw = <0x07>; 2064 }; 2065 2066 opp-180000000 { 2067 opp-hz = /bits/ 64 <180000000>; 2068 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2069 opp-peak-kBps = <1804000>; 2070 opp-supported-hw = <0x07>; 2071 }; 2072 }; 2073 }; 2074 2075 adreno_smmu: iommu@5040000 { 2076 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2077 reg = <0 0x05040000 0 0x10000>; 2078 #iommu-cells = <1>; 2079 #global-interrupts = <2>; 2080 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2083 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2084 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2085 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2086 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2087 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2088 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2089 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2090 2091 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2092 <&gcc GCC_GPU_CFG_AHB_CLK>; 2093 clock-names = "bus", "iface"; 2094 2095 power-domains = <&gpucc CX_GDSC>; 2096 }; 2097 2098 gmu: gmu@506a000 { 2099 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2100 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2101 <0 0x0b490000 0 0x10000>; 2102 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2103 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2105 interrupt-names = "hfi", "gmu"; 2106 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2107 <&gpucc GPU_CC_CXO_CLK>, 2108 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2109 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2110 clock-names = "gmu", "cxo", "axi", "memnoc"; 2111 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2112 power-domain-names = "cx", "gx"; 2113 iommus = <&adreno_smmu 5>; 2114 operating-points-v2 = <&gmu_opp_table>; 2115 2116 gmu_opp_table: opp-table { 2117 compatible = "operating-points-v2"; 2118 2119 opp-200000000 { 2120 opp-hz = /bits/ 64 <200000000>; 2121 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2122 }; 2123 }; 2124 }; 2125 2126 gpucc: clock-controller@5090000 { 2127 compatible = "qcom,sc7180-gpucc"; 2128 reg = <0 0x05090000 0 0x9000>; 2129 clocks = <&rpmhcc RPMH_CXO_CLK>, 2130 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2131 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2132 clock-names = "bi_tcxo", 2133 "gcc_gpu_gpll0_clk_src", 2134 "gcc_gpu_gpll0_div_clk_src"; 2135 #clock-cells = <1>; 2136 #reset-cells = <1>; 2137 #power-domain-cells = <1>; 2138 }; 2139 2140 dma@10a2000 { 2141 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2142 reg = <0x0 0x010a2000 0x0 0x1000>, 2143 <0x0 0x010ae000 0x0 0x2000>; 2144 }; 2145 2146 stm@6002000 { 2147 compatible = "arm,coresight-stm", "arm,primecell"; 2148 reg = <0 0x06002000 0 0x1000>, 2149 <0 0x16280000 0 0x180000>; 2150 reg-names = "stm-base", "stm-stimulus-base"; 2151 2152 clocks = <&aoss_qmp>; 2153 clock-names = "apb_pclk"; 2154 2155 out-ports { 2156 port { 2157 stm_out: endpoint { 2158 remote-endpoint = <&funnel0_in7>; 2159 }; 2160 }; 2161 }; 2162 }; 2163 2164 funnel@6041000 { 2165 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2166 reg = <0 0x06041000 0 0x1000>; 2167 2168 clocks = <&aoss_qmp>; 2169 clock-names = "apb_pclk"; 2170 2171 out-ports { 2172 port { 2173 funnel0_out: endpoint { 2174 remote-endpoint = <&merge_funnel_in0>; 2175 }; 2176 }; 2177 }; 2178 2179 in-ports { 2180 #address-cells = <1>; 2181 #size-cells = <0>; 2182 2183 port@7 { 2184 reg = <7>; 2185 funnel0_in7: endpoint { 2186 remote-endpoint = <&stm_out>; 2187 }; 2188 }; 2189 }; 2190 }; 2191 2192 funnel@6042000 { 2193 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2194 reg = <0 0x06042000 0 0x1000>; 2195 2196 clocks = <&aoss_qmp>; 2197 clock-names = "apb_pclk"; 2198 2199 out-ports { 2200 port { 2201 funnel1_out: endpoint { 2202 remote-endpoint = <&merge_funnel_in1>; 2203 }; 2204 }; 2205 }; 2206 2207 in-ports { 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 2211 port@4 { 2212 reg = <4>; 2213 funnel1_in4: endpoint { 2214 remote-endpoint = <&apss_merge_funnel_out>; 2215 }; 2216 }; 2217 }; 2218 }; 2219 2220 funnel@6045000 { 2221 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2222 reg = <0 0x06045000 0 0x1000>; 2223 2224 clocks = <&aoss_qmp>; 2225 clock-names = "apb_pclk"; 2226 2227 out-ports { 2228 port { 2229 merge_funnel_out: endpoint { 2230 remote-endpoint = <&swao_funnel_in>; 2231 }; 2232 }; 2233 }; 2234 2235 in-ports { 2236 #address-cells = <1>; 2237 #size-cells = <0>; 2238 2239 port@0 { 2240 reg = <0>; 2241 merge_funnel_in0: endpoint { 2242 remote-endpoint = <&funnel0_out>; 2243 }; 2244 }; 2245 2246 port@1 { 2247 reg = <1>; 2248 merge_funnel_in1: endpoint { 2249 remote-endpoint = <&funnel1_out>; 2250 }; 2251 }; 2252 }; 2253 }; 2254 2255 replicator@6046000 { 2256 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2257 reg = <0 0x06046000 0 0x1000>; 2258 2259 clocks = <&aoss_qmp>; 2260 clock-names = "apb_pclk"; 2261 2262 out-ports { 2263 port { 2264 replicator_out: endpoint { 2265 remote-endpoint = <&etr_in>; 2266 }; 2267 }; 2268 }; 2269 2270 in-ports { 2271 port { 2272 replicator_in: endpoint { 2273 remote-endpoint = <&swao_replicator_out>; 2274 }; 2275 }; 2276 }; 2277 }; 2278 2279 etr@6048000 { 2280 compatible = "arm,coresight-tmc", "arm,primecell"; 2281 reg = <0 0x06048000 0 0x1000>; 2282 iommus = <&apps_smmu 0x04a0 0x20>; 2283 2284 clocks = <&aoss_qmp>; 2285 clock-names = "apb_pclk"; 2286 arm,scatter-gather; 2287 2288 in-ports { 2289 port { 2290 etr_in: endpoint { 2291 remote-endpoint = <&replicator_out>; 2292 }; 2293 }; 2294 }; 2295 }; 2296 2297 funnel@6b04000 { 2298 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2299 reg = <0 0x06b04000 0 0x1000>; 2300 2301 clocks = <&aoss_qmp>; 2302 clock-names = "apb_pclk"; 2303 2304 out-ports { 2305 port { 2306 swao_funnel_out: endpoint { 2307 remote-endpoint = <&etf_in>; 2308 }; 2309 }; 2310 }; 2311 2312 in-ports { 2313 #address-cells = <1>; 2314 #size-cells = <0>; 2315 2316 port@7 { 2317 reg = <7>; 2318 swao_funnel_in: endpoint { 2319 remote-endpoint = <&merge_funnel_out>; 2320 }; 2321 }; 2322 }; 2323 }; 2324 2325 etf@6b05000 { 2326 compatible = "arm,coresight-tmc", "arm,primecell"; 2327 reg = <0 0x06b05000 0 0x1000>; 2328 2329 clocks = <&aoss_qmp>; 2330 clock-names = "apb_pclk"; 2331 2332 out-ports { 2333 port { 2334 etf_out: endpoint { 2335 remote-endpoint = <&swao_replicator_in>; 2336 }; 2337 }; 2338 }; 2339 2340 in-ports { 2341 port { 2342 etf_in: endpoint { 2343 remote-endpoint = <&swao_funnel_out>; 2344 }; 2345 }; 2346 }; 2347 }; 2348 2349 replicator@6b06000 { 2350 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2351 reg = <0 0x06b06000 0 0x1000>; 2352 2353 clocks = <&aoss_qmp>; 2354 clock-names = "apb_pclk"; 2355 qcom,replicator-loses-context; 2356 2357 out-ports { 2358 port { 2359 swao_replicator_out: endpoint { 2360 remote-endpoint = <&replicator_in>; 2361 }; 2362 }; 2363 }; 2364 2365 in-ports { 2366 port { 2367 swao_replicator_in: endpoint { 2368 remote-endpoint = <&etf_out>; 2369 }; 2370 }; 2371 }; 2372 }; 2373 2374 etm@7040000 { 2375 compatible = "arm,coresight-etm4x", "arm,primecell"; 2376 reg = <0 0x07040000 0 0x1000>; 2377 2378 cpu = <&CPU0>; 2379 2380 clocks = <&aoss_qmp>; 2381 clock-names = "apb_pclk"; 2382 arm,coresight-loses-context-with-cpu; 2383 qcom,skip-power-up; 2384 2385 out-ports { 2386 port { 2387 etm0_out: endpoint { 2388 remote-endpoint = <&apss_funnel_in0>; 2389 }; 2390 }; 2391 }; 2392 }; 2393 2394 etm@7140000 { 2395 compatible = "arm,coresight-etm4x", "arm,primecell"; 2396 reg = <0 0x07140000 0 0x1000>; 2397 2398 cpu = <&CPU1>; 2399 2400 clocks = <&aoss_qmp>; 2401 clock-names = "apb_pclk"; 2402 arm,coresight-loses-context-with-cpu; 2403 qcom,skip-power-up; 2404 2405 out-ports { 2406 port { 2407 etm1_out: endpoint { 2408 remote-endpoint = <&apss_funnel_in1>; 2409 }; 2410 }; 2411 }; 2412 }; 2413 2414 etm@7240000 { 2415 compatible = "arm,coresight-etm4x", "arm,primecell"; 2416 reg = <0 0x07240000 0 0x1000>; 2417 2418 cpu = <&CPU2>; 2419 2420 clocks = <&aoss_qmp>; 2421 clock-names = "apb_pclk"; 2422 arm,coresight-loses-context-with-cpu; 2423 qcom,skip-power-up; 2424 2425 out-ports { 2426 port { 2427 etm2_out: endpoint { 2428 remote-endpoint = <&apss_funnel_in2>; 2429 }; 2430 }; 2431 }; 2432 }; 2433 2434 etm@7340000 { 2435 compatible = "arm,coresight-etm4x", "arm,primecell"; 2436 reg = <0 0x07340000 0 0x1000>; 2437 2438 cpu = <&CPU3>; 2439 2440 clocks = <&aoss_qmp>; 2441 clock-names = "apb_pclk"; 2442 arm,coresight-loses-context-with-cpu; 2443 qcom,skip-power-up; 2444 2445 out-ports { 2446 port { 2447 etm3_out: endpoint { 2448 remote-endpoint = <&apss_funnel_in3>; 2449 }; 2450 }; 2451 }; 2452 }; 2453 2454 etm@7440000 { 2455 compatible = "arm,coresight-etm4x", "arm,primecell"; 2456 reg = <0 0x07440000 0 0x1000>; 2457 2458 cpu = <&CPU4>; 2459 2460 clocks = <&aoss_qmp>; 2461 clock-names = "apb_pclk"; 2462 arm,coresight-loses-context-with-cpu; 2463 qcom,skip-power-up; 2464 2465 out-ports { 2466 port { 2467 etm4_out: endpoint { 2468 remote-endpoint = <&apss_funnel_in4>; 2469 }; 2470 }; 2471 }; 2472 }; 2473 2474 etm@7540000 { 2475 compatible = "arm,coresight-etm4x", "arm,primecell"; 2476 reg = <0 0x07540000 0 0x1000>; 2477 2478 cpu = <&CPU5>; 2479 2480 clocks = <&aoss_qmp>; 2481 clock-names = "apb_pclk"; 2482 arm,coresight-loses-context-with-cpu; 2483 qcom,skip-power-up; 2484 2485 out-ports { 2486 port { 2487 etm5_out: endpoint { 2488 remote-endpoint = <&apss_funnel_in5>; 2489 }; 2490 }; 2491 }; 2492 }; 2493 2494 etm@7640000 { 2495 compatible = "arm,coresight-etm4x", "arm,primecell"; 2496 reg = <0 0x07640000 0 0x1000>; 2497 2498 cpu = <&CPU6>; 2499 2500 clocks = <&aoss_qmp>; 2501 clock-names = "apb_pclk"; 2502 arm,coresight-loses-context-with-cpu; 2503 qcom,skip-power-up; 2504 2505 out-ports { 2506 port { 2507 etm6_out: endpoint { 2508 remote-endpoint = <&apss_funnel_in6>; 2509 }; 2510 }; 2511 }; 2512 }; 2513 2514 etm@7740000 { 2515 compatible = "arm,coresight-etm4x", "arm,primecell"; 2516 reg = <0 0x07740000 0 0x1000>; 2517 2518 cpu = <&CPU7>; 2519 2520 clocks = <&aoss_qmp>; 2521 clock-names = "apb_pclk"; 2522 arm,coresight-loses-context-with-cpu; 2523 qcom,skip-power-up; 2524 2525 out-ports { 2526 port { 2527 etm7_out: endpoint { 2528 remote-endpoint = <&apss_funnel_in7>; 2529 }; 2530 }; 2531 }; 2532 }; 2533 2534 funnel@7800000 { /* APSS Funnel */ 2535 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2536 reg = <0 0x07800000 0 0x1000>; 2537 2538 clocks = <&aoss_qmp>; 2539 clock-names = "apb_pclk"; 2540 2541 out-ports { 2542 port { 2543 apss_funnel_out: endpoint { 2544 remote-endpoint = <&apss_merge_funnel_in>; 2545 }; 2546 }; 2547 }; 2548 2549 in-ports { 2550 #address-cells = <1>; 2551 #size-cells = <0>; 2552 2553 port@0 { 2554 reg = <0>; 2555 apss_funnel_in0: endpoint { 2556 remote-endpoint = <&etm0_out>; 2557 }; 2558 }; 2559 2560 port@1 { 2561 reg = <1>; 2562 apss_funnel_in1: endpoint { 2563 remote-endpoint = <&etm1_out>; 2564 }; 2565 }; 2566 2567 port@2 { 2568 reg = <2>; 2569 apss_funnel_in2: endpoint { 2570 remote-endpoint = <&etm2_out>; 2571 }; 2572 }; 2573 2574 port@3 { 2575 reg = <3>; 2576 apss_funnel_in3: endpoint { 2577 remote-endpoint = <&etm3_out>; 2578 }; 2579 }; 2580 2581 port@4 { 2582 reg = <4>; 2583 apss_funnel_in4: endpoint { 2584 remote-endpoint = <&etm4_out>; 2585 }; 2586 }; 2587 2588 port@5 { 2589 reg = <5>; 2590 apss_funnel_in5: endpoint { 2591 remote-endpoint = <&etm5_out>; 2592 }; 2593 }; 2594 2595 port@6 { 2596 reg = <6>; 2597 apss_funnel_in6: endpoint { 2598 remote-endpoint = <&etm6_out>; 2599 }; 2600 }; 2601 2602 port@7 { 2603 reg = <7>; 2604 apss_funnel_in7: endpoint { 2605 remote-endpoint = <&etm7_out>; 2606 }; 2607 }; 2608 }; 2609 }; 2610 2611 funnel@7810000 { 2612 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2613 reg = <0 0x07810000 0 0x1000>; 2614 2615 clocks = <&aoss_qmp>; 2616 clock-names = "apb_pclk"; 2617 2618 out-ports { 2619 port { 2620 apss_merge_funnel_out: endpoint { 2621 remote-endpoint = <&funnel1_in4>; 2622 }; 2623 }; 2624 }; 2625 2626 in-ports { 2627 port { 2628 apss_merge_funnel_in: endpoint { 2629 remote-endpoint = <&apss_funnel_out>; 2630 }; 2631 }; 2632 }; 2633 }; 2634 2635 sdhc_2: mmc@8804000 { 2636 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2637 reg = <0 0x08804000 0 0x1000>; 2638 2639 iommus = <&apps_smmu 0x80 0>; 2640 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2641 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2642 interrupt-names = "hc_irq", "pwr_irq"; 2643 2644 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2645 <&gcc GCC_SDCC2_APPS_CLK>, 2646 <&rpmhcc RPMH_CXO_CLK>; 2647 clock-names = "iface", "core", "xo"; 2648 2649 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2650 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2651 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2652 power-domains = <&rpmhpd SC7180_CX>; 2653 operating-points-v2 = <&sdhc2_opp_table>; 2654 2655 bus-width = <4>; 2656 2657 status = "disabled"; 2658 2659 sdhc2_opp_table: opp-table { 2660 compatible = "operating-points-v2"; 2661 2662 opp-100000000 { 2663 opp-hz = /bits/ 64 <100000000>; 2664 required-opps = <&rpmhpd_opp_low_svs>; 2665 opp-peak-kBps = <1800000 600000>; 2666 opp-avg-kBps = <100000 0>; 2667 }; 2668 2669 opp-202000000 { 2670 opp-hz = /bits/ 64 <202000000>; 2671 required-opps = <&rpmhpd_opp_nom>; 2672 opp-peak-kBps = <5400000 1600000>; 2673 opp-avg-kBps = <200000 0>; 2674 }; 2675 }; 2676 }; 2677 2678 qspi: spi@88dc000 { 2679 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2680 reg = <0 0x088dc000 0 0x600>; 2681 #address-cells = <1>; 2682 #size-cells = <0>; 2683 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2684 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2685 <&gcc GCC_QSPI_CORE_CLK>; 2686 clock-names = "iface", "core"; 2687 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2688 &config_noc SLAVE_QSPI_0 0>; 2689 interconnect-names = "qspi-config"; 2690 power-domains = <&rpmhpd SC7180_CX>; 2691 operating-points-v2 = <&qspi_opp_table>; 2692 status = "disabled"; 2693 }; 2694 2695 usb_1_hsphy: phy@88e3000 { 2696 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2697 reg = <0 0x088e3000 0 0x400>; 2698 status = "disabled"; 2699 #phy-cells = <0>; 2700 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2701 <&rpmhcc RPMH_CXO_CLK>; 2702 clock-names = "cfg_ahb", "ref"; 2703 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2704 2705 nvmem-cells = <&qusb2p_hstx_trim>; 2706 }; 2707 2708 usb_1_qmpphy: phy-wrapper@88e9000 { 2709 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2710 reg = <0 0x088e9000 0 0x18c>, 2711 <0 0x088e8000 0 0x3c>, 2712 <0 0x088ea000 0 0x18c>; 2713 status = "disabled"; 2714 #address-cells = <2>; 2715 #size-cells = <2>; 2716 ranges; 2717 2718 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2719 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2720 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2721 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2722 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2723 2724 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2725 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2726 reset-names = "phy", "common"; 2727 2728 usb_1_ssphy: usb3-phy@88e9200 { 2729 reg = <0 0x088e9200 0 0x128>, 2730 <0 0x088e9400 0 0x200>, 2731 <0 0x088e9c00 0 0x218>, 2732 <0 0x088e9600 0 0x128>, 2733 <0 0x088e9800 0 0x200>, 2734 <0 0x088e9a00 0 0x18>; 2735 #clock-cells = <0>; 2736 #phy-cells = <0>; 2737 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2738 clock-names = "pipe0"; 2739 clock-output-names = "usb3_phy_pipe_clk_src"; 2740 }; 2741 2742 dp_phy: dp-phy@88ea200 { 2743 reg = <0 0x088ea200 0 0x200>, 2744 <0 0x088ea400 0 0x200>, 2745 <0 0x088eaa00 0 0x200>, 2746 <0 0x088ea600 0 0x200>, 2747 <0 0x088ea800 0 0x200>; 2748 #clock-cells = <1>; 2749 #phy-cells = <0>; 2750 }; 2751 }; 2752 2753 dc_noc: interconnect@9160000 { 2754 compatible = "qcom,sc7180-dc-noc"; 2755 reg = <0 0x09160000 0 0x03200>; 2756 #interconnect-cells = <2>; 2757 qcom,bcm-voters = <&apps_bcm_voter>; 2758 }; 2759 2760 system-cache-controller@9200000 { 2761 compatible = "qcom,sc7180-llcc"; 2762 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2763 reg-names = "llcc_base", "llcc_broadcast_base"; 2764 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2765 }; 2766 2767 gem_noc: interconnect@9680000 { 2768 compatible = "qcom,sc7180-gem-noc"; 2769 reg = <0 0x09680000 0 0x3e200>; 2770 #interconnect-cells = <2>; 2771 qcom,bcm-voters = <&apps_bcm_voter>; 2772 }; 2773 2774 npu_noc: interconnect@9990000 { 2775 compatible = "qcom,sc7180-npu-noc"; 2776 reg = <0 0x09990000 0 0x1600>; 2777 #interconnect-cells = <2>; 2778 qcom,bcm-voters = <&apps_bcm_voter>; 2779 }; 2780 2781 usb_1: usb@a6f8800 { 2782 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2783 reg = <0 0x0a6f8800 0 0x400>; 2784 status = "disabled"; 2785 #address-cells = <2>; 2786 #size-cells = <2>; 2787 ranges; 2788 dma-ranges; 2789 2790 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2791 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2792 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2793 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2794 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2795 clock-names = "cfg_noc", 2796 "core", 2797 "iface", 2798 "sleep", 2799 "mock_utmi"; 2800 2801 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2802 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2803 assigned-clock-rates = <19200000>, <150000000>; 2804 2805 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2806 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2807 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, 2808 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; 2809 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2810 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2811 2812 power-domains = <&gcc USB30_PRIM_GDSC>; 2813 required-opps = <&rpmhpd_opp_nom>; 2814 2815 resets = <&gcc GCC_USB30_PRIM_BCR>; 2816 2817 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2818 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2819 interconnect-names = "usb-ddr", "apps-usb"; 2820 2821 wakeup-source; 2822 2823 usb_1_dwc3: usb@a600000 { 2824 compatible = "snps,dwc3"; 2825 reg = <0 0x0a600000 0 0xe000>; 2826 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2827 iommus = <&apps_smmu 0x540 0>; 2828 snps,dis_u2_susphy_quirk; 2829 snps,dis_enblslpm_quirk; 2830 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2831 phy-names = "usb2-phy", "usb3-phy"; 2832 maximum-speed = "super-speed"; 2833 }; 2834 }; 2835 2836 venus: video-codec@aa00000 { 2837 compatible = "qcom,sc7180-venus"; 2838 reg = <0 0x0aa00000 0 0xff000>; 2839 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2840 power-domains = <&videocc VENUS_GDSC>, 2841 <&videocc VCODEC0_GDSC>, 2842 <&rpmhpd SC7180_CX>; 2843 power-domain-names = "venus", "vcodec0", "cx"; 2844 operating-points-v2 = <&venus_opp_table>; 2845 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2846 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2847 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2848 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2849 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2850 clock-names = "core", "iface", "bus", 2851 "vcodec0_core", "vcodec0_bus"; 2852 iommus = <&apps_smmu 0x0c00 0x60>; 2853 memory-region = <&venus_mem>; 2854 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2856 interconnect-names = "video-mem", "cpu-cfg"; 2857 2858 video-decoder { 2859 compatible = "venus-decoder"; 2860 }; 2861 2862 video-encoder { 2863 compatible = "venus-encoder"; 2864 }; 2865 2866 venus_opp_table: opp-table { 2867 compatible = "operating-points-v2"; 2868 2869 opp-150000000 { 2870 opp-hz = /bits/ 64 <150000000>; 2871 required-opps = <&rpmhpd_opp_low_svs>; 2872 }; 2873 2874 opp-270000000 { 2875 opp-hz = /bits/ 64 <270000000>; 2876 required-opps = <&rpmhpd_opp_svs>; 2877 }; 2878 2879 opp-340000000 { 2880 opp-hz = /bits/ 64 <340000000>; 2881 required-opps = <&rpmhpd_opp_svs_l1>; 2882 }; 2883 2884 opp-434000000 { 2885 opp-hz = /bits/ 64 <434000000>; 2886 required-opps = <&rpmhpd_opp_nom>; 2887 }; 2888 2889 opp-500000097 { 2890 opp-hz = /bits/ 64 <500000097>; 2891 required-opps = <&rpmhpd_opp_turbo>; 2892 }; 2893 }; 2894 }; 2895 2896 videocc: clock-controller@ab00000 { 2897 compatible = "qcom,sc7180-videocc"; 2898 reg = <0 0x0ab00000 0 0x10000>; 2899 clocks = <&rpmhcc RPMH_CXO_CLK>; 2900 clock-names = "bi_tcxo"; 2901 #clock-cells = <1>; 2902 #reset-cells = <1>; 2903 #power-domain-cells = <1>; 2904 }; 2905 2906 camnoc_virt: interconnect@ac00000 { 2907 compatible = "qcom,sc7180-camnoc-virt"; 2908 reg = <0 0x0ac00000 0 0x1000>; 2909 #interconnect-cells = <2>; 2910 qcom,bcm-voters = <&apps_bcm_voter>; 2911 }; 2912 2913 camcc: clock-controller@ad00000 { 2914 compatible = "qcom,sc7180-camcc"; 2915 reg = <0 0x0ad00000 0 0x10000>; 2916 clocks = <&rpmhcc RPMH_CXO_CLK>, 2917 <&gcc GCC_CAMERA_AHB_CLK>, 2918 <&gcc GCC_CAMERA_XO_CLK>; 2919 clock-names = "bi_tcxo", "iface", "xo"; 2920 #clock-cells = <1>; 2921 #reset-cells = <1>; 2922 #power-domain-cells = <1>; 2923 }; 2924 2925 mdss: display-subsystem@ae00000 { 2926 compatible = "qcom,sc7180-mdss"; 2927 reg = <0 0x0ae00000 0 0x1000>; 2928 reg-names = "mdss"; 2929 2930 power-domains = <&dispcc MDSS_GDSC>; 2931 2932 clocks = <&gcc GCC_DISP_AHB_CLK>, 2933 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2934 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2935 clock-names = "iface", "ahb", "core"; 2936 2937 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2938 interrupt-controller; 2939 #interrupt-cells = <1>; 2940 2941 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2942 interconnect-names = "mdp0-mem"; 2943 2944 iommus = <&apps_smmu 0x800 0x2>; 2945 2946 #address-cells = <2>; 2947 #size-cells = <2>; 2948 ranges; 2949 2950 status = "disabled"; 2951 2952 mdp: display-controller@ae01000 { 2953 compatible = "qcom,sc7180-dpu"; 2954 reg = <0 0x0ae01000 0 0x8f000>, 2955 <0 0x0aeb0000 0 0x2008>; 2956 reg-names = "mdp", "vbif"; 2957 2958 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2959 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2960 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2961 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2962 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2963 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2964 clock-names = "bus", "iface", "rot", "lut", "core", 2965 "vsync"; 2966 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2967 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2968 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2969 assigned-clock-rates = <19200000>, 2970 <19200000>, 2971 <19200000>; 2972 operating-points-v2 = <&mdp_opp_table>; 2973 power-domains = <&rpmhpd SC7180_CX>; 2974 2975 interrupt-parent = <&mdss>; 2976 interrupts = <0>; 2977 2978 status = "disabled"; 2979 2980 ports { 2981 #address-cells = <1>; 2982 #size-cells = <0>; 2983 2984 port@0 { 2985 reg = <0>; 2986 dpu_intf1_out: endpoint { 2987 remote-endpoint = <&dsi0_in>; 2988 }; 2989 }; 2990 2991 port@2 { 2992 reg = <2>; 2993 dpu_intf0_out: endpoint { 2994 remote-endpoint = <&dp_in>; 2995 }; 2996 }; 2997 }; 2998 2999 mdp_opp_table: opp-table { 3000 compatible = "operating-points-v2"; 3001 3002 opp-200000000 { 3003 opp-hz = /bits/ 64 <200000000>; 3004 required-opps = <&rpmhpd_opp_low_svs>; 3005 }; 3006 3007 opp-300000000 { 3008 opp-hz = /bits/ 64 <300000000>; 3009 required-opps = <&rpmhpd_opp_svs>; 3010 }; 3011 3012 opp-345000000 { 3013 opp-hz = /bits/ 64 <345000000>; 3014 required-opps = <&rpmhpd_opp_svs_l1>; 3015 }; 3016 3017 opp-460000000 { 3018 opp-hz = /bits/ 64 <460000000>; 3019 required-opps = <&rpmhpd_opp_nom>; 3020 }; 3021 }; 3022 3023 }; 3024 3025 dsi0: dsi@ae94000 { 3026 compatible = "qcom,sc7180-dsi-ctrl", 3027 "qcom,mdss-dsi-ctrl"; 3028 reg = <0 0x0ae94000 0 0x400>; 3029 reg-names = "dsi_ctrl"; 3030 3031 interrupt-parent = <&mdss>; 3032 interrupts = <4>; 3033 3034 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3035 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3036 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3037 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3038 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3039 <&gcc GCC_DISP_HF_AXI_CLK>; 3040 clock-names = "byte", 3041 "byte_intf", 3042 "pixel", 3043 "core", 3044 "iface", 3045 "bus"; 3046 3047 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3048 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 3049 3050 operating-points-v2 = <&dsi_opp_table>; 3051 power-domains = <&rpmhpd SC7180_CX>; 3052 3053 phys = <&dsi_phy>; 3054 3055 #address-cells = <1>; 3056 #size-cells = <0>; 3057 3058 status = "disabled"; 3059 3060 ports { 3061 #address-cells = <1>; 3062 #size-cells = <0>; 3063 3064 port@0 { 3065 reg = <0>; 3066 dsi0_in: endpoint { 3067 remote-endpoint = <&dpu_intf1_out>; 3068 }; 3069 }; 3070 3071 port@1 { 3072 reg = <1>; 3073 dsi0_out: endpoint { 3074 }; 3075 }; 3076 }; 3077 3078 dsi_opp_table: opp-table { 3079 compatible = "operating-points-v2"; 3080 3081 opp-187500000 { 3082 opp-hz = /bits/ 64 <187500000>; 3083 required-opps = <&rpmhpd_opp_low_svs>; 3084 }; 3085 3086 opp-300000000 { 3087 opp-hz = /bits/ 64 <300000000>; 3088 required-opps = <&rpmhpd_opp_svs>; 3089 }; 3090 3091 opp-358000000 { 3092 opp-hz = /bits/ 64 <358000000>; 3093 required-opps = <&rpmhpd_opp_svs_l1>; 3094 }; 3095 }; 3096 }; 3097 3098 dsi_phy: phy@ae94400 { 3099 compatible = "qcom,dsi-phy-10nm"; 3100 reg = <0 0x0ae94400 0 0x200>, 3101 <0 0x0ae94600 0 0x280>, 3102 <0 0x0ae94a00 0 0x1e0>; 3103 reg-names = "dsi_phy", 3104 "dsi_phy_lane", 3105 "dsi_pll"; 3106 3107 #clock-cells = <1>; 3108 #phy-cells = <0>; 3109 3110 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3111 <&rpmhcc RPMH_CXO_CLK>; 3112 clock-names = "iface", "ref"; 3113 3114 status = "disabled"; 3115 }; 3116 3117 mdss_dp: displayport-controller@ae90000 { 3118 compatible = "qcom,sc7180-dp"; 3119 status = "disabled"; 3120 3121 reg = <0 0x0ae90000 0 0x200>, 3122 <0 0x0ae90200 0 0x200>, 3123 <0 0x0ae90400 0 0xc00>, 3124 <0 0x0ae91000 0 0x400>, 3125 <0 0x0ae91400 0 0x400>; 3126 3127 interrupt-parent = <&mdss>; 3128 interrupts = <12>; 3129 3130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3131 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3132 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3133 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3134 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3135 clock-names = "core_iface", "core_aux", "ctrl_link", 3136 "ctrl_link_iface", "stream_pixel"; 3137 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3138 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3139 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3140 phys = <&dp_phy>; 3141 phy-names = "dp"; 3142 3143 operating-points-v2 = <&dp_opp_table>; 3144 power-domains = <&rpmhpd SC7180_CX>; 3145 3146 #sound-dai-cells = <0>; 3147 3148 ports { 3149 #address-cells = <1>; 3150 #size-cells = <0>; 3151 port@0 { 3152 reg = <0>; 3153 dp_in: endpoint { 3154 remote-endpoint = <&dpu_intf0_out>; 3155 }; 3156 }; 3157 3158 port@1 { 3159 reg = <1>; 3160 mdss_dp_out: endpoint { }; 3161 }; 3162 }; 3163 3164 dp_opp_table: opp-table { 3165 compatible = "operating-points-v2"; 3166 3167 opp-160000000 { 3168 opp-hz = /bits/ 64 <160000000>; 3169 required-opps = <&rpmhpd_opp_low_svs>; 3170 }; 3171 3172 opp-270000000 { 3173 opp-hz = /bits/ 64 <270000000>; 3174 required-opps = <&rpmhpd_opp_svs>; 3175 }; 3176 3177 opp-540000000 { 3178 opp-hz = /bits/ 64 <540000000>; 3179 required-opps = <&rpmhpd_opp_svs_l1>; 3180 }; 3181 3182 opp-810000000 { 3183 opp-hz = /bits/ 64 <810000000>; 3184 required-opps = <&rpmhpd_opp_nom>; 3185 }; 3186 }; 3187 }; 3188 }; 3189 3190 dispcc: clock-controller@af00000 { 3191 compatible = "qcom,sc7180-dispcc"; 3192 reg = <0 0x0af00000 0 0x200000>; 3193 clocks = <&rpmhcc RPMH_CXO_CLK>, 3194 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3195 <&dsi_phy 0>, 3196 <&dsi_phy 1>, 3197 <&dp_phy 0>, 3198 <&dp_phy 1>; 3199 clock-names = "bi_tcxo", 3200 "gcc_disp_gpll0_clk_src", 3201 "dsi0_phy_pll_out_byteclk", 3202 "dsi0_phy_pll_out_dsiclk", 3203 "dp_phy_pll_link_clk", 3204 "dp_phy_pll_vco_div_clk"; 3205 #clock-cells = <1>; 3206 #reset-cells = <1>; 3207 #power-domain-cells = <1>; 3208 }; 3209 3210 pdc: interrupt-controller@b220000 { 3211 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3212 reg = <0 0x0b220000 0 0x30000>; 3213 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3214 #interrupt-cells = <2>; 3215 interrupt-parent = <&intc>; 3216 interrupt-controller; 3217 }; 3218 3219 pdc_reset: reset-controller@b2e0000 { 3220 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3221 reg = <0 0x0b2e0000 0 0x20000>; 3222 #reset-cells = <1>; 3223 }; 3224 3225 tsens0: thermal-sensor@c263000 { 3226 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3227 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3228 <0 0x0c222000 0 0x1ff>; /* SROT */ 3229 #qcom,sensors = <15>; 3230 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3232 interrupt-names = "uplow","critical"; 3233 #thermal-sensor-cells = <1>; 3234 }; 3235 3236 tsens1: thermal-sensor@c265000 { 3237 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3238 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3239 <0 0x0c223000 0 0x1ff>; /* SROT */ 3240 #qcom,sensors = <10>; 3241 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3243 interrupt-names = "uplow","critical"; 3244 #thermal-sensor-cells = <1>; 3245 }; 3246 3247 aoss_reset: reset-controller@c2a0000 { 3248 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3249 reg = <0 0x0c2a0000 0 0x31000>; 3250 #reset-cells = <1>; 3251 }; 3252 3253 aoss_qmp: power-management@c300000 { 3254 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3255 reg = <0 0x0c300000 0 0x400>; 3256 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3257 mboxes = <&apss_shared 0>; 3258 3259 #clock-cells = <0>; 3260 }; 3261 3262 sram@c3f0000 { 3263 compatible = "qcom,rpmh-stats"; 3264 reg = <0 0x0c3f0000 0 0x400>; 3265 }; 3266 3267 spmi_bus: spmi@c440000 { 3268 compatible = "qcom,spmi-pmic-arb"; 3269 reg = <0 0x0c440000 0 0x1100>, 3270 <0 0x0c600000 0 0x2000000>, 3271 <0 0x0e600000 0 0x100000>, 3272 <0 0x0e700000 0 0xa0000>, 3273 <0 0x0c40a000 0 0x26000>; 3274 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3275 interrupt-names = "periph_irq"; 3276 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3277 qcom,ee = <0>; 3278 qcom,channel = <0>; 3279 #address-cells = <2>; 3280 #size-cells = <0>; 3281 interrupt-controller; 3282 #interrupt-cells = <4>; 3283 cell-index = <0>; 3284 }; 3285 3286 sram@146aa000 { 3287 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3288 reg = <0 0x146aa000 0 0x2000>; 3289 3290 #address-cells = <1>; 3291 #size-cells = <1>; 3292 3293 ranges = <0 0 0x146aa000 0x2000>; 3294 3295 pil-reloc@94c { 3296 compatible = "qcom,pil-reloc-info"; 3297 reg = <0x94c 0xc8>; 3298 }; 3299 }; 3300 3301 apps_smmu: iommu@15000000 { 3302 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3303 reg = <0 0x15000000 0 0x100000>; 3304 #iommu-cells = <2>; 3305 #global-interrupts = <1>; 3306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3387 }; 3388 3389 intc: interrupt-controller@17a00000 { 3390 compatible = "arm,gic-v3"; 3391 #address-cells = <2>; 3392 #size-cells = <2>; 3393 ranges; 3394 #interrupt-cells = <3>; 3395 interrupt-controller; 3396 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3397 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3398 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3399 3400 msi-controller@17a40000 { 3401 compatible = "arm,gic-v3-its"; 3402 msi-controller; 3403 #msi-cells = <1>; 3404 reg = <0 0x17a40000 0 0x20000>; 3405 status = "disabled"; 3406 }; 3407 }; 3408 3409 apss_shared: mailbox@17c00000 { 3410 compatible = "qcom,sc7180-apss-shared"; 3411 reg = <0 0x17c00000 0 0x10000>; 3412 #mbox-cells = <1>; 3413 }; 3414 3415 watchdog@17c10000 { 3416 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3417 reg = <0 0x17c10000 0 0x1000>; 3418 clocks = <&sleep_clk>; 3419 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3420 }; 3421 3422 timer@17c20000 { 3423 #address-cells = <1>; 3424 #size-cells = <1>; 3425 ranges = <0 0 0 0x20000000>; 3426 compatible = "arm,armv7-timer-mem"; 3427 reg = <0 0x17c20000 0 0x1000>; 3428 3429 frame@17c21000 { 3430 frame-number = <0>; 3431 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3433 reg = <0x17c21000 0x1000>, 3434 <0x17c22000 0x1000>; 3435 }; 3436 3437 frame@17c23000 { 3438 frame-number = <1>; 3439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3440 reg = <0x17c23000 0x1000>; 3441 status = "disabled"; 3442 }; 3443 3444 frame@17c25000 { 3445 frame-number = <2>; 3446 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3447 reg = <0x17c25000 0x1000>; 3448 status = "disabled"; 3449 }; 3450 3451 frame@17c27000 { 3452 frame-number = <3>; 3453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3454 reg = <0x17c27000 0x1000>; 3455 status = "disabled"; 3456 }; 3457 3458 frame@17c29000 { 3459 frame-number = <4>; 3460 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3461 reg = <0x17c29000 0x1000>; 3462 status = "disabled"; 3463 }; 3464 3465 frame@17c2b000 { 3466 frame-number = <5>; 3467 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3468 reg = <0x17c2b000 0x1000>; 3469 status = "disabled"; 3470 }; 3471 3472 frame@17c2d000 { 3473 frame-number = <6>; 3474 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3475 reg = <0x17c2d000 0x1000>; 3476 status = "disabled"; 3477 }; 3478 }; 3479 3480 apps_rsc: rsc@18200000 { 3481 compatible = "qcom,rpmh-rsc"; 3482 reg = <0 0x18200000 0 0x10000>, 3483 <0 0x18210000 0 0x10000>, 3484 <0 0x18220000 0 0x10000>; 3485 reg-names = "drv-0", "drv-1", "drv-2"; 3486 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3489 qcom,tcs-offset = <0xd00>; 3490 qcom,drv-id = <2>; 3491 qcom,tcs-config = <ACTIVE_TCS 2>, 3492 <SLEEP_TCS 3>, 3493 <WAKE_TCS 3>, 3494 <CONTROL_TCS 1>; 3495 3496 rpmhcc: clock-controller { 3497 compatible = "qcom,sc7180-rpmh-clk"; 3498 clocks = <&xo_board>; 3499 clock-names = "xo"; 3500 #clock-cells = <1>; 3501 }; 3502 3503 rpmhpd: power-controller { 3504 compatible = "qcom,sc7180-rpmhpd"; 3505 #power-domain-cells = <1>; 3506 operating-points-v2 = <&rpmhpd_opp_table>; 3507 3508 rpmhpd_opp_table: opp-table { 3509 compatible = "operating-points-v2"; 3510 3511 rpmhpd_opp_ret: opp1 { 3512 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3513 }; 3514 3515 rpmhpd_opp_min_svs: opp2 { 3516 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3517 }; 3518 3519 rpmhpd_opp_low_svs: opp3 { 3520 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3521 }; 3522 3523 rpmhpd_opp_svs: opp4 { 3524 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3525 }; 3526 3527 rpmhpd_opp_svs_l1: opp5 { 3528 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3529 }; 3530 3531 rpmhpd_opp_svs_l2: opp6 { 3532 opp-level = <224>; 3533 }; 3534 3535 rpmhpd_opp_nom: opp7 { 3536 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3537 }; 3538 3539 rpmhpd_opp_nom_l1: opp8 { 3540 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3541 }; 3542 3543 rpmhpd_opp_nom_l2: opp9 { 3544 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3545 }; 3546 3547 rpmhpd_opp_turbo: opp10 { 3548 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3549 }; 3550 3551 rpmhpd_opp_turbo_l1: opp11 { 3552 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3553 }; 3554 }; 3555 }; 3556 3557 apps_bcm_voter: bcm-voter { 3558 compatible = "qcom,bcm-voter"; 3559 }; 3560 }; 3561 3562 osm_l3: interconnect@18321000 { 3563 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3564 reg = <0 0x18321000 0 0x1400>; 3565 3566 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3567 clock-names = "xo", "alternate"; 3568 3569 #interconnect-cells = <1>; 3570 }; 3571 3572 cpufreq_hw: cpufreq@18323000 { 3573 compatible = "qcom,cpufreq-hw"; 3574 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3575 reg-names = "freq-domain0", "freq-domain1"; 3576 3577 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3578 clock-names = "xo", "alternate"; 3579 3580 #freq-domain-cells = <1>; 3581 }; 3582 3583 wifi: wifi@18800000 { 3584 compatible = "qcom,wcn3990-wifi"; 3585 reg = <0 0x18800000 0 0x800000>; 3586 reg-names = "membase"; 3587 iommus = <&apps_smmu 0xc0 0x1>; 3588 interrupts = 3589 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3590 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3591 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3592 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3593 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3594 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3595 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3596 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3597 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3598 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3599 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3600 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3601 memory-region = <&wlan_mem>; 3602 qcom,msa-fixed-perm; 3603 status = "disabled"; 3604 }; 3605 3606 lpasscc: clock-controller@62d00000 { 3607 compatible = "qcom,sc7180-lpasscorecc"; 3608 reg = <0 0x62d00000 0 0x50000>, 3609 <0 0x62780000 0 0x30000>; 3610 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3611 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3612 <&rpmhcc RPMH_CXO_CLK>; 3613 clock-names = "iface", "bi_tcxo"; 3614 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3615 #clock-cells = <1>; 3616 #power-domain-cells = <1>; 3617 }; 3618 3619 lpass_cpu: lpass@62d87000 { 3620 compatible = "qcom,sc7180-lpass-cpu"; 3621 3622 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3623 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3624 3625 iommus = <&apps_smmu 0x1020 0>, 3626 <&apps_smmu 0x1021 0>, 3627 <&apps_smmu 0x1032 0>; 3628 3629 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3630 required-opps = <&rpmhpd_opp_nom>; 3631 3632 status = "disabled"; 3633 3634 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3635 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3636 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3637 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3638 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3639 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3640 3641 clock-names = "pcnoc-sway-clk", "audio-core", 3642 "mclk0", "pcnoc-mport-clk", 3643 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3644 3645 3646 #sound-dai-cells = <1>; 3647 #address-cells = <1>; 3648 #size-cells = <0>; 3649 3650 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3652 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3653 }; 3654 3655 lpass_hm: clock-controller@63000000 { 3656 compatible = "qcom,sc7180-lpasshm"; 3657 reg = <0 0x63000000 0 0x28>; 3658 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3659 <&rpmhcc RPMH_CXO_CLK>; 3660 clock-names = "iface", "bi_tcxo"; 3661 power-domains = <&rpmhpd SC7180_CX>; 3662 3663 #clock-cells = <1>; 3664 #power-domain-cells = <1>; 3665 }; 3666 }; 3667 3668 thermal-zones { 3669 cpu0_thermal: cpu0-thermal { 3670 polling-delay-passive = <250>; 3671 polling-delay = <0>; 3672 3673 thermal-sensors = <&tsens0 1>; 3674 sustainable-power = <1052>; 3675 3676 trips { 3677 cpu0_alert0: trip-point0 { 3678 temperature = <90000>; 3679 hysteresis = <2000>; 3680 type = "passive"; 3681 }; 3682 3683 cpu0_alert1: trip-point1 { 3684 temperature = <95000>; 3685 hysteresis = <2000>; 3686 type = "passive"; 3687 }; 3688 3689 cpu0_crit: cpu-crit { 3690 temperature = <110000>; 3691 hysteresis = <1000>; 3692 type = "critical"; 3693 }; 3694 }; 3695 3696 cooling-maps { 3697 map0 { 3698 trip = <&cpu0_alert0>; 3699 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3700 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3701 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3702 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3703 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3704 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3705 }; 3706 map1 { 3707 trip = <&cpu0_alert1>; 3708 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3709 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3710 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3711 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3712 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3713 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3714 }; 3715 }; 3716 }; 3717 3718 cpu1_thermal: cpu1-thermal { 3719 polling-delay-passive = <250>; 3720 polling-delay = <0>; 3721 3722 thermal-sensors = <&tsens0 2>; 3723 sustainable-power = <1052>; 3724 3725 trips { 3726 cpu1_alert0: trip-point0 { 3727 temperature = <90000>; 3728 hysteresis = <2000>; 3729 type = "passive"; 3730 }; 3731 3732 cpu1_alert1: trip-point1 { 3733 temperature = <95000>; 3734 hysteresis = <2000>; 3735 type = "passive"; 3736 }; 3737 3738 cpu1_crit: cpu-crit { 3739 temperature = <110000>; 3740 hysteresis = <1000>; 3741 type = "critical"; 3742 }; 3743 }; 3744 3745 cooling-maps { 3746 map0 { 3747 trip = <&cpu1_alert0>; 3748 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3749 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3750 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3751 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3752 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3753 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3754 }; 3755 map1 { 3756 trip = <&cpu1_alert1>; 3757 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3758 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3759 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3760 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3761 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3762 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3763 }; 3764 }; 3765 }; 3766 3767 cpu2_thermal: cpu2-thermal { 3768 polling-delay-passive = <250>; 3769 polling-delay = <0>; 3770 3771 thermal-sensors = <&tsens0 3>; 3772 sustainable-power = <1052>; 3773 3774 trips { 3775 cpu2_alert0: trip-point0 { 3776 temperature = <90000>; 3777 hysteresis = <2000>; 3778 type = "passive"; 3779 }; 3780 3781 cpu2_alert1: trip-point1 { 3782 temperature = <95000>; 3783 hysteresis = <2000>; 3784 type = "passive"; 3785 }; 3786 3787 cpu2_crit: cpu-crit { 3788 temperature = <110000>; 3789 hysteresis = <1000>; 3790 type = "critical"; 3791 }; 3792 }; 3793 3794 cooling-maps { 3795 map0 { 3796 trip = <&cpu2_alert0>; 3797 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3798 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3799 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3800 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3801 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3802 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3803 }; 3804 map1 { 3805 trip = <&cpu2_alert1>; 3806 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3808 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3809 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3810 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3812 }; 3813 }; 3814 }; 3815 3816 cpu3_thermal: cpu3-thermal { 3817 polling-delay-passive = <250>; 3818 polling-delay = <0>; 3819 3820 thermal-sensors = <&tsens0 4>; 3821 sustainable-power = <1052>; 3822 3823 trips { 3824 cpu3_alert0: trip-point0 { 3825 temperature = <90000>; 3826 hysteresis = <2000>; 3827 type = "passive"; 3828 }; 3829 3830 cpu3_alert1: trip-point1 { 3831 temperature = <95000>; 3832 hysteresis = <2000>; 3833 type = "passive"; 3834 }; 3835 3836 cpu3_crit: cpu-crit { 3837 temperature = <110000>; 3838 hysteresis = <1000>; 3839 type = "critical"; 3840 }; 3841 }; 3842 3843 cooling-maps { 3844 map0 { 3845 trip = <&cpu3_alert0>; 3846 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3847 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3848 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3849 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3852 }; 3853 map1 { 3854 trip = <&cpu3_alert1>; 3855 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3860 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3861 }; 3862 }; 3863 }; 3864 3865 cpu4_thermal: cpu4-thermal { 3866 polling-delay-passive = <250>; 3867 polling-delay = <0>; 3868 3869 thermal-sensors = <&tsens0 5>; 3870 sustainable-power = <1052>; 3871 3872 trips { 3873 cpu4_alert0: trip-point0 { 3874 temperature = <90000>; 3875 hysteresis = <2000>; 3876 type = "passive"; 3877 }; 3878 3879 cpu4_alert1: trip-point1 { 3880 temperature = <95000>; 3881 hysteresis = <2000>; 3882 type = "passive"; 3883 }; 3884 3885 cpu4_crit: cpu-crit { 3886 temperature = <110000>; 3887 hysteresis = <1000>; 3888 type = "critical"; 3889 }; 3890 }; 3891 3892 cooling-maps { 3893 map0 { 3894 trip = <&cpu4_alert0>; 3895 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3896 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3897 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3898 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3899 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3901 }; 3902 map1 { 3903 trip = <&cpu4_alert1>; 3904 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3905 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3906 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3907 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3908 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3909 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3910 }; 3911 }; 3912 }; 3913 3914 cpu5_thermal: cpu5-thermal { 3915 polling-delay-passive = <250>; 3916 polling-delay = <0>; 3917 3918 thermal-sensors = <&tsens0 6>; 3919 sustainable-power = <1052>; 3920 3921 trips { 3922 cpu5_alert0: trip-point0 { 3923 temperature = <90000>; 3924 hysteresis = <2000>; 3925 type = "passive"; 3926 }; 3927 3928 cpu5_alert1: trip-point1 { 3929 temperature = <95000>; 3930 hysteresis = <2000>; 3931 type = "passive"; 3932 }; 3933 3934 cpu5_crit: cpu-crit { 3935 temperature = <110000>; 3936 hysteresis = <1000>; 3937 type = "critical"; 3938 }; 3939 }; 3940 3941 cooling-maps { 3942 map0 { 3943 trip = <&cpu5_alert0>; 3944 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3948 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3949 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3950 }; 3951 map1 { 3952 trip = <&cpu5_alert1>; 3953 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3954 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3955 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3956 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3957 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3958 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3959 }; 3960 }; 3961 }; 3962 3963 cpu6_thermal: cpu6-thermal { 3964 polling-delay-passive = <250>; 3965 polling-delay = <0>; 3966 3967 thermal-sensors = <&tsens0 9>; 3968 sustainable-power = <1425>; 3969 3970 trips { 3971 cpu6_alert0: trip-point0 { 3972 temperature = <90000>; 3973 hysteresis = <2000>; 3974 type = "passive"; 3975 }; 3976 3977 cpu6_alert1: trip-point1 { 3978 temperature = <95000>; 3979 hysteresis = <2000>; 3980 type = "passive"; 3981 }; 3982 3983 cpu6_crit: cpu-crit { 3984 temperature = <110000>; 3985 hysteresis = <1000>; 3986 type = "critical"; 3987 }; 3988 }; 3989 3990 cooling-maps { 3991 map0 { 3992 trip = <&cpu6_alert0>; 3993 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3994 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3995 }; 3996 map1 { 3997 trip = <&cpu6_alert1>; 3998 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4000 }; 4001 }; 4002 }; 4003 4004 cpu7_thermal: cpu7-thermal { 4005 polling-delay-passive = <250>; 4006 polling-delay = <0>; 4007 4008 thermal-sensors = <&tsens0 10>; 4009 sustainable-power = <1425>; 4010 4011 trips { 4012 cpu7_alert0: trip-point0 { 4013 temperature = <90000>; 4014 hysteresis = <2000>; 4015 type = "passive"; 4016 }; 4017 4018 cpu7_alert1: trip-point1 { 4019 temperature = <95000>; 4020 hysteresis = <2000>; 4021 type = "passive"; 4022 }; 4023 4024 cpu7_crit: cpu-crit { 4025 temperature = <110000>; 4026 hysteresis = <1000>; 4027 type = "critical"; 4028 }; 4029 }; 4030 4031 cooling-maps { 4032 map0 { 4033 trip = <&cpu7_alert0>; 4034 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4036 }; 4037 map1 { 4038 trip = <&cpu7_alert1>; 4039 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4041 }; 4042 }; 4043 }; 4044 4045 cpu8_thermal: cpu8-thermal { 4046 polling-delay-passive = <250>; 4047 polling-delay = <0>; 4048 4049 thermal-sensors = <&tsens0 11>; 4050 sustainable-power = <1425>; 4051 4052 trips { 4053 cpu8_alert0: trip-point0 { 4054 temperature = <90000>; 4055 hysteresis = <2000>; 4056 type = "passive"; 4057 }; 4058 4059 cpu8_alert1: trip-point1 { 4060 temperature = <95000>; 4061 hysteresis = <2000>; 4062 type = "passive"; 4063 }; 4064 4065 cpu8_crit: cpu-crit { 4066 temperature = <110000>; 4067 hysteresis = <1000>; 4068 type = "critical"; 4069 }; 4070 }; 4071 4072 cooling-maps { 4073 map0 { 4074 trip = <&cpu8_alert0>; 4075 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4077 }; 4078 map1 { 4079 trip = <&cpu8_alert1>; 4080 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4082 }; 4083 }; 4084 }; 4085 4086 cpu9_thermal: cpu9-thermal { 4087 polling-delay-passive = <250>; 4088 polling-delay = <0>; 4089 4090 thermal-sensors = <&tsens0 12>; 4091 sustainable-power = <1425>; 4092 4093 trips { 4094 cpu9_alert0: trip-point0 { 4095 temperature = <90000>; 4096 hysteresis = <2000>; 4097 type = "passive"; 4098 }; 4099 4100 cpu9_alert1: trip-point1 { 4101 temperature = <95000>; 4102 hysteresis = <2000>; 4103 type = "passive"; 4104 }; 4105 4106 cpu9_crit: cpu-crit { 4107 temperature = <110000>; 4108 hysteresis = <1000>; 4109 type = "critical"; 4110 }; 4111 }; 4112 4113 cooling-maps { 4114 map0 { 4115 trip = <&cpu9_alert0>; 4116 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4118 }; 4119 map1 { 4120 trip = <&cpu9_alert1>; 4121 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4123 }; 4124 }; 4125 }; 4126 4127 aoss0-thermal { 4128 polling-delay-passive = <250>; 4129 polling-delay = <0>; 4130 4131 thermal-sensors = <&tsens0 0>; 4132 4133 trips { 4134 aoss0_alert0: trip-point0 { 4135 temperature = <90000>; 4136 hysteresis = <2000>; 4137 type = "hot"; 4138 }; 4139 4140 aoss0_crit: aoss0-crit { 4141 temperature = <110000>; 4142 hysteresis = <2000>; 4143 type = "critical"; 4144 }; 4145 }; 4146 }; 4147 4148 cpuss0-thermal { 4149 polling-delay-passive = <250>; 4150 polling-delay = <0>; 4151 4152 thermal-sensors = <&tsens0 7>; 4153 4154 trips { 4155 cpuss0_alert0: trip-point0 { 4156 temperature = <90000>; 4157 hysteresis = <2000>; 4158 type = "hot"; 4159 }; 4160 cpuss0_crit: cluster0-crit { 4161 temperature = <110000>; 4162 hysteresis = <2000>; 4163 type = "critical"; 4164 }; 4165 }; 4166 }; 4167 4168 cpuss1-thermal { 4169 polling-delay-passive = <250>; 4170 polling-delay = <0>; 4171 4172 thermal-sensors = <&tsens0 8>; 4173 4174 trips { 4175 cpuss1_alert0: trip-point0 { 4176 temperature = <90000>; 4177 hysteresis = <2000>; 4178 type = "hot"; 4179 }; 4180 cpuss1_crit: cluster0-crit { 4181 temperature = <110000>; 4182 hysteresis = <2000>; 4183 type = "critical"; 4184 }; 4185 }; 4186 }; 4187 4188 gpuss0-thermal { 4189 polling-delay-passive = <250>; 4190 polling-delay = <0>; 4191 4192 thermal-sensors = <&tsens0 13>; 4193 4194 trips { 4195 gpuss0_alert0: trip-point0 { 4196 temperature = <95000>; 4197 hysteresis = <2000>; 4198 type = "passive"; 4199 }; 4200 4201 gpuss0_crit: gpuss0-crit { 4202 temperature = <110000>; 4203 hysteresis = <2000>; 4204 type = "critical"; 4205 }; 4206 }; 4207 4208 cooling-maps { 4209 map0 { 4210 trip = <&gpuss0_alert0>; 4211 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4212 }; 4213 }; 4214 }; 4215 4216 gpuss1-thermal { 4217 polling-delay-passive = <250>; 4218 polling-delay = <0>; 4219 4220 thermal-sensors = <&tsens0 14>; 4221 4222 trips { 4223 gpuss1_alert0: trip-point0 { 4224 temperature = <95000>; 4225 hysteresis = <2000>; 4226 type = "passive"; 4227 }; 4228 4229 gpuss1_crit: gpuss1-crit { 4230 temperature = <110000>; 4231 hysteresis = <2000>; 4232 type = "critical"; 4233 }; 4234 }; 4235 4236 cooling-maps { 4237 map0 { 4238 trip = <&gpuss1_alert0>; 4239 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4240 }; 4241 }; 4242 }; 4243 4244 aoss1-thermal { 4245 polling-delay-passive = <250>; 4246 polling-delay = <0>; 4247 4248 thermal-sensors = <&tsens1 0>; 4249 4250 trips { 4251 aoss1_alert0: trip-point0 { 4252 temperature = <90000>; 4253 hysteresis = <2000>; 4254 type = "hot"; 4255 }; 4256 4257 aoss1_crit: aoss1-crit { 4258 temperature = <110000>; 4259 hysteresis = <2000>; 4260 type = "critical"; 4261 }; 4262 }; 4263 }; 4264 4265 cwlan-thermal { 4266 polling-delay-passive = <250>; 4267 polling-delay = <0>; 4268 4269 thermal-sensors = <&tsens1 1>; 4270 4271 trips { 4272 cwlan_alert0: trip-point0 { 4273 temperature = <90000>; 4274 hysteresis = <2000>; 4275 type = "hot"; 4276 }; 4277 4278 cwlan_crit: cwlan-crit { 4279 temperature = <110000>; 4280 hysteresis = <2000>; 4281 type = "critical"; 4282 }; 4283 }; 4284 }; 4285 4286 audio-thermal { 4287 polling-delay-passive = <250>; 4288 polling-delay = <0>; 4289 4290 thermal-sensors = <&tsens1 2>; 4291 4292 trips { 4293 audio_alert0: trip-point0 { 4294 temperature = <90000>; 4295 hysteresis = <2000>; 4296 type = "hot"; 4297 }; 4298 4299 audio_crit: audio-crit { 4300 temperature = <110000>; 4301 hysteresis = <2000>; 4302 type = "critical"; 4303 }; 4304 }; 4305 }; 4306 4307 ddr-thermal { 4308 polling-delay-passive = <250>; 4309 polling-delay = <0>; 4310 4311 thermal-sensors = <&tsens1 3>; 4312 4313 trips { 4314 ddr_alert0: trip-point0 { 4315 temperature = <90000>; 4316 hysteresis = <2000>; 4317 type = "hot"; 4318 }; 4319 4320 ddr_crit: ddr-crit { 4321 temperature = <110000>; 4322 hysteresis = <2000>; 4323 type = "critical"; 4324 }; 4325 }; 4326 }; 4327 4328 q6-hvx-thermal { 4329 polling-delay-passive = <250>; 4330 polling-delay = <0>; 4331 4332 thermal-sensors = <&tsens1 4>; 4333 4334 trips { 4335 q6_hvx_alert0: trip-point0 { 4336 temperature = <90000>; 4337 hysteresis = <2000>; 4338 type = "hot"; 4339 }; 4340 4341 q6_hvx_crit: q6-hvx-crit { 4342 temperature = <110000>; 4343 hysteresis = <2000>; 4344 type = "critical"; 4345 }; 4346 }; 4347 }; 4348 4349 camera-thermal { 4350 polling-delay-passive = <250>; 4351 polling-delay = <0>; 4352 4353 thermal-sensors = <&tsens1 5>; 4354 4355 trips { 4356 camera_alert0: trip-point0 { 4357 temperature = <90000>; 4358 hysteresis = <2000>; 4359 type = "hot"; 4360 }; 4361 4362 camera_crit: camera-crit { 4363 temperature = <110000>; 4364 hysteresis = <2000>; 4365 type = "critical"; 4366 }; 4367 }; 4368 }; 4369 4370 mdm-core-thermal { 4371 polling-delay-passive = <250>; 4372 polling-delay = <0>; 4373 4374 thermal-sensors = <&tsens1 6>; 4375 4376 trips { 4377 mdm_alert0: trip-point0 { 4378 temperature = <90000>; 4379 hysteresis = <2000>; 4380 type = "hot"; 4381 }; 4382 4383 mdm_crit: mdm-crit { 4384 temperature = <110000>; 4385 hysteresis = <2000>; 4386 type = "critical"; 4387 }; 4388 }; 4389 }; 4390 4391 mdm-dsp-thermal { 4392 polling-delay-passive = <250>; 4393 polling-delay = <0>; 4394 4395 thermal-sensors = <&tsens1 7>; 4396 4397 trips { 4398 mdm_dsp_alert0: trip-point0 { 4399 temperature = <90000>; 4400 hysteresis = <2000>; 4401 type = "hot"; 4402 }; 4403 4404 mdm_dsp_crit: mdm-dsp-crit { 4405 temperature = <110000>; 4406 hysteresis = <2000>; 4407 type = "critical"; 4408 }; 4409 }; 4410 }; 4411 4412 npu-thermal { 4413 polling-delay-passive = <250>; 4414 polling-delay = <0>; 4415 4416 thermal-sensors = <&tsens1 8>; 4417 4418 trips { 4419 npu_alert0: trip-point0 { 4420 temperature = <90000>; 4421 hysteresis = <2000>; 4422 type = "hot"; 4423 }; 4424 4425 npu_crit: npu-crit { 4426 temperature = <110000>; 4427 hysteresis = <2000>; 4428 type = "critical"; 4429 }; 4430 }; 4431 }; 4432 4433 video-thermal { 4434 polling-delay-passive = <250>; 4435 polling-delay = <0>; 4436 4437 thermal-sensors = <&tsens1 9>; 4438 4439 trips { 4440 video_alert0: trip-point0 { 4441 temperature = <90000>; 4442 hysteresis = <2000>; 4443 type = "hot"; 4444 }; 4445 4446 video_crit: video-crit { 4447 temperature = <110000>; 4448 hysteresis = <2000>; 4449 type = "critical"; 4450 }; 4451 }; 4452 }; 4453 }; 4454 4455 timer { 4456 compatible = "arm,armv8-timer"; 4457 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4458 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4459 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4460 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4461 }; 4462}; 4463