1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,icc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 10#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clocks { 21 xo_board_clk: xo-board-clk { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 }; 25 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "qcom,kryo"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 qcom,freq-domain = <&cpufreq_hw 0>; 42 next-level-cache = <&L2_0>; 43 L2_0: l2-cache { 44 compatible = "cache"; 45 next-level-cache = <&L3_0>; 46 L3_0: l3-cache { 47 compatible = "cache"; 48 }; 49 }; 50 }; 51 52 CPU1: cpu@100 { 53 device_type = "cpu"; 54 compatible = "qcom,kryo"; 55 reg = <0x0 0x100>; 56 enable-method = "psci"; 57 qcom,freq-domain = <&cpufreq_hw 0>; 58 next-level-cache = <&L2_1>; 59 L2_1: l2-cache { 60 compatible = "cache"; 61 next-level-cache = <&L3_0>; 62 }; 63 }; 64 65 CPU2: cpu@200 { 66 device_type = "cpu"; 67 compatible = "qcom,kryo"; 68 reg = <0x0 0x200>; 69 enable-method = "psci"; 70 qcom,freq-domain = <&cpufreq_hw 0>; 71 next-level-cache = <&L2_2>; 72 L2_2: l2-cache { 73 compatible = "cache"; 74 next-level-cache = <&L3_0>; 75 }; 76 }; 77 78 CPU3: cpu@300 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo"; 81 reg = <0x0 0x300>; 82 enable-method = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 next-level-cache = <&L2_3>; 85 L2_3: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 }; 90 91 CPU4: cpu@10000 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo"; 94 reg = <0x0 0x10000>; 95 enable-method = "psci"; 96 qcom,freq-domain = <&cpufreq_hw 1>; 97 next-level-cache = <&L2_4>; 98 L2_4: l2-cache { 99 compatible = "cache"; 100 next-level-cache = <&L3_1>; 101 L3_1: l3-cache { 102 compatible = "cache"; 103 }; 104 105 }; 106 }; 107 108 CPU5: cpu@10100 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo"; 111 reg = <0x0 0x10100>; 112 enable-method = "psci"; 113 qcom,freq-domain = <&cpufreq_hw 1>; 114 next-level-cache = <&L2_5>; 115 L2_5: l2-cache { 116 compatible = "cache"; 117 next-level-cache = <&L3_1>; 118 }; 119 }; 120 121 CPU6: cpu@10200 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo"; 124 reg = <0x0 0x10200>; 125 enable-method = "psci"; 126 qcom,freq-domain = <&cpufreq_hw 1>; 127 next-level-cache = <&L2_6>; 128 L2_6: l2-cache { 129 compatible = "cache"; 130 next-level-cache = <&L3_1>; 131 }; 132 }; 133 134 CPU7: cpu@10300 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo"; 137 reg = <0x0 0x10300>; 138 enable-method = "psci"; 139 qcom,freq-domain = <&cpufreq_hw 1>; 140 next-level-cache = <&L2_7>; 141 L2_7: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_1>; 144 }; 145 }; 146 147 cpu-map { 148 cluster0 { 149 core0 { 150 cpu = <&CPU0>; 151 }; 152 153 core1 { 154 cpu = <&CPU1>; 155 }; 156 157 core2 { 158 cpu = <&CPU2>; 159 }; 160 161 core3 { 162 cpu = <&CPU3>; 163 }; 164 }; 165 166 cluster1 { 167 core0 { 168 cpu = <&CPU4>; 169 }; 170 171 core1 { 172 cpu = <&CPU5>; 173 }; 174 175 core2 { 176 cpu = <&CPU6>; 177 }; 178 179 core3 { 180 cpu = <&CPU7>; 181 }; 182 }; 183 }; 184 }; 185 186 firmware { 187 scm { 188 compatible = "qcom,scm-sa8775p", "qcom,scm"; 189 }; 190 }; 191 192 aggre1_noc: interconnect-aggre1-noc { 193 compatible = "qcom,sa8775p-aggre1-noc"; 194 #interconnect-cells = <2>; 195 qcom,bcm-voters = <&apps_bcm_voter>; 196 }; 197 198 aggre2_noc: interconnect-aggre2-noc { 199 compatible = "qcom,sa8775p-aggre2-noc"; 200 #interconnect-cells = <2>; 201 qcom,bcm-voters = <&apps_bcm_voter>; 202 }; 203 204 clk_virt: interconnect-clk-virt { 205 compatible = "qcom,sa8775p-clk-virt"; 206 #interconnect-cells = <2>; 207 qcom,bcm-voters = <&apps_bcm_voter>; 208 }; 209 210 config_noc: interconnect-config-noc { 211 compatible = "qcom,sa8775p-config-noc"; 212 #interconnect-cells = <2>; 213 qcom,bcm-voters = <&apps_bcm_voter>; 214 }; 215 216 dc_noc: interconnect-dc-noc { 217 compatible = "qcom,sa8775p-dc-noc"; 218 #interconnect-cells = <2>; 219 qcom,bcm-voters = <&apps_bcm_voter>; 220 }; 221 222 gem_noc: interconnect-gem-noc { 223 compatible = "qcom,sa8775p-gem-noc"; 224 #interconnect-cells = <2>; 225 qcom,bcm-voters = <&apps_bcm_voter>; 226 }; 227 228 gpdsp_anoc: interconnect-gpdsp-anoc { 229 compatible = "qcom,sa8775p-gpdsp-anoc"; 230 #interconnect-cells = <2>; 231 qcom,bcm-voters = <&apps_bcm_voter>; 232 }; 233 234 lpass_ag_noc: interconnect-lpass-ag-noc { 235 compatible = "qcom,sa8775p-lpass-ag-noc"; 236 #interconnect-cells = <2>; 237 qcom,bcm-voters = <&apps_bcm_voter>; 238 }; 239 240 mc_virt: interconnect-mc-virt { 241 compatible = "qcom,sa8775p-mc-virt"; 242 #interconnect-cells = <2>; 243 qcom,bcm-voters = <&apps_bcm_voter>; 244 }; 245 246 mmss_noc: interconnect-mmss-noc { 247 compatible = "qcom,sa8775p-mmss-noc"; 248 #interconnect-cells = <2>; 249 qcom,bcm-voters = <&apps_bcm_voter>; 250 }; 251 252 nspa_noc: interconnect-nspa-noc { 253 compatible = "qcom,sa8775p-nspa-noc"; 254 #interconnect-cells = <2>; 255 qcom,bcm-voters = <&apps_bcm_voter>; 256 }; 257 258 nspb_noc: interconnect-nspb-noc { 259 compatible = "qcom,sa8775p-nspb-noc"; 260 #interconnect-cells = <2>; 261 qcom,bcm-voters = <&apps_bcm_voter>; 262 }; 263 264 pcie_anoc: interconnect-pcie-anoc { 265 compatible = "qcom,sa8775p-pcie-anoc"; 266 #interconnect-cells = <2>; 267 qcom,bcm-voters = <&apps_bcm_voter>; 268 }; 269 270 system_noc: interconnect-system-noc { 271 compatible = "qcom,sa8775p-system-noc"; 272 #interconnect-cells = <2>; 273 qcom,bcm-voters = <&apps_bcm_voter>; 274 }; 275 276 /* Will be updated by the bootloader. */ 277 memory@80000000 { 278 device_type = "memory"; 279 reg = <0x0 0x80000000 0x0 0x0>; 280 }; 281 282 qup_opp_table_100mhz: opp-table-qup100mhz { 283 compatible = "operating-points-v2"; 284 285 opp-100000000 { 286 opp-hz = /bits/ 64 <100000000>; 287 required-opps = <&rpmhpd_opp_svs_l1>; 288 }; 289 }; 290 291 psci { 292 compatible = "arm,psci-1.0"; 293 method = "smc"; 294 }; 295 296 reserved-memory { 297 #address-cells = <2>; 298 #size-cells = <2>; 299 ranges; 300 301 sail_ss_mem: sail-ss@80000000 { 302 reg = <0x0 0x80000000 0x0 0x10000000>; 303 no-map; 304 }; 305 306 hyp_mem: hyp@90000000 { 307 reg = <0x0 0x90000000 0x0 0x600000>; 308 no-map; 309 }; 310 311 xbl_boot_mem: xbl-boot@90600000 { 312 reg = <0x0 0x90600000 0x0 0x200000>; 313 no-map; 314 }; 315 316 aop_image_mem: aop-image@90800000 { 317 reg = <0x0 0x90800000 0x0 0x60000>; 318 no-map; 319 }; 320 321 aop_cmd_db_mem: aop-cmd-db@90860000 { 322 compatible = "qcom,cmd-db"; 323 reg = <0x0 0x90860000 0x0 0x20000>; 324 no-map; 325 }; 326 327 uefi_log: uefi-log@908b0000 { 328 reg = <0x0 0x908b0000 0x0 0x10000>; 329 no-map; 330 }; 331 332 reserved_mem: reserved@908f0000 { 333 reg = <0x0 0x908f0000 0x0 0xf000>; 334 no-map; 335 }; 336 337 secdata_apss_mem: secdata-apss@908ff000 { 338 reg = <0x0 0x908ff000 0x0 0x1000>; 339 no-map; 340 }; 341 342 smem_mem: smem@90900000 { 343 compatible = "qcom,smem"; 344 reg = <0x0 0x90900000 0x0 0x200000>; 345 no-map; 346 hwlocks = <&tcsr_mutex 3>; 347 }; 348 349 cpucp_fw_mem: cpucp-fw@90b00000 { 350 reg = <0x0 0x90b00000 0x0 0x100000>; 351 no-map; 352 }; 353 354 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 355 reg = <0x0 0x93b00000 0x0 0xf00000>; 356 no-map; 357 }; 358 359 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 360 reg = <0x0 0x94a00000 0x0 0x800000>; 361 no-map; 362 }; 363 364 pil_camera_mem: pil-camera@95200000 { 365 reg = <0x0 0x95200000 0x0 0x500000>; 366 no-map; 367 }; 368 369 pil_adsp_mem: pil-adsp@95c00000 { 370 reg = <0x0 0x95c00000 0x0 0x1e00000>; 371 no-map; 372 }; 373 374 pil_gdsp0_mem: pil-gdsp0@97b00000 { 375 reg = <0x0 0x97b00000 0x0 0x1e00000>; 376 no-map; 377 }; 378 379 pil_gdsp1_mem: pil-gdsp1@99900000 { 380 reg = <0x0 0x99900000 0x0 0x1e00000>; 381 no-map; 382 }; 383 384 pil_cdsp0_mem: pil-cdsp0@9b800000 { 385 reg = <0x0 0x9b800000 0x0 0x1e00000>; 386 no-map; 387 }; 388 389 pil_gpu_mem: pil-gpu@9d600000 { 390 reg = <0x0 0x9d600000 0x0 0x2000>; 391 no-map; 392 }; 393 394 pil_cdsp1_mem: pil-cdsp1@9d700000 { 395 reg = <0x0 0x9d700000 0x0 0x1e00000>; 396 no-map; 397 }; 398 399 pil_cvp_mem: pil-cvp@9f500000 { 400 reg = <0x0 0x9f500000 0x0 0x700000>; 401 no-map; 402 }; 403 404 pil_video_mem: pil-video@9fc00000 { 405 reg = <0x0 0x9fc00000 0x0 0x700000>; 406 no-map; 407 }; 408 409 hyptz_reserved_mem: hyptz-reserved@beb00000 { 410 reg = <0x0 0xbeb00000 0x0 0x11500000>; 411 no-map; 412 }; 413 414 tz_stat_mem: tz-stat@d0000000 { 415 reg = <0x0 0xd0000000 0x0 0x100000>; 416 no-map; 417 }; 418 419 tags_mem: tags@d0100000 { 420 reg = <0x0 0xd0100000 0x0 0x1200000>; 421 no-map; 422 }; 423 424 qtee_mem: qtee@d1300000 { 425 reg = <0x0 0xd1300000 0x0 0x500000>; 426 no-map; 427 }; 428 429 trusted_apps_mem: trusted-apps@d1800000 { 430 reg = <0x0 0xd1800000 0x0 0x3900000>; 431 no-map; 432 }; 433 }; 434 435 soc: soc@0 { 436 compatible = "simple-bus"; 437 #address-cells = <2>; 438 #size-cells = <2>; 439 ranges = <0 0 0 0 0x10 0>; 440 441 gcc: clock-controller@100000 { 442 compatible = "qcom,sa8775p-gcc"; 443 reg = <0x0 0x00100000 0x0 0xc7018>; 444 #clock-cells = <1>; 445 #reset-cells = <1>; 446 #power-domain-cells = <1>; 447 clocks = <&rpmhcc RPMH_CXO_CLK>, 448 <&sleep_clk>, 449 <0>, 450 <0>, 451 <0>, 452 <0>, 453 <0>, 454 <0>, 455 <0>, 456 <0>, 457 <0>, 458 <0>, 459 <0>, 460 <0>, 461 <0>; 462 power-domains = <&rpmhpd SA8775P_CX>; 463 }; 464 465 ipcc: mailbox@408000 { 466 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 467 reg = <0x0 0x00408000 0x0 0x1000>; 468 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-controller; 470 #interrupt-cells = <3>; 471 #mbox-cells = <2>; 472 }; 473 474 qupv3_id_2: geniqup@8c0000 { 475 compatible = "qcom,geni-se-qup"; 476 reg = <0x0 0x008c0000 0x0 0x6000>; 477 ranges; 478 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 479 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 480 clock-names = "m-ahb", "s-ahb"; 481 iommus = <&apps_smmu 0x5a3 0x0>; 482 #address-cells = <2>; 483 #size-cells = <2>; 484 status = "disabled"; 485 486 spi16: spi@888000 { 487 compatible = "qcom,geni-spi"; 488 reg = <0x0 0x00888000 0x0 0x4000>; 489 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 491 clock-names = "se"; 492 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 493 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 494 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 495 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 496 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 497 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 498 interconnect-names = "qup-core", 499 "qup-config", 500 "qup-memory"; 501 power-domains = <&rpmhpd SA8775P_CX>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505 }; 506 507 uart17: serial@88c000 { 508 compatible = "qcom,geni-uart"; 509 reg = <0x0 0x0088c000 0x0 0x4000>; 510 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 512 clock-names = "se"; 513 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 514 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 515 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 516 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 517 interconnect-names = "qup-core", "qup-config"; 518 power-domains = <&rpmhpd SA8775P_CX>; 519 status = "disabled"; 520 }; 521 522 i2c18: i2c@890000 { 523 compatible = "qcom,geni-i2c"; 524 reg = <0x0 0x00890000 0x0 0x4000>; 525 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 527 clock-names = "se"; 528 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 529 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 530 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 531 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 532 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 533 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 534 interconnect-names = "qup-core", 535 "qup-config", 536 "qup-memory"; 537 power-domains = <&rpmhpd SA8775P_CX>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 }; 543 544 qupv3_id_1: geniqup@ac0000 { 545 compatible = "qcom,geni-se-qup"; 546 reg = <0x0 0x00ac0000 0x0 0x6000>; 547 #address-cells = <2>; 548 #size-cells = <2>; 549 ranges; 550 clock-names = "m-ahb", "s-ahb"; 551 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 552 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 553 iommus = <&apps_smmu 0x443 0x0>; 554 status = "disabled"; 555 556 uart10: serial@a8c000 { 557 compatible = "qcom,geni-uart"; 558 reg = <0x0 0x00a8c000 0x0 0x4000>; 559 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 560 clock-names = "se"; 561 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 562 interconnect-names = "qup-core", "qup-config"; 563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 564 &clk_virt SLAVE_QUP_CORE_1 0>, 565 <&gem_noc MASTER_APPSS_PROC 0 566 &config_noc SLAVE_QUP_1 0>; 567 power-domains = <&rpmhpd SA8775P_CX>; 568 operating-points-v2 = <&qup_opp_table_100mhz>; 569 status = "disabled"; 570 }; 571 572 uart12: serial@a94000 { 573 compatible = "qcom,geni-uart"; 574 reg = <0x0 0x00a94000 0x0 0x4000>; 575 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 577 clock-names = "se"; 578 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 579 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 580 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 581 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 582 interconnect-names = "qup-core", "qup-config"; 583 power-domains = <&rpmhpd SA8775P_CX>; 584 status = "disabled"; 585 }; 586 }; 587 588 tcsr_mutex: hwlock@1f40000 { 589 compatible = "qcom,tcsr-mutex"; 590 reg = <0x0 0x01f40000 0x0 0x20000>; 591 #hwlock-cells = <1>; 592 }; 593 594 pdc: interrupt-controller@b220000 { 595 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 596 reg = <0x0 0x0b220000 0x0 0x30000>, 597 <0x0 0x17c000f0 0x0 0x64>; 598 qcom,pdc-ranges = <0 480 40>, 599 <40 140 14>, 600 <54 263 1>, 601 <55 306 4>, 602 <59 312 3>, 603 <62 374 2>, 604 <64 434 2>, 605 <66 438 2>, 606 <70 520 1>, 607 <73 523 1>, 608 <118 568 6>, 609 <124 609 3>, 610 <159 638 1>, 611 <160 720 3>, 612 <169 728 30>, 613 <199 416 2>, 614 <201 449 1>, 615 <202 89 1>, 616 <203 451 1>, 617 <204 462 1>, 618 <205 264 1>, 619 <206 579 1>, 620 <207 653 1>, 621 <208 656 1>, 622 <209 659 1>, 623 <210 122 1>, 624 <211 699 1>, 625 <212 705 1>, 626 <213 450 1>, 627 <214 643 2>, 628 <216 646 5>, 629 <221 390 5>, 630 <226 700 2>, 631 <228 440 1>, 632 <229 663 1>, 633 <230 524 2>, 634 <232 612 3>, 635 <235 723 5>; 636 #interrupt-cells = <2>; 637 interrupt-parent = <&intc>; 638 interrupt-controller; 639 }; 640 641 spmi_bus: spmi@c440000 { 642 compatible = "qcom,spmi-pmic-arb"; 643 reg = <0x0 0x0c440000 0x0 0x1100>, 644 <0x0 0x0c600000 0x0 0x2000000>, 645 <0x0 0x0e600000 0x0 0x100000>, 646 <0x0 0x0e700000 0x0 0xa0000>, 647 <0x0 0x0c40a000 0x0 0x26000>; 648 reg-names = "core", 649 "chnls", 650 "obsrvr", 651 "intr", 652 "cnfg"; 653 qcom,channel = <0>; 654 qcom,ee = <0>; 655 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 656 interrupt-names = "periph_irq"; 657 interrupt-controller; 658 #interrupt-cells = <4>; 659 #address-cells = <2>; 660 #size-cells = <0>; 661 }; 662 663 tlmm: pinctrl@f000000 { 664 compatible = "qcom,sa8775p-tlmm"; 665 reg = <0x0 0x0f000000 0x0 0x1000000>; 666 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 667 gpio-controller; 668 #gpio-cells = <2>; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 gpio-ranges = <&tlmm 0 0 149>; 672 }; 673 674 apps_smmu: iommu@15000000 { 675 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 676 reg = <0x0 0x15000000 0x0 0x100000>; 677 #iommu-cells = <2>; 678 #global-interrupts = <2>; 679 680 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 810 }; 811 812 intc: interrupt-controller@17a00000 { 813 compatible = "arm,gic-v3"; 814 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 815 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 816 interrupt-controller; 817 #interrupt-cells = <3>; 818 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 819 #redistributor-regions = <1>; 820 redistributor-stride = <0x0 0x20000>; 821 }; 822 823 memtimer: timer@17c20000 { 824 compatible = "arm,armv7-timer-mem"; 825 reg = <0x0 0x17c20000 0x0 0x1000>; 826 ranges = <0x0 0x0 0x0 0x20000000>; 827 #address-cells = <1>; 828 #size-cells = <1>; 829 830 frame@17c21000 { 831 reg = <0x17c21000 0x1000>, 832 <0x17c22000 0x1000>; 833 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 835 frame-number = <0>; 836 }; 837 838 frame@17c23000 { 839 reg = <0x17c23000 0x1000>; 840 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 841 frame-number = <1>; 842 status = "disabled"; 843 }; 844 845 frame@17c25000 { 846 reg = <0x17c25000 0x1000>; 847 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 848 frame-number = <2>; 849 status = "disabled"; 850 }; 851 852 frame@17c27000 { 853 reg = <0x17c27000 0x1000>; 854 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 855 frame-number = <3>; 856 status = "disabled"; 857 }; 858 859 frame@17c29000 { 860 reg = <0x17c29000 0x1000>; 861 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 862 frame-number = <4>; 863 status = "disabled"; 864 }; 865 866 frame@17c2b000 { 867 reg = <0x17c2b000 0x1000>; 868 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 869 frame-number = <5>; 870 status = "disabled"; 871 }; 872 873 frame@17c2d000 { 874 reg = <0x17c2d000 0x1000>; 875 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 876 frame-number = <6>; 877 status = "disabled"; 878 }; 879 }; 880 881 apps_rsc: rsc@18200000 { 882 compatible = "qcom,rpmh-rsc"; 883 reg = <0x0 0x18200000 0x0 0x10000>, 884 <0x0 0x18210000 0x0 0x10000>, 885 <0x0 0x18220000 0x0 0x10000>; 886 reg-names = "drv-0", "drv-1", "drv-2"; 887 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 890 qcom,tcs-offset = <0xd00>; 891 qcom,drv-id = <2>; 892 qcom,tcs-config = <ACTIVE_TCS 2>, 893 <SLEEP_TCS 3>, 894 <WAKE_TCS 3>, 895 <CONTROL_TCS 0>; 896 label = "apps_rsc"; 897 898 apps_bcm_voter: bcm-voter { 899 compatible = "qcom,bcm-voter"; 900 }; 901 902 rpmhcc: clock-controller { 903 compatible = "qcom,sa8775p-rpmh-clk"; 904 #clock-cells = <1>; 905 clock-names = "xo"; 906 clocks = <&xo_board_clk>; 907 }; 908 909 rpmhpd: power-controller { 910 compatible = "qcom,sa8775p-rpmhpd"; 911 #power-domain-cells = <1>; 912 operating-points-v2 = <&rpmhpd_opp_table>; 913 914 rpmhpd_opp_table: opp-table { 915 compatible = "operating-points-v2"; 916 917 rpmhpd_opp_ret: opp-0 { 918 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 919 }; 920 921 rpmhpd_opp_min_svs: opp-1 { 922 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 923 }; 924 925 rpmhpd_opp_low_svs: opp2 { 926 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 927 }; 928 929 rpmhpd_opp_svs: opp3 { 930 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 931 }; 932 933 rpmhpd_opp_svs_l1: opp-4 { 934 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 935 }; 936 937 rpmhpd_opp_nom: opp-5 { 938 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 939 }; 940 941 rpmhpd_opp_nom_l1: opp-6 { 942 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 943 }; 944 945 rpmhpd_opp_nom_l2: opp-7 { 946 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 947 }; 948 949 rpmhpd_opp_turbo: opp-8 { 950 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 951 }; 952 953 rpmhpd_opp_turbo_l1: opp-9 { 954 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 955 }; 956 }; 957 }; 958 }; 959 960 cpufreq_hw: cpufreq@18591000 { 961 compatible = "qcom,sa8775p-cpufreq-epss", 962 "qcom,cpufreq-epss"; 963 reg = <0x0 0x18591000 0x0 0x1000>, 964 <0x0 0x18593000 0x0 0x1000>; 965 reg-names = "freq-domain0", "freq-domain1"; 966 967 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 968 clock-names = "xo", "alternate"; 969 970 #freq-domain-cells = <1>; 971 }; 972 }; 973 974 arch_timer: timer { 975 compatible = "arm,armv8-timer"; 976 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 977 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 978 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 979 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 980 }; 981}; 982