xref: /openbmc/linux/arch/arm64/boot/dts/qcom/sa8775p.dtsi (revision 12109610)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2023, Linaro Limited
4 */
5
6#include <dt-bindings/interconnect/qcom,icc.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
12#include <dt-bindings/mailbox/qcom-ipcc.h>
13#include <dt-bindings/power/qcom-rpmpd.h>
14#include <dt-bindings/soc/qcom,rpmh-rsc.h>
15
16/ {
17	interrupt-parent = <&intc>;
18
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	clocks {
23		xo_board_clk: xo-board-clk {
24			compatible = "fixed-clock";
25			#clock-cells = <0>;
26		};
27
28		sleep_clk: sleep-clk {
29			compatible = "fixed-clock";
30			#clock-cells = <0>;
31		};
32	};
33
34	cpus {
35		#address-cells = <2>;
36		#size-cells = <0>;
37
38		CPU0: cpu@0 {
39			device_type = "cpu";
40			compatible = "qcom,kryo";
41			reg = <0x0 0x0>;
42			enable-method = "psci";
43			qcom,freq-domain = <&cpufreq_hw 0>;
44			next-level-cache = <&L2_0>;
45			L2_0: l2-cache {
46				compatible = "cache";
47				next-level-cache = <&L3_0>;
48				L3_0: l3-cache {
49					compatible = "cache";
50				};
51			};
52		};
53
54		CPU1: cpu@100 {
55			device_type = "cpu";
56			compatible = "qcom,kryo";
57			reg = <0x0 0x100>;
58			enable-method = "psci";
59			qcom,freq-domain = <&cpufreq_hw 0>;
60			next-level-cache = <&L2_1>;
61			L2_1: l2-cache {
62				compatible = "cache";
63				next-level-cache = <&L3_0>;
64			};
65		};
66
67		CPU2: cpu@200 {
68			device_type = "cpu";
69			compatible = "qcom,kryo";
70			reg = <0x0 0x200>;
71			enable-method = "psci";
72			qcom,freq-domain = <&cpufreq_hw 0>;
73			next-level-cache = <&L2_2>;
74			L2_2: l2-cache {
75				compatible = "cache";
76				next-level-cache = <&L3_0>;
77			};
78		};
79
80		CPU3: cpu@300 {
81			device_type = "cpu";
82			compatible = "qcom,kryo";
83			reg = <0x0 0x300>;
84			enable-method = "psci";
85			qcom,freq-domain = <&cpufreq_hw 0>;
86			next-level-cache = <&L2_3>;
87			L2_3: l2-cache {
88				compatible = "cache";
89				next-level-cache = <&L3_0>;
90			};
91		};
92
93		CPU4: cpu@10000 {
94			device_type = "cpu";
95			compatible = "qcom,kryo";
96			reg = <0x0 0x10000>;
97			enable-method = "psci";
98			qcom,freq-domain = <&cpufreq_hw 1>;
99			next-level-cache = <&L2_4>;
100			L2_4: l2-cache {
101				compatible = "cache";
102				next-level-cache = <&L3_1>;
103				L3_1: l3-cache {
104					compatible = "cache";
105				};
106
107			};
108		};
109
110		CPU5: cpu@10100 {
111			device_type = "cpu";
112			compatible = "qcom,kryo";
113			reg = <0x0 0x10100>;
114			enable-method = "psci";
115			qcom,freq-domain = <&cpufreq_hw 1>;
116			next-level-cache = <&L2_5>;
117			L2_5: l2-cache {
118				compatible = "cache";
119				next-level-cache = <&L3_1>;
120			};
121		};
122
123		CPU6: cpu@10200 {
124			device_type = "cpu";
125			compatible = "qcom,kryo";
126			reg = <0x0 0x10200>;
127			enable-method = "psci";
128			qcom,freq-domain = <&cpufreq_hw 1>;
129			next-level-cache = <&L2_6>;
130			L2_6: l2-cache {
131				compatible = "cache";
132				next-level-cache = <&L3_1>;
133			};
134		};
135
136		CPU7: cpu@10300 {
137			device_type = "cpu";
138			compatible = "qcom,kryo";
139			reg = <0x0 0x10300>;
140			enable-method = "psci";
141			qcom,freq-domain = <&cpufreq_hw 1>;
142			next-level-cache = <&L2_7>;
143			L2_7: l2-cache {
144				compatible = "cache";
145				next-level-cache = <&L3_1>;
146			};
147		};
148
149		cpu-map {
150			cluster0 {
151				core0 {
152					cpu = <&CPU0>;
153				};
154
155				core1 {
156					cpu = <&CPU1>;
157				};
158
159				core2 {
160					cpu = <&CPU2>;
161				};
162
163				core3 {
164					cpu = <&CPU3>;
165				};
166			};
167
168			cluster1 {
169				core0 {
170					cpu = <&CPU4>;
171				};
172
173				core1 {
174					cpu = <&CPU5>;
175				};
176
177				core2 {
178					cpu = <&CPU6>;
179				};
180
181				core3 {
182					cpu = <&CPU7>;
183				};
184			};
185		};
186	};
187
188	firmware {
189		scm {
190			compatible = "qcom,scm-sa8775p", "qcom,scm";
191		};
192	};
193
194	aggre1_noc: interconnect-aggre1-noc {
195		compatible = "qcom,sa8775p-aggre1-noc";
196		#interconnect-cells = <2>;
197		qcom,bcm-voters = <&apps_bcm_voter>;
198	};
199
200	aggre2_noc: interconnect-aggre2-noc {
201		compatible = "qcom,sa8775p-aggre2-noc";
202		#interconnect-cells = <2>;
203		qcom,bcm-voters = <&apps_bcm_voter>;
204	};
205
206	clk_virt: interconnect-clk-virt {
207		compatible = "qcom,sa8775p-clk-virt";
208		#interconnect-cells = <2>;
209		qcom,bcm-voters = <&apps_bcm_voter>;
210	};
211
212	config_noc: interconnect-config-noc {
213		compatible = "qcom,sa8775p-config-noc";
214		#interconnect-cells = <2>;
215		qcom,bcm-voters = <&apps_bcm_voter>;
216	};
217
218	dc_noc: interconnect-dc-noc {
219		compatible = "qcom,sa8775p-dc-noc";
220		#interconnect-cells = <2>;
221		qcom,bcm-voters = <&apps_bcm_voter>;
222	};
223
224	gem_noc: interconnect-gem-noc {
225		compatible = "qcom,sa8775p-gem-noc";
226		#interconnect-cells = <2>;
227		qcom,bcm-voters = <&apps_bcm_voter>;
228	};
229
230	gpdsp_anoc: interconnect-gpdsp-anoc {
231		compatible = "qcom,sa8775p-gpdsp-anoc";
232		#interconnect-cells = <2>;
233		qcom,bcm-voters = <&apps_bcm_voter>;
234	};
235
236	lpass_ag_noc: interconnect-lpass-ag-noc {
237		compatible = "qcom,sa8775p-lpass-ag-noc";
238		#interconnect-cells = <2>;
239		qcom,bcm-voters = <&apps_bcm_voter>;
240	};
241
242	mc_virt: interconnect-mc-virt {
243		compatible = "qcom,sa8775p-mc-virt";
244		#interconnect-cells = <2>;
245		qcom,bcm-voters = <&apps_bcm_voter>;
246	};
247
248	mmss_noc: interconnect-mmss-noc {
249		compatible = "qcom,sa8775p-mmss-noc";
250		#interconnect-cells = <2>;
251		qcom,bcm-voters = <&apps_bcm_voter>;
252	};
253
254	nspa_noc: interconnect-nspa-noc {
255		compatible = "qcom,sa8775p-nspa-noc";
256		#interconnect-cells = <2>;
257		qcom,bcm-voters = <&apps_bcm_voter>;
258	};
259
260	nspb_noc: interconnect-nspb-noc {
261		compatible = "qcom,sa8775p-nspb-noc";
262		#interconnect-cells = <2>;
263		qcom,bcm-voters = <&apps_bcm_voter>;
264	};
265
266	pcie_anoc: interconnect-pcie-anoc {
267		compatible = "qcom,sa8775p-pcie-anoc";
268		#interconnect-cells = <2>;
269		qcom,bcm-voters = <&apps_bcm_voter>;
270	};
271
272	system_noc: interconnect-system-noc {
273		compatible = "qcom,sa8775p-system-noc";
274		#interconnect-cells = <2>;
275		qcom,bcm-voters = <&apps_bcm_voter>;
276	};
277
278	/* Will be updated by the bootloader. */
279	memory@80000000 {
280		device_type = "memory";
281		reg = <0x0 0x80000000 0x0 0x0>;
282	};
283
284	qup_opp_table_100mhz: opp-table-qup100mhz {
285		compatible = "operating-points-v2";
286
287		opp-100000000 {
288			opp-hz = /bits/ 64 <100000000>;
289			required-opps = <&rpmhpd_opp_svs_l1>;
290		};
291	};
292
293	pmu {
294		compatible = "arm,armv8-pmuv3";
295		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
296	};
297
298	psci {
299		compatible = "arm,psci-1.0";
300		method = "smc";
301	};
302
303	reserved-memory {
304		#address-cells = <2>;
305		#size-cells = <2>;
306		ranges;
307
308		sail_ss_mem: sail-ss@80000000 {
309			reg = <0x0 0x80000000 0x0 0x10000000>;
310			no-map;
311		};
312
313		hyp_mem: hyp@90000000 {
314			reg = <0x0 0x90000000 0x0 0x600000>;
315			no-map;
316		};
317
318		xbl_boot_mem: xbl-boot@90600000 {
319			reg = <0x0 0x90600000 0x0 0x200000>;
320			no-map;
321		};
322
323		aop_image_mem: aop-image@90800000 {
324			reg = <0x0 0x90800000 0x0 0x60000>;
325			no-map;
326		};
327
328		aop_cmd_db_mem: aop-cmd-db@90860000 {
329			compatible = "qcom,cmd-db";
330			reg = <0x0 0x90860000 0x0 0x20000>;
331			no-map;
332		};
333
334		uefi_log: uefi-log@908b0000 {
335			reg = <0x0 0x908b0000 0x0 0x10000>;
336			no-map;
337		};
338
339		reserved_mem: reserved@908f0000 {
340			reg = <0x0 0x908f0000 0x0 0xf000>;
341			no-map;
342		};
343
344		secdata_apss_mem: secdata-apss@908ff000 {
345			reg = <0x0 0x908ff000 0x0 0x1000>;
346			no-map;
347		};
348
349		smem_mem: smem@90900000 {
350			compatible = "qcom,smem";
351			reg = <0x0 0x90900000 0x0 0x200000>;
352			no-map;
353			hwlocks = <&tcsr_mutex 3>;
354		};
355
356		cpucp_fw_mem: cpucp-fw@90b00000 {
357			reg = <0x0 0x90b00000 0x0 0x100000>;
358			no-map;
359		};
360
361		lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
362			reg = <0x0 0x93b00000 0x0 0xf00000>;
363			no-map;
364		};
365
366		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
367			reg = <0x0 0x94a00000 0x0 0x800000>;
368			no-map;
369		};
370
371		pil_camera_mem: pil-camera@95200000 {
372			reg = <0x0 0x95200000 0x0 0x500000>;
373			no-map;
374		};
375
376		pil_adsp_mem: pil-adsp@95c00000 {
377			reg = <0x0 0x95c00000 0x0 0x1e00000>;
378			no-map;
379		};
380
381		pil_gdsp0_mem: pil-gdsp0@97b00000 {
382			reg = <0x0 0x97b00000 0x0 0x1e00000>;
383			no-map;
384		};
385
386		pil_gdsp1_mem: pil-gdsp1@99900000 {
387			reg = <0x0 0x99900000 0x0 0x1e00000>;
388			no-map;
389		};
390
391		pil_cdsp0_mem: pil-cdsp0@9b800000 {
392			reg = <0x0 0x9b800000 0x0 0x1e00000>;
393			no-map;
394		};
395
396		pil_gpu_mem: pil-gpu@9d600000 {
397			reg = <0x0 0x9d600000 0x0 0x2000>;
398			no-map;
399		};
400
401		pil_cdsp1_mem: pil-cdsp1@9d700000 {
402			reg = <0x0 0x9d700000 0x0 0x1e00000>;
403			no-map;
404		};
405
406		pil_cvp_mem: pil-cvp@9f500000 {
407			reg = <0x0 0x9f500000 0x0 0x700000>;
408			no-map;
409		};
410
411		pil_video_mem: pil-video@9fc00000 {
412			reg = <0x0 0x9fc00000 0x0 0x700000>;
413			no-map;
414		};
415
416		hyptz_reserved_mem: hyptz-reserved@beb00000 {
417			reg = <0x0 0xbeb00000 0x0 0x11500000>;
418			no-map;
419		};
420
421		tz_stat_mem: tz-stat@d0000000 {
422			reg = <0x0 0xd0000000 0x0 0x100000>;
423			no-map;
424		};
425
426		tags_mem: tags@d0100000 {
427			reg = <0x0 0xd0100000 0x0 0x1200000>;
428			no-map;
429		};
430
431		qtee_mem: qtee@d1300000 {
432			reg = <0x0 0xd1300000 0x0 0x500000>;
433			no-map;
434		};
435
436		trusted_apps_mem: trusted-apps@d1800000 {
437			reg = <0x0 0xd1800000 0x0 0x3900000>;
438			no-map;
439		};
440	};
441
442	soc: soc@0 {
443		compatible = "simple-bus";
444		#address-cells = <2>;
445		#size-cells = <2>;
446		ranges = <0 0 0 0 0x10 0>;
447
448		gcc: clock-controller@100000 {
449			compatible = "qcom,sa8775p-gcc";
450			reg = <0x0 0x00100000 0x0 0xc7018>;
451			#clock-cells = <1>;
452			#reset-cells = <1>;
453			#power-domain-cells = <1>;
454			clocks = <&rpmhcc RPMH_CXO_CLK>,
455				 <&sleep_clk>,
456				 <0>,
457				 <0>,
458				 <0>,
459				 <&usb_0_qmpphy>,
460				 <&usb_1_qmpphy>,
461				 <0>,
462				 <0>,
463				 <0>,
464				 <0>,
465				 <0>,
466				 <0>,
467				 <0>,
468				 <0>;
469			power-domains = <&rpmhpd SA8775P_CX>;
470		};
471
472		ipcc: mailbox@408000 {
473			compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
474			reg = <0x0 0x00408000 0x0 0x1000>;
475			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
476			interrupt-controller;
477			#interrupt-cells = <3>;
478			#mbox-cells = <2>;
479		};
480
481		qupv3_id_2: geniqup@8c0000 {
482			compatible = "qcom,geni-se-qup";
483			reg = <0x0 0x008c0000 0x0 0x6000>;
484			ranges;
485			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
486				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
487			clock-names = "m-ahb", "s-ahb";
488			iommus = <&apps_smmu 0x5a3 0x0>;
489			#address-cells = <2>;
490			#size-cells = <2>;
491			status = "disabled";
492
493			i2c14: i2c@880000 {
494				compatible = "qcom,geni-i2c";
495				reg = <0x0 0x880000 0x0 0x4000>;
496				#address-cells = <1>;
497				#size-cells = <0>;
498				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
499				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
500				clock-names = "se";
501				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
502						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
503						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
504						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
505						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
506						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
507				interconnect-names = "qup-core",
508						     "qup-config",
509						     "qup-memory";
510				power-domains = <&rpmhpd SA8775P_CX>;
511				status = "disabled";
512			};
513
514			spi14: spi@880000 {
515				compatible = "qcom,geni-spi";
516				reg = <0x0 0x880000 0x0 0x4000>;
517				#address-cells = <1>;
518				#size-cells = <0>;
519				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
520				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
521				clock-names = "se";
522				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
523						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
524						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
525						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
526						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
527						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
528				interconnect-names = "qup-core",
529						     "qup-config",
530						     "qup-memory";
531				power-domains = <&rpmhpd SA8775P_CX>;
532				status = "disabled";
533			};
534
535			i2c15: i2c@884000 {
536				compatible = "qcom,geni-i2c";
537				reg = <0x0 0x884000 0x0 0x4000>;
538				#address-cells = <1>;
539				#size-cells = <0>;
540				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
541				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
542				clock-names = "se";
543				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
544						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
545						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
546						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
547						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
548						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
549				interconnect-names = "qup-core",
550						     "qup-config",
551						     "qup-memory";
552				power-domains = <&rpmhpd SA8775P_CX>;
553				status = "disabled";
554			};
555
556			spi15: spi@884000 {
557				compatible = "qcom,geni-spi";
558				reg = <0x0 0x884000 0x0 0x4000>;
559				#address-cells = <1>;
560				#size-cells = <0>;
561				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
562				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
563				clock-names = "se";
564				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
565						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
566						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
567						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
568						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
569						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
570				interconnect-names = "qup-core",
571						     "qup-config",
572						     "qup-memory";
573				power-domains = <&rpmhpd SA8775P_CX>;
574				status = "disabled";
575			};
576
577			i2c16: i2c@888000 {
578				compatible = "qcom,geni-i2c";
579				reg = <0x0 0x888000 0x0 0x4000>;
580				#address-cells = <1>;
581				#size-cells = <0>;
582				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
583				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
584				clock-names = "se";
585				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
586						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
587						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
588						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
589						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
590						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
591				interconnect-names = "qup-core",
592						     "qup-config",
593						     "qup-memory";
594				power-domains = <&rpmhpd SA8775P_CX>;
595				status = "disabled";
596			};
597
598			spi16: spi@888000 {
599				compatible = "qcom,geni-spi";
600				reg = <0x0 0x00888000 0x0 0x4000>;
601				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
602				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
603				clock-names = "se";
604				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
605						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
606						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
607						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
608						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
609						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
610				interconnect-names = "qup-core",
611						     "qup-config",
612						     "qup-memory";
613				power-domains = <&rpmhpd SA8775P_CX>;
614				#address-cells = <1>;
615				#size-cells = <0>;
616				status = "disabled";
617			};
618
619			i2c17: i2c@88c000 {
620				compatible = "qcom,geni-i2c";
621				reg = <0x0 0x88c000 0x0 0x4000>;
622				#address-cells = <1>;
623				#size-cells = <0>;
624				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
625				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
626				clock-names = "se";
627				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
628						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
629						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
630						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
631						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
632						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
633				interconnect-names = "qup-core",
634						     "qup-config",
635						     "qup-memory";
636				power-domains = <&rpmhpd SA8775P_CX>;
637				status = "disabled";
638			};
639
640			spi17: spi@88c000 {
641				compatible = "qcom,geni-spi";
642				reg = <0x0 0x88c000 0x0 0x4000>;
643				#address-cells = <1>;
644				#size-cells = <0>;
645				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
646				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
647				clock-names = "se";
648				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
649						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
650						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
651						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
652						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
653						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
654				interconnect-names = "qup-core",
655						     "qup-config",
656						     "qup-memory";
657				power-domains = <&rpmhpd SA8775P_CX>;
658				status = "disabled";
659			};
660
661			uart17: serial@88c000 {
662				compatible = "qcom,geni-uart";
663				reg = <0x0 0x0088c000 0x0 0x4000>;
664				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
665				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
666				clock-names = "se";
667				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
668						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
669						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
670						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
671				interconnect-names = "qup-core", "qup-config";
672				power-domains = <&rpmhpd SA8775P_CX>;
673				status = "disabled";
674			};
675
676			i2c18: i2c@890000 {
677				compatible = "qcom,geni-i2c";
678				reg = <0x0 0x00890000 0x0 0x4000>;
679				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
680				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
681				clock-names = "se";
682				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
683						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
684						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
685						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
686						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
687						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
688				interconnect-names = "qup-core",
689						     "qup-config",
690						     "qup-memory";
691				power-domains = <&rpmhpd SA8775P_CX>;
692				#address-cells = <1>;
693				#size-cells = <0>;
694				status = "disabled";
695			};
696
697			spi18: spi@890000 {
698				compatible = "qcom,geni-spi";
699				reg = <0x0 0x890000 0x0 0x4000>;
700				#address-cells = <1>;
701				#size-cells = <0>;
702				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
703				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
704				clock-names = "se";
705				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
706						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
707						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
708						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
709						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
710						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
711				interconnect-names = "qup-core",
712						     "qup-config",
713						     "qup-memory";
714				power-domains = <&rpmhpd SA8775P_CX>;
715				status = "disabled";
716			};
717
718			i2c19: i2c@894000 {
719				compatible = "qcom,geni-i2c";
720				reg = <0x0 0x894000 0x0 0x4000>;
721				#address-cells = <1>;
722				#size-cells = <0>;
723				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
724				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
725				clock-names = "se";
726				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
727						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
728						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
729						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
730						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
731						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
732				interconnect-names = "qup-core",
733						     "qup-config",
734						     "qup-memory";
735				power-domains = <&rpmhpd SA8775P_CX>;
736				status = "disabled";
737			};
738
739			spi19: spi@894000 {
740				compatible = "qcom,geni-spi";
741				reg = <0x0 0x894000 0x0 0x4000>;
742				#address-cells = <1>;
743				#size-cells = <0>;
744				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
745				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
746				clock-names = "se";
747				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
748						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
749						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
750						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
751						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
752						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
753				interconnect-names = "qup-core",
754						     "qup-config",
755						     "qup-memory";
756				power-domains = <&rpmhpd SA8775P_CX>;
757				status = "disabled";
758			};
759
760			i2c20: i2c@898000 {
761				compatible = "qcom,geni-i2c";
762				reg = <0x0 0x898000 0x0 0x4000>;
763				#address-cells = <1>;
764				#size-cells = <0>;
765				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
766				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
767				clock-names = "se";
768				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
769						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
770						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
771						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
772						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
773						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
774				interconnect-names = "qup-core",
775						     "qup-config",
776						     "qup-memory";
777				power-domains = <&rpmhpd SA8775P_CX>;
778				status = "disabled";
779			};
780
781			spi20: spi@898000 {
782				compatible = "qcom,geni-spi";
783				reg = <0x0 0x898000 0x0 0x4000>;
784				#address-cells = <1>;
785				#size-cells = <0>;
786				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
787				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
788				clock-names = "se";
789				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
790						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
791						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
792						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
793						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
794						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
795				interconnect-names = "qup-core",
796						     "qup-config",
797						     "qup-memory";
798				power-domains = <&rpmhpd SA8775P_CX>;
799				status = "disabled";
800			};
801		};
802
803		qupv3_id_0: geniqup@9c0000 {
804			compatible = "qcom,geni-se-qup";
805			reg = <0x0 0x9c0000 0x0 0x6000>;
806			#address-cells = <2>;
807			#size-cells = <2>;
808			ranges;
809			clock-names = "m-ahb", "s-ahb";
810			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
811				<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
812			iommus = <&apps_smmu 0x403 0x0>;
813			status = "disabled";
814
815			i2c0: i2c@980000 {
816				compatible = "qcom,geni-i2c";
817				reg = <0x0 0x980000 0x0 0x4000>;
818				#address-cells = <1>;
819				#size-cells = <0>;
820				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
821				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
822				clock-names = "se";
823				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
824						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
825						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
826						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
827						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
828						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
829				interconnect-names = "qup-core",
830						     "qup-config",
831						     "qup-memory";
832				power-domains = <&rpmhpd SA8775P_CX>;
833				status = "disabled";
834			};
835
836			spi0: spi@980000 {
837				compatible = "qcom,geni-spi";
838				reg = <0x0 0x980000 0x0 0x4000>;
839				#address-cells = <1>;
840				#size-cells = <0>;
841				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
842				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
843				clock-names = "se";
844				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
845						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
846						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
847						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
848						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
849						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
850				interconnect-names = "qup-core",
851						     "qup-config",
852						     "qup-memory";
853				power-domains = <&rpmhpd SA8775P_CX>;
854				status = "disabled";
855			};
856
857			i2c1: i2c@984000 {
858				compatible = "qcom,geni-i2c";
859				reg = <0x0 0x984000 0x0 0x4000>;
860				#address-cells = <1>;
861				#size-cells = <0>;
862				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
863				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
864				clock-names = "se";
865				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
866						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
867						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
868						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
869						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
870						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
871				interconnect-names = "qup-core",
872						     "qup-config",
873						     "qup-memory";
874				power-domains = <&rpmhpd SA8775P_CX>;
875				status = "disabled";
876			};
877
878			spi1: spi@984000 {
879				compatible = "qcom,geni-spi";
880				reg = <0x0 0x984000 0x0 0x4000>;
881				#address-cells = <1>;
882				#size-cells = <0>;
883				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
884				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
885				clock-names = "se";
886				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
887						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
888						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
889						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
890						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
891						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
892				interconnect-names = "qup-core",
893						     "qup-config",
894						     "qup-memory";
895				power-domains = <&rpmhpd SA8775P_CX>;
896				status = "disabled";
897			};
898
899			i2c2: i2c@988000 {
900				compatible = "qcom,geni-i2c";
901				reg = <0x0 0x988000 0x0 0x4000>;
902				#address-cells = <1>;
903				#size-cells = <0>;
904				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
905				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
906				clock-names = "se";
907				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
908						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
909						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
910						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
911						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
912						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
913				interconnect-names = "qup-core",
914						     "qup-config",
915						     "qup-memory";
916				power-domains = <&rpmhpd SA8775P_CX>;
917				status = "disabled";
918			};
919
920			spi2: spi@988000 {
921				compatible = "qcom,geni-spi";
922				reg = <0x0 0x988000 0x0 0x4000>;
923				#address-cells = <1>;
924				#size-cells = <0>;
925				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
926				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
927				clock-names = "se";
928				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
929						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
930						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
931						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
932						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
933						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
934				interconnect-names = "qup-core",
935						     "qup-config",
936						     "qup-memory";
937				power-domains = <&rpmhpd SA8775P_CX>;
938				status = "disabled";
939			};
940
941			i2c3: i2c@98c000 {
942				compatible = "qcom,geni-i2c";
943				reg = <0x0 0x98c000 0x0 0x4000>;
944				#address-cells = <1>;
945				#size-cells = <0>;
946				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
947				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
948				clock-names = "se";
949				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
950						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
951						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
952						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
953						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
954						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
955				interconnect-names = "qup-core",
956						     "qup-config",
957						     "qup-memory";
958				power-domains = <&rpmhpd SA8775P_CX>;
959				status = "disabled";
960			};
961
962			spi3: spi@98c000 {
963				compatible = "qcom,geni-spi";
964				reg = <0x0 0x98c000 0x0 0x4000>;
965				#address-cells = <1>;
966				#size-cells = <0>;
967				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
968				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
969				clock-names = "se";
970				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
971						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
972						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
973						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
974						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
975						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
976				interconnect-names = "qup-core",
977						     "qup-config",
978						     "qup-memory";
979				power-domains = <&rpmhpd SA8775P_CX>;
980				status = "disabled";
981			};
982
983			i2c4: i2c@990000 {
984				compatible = "qcom,geni-i2c";
985				reg = <0x0 0x990000 0x0 0x4000>;
986				#address-cells = <1>;
987				#size-cells = <0>;
988				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
989				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
990				clock-names = "se";
991				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
992						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
993						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
994						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
995						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
996						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
997				interconnect-names = "qup-core",
998						     "qup-config",
999						     "qup-memory";
1000				power-domains = <&rpmhpd SA8775P_CX>;
1001				status = "disabled";
1002			};
1003
1004			spi4: spi@990000 {
1005				compatible = "qcom,geni-spi";
1006				reg = <0x0 0x990000 0x0 0x4000>;
1007				#address-cells = <1>;
1008				#size-cells = <0>;
1009				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1010				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1011				clock-names = "se";
1012				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1013						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1014						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1015						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1016						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1017						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1018				interconnect-names = "qup-core",
1019						     "qup-config",
1020						     "qup-memory";
1021				power-domains = <&rpmhpd SA8775P_CX>;
1022				status = "disabled";
1023			};
1024
1025			i2c5: i2c@994000 {
1026				compatible = "qcom,geni-i2c";
1027				reg = <0x0 0x994000 0x0 0x4000>;
1028				#address-cells = <1>;
1029				#size-cells = <0>;
1030				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1031				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1032				clock-names = "se";
1033				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1034						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1035						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1036						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1037						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1038						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1039				interconnect-names = "qup-core",
1040						     "qup-config",
1041						     "qup-memory";
1042				power-domains = <&rpmhpd SA8775P_CX>;
1043				status = "disabled";
1044			};
1045
1046			spi5: spi@994000 {
1047				compatible = "qcom,geni-spi";
1048				reg = <0x0 0x994000 0x0 0x4000>;
1049				#address-cells = <1>;
1050				#size-cells = <0>;
1051				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1052				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1053				clock-names = "se";
1054				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1055						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1056						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1057						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1058						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1059						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1060				interconnect-names = "qup-core",
1061						     "qup-config",
1062						     "qup-memory";
1063				power-domains = <&rpmhpd SA8775P_CX>;
1064				status = "disabled";
1065			};
1066
1067			uart5: serial@994000 {
1068				compatible = "qcom,geni-uart";
1069				reg = <0x0 0x994000 0x0 0x4000>;
1070				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1071				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1072				clock-names = "se";
1073				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1074						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1075						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1076						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
1077				interconnect-names = "qup-core", "qup-config";
1078				power-domains = <&rpmhpd SA8775P_CX>;
1079				status = "disabled";
1080			};
1081		};
1082
1083		qupv3_id_1: geniqup@ac0000 {
1084			compatible = "qcom,geni-se-qup";
1085			reg = <0x0 0x00ac0000 0x0 0x6000>;
1086			#address-cells = <2>;
1087			#size-cells = <2>;
1088			ranges;
1089			clock-names = "m-ahb", "s-ahb";
1090			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1091				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1092			iommus = <&apps_smmu 0x443 0x0>;
1093			status = "disabled";
1094
1095			i2c7: i2c@a80000 {
1096				compatible = "qcom,geni-i2c";
1097				reg = <0x0 0xa80000 0x0 0x4000>;
1098				#address-cells = <1>;
1099				#size-cells = <0>;
1100				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1101				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1102				clock-names = "se";
1103				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1104						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1105						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1106						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1107						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1108						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1109				interconnect-names = "qup-core",
1110						     "qup-config",
1111						     "qup-memory";
1112				power-domains = <&rpmhpd SA8775P_CX>;
1113				status = "disabled";
1114			};
1115
1116			spi7: spi@a80000 {
1117				compatible = "qcom,geni-spi";
1118				reg = <0x0 0xa80000 0x0 0x4000>;
1119				#address-cells = <1>;
1120				#size-cells = <0>;
1121				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1122				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1123				clock-names = "se";
1124				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1125						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1126						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1127						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1128						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1129						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1130				interconnect-names = "qup-core",
1131						     "qup-config",
1132						     "qup-memory";
1133				power-domains = <&rpmhpd SA8775P_CX>;
1134				status = "disabled";
1135			};
1136
1137			i2c8: i2c@a84000 {
1138				compatible = "qcom,geni-i2c";
1139				reg = <0x0 0xa84000 0x0 0x4000>;
1140				#address-cells = <1>;
1141				#size-cells = <0>;
1142				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1143				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1144				clock-names = "se";
1145				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1146						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1147						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1148						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1149						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1150						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1151				interconnect-names = "qup-core",
1152						     "qup-config",
1153						     "qup-memory";
1154				power-domains = <&rpmhpd SA8775P_CX>;
1155				status = "disabled";
1156			};
1157
1158			spi8: spi@a84000 {
1159				compatible = "qcom,geni-spi";
1160				reg = <0x0 0xa84000 0x0 0x4000>;
1161				#address-cells = <1>;
1162				#size-cells = <0>;
1163				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1164				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1165				clock-names = "se";
1166				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1167						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1168						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1169						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1170						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1171						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1172				interconnect-names = "qup-core",
1173						     "qup-config",
1174						     "qup-memory";
1175				power-domains = <&rpmhpd SA8775P_CX>;
1176				status = "disabled";
1177			};
1178
1179			i2c9: i2c@a88000 {
1180				compatible = "qcom,geni-i2c";
1181				reg = <0x0 0xa88000 0x0 0x4000>;
1182				#address-cells = <1>;
1183				#size-cells = <0>;
1184				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1185				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1186				clock-names = "se";
1187				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1188						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1189						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1190						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1191						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1192						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1193				interconnect-names = "qup-core",
1194						     "qup-config",
1195						     "qup-memory";
1196				power-domains = <&rpmhpd SA8775P_CX>;
1197				status = "disabled";
1198			};
1199
1200			spi9: spi@a88000 {
1201				compatible = "qcom,geni-spi";
1202				reg = <0x0 0xa88000 0x0 0x4000>;
1203				#address-cells = <1>;
1204				#size-cells = <0>;
1205				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1206				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1207				clock-names = "se";
1208				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1209						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1210						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1211						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1212						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1213						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1214				interconnect-names = "qup-core",
1215						     "qup-config",
1216						     "qup-memory";
1217				power-domains = <&rpmhpd SA8775P_CX>;
1218				status = "disabled";
1219			};
1220
1221			uart9: serial@a88000 {
1222				compatible = "qcom,geni-uart";
1223				reg = <0x0 0xa88000 0x0 0x4000>;
1224				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1225				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1226				clock-names = "se";
1227				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1228						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1229						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1230						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1231				interconnect-names = "qup-core", "qup-config";
1232				power-domains = <&rpmhpd SA8775P_CX>;
1233				status = "disabled";
1234			};
1235
1236			i2c10: i2c@a8c000 {
1237				compatible = "qcom,geni-i2c";
1238				reg = <0x0 0xa8c000 0x0 0x4000>;
1239				#address-cells = <1>;
1240				#size-cells = <0>;
1241				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1242				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1243				clock-names = "se";
1244				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1245						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1246						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1247						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1248						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1249						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1250				interconnect-names = "qup-core",
1251						     "qup-config",
1252						     "qup-memory";
1253				power-domains = <&rpmhpd SA8775P_CX>;
1254				status = "disabled";
1255			};
1256
1257			spi10: spi@a8c000 {
1258				compatible = "qcom,geni-spi";
1259				reg = <0x0 0xa8c000 0x0 0x4000>;
1260				#address-cells = <1>;
1261				#size-cells = <0>;
1262				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1263				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1264				clock-names = "se";
1265				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1266						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1267						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1268						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1269						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1270						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1271				interconnect-names = "qup-core",
1272						     "qup-config",
1273						     "qup-memory";
1274				power-domains = <&rpmhpd SA8775P_CX>;
1275				status = "disabled";
1276			};
1277
1278			uart10: serial@a8c000 {
1279				compatible = "qcom,geni-uart";
1280				reg = <0x0 0x00a8c000 0x0 0x4000>;
1281				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1282				clock-names = "se";
1283				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1284				interconnect-names = "qup-core", "qup-config";
1285				interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1286						 &clk_virt SLAVE_QUP_CORE_1 0>,
1287						<&gem_noc MASTER_APPSS_PROC 0
1288						 &config_noc SLAVE_QUP_1 0>;
1289				power-domains = <&rpmhpd SA8775P_CX>;
1290				operating-points-v2 = <&qup_opp_table_100mhz>;
1291				status = "disabled";
1292			};
1293
1294			i2c11: i2c@a90000 {
1295				compatible = "qcom,geni-i2c";
1296				reg = <0x0 0xa90000 0x0 0x4000>;
1297				#address-cells = <1>;
1298				#size-cells = <0>;
1299				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1300				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1301				clock-names = "se";
1302				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1303						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1304						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1305						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1306						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1307						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1308				interconnect-names = "qup-core",
1309						     "qup-config",
1310						     "qup-memory";
1311				power-domains = <&rpmhpd SA8775P_CX>;
1312				status = "disabled";
1313			};
1314
1315			spi11: spi@a90000 {
1316				compatible = "qcom,geni-spi";
1317				reg = <0x0 0xa90000 0x0 0x4000>;
1318				#address-cells = <1>;
1319				#size-cells = <0>;
1320				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1321				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1322				clock-names = "se";
1323				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1324						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1325						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1326						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1327						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1328						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1329				interconnect-names = "qup-core",
1330						     "qup-config",
1331						     "qup-memory";
1332				power-domains = <&rpmhpd SA8775P_CX>;
1333				status = "disabled";
1334			};
1335
1336			i2c12: i2c@a94000 {
1337				compatible = "qcom,geni-i2c";
1338				reg = <0x0 0xa94000 0x0 0x4000>;
1339				#address-cells = <1>;
1340				#size-cells = <0>;
1341				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1342				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1343				clock-names = "se";
1344				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1345						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1346						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1347						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1348						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1349						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1350				interconnect-names = "qup-core",
1351						     "qup-config",
1352						     "qup-memory";
1353				power-domains = <&rpmhpd SA8775P_CX>;
1354				status = "disabled";
1355			};
1356
1357			spi12: spi@a94000 {
1358				compatible = "qcom,geni-spi";
1359				reg = <0x0 0xa94000 0x0 0x4000>;
1360				#address-cells = <1>;
1361				#size-cells = <0>;
1362				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1363				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1364				clock-names = "se";
1365				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1366						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1367						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1368						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1369						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1370						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1371				interconnect-names = "qup-core",
1372						     "qup-config",
1373						     "qup-memory";
1374				power-domains = <&rpmhpd SA8775P_CX>;
1375				status = "disabled";
1376			};
1377
1378			uart12: serial@a94000 {
1379				compatible = "qcom,geni-uart";
1380				reg = <0x0 0x00a94000 0x0 0x4000>;
1381				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1382				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1383				clock-names = "se";
1384				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1385						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1386						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1387						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1388				interconnect-names = "qup-core", "qup-config";
1389				power-domains = <&rpmhpd SA8775P_CX>;
1390				status = "disabled";
1391			};
1392
1393			i2c13: i2c@a98000 {
1394				compatible = "qcom,geni-i2c";
1395				reg = <0x0 0xa98000 0x0 0x4000>;
1396				#address-cells = <1>;
1397				#size-cells = <0>;
1398				interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1399				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1400				clock-names = "se";
1401				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1402						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1403						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1404						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1405						<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1406						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1407				interconnect-names = "qup-core",
1408						     "qup-config",
1409						     "qup-memory";
1410				power-domains = <&rpmhpd SA8775P_CX>;
1411				status = "disabled";
1412			};
1413		};
1414
1415		qupv3_id_3: geniqup@bc0000 {
1416			compatible = "qcom,geni-se-qup";
1417			reg = <0x0 0xbc0000 0x0 0x6000>;
1418			#address-cells = <2>;
1419			#size-cells = <2>;
1420			ranges;
1421			clock-names = "m-ahb", "s-ahb";
1422			clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
1423				<&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1424			iommus = <&apps_smmu 0x43 0x0>;
1425			status = "disabled";
1426
1427			i2c21: i2c@b80000 {
1428				compatible = "qcom,geni-i2c";
1429				reg = <0x0 0xb80000 0x0 0x4000>;
1430				#address-cells = <1>;
1431				#size-cells = <0>;
1432				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1433				clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1434				clock-names = "se";
1435				interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1436						&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1437					   <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1438						&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1439					   <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1440						&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1441				interconnect-names = "qup-core",
1442							 "qup-config",
1443							 "qup-memory";
1444				power-domains = <&rpmhpd SA8775P_CX>;
1445				status = "disabled";
1446			};
1447
1448			spi21: spi@b80000 {
1449				compatible = "qcom,geni-spi";
1450				reg = <0x0 0xb80000 0x0 0x4000>;
1451				#address-cells = <1>;
1452				#size-cells = <0>;
1453				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1454				clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1455				clock-names = "se";
1456				interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1457						&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1458					   <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1459						&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1460					   <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1461						&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1462				interconnect-names = "qup-core",
1463							 "qup-config",
1464							 "qup-memory";
1465				power-domains = <&rpmhpd SA8775P_CX>;
1466				status = "disabled";
1467			};
1468		};
1469
1470		ufs_mem_hc: ufs@1d84000 {
1471			compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1472			reg = <0x0 0x01d84000 0x0 0x3000>;
1473			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1474			phys = <&ufs_mem_phy>;
1475			phy-names = "ufsphy";
1476			lanes-per-direction = <2>;
1477			#reset-cells = <1>;
1478			resets = <&gcc GCC_UFS_PHY_BCR>;
1479			reset-names = "rst";
1480			power-domains = <&gcc UFS_PHY_GDSC>;
1481			required-opps = <&rpmhpd_opp_nom>;
1482			iommus = <&apps_smmu 0x100 0x0>;
1483			dma-coherent;
1484			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1485				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1486				 <&gcc GCC_UFS_PHY_AHB_CLK>,
1487				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1488				 <&rpmhcc RPMH_CXO_CLK>,
1489				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1490				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1491				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1492			clock-names = "core_clk",
1493				      "bus_aggr_clk",
1494				      "iface_clk",
1495				      "core_clk_unipro",
1496				      "ref_clk",
1497				      "tx_lane0_sync_clk",
1498				      "rx_lane0_sync_clk",
1499				      "rx_lane1_sync_clk";
1500			freq-table-hz = <75000000 300000000>,
1501					<0 0>,
1502					<0 0>,
1503					<75000000 300000000>,
1504					<0 0>,
1505					<0 0>,
1506					<0 0>,
1507					<0 0>;
1508			status = "disabled";
1509		};
1510
1511		ufs_mem_phy: phy@1d87000 {
1512			compatible = "qcom,sa8775p-qmp-ufs-phy";
1513			reg = <0x0 0x01d87000 0x0 0xe10>;
1514			/*
1515			 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
1516			 * enables the CXO clock to eDP *and* UFS PHY.
1517			 */
1518			clocks = <&rpmhcc RPMH_CXO_CLK>,
1519				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1520				 <&gcc GCC_EDP_REF_CLKREF_EN>;
1521			clock-names = "ref", "ref_aux", "qref";
1522			power-domains = <&gcc UFS_PHY_GDSC>;
1523			resets = <&ufs_mem_hc 0>;
1524			reset-names = "ufsphy";
1525			#phy-cells = <0>;
1526			status = "disabled";
1527		};
1528
1529		usb_0_hsphy: phy@88e4000 {
1530			compatible = "qcom,sa8775p-usb-hs-phy",
1531				     "qcom,usb-snps-hs-5nm-phy";
1532			reg = <0 0x088e4000 0 0x120>;
1533			clocks = <&rpmhcc RPMH_CXO_CLK>;
1534			clock-names = "ref";
1535			resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
1536
1537			#phy-cells = <0>;
1538
1539			status = "disabled";
1540		};
1541
1542		usb_0_qmpphy: phy@88e8000 {
1543			compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
1544			reg = <0 0x088e8000 0 0x2000>;
1545
1546			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1547				 <&gcc GCC_USB_CLKREF_EN>,
1548				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1549				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1550			clock-names = "aux", "ref", "com_aux", "pipe";
1551
1552			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1553				 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
1554			reset-names = "phy", "phy_phy";
1555
1556			power-domains = <&gcc USB30_PRIM_GDSC>;
1557
1558			#clock-cells = <0>;
1559			clock-output-names = "usb3_prim_phy_pipe_clk_src";
1560
1561			#phy-cells = <0>;
1562
1563			status = "disabled";
1564		};
1565
1566		usb_0: usb@a6f8800 {
1567			compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1568			reg = <0 0x0a6f8800 0 0x400>;
1569			#address-cells = <2>;
1570			#size-cells = <2>;
1571			ranges;
1572
1573			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1574				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1575				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1576				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1577				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1578			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1579
1580			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1581					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1582			assigned-clock-rates = <19200000>, <200000000>;
1583
1584			interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
1585					      <&pdc 14 IRQ_TYPE_EDGE_RISING>,
1586					      <&pdc 15 IRQ_TYPE_EDGE_RISING>,
1587					      <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
1588			interrupt-names = "pwr_event",
1589					  "dp_hs_phy_irq",
1590					  "dm_hs_phy_irq",
1591					  "ss_phy_irq";
1592
1593			power-domains = <&gcc USB30_PRIM_GDSC>;
1594			required-opps = <&rpmhpd_opp_nom>;
1595
1596			resets = <&gcc GCC_USB30_PRIM_BCR>;
1597
1598			interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1599					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1600			interconnect-names = "usb-ddr", "apps-usb";
1601
1602			wakeup-source;
1603
1604			status = "disabled";
1605
1606			usb_0_dwc3: usb@a600000 {
1607				compatible = "snps,dwc3";
1608				reg = <0 0x0a600000 0 0xe000>;
1609				interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1610				iommus = <&apps_smmu 0x080 0x0>;
1611				phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
1612				phy-names = "usb2-phy", "usb3-phy";
1613			};
1614		};
1615
1616		usb_1_hsphy: phy@88e6000 {
1617			compatible = "qcom,sa8775p-usb-hs-phy",
1618				     "qcom,usb-snps-hs-5nm-phy";
1619			reg = <0 0x088e6000 0 0x120>;
1620			clocks = <&gcc GCC_USB_CLKREF_EN>;
1621			clock-names = "ref";
1622			resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
1623
1624			#phy-cells = <0>;
1625
1626			status = "disabled";
1627		};
1628
1629		usb_1_qmpphy: phy@88ea000 {
1630			compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
1631			reg = <0 0x088ea000 0 0x2000>;
1632
1633			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1634				 <&gcc GCC_USB_CLKREF_EN>,
1635				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
1636				 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1637			clock-names = "aux", "ref", "com_aux", "pipe";
1638
1639			resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1640				 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
1641			reset-names = "phy", "phy_phy";
1642
1643			power-domains = <&gcc USB30_SEC_GDSC>;
1644
1645			#clock-cells = <0>;
1646			clock-output-names = "usb3_sec_phy_pipe_clk_src";
1647
1648			#phy-cells = <0>;
1649
1650			status = "disabled";
1651		};
1652
1653		usb_1: usb@a8f8800 {
1654			compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1655			reg = <0 0x0a8f8800 0 0x400>;
1656			#address-cells = <2>;
1657			#size-cells = <2>;
1658			ranges;
1659
1660			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1661				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1662				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1663				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1664				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
1665			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1666
1667			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1668					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
1669			assigned-clock-rates = <19200000>, <200000000>;
1670
1671			interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
1672					      <&pdc 8 IRQ_TYPE_EDGE_RISING>,
1673					      <&pdc 7 IRQ_TYPE_EDGE_RISING>,
1674					      <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
1675			interrupt-names = "pwr_event",
1676					  "dp_hs_phy_irq",
1677					  "dm_hs_phy_irq",
1678					  "ss_phy_irq";
1679
1680			power-domains = <&gcc USB30_SEC_GDSC>;
1681			required-opps = <&rpmhpd_opp_nom>;
1682
1683			resets = <&gcc GCC_USB30_SEC_BCR>;
1684
1685			interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1686					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1687			interconnect-names = "usb-ddr", "apps-usb";
1688
1689			wakeup-source;
1690
1691			status = "disabled";
1692
1693			usb_1_dwc3: usb@a800000 {
1694				compatible = "snps,dwc3";
1695				reg = <0 0x0a800000 0 0xe000>;
1696				interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
1697				iommus = <&apps_smmu 0x0a0 0x0>;
1698				phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
1699				phy-names = "usb2-phy", "usb3-phy";
1700			};
1701		};
1702
1703		usb_2_hsphy: phy@88e7000 {
1704			compatible = "qcom,sa8775p-usb-hs-phy",
1705				     "qcom,usb-snps-hs-5nm-phy";
1706			reg = <0 0x088e7000 0 0x120>;
1707			clocks = <&gcc GCC_USB_CLKREF_EN>;
1708			clock-names = "ref";
1709			resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
1710
1711			#phy-cells = <0>;
1712
1713			status = "disabled";
1714		};
1715
1716		usb_2: usb@a4f8800 {
1717			compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1718			reg = <0 0x0a4f8800 0 0x400>;
1719			#address-cells = <2>;
1720			#size-cells = <2>;
1721			ranges;
1722
1723			clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
1724				 <&gcc GCC_USB20_MASTER_CLK>,
1725				 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
1726				 <&gcc GCC_USB20_SLEEP_CLK>,
1727				 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1728			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1729
1730			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1731					  <&gcc GCC_USB20_MASTER_CLK>;
1732			assigned-clock-rates = <19200000>, <200000000>;
1733
1734			interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
1735					      <&pdc 10 IRQ_TYPE_EDGE_RISING>,
1736					      <&pdc 9 IRQ_TYPE_EDGE_RISING>;
1737			interrupt-names = "pwr_event",
1738					  "dp_hs_phy_irq",
1739					  "dm_hs_phy_irq";
1740
1741			power-domains = <&gcc USB20_PRIM_GDSC>;
1742			required-opps = <&rpmhpd_opp_nom>;
1743
1744			resets = <&gcc GCC_USB20_PRIM_BCR>;
1745
1746			interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
1747					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
1748			interconnect-names = "usb-ddr", "apps-usb";
1749
1750			wakeup-source;
1751
1752			status = "disabled";
1753
1754			usb_2_dwc3: usb@a400000 {
1755				compatible = "snps,dwc3";
1756				reg = <0 0x0a400000 0 0xe000>;
1757				interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
1758				iommus = <&apps_smmu 0x020 0x0>;
1759				phys = <&usb_2_hsphy>;
1760				phy-names = "usb2-phy";
1761			};
1762		};
1763
1764		tcsr_mutex: hwlock@1f40000 {
1765			compatible = "qcom,tcsr-mutex";
1766			reg = <0x0 0x01f40000 0x0 0x20000>;
1767			#hwlock-cells = <1>;
1768		};
1769
1770		gpucc: clock-controller@3d90000 {
1771			compatible = "qcom,sa8775p-gpucc";
1772			reg = <0x0 0x03d90000 0x0 0xa000>;
1773			clocks = <&rpmhcc RPMH_CXO_CLK>,
1774				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1775				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1776			clock-names = "bi_tcxo",
1777				      "gcc_gpu_gpll0_clk_src",
1778				      "gcc_gpu_gpll0_div_clk_src";
1779			#clock-cells = <1>;
1780			#reset-cells = <1>;
1781			#power-domain-cells = <1>;
1782		};
1783
1784		adreno_smmu: iommu@3da0000 {
1785			compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
1786				     "qcom,smmu-500", "arm,mmu-500";
1787			reg = <0x0 0x03da0000 0x0 0x20000>;
1788			#iommu-cells = <2>;
1789			#global-interrupts = <2>;
1790			dma-coherent;
1791			power-domains = <&gpucc GPU_CC_CX_GDSC>;
1792			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1793				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1794				 <&gpucc GPU_CC_AHB_CLK>,
1795				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1796				 <&gpucc GPU_CC_CX_GMU_CLK>,
1797				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1798				 <&gpucc GPU_CC_HUB_AON_CLK>;
1799			clock-names = "gcc_gpu_memnoc_gfx_clk",
1800				      "gcc_gpu_snoc_dvm_gfx_clk",
1801				      "gpu_cc_ahb_clk",
1802				      "gpu_cc_hlos1_vote_gpu_smmu_clk",
1803				      "gpu_cc_cx_gmu_clk",
1804				      "gpu_cc_hub_cx_int_clk",
1805				      "gpu_cc_hub_aon_clk";
1806			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1807				     <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
1808				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1809				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1810				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1811				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1812				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1813				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1814				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1815				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1816				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1817				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1818		};
1819
1820		pdc: interrupt-controller@b220000 {
1821			compatible = "qcom,sa8775p-pdc", "qcom,pdc";
1822			reg = <0x0 0x0b220000 0x0 0x30000>,
1823			      <0x0 0x17c000f0 0x0 0x64>;
1824			qcom,pdc-ranges = <0 480 40>,
1825					  <40 140 14>,
1826					  <54 263 1>,
1827					  <55 306 4>,
1828					  <59 312 3>,
1829					  <62 374 2>,
1830					  <64 434 2>,
1831					  <66 438 2>,
1832					  <70 520 1>,
1833					  <73 523 1>,
1834					  <118 568 6>,
1835					  <124 609 3>,
1836					  <159 638 1>,
1837					  <160 720 3>,
1838					  <169 728 30>,
1839					  <199 416 2>,
1840					  <201 449 1>,
1841					  <202 89 1>,
1842					  <203 451 1>,
1843					  <204 462 1>,
1844					  <205 264 1>,
1845					  <206 579 1>,
1846					  <207 653 1>,
1847					  <208 656 1>,
1848					  <209 659 1>,
1849					  <210 122 1>,
1850					  <211 699 1>,
1851					  <212 705 1>,
1852					  <213 450 1>,
1853					  <214 643 2>,
1854					  <216 646 5>,
1855					  <221 390 5>,
1856					  <226 700 2>,
1857					  <228 440 1>,
1858					  <229 663 1>,
1859					  <230 524 2>,
1860					  <232 612 3>,
1861					  <235 723 5>;
1862			#interrupt-cells = <2>;
1863			interrupt-parent = <&intc>;
1864			interrupt-controller;
1865		};
1866
1867		aoss_qmp: power-management@c300000 {
1868			compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
1869			reg = <0x0 0x0c300000 0x0 0x400>;
1870			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1871					       IPCC_MPROC_SIGNAL_GLINK_QMP
1872					       IRQ_TYPE_EDGE_RISING>;
1873			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1874			#clock-cells = <0>;
1875		};
1876
1877		spmi_bus: spmi@c440000 {
1878			compatible = "qcom,spmi-pmic-arb";
1879			reg = <0x0 0x0c440000 0x0 0x1100>,
1880			      <0x0 0x0c600000 0x0 0x2000000>,
1881			      <0x0 0x0e600000 0x0 0x100000>,
1882			      <0x0 0x0e700000 0x0 0xa0000>,
1883			      <0x0 0x0c40a000 0x0 0x26000>;
1884			reg-names = "core",
1885				    "chnls",
1886				    "obsrvr",
1887				    "intr",
1888				    "cnfg";
1889			qcom,channel = <0>;
1890			qcom,ee = <0>;
1891			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1892			interrupt-names = "periph_irq";
1893			interrupt-controller;
1894			#interrupt-cells = <4>;
1895			#address-cells = <2>;
1896			#size-cells = <0>;
1897		};
1898
1899		tlmm: pinctrl@f000000 {
1900			compatible = "qcom,sa8775p-tlmm";
1901			reg = <0x0 0x0f000000 0x0 0x1000000>;
1902			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1903			gpio-controller;
1904			#gpio-cells = <2>;
1905			interrupt-controller;
1906			#interrupt-cells = <2>;
1907			gpio-ranges = <&tlmm 0 0 149>;
1908		};
1909
1910		apps_smmu: iommu@15000000 {
1911			compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1912			reg = <0x0 0x15000000 0x0 0x100000>;
1913			#iommu-cells = <2>;
1914			#global-interrupts = <2>;
1915
1916			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1917				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1918				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1919				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1920				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1921				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1922				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1923				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1924				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1925				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1926				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1927				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1928				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1929				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1930				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1931				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1932				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1933				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1934				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1935				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1936				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1937				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1938				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1939				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1940				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1941				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1942				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1943				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1944				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1945				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1946				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1947				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1948				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1949				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1950				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1951				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1952				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1953				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1954				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1955				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1956				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1957				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1958				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1959				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1960				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1961				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1962				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1963				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1964				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1965				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1966				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1967				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1968				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1969				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1970				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1971				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1972				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1973				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1974				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1975				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1976				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1977				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1978				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1979				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1980				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1981				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1982				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1983				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1984				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1985				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1986				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1987				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1988				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1989				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1990				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1991				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1992				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1993				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1994				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1995				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1996				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1997				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
1998				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1999				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2000				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2001				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
2002				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2003				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2004				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2005				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2006				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2007				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2008				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2009				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2010				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2011				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2012				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2013				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2014				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2015				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
2016				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
2017				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
2018				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
2019				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2020				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
2021				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
2022				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
2023				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
2024				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
2025				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
2026				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
2027				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
2028				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
2029				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
2030				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
2031				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
2032				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
2033				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
2034				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
2035				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
2036				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
2037				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
2038				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
2039				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
2040				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
2041				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
2042				     <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
2043				     <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
2044				     <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
2045				     <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
2046		};
2047
2048		pcie_smmu: iommu@15200000 {
2049			compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2050			reg = <0x0 0x15200000 0x0 0x80000>;
2051			#iommu-cells = <2>;
2052			#global-interrupts = <2>;
2053
2054			interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
2055				     <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
2056				     <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
2057				     <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
2058				     <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
2059				     <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
2060				     <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
2061				     <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
2062				     <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
2063				     <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
2064				     <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
2065				     <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
2066				     <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
2067				     <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
2068				     <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
2069				     <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
2070				     <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
2071				     <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
2072				     <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
2073				     <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
2074				     <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
2075				     <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
2076				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
2077				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
2078				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
2079				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
2080				     <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
2081				     <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
2082				     <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
2083				     <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
2084				     <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
2085				     <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
2086				     <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
2087				     <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
2088				     <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
2089				     <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
2090				     <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
2091				     <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
2092				     <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
2093				     <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
2094				     <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
2095				     <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
2096				     <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
2097				     <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
2098				     <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
2099				     <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
2100				     <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
2101				     <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
2102				     <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
2103				     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
2104				     <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
2105				     <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
2106				     <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
2107				     <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
2108				     <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
2109				     <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
2110				     <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
2111				     <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
2112				     <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
2113				     <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
2114				     <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
2115				     <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
2116				     <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
2117				     <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
2118				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
2119				     <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
2120		};
2121
2122		intc: interrupt-controller@17a00000 {
2123			compatible = "arm,gic-v3";
2124			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2125			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2126			interrupt-controller;
2127			#interrupt-cells = <3>;
2128			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2129			#redistributor-regions = <1>;
2130			redistributor-stride = <0x0 0x20000>;
2131		};
2132
2133		watchdog@17c10000 {
2134			compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
2135			reg = <0x0 0x17c10000 0x0 0x1000>;
2136			clocks = <&sleep_clk>;
2137			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2138		};
2139
2140		memtimer: timer@17c20000 {
2141			compatible = "arm,armv7-timer-mem";
2142			reg = <0x0 0x17c20000 0x0 0x1000>;
2143			ranges = <0x0 0x0 0x0 0x20000000>;
2144			#address-cells = <1>;
2145			#size-cells = <1>;
2146
2147			frame@17c21000 {
2148				reg = <0x17c21000 0x1000>,
2149				      <0x17c22000 0x1000>;
2150				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2151					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2152				frame-number = <0>;
2153			};
2154
2155			frame@17c23000 {
2156				reg = <0x17c23000 0x1000>;
2157				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2158				frame-number = <1>;
2159				status = "disabled";
2160			};
2161
2162			frame@17c25000 {
2163				reg = <0x17c25000 0x1000>;
2164				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2165				frame-number = <2>;
2166				status = "disabled";
2167			};
2168
2169			frame@17c27000 {
2170				reg = <0x17c27000 0x1000>;
2171				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2172				frame-number = <3>;
2173				status = "disabled";
2174			};
2175
2176			frame@17c29000 {
2177				reg = <0x17c29000 0x1000>;
2178				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2179				frame-number = <4>;
2180				status = "disabled";
2181			};
2182
2183			frame@17c2b000 {
2184				reg = <0x17c2b000 0x1000>;
2185				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2186				frame-number = <5>;
2187				status = "disabled";
2188			};
2189
2190			frame@17c2d000 {
2191				reg = <0x17c2d000 0x1000>;
2192				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2193				frame-number = <6>;
2194				status = "disabled";
2195			};
2196		};
2197
2198		apps_rsc: rsc@18200000 {
2199			compatible = "qcom,rpmh-rsc";
2200			reg = <0x0 0x18200000 0x0 0x10000>,
2201			      <0x0 0x18210000 0x0 0x10000>,
2202			      <0x0 0x18220000 0x0 0x10000>;
2203			reg-names = "drv-0", "drv-1", "drv-2";
2204			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2205			      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2206			      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2207			qcom,tcs-offset = <0xd00>;
2208			qcom,drv-id = <2>;
2209			qcom,tcs-config = <ACTIVE_TCS 2>,
2210					  <SLEEP_TCS 3>,
2211					  <WAKE_TCS 3>,
2212					  <CONTROL_TCS 0>;
2213			label = "apps_rsc";
2214
2215			apps_bcm_voter: bcm-voter {
2216				compatible = "qcom,bcm-voter";
2217			};
2218
2219			rpmhcc: clock-controller {
2220				compatible = "qcom,sa8775p-rpmh-clk";
2221				#clock-cells = <1>;
2222				clock-names = "xo";
2223				clocks = <&xo_board_clk>;
2224			};
2225
2226			rpmhpd: power-controller {
2227				compatible = "qcom,sa8775p-rpmhpd";
2228				#power-domain-cells = <1>;
2229				operating-points-v2 = <&rpmhpd_opp_table>;
2230
2231				rpmhpd_opp_table: opp-table {
2232					compatible = "operating-points-v2";
2233
2234					rpmhpd_opp_ret: opp-0 {
2235						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2236					};
2237
2238					rpmhpd_opp_min_svs: opp-1 {
2239						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2240					};
2241
2242					rpmhpd_opp_low_svs: opp2 {
2243						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2244					};
2245
2246					rpmhpd_opp_svs: opp3 {
2247						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2248					};
2249
2250					rpmhpd_opp_svs_l1: opp-4 {
2251						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2252					};
2253
2254					rpmhpd_opp_nom: opp-5 {
2255						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2256					};
2257
2258					rpmhpd_opp_nom_l1: opp-6 {
2259						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2260					};
2261
2262					rpmhpd_opp_nom_l2: opp-7 {
2263						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2264					};
2265
2266					rpmhpd_opp_turbo: opp-8 {
2267						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2268					};
2269
2270					rpmhpd_opp_turbo_l1: opp-9 {
2271						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2272					};
2273				};
2274			};
2275		};
2276
2277		cpufreq_hw: cpufreq@18591000 {
2278			compatible = "qcom,sa8775p-cpufreq-epss",
2279				     "qcom,cpufreq-epss";
2280			reg = <0x0 0x18591000 0x0 0x1000>,
2281			      <0x0 0x18593000 0x0 0x1000>;
2282			reg-names = "freq-domain0", "freq-domain1";
2283
2284			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2285			clock-names = "xo", "alternate";
2286
2287			#freq-domain-cells = <1>;
2288		};
2289	};
2290
2291	arch_timer: timer {
2292		compatible = "arm,armv8-timer";
2293		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2294			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2295			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2296			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2297	};
2298};
2299