1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-qcs404.h> 8#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32768>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x100>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 next-level-cache = <&L2_0>; 46 #cooling-cells = <2>; 47 clocks = <&apcs_glb>; 48 operating-points-v2 = <&cpu_opp_table>; 49 power-domains = <&cpr>; 50 power-domain-names = "cpr"; 51 }; 52 53 CPU1: cpu@101 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x101>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 next-level-cache = <&L2_0>; 60 #cooling-cells = <2>; 61 clocks = <&apcs_glb>; 62 operating-points-v2 = <&cpu_opp_table>; 63 power-domains = <&cpr>; 64 power-domain-names = "cpr"; 65 }; 66 67 CPU2: cpu@102 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x102>; 71 enable-method = "psci"; 72 cpu-idle-states = <&CPU_SLEEP_0>; 73 next-level-cache = <&L2_0>; 74 #cooling-cells = <2>; 75 clocks = <&apcs_glb>; 76 operating-points-v2 = <&cpu_opp_table>; 77 power-domains = <&cpr>; 78 power-domain-names = "cpr"; 79 }; 80 81 CPU3: cpu@103 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x103>; 85 enable-method = "psci"; 86 cpu-idle-states = <&CPU_SLEEP_0>; 87 next-level-cache = <&L2_0>; 88 #cooling-cells = <2>; 89 clocks = <&apcs_glb>; 90 operating-points-v2 = <&cpu_opp_table>; 91 power-domains = <&cpr>; 92 power-domain-names = "cpr"; 93 }; 94 95 L2_0: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 }; 99 100 idle-states { 101 entry-method = "psci"; 102 103 CPU_SLEEP_0: cpu-sleep-0 { 104 compatible = "arm,idle-state"; 105 idle-state-name = "standalone-power-collapse"; 106 arm,psci-suspend-param = <0x40000003>; 107 entry-latency-us = <125>; 108 exit-latency-us = <180>; 109 min-residency-us = <595>; 110 local-timer-stop; 111 }; 112 }; 113 }; 114 115 cpu_opp_table: opp-table-cpu { 116 compatible = "operating-points-v2-kryo-cpu"; 117 opp-shared; 118 119 opp-1094400000 { 120 opp-hz = /bits/ 64 <1094400000>; 121 required-opps = <&cpr_opp1>; 122 }; 123 opp-1248000000 { 124 opp-hz = /bits/ 64 <1248000000>; 125 required-opps = <&cpr_opp2>; 126 }; 127 opp-1401600000 { 128 opp-hz = /bits/ 64 <1401600000>; 129 required-opps = <&cpr_opp3>; 130 }; 131 }; 132 133 cpr_opp_table: opp-table-cpr { 134 compatible = "operating-points-v2-qcom-level"; 135 136 cpr_opp1: opp1 { 137 opp-level = <1>; 138 qcom,opp-fuse-level = <1>; 139 }; 140 cpr_opp2: opp2 { 141 opp-level = <2>; 142 qcom,opp-fuse-level = <2>; 143 }; 144 cpr_opp3: opp3 { 145 opp-level = <3>; 146 qcom,opp-fuse-level = <3>; 147 }; 148 }; 149 150 firmware { 151 scm: scm { 152 compatible = "qcom,scm-qcs404", "qcom,scm"; 153 #reset-cells = <1>; 154 }; 155 }; 156 157 memory@80000000 { 158 device_type = "memory"; 159 /* We expect the bootloader to fill in the size */ 160 reg = <0 0x80000000 0 0>; 161 }; 162 163 psci { 164 compatible = "arm,psci-1.0"; 165 method = "smc"; 166 }; 167 168 reserved-memory { 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 173 tz_apps_mem: memory@85900000 { 174 reg = <0 0x85900000 0 0x500000>; 175 no-map; 176 }; 177 178 xbl_mem: memory@85e00000 { 179 reg = <0 0x85e00000 0 0x100000>; 180 no-map; 181 }; 182 183 smem_region: memory@85f00000 { 184 reg = <0 0x85f00000 0 0x200000>; 185 no-map; 186 }; 187 188 tz_mem: memory@86100000 { 189 reg = <0 0x86100000 0 0x300000>; 190 no-map; 191 }; 192 193 wlan_fw_mem: memory@86400000 { 194 reg = <0 0x86400000 0 0x1100000>; 195 no-map; 196 }; 197 198 adsp_fw_mem: memory@87500000 { 199 reg = <0 0x87500000 0 0x1a00000>; 200 no-map; 201 }; 202 203 cdsp_fw_mem: memory@88f00000 { 204 reg = <0 0x88f00000 0 0x600000>; 205 no-map; 206 }; 207 208 wlan_msa_mem: memory@89500000 { 209 reg = <0 0x89500000 0 0x100000>; 210 no-map; 211 }; 212 213 uefi_mem: memory@9f800000 { 214 reg = <0 0x9f800000 0 0x800000>; 215 no-map; 216 }; 217 }; 218 219 rpm-glink { 220 compatible = "qcom,glink-rpm"; 221 222 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 223 qcom,rpm-msg-ram = <&rpm_msg_ram>; 224 mboxes = <&apcs_glb 0>; 225 226 rpm_requests: rpm-requests { 227 compatible = "qcom,rpm-qcs404"; 228 qcom,glink-channels = "rpm_requests"; 229 230 rpmcc: clock-controller { 231 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; 232 #clock-cells = <1>; 233 clocks = <&xo_board>; 234 clock-names = "xo"; 235 }; 236 237 rpmpd: power-controller { 238 compatible = "qcom,qcs404-rpmpd"; 239 #power-domain-cells = <1>; 240 operating-points-v2 = <&rpmpd_opp_table>; 241 242 rpmpd_opp_table: opp-table { 243 compatible = "operating-points-v2"; 244 245 rpmpd_opp_ret: opp1 { 246 opp-level = <16>; 247 }; 248 249 rpmpd_opp_ret_plus: opp2 { 250 opp-level = <32>; 251 }; 252 253 rpmpd_opp_min_svs: opp3 { 254 opp-level = <48>; 255 }; 256 257 rpmpd_opp_low_svs: opp4 { 258 opp-level = <64>; 259 }; 260 261 rpmpd_opp_svs: opp5 { 262 opp-level = <128>; 263 }; 264 265 rpmpd_opp_svs_plus: opp6 { 266 opp-level = <192>; 267 }; 268 269 rpmpd_opp_nom: opp7 { 270 opp-level = <256>; 271 }; 272 273 rpmpd_opp_nom_plus: opp8 { 274 opp-level = <320>; 275 }; 276 277 rpmpd_opp_turbo: opp9 { 278 opp-level = <384>; 279 }; 280 281 rpmpd_opp_turbo_no_cpr: opp10 { 282 opp-level = <416>; 283 }; 284 285 rpmpd_opp_turbo_plus: opp11 { 286 opp-level = <512>; 287 }; 288 }; 289 }; 290 }; 291 }; 292 293 smem { 294 compatible = "qcom,smem"; 295 296 memory-region = <&smem_region>; 297 qcom,rpm-msg-ram = <&rpm_msg_ram>; 298 299 hwlocks = <&tcsr_mutex 3>; 300 }; 301 302 soc: soc@0 { 303 #address-cells = <1>; 304 #size-cells = <1>; 305 ranges = <0 0 0 0xffffffff>; 306 compatible = "simple-bus"; 307 308 turingcc: clock-controller@800000 { 309 compatible = "qcom,qcs404-turingcc"; 310 reg = <0x00800000 0x30000>; 311 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 312 313 #clock-cells = <1>; 314 #reset-cells = <1>; 315 316 status = "disabled"; 317 }; 318 319 rpm_msg_ram: sram@60000 { 320 compatible = "qcom,rpm-msg-ram"; 321 reg = <0x00060000 0x6000>; 322 }; 323 324 usb3_phy: phy@78000 { 325 compatible = "qcom,usb-ss-28nm-phy"; 326 reg = <0x00078000 0x400>; 327 #phy-cells = <0>; 328 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 329 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 330 <&gcc GCC_USB3_PHY_PIPE_CLK>; 331 clock-names = "ref", "ahb", "pipe"; 332 resets = <&gcc GCC_USB3_PHY_BCR>, 333 <&gcc GCC_USB3PHY_PHY_BCR>; 334 reset-names = "com", "phy"; 335 status = "disabled"; 336 }; 337 338 usb2_phy_prim: phy@7a000 { 339 compatible = "qcom,usb-hs-28nm-femtophy"; 340 reg = <0x0007a000 0x200>; 341 #phy-cells = <0>; 342 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 343 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 344 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 345 clock-names = "ref", "ahb", "sleep"; 346 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 347 <&gcc GCC_USB2A_PHY_BCR>; 348 reset-names = "phy", "por"; 349 status = "disabled"; 350 }; 351 352 usb2_phy_sec: phy@7c000 { 353 compatible = "qcom,usb-hs-28nm-femtophy"; 354 reg = <0x0007c000 0x200>; 355 #phy-cells = <0>; 356 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 357 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 358 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 359 clock-names = "ref", "ahb", "sleep"; 360 resets = <&gcc GCC_QUSB2_PHY_BCR>, 361 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 362 reset-names = "phy", "por"; 363 status = "disabled"; 364 }; 365 366 qfprom: qfprom@a4000 { 367 compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; 368 reg = <0x000a4000 0x1000>; 369 #address-cells = <1>; 370 #size-cells = <1>; 371 cpr_efuse_speedbin: speedbin@13c { 372 reg = <0x13c 0x4>; 373 bits = <2 3>; 374 }; 375 376 tsens_s0_p1: s0-p1@1f8 { 377 reg = <0x1f8 0x1>; 378 bits = <0 6>; 379 }; 380 381 tsens_s0_p2: s0-p2@1f8 { 382 reg = <0x1f8 0x2>; 383 bits = <6 6>; 384 }; 385 386 tsens_s1_p1: s1-p1@1f9 { 387 reg = <0x1f9 0x2>; 388 bits = <4 6>; 389 }; 390 391 tsens_s1_p2: s1-p2@1fa { 392 reg = <0x1fa 0x1>; 393 bits = <2 6>; 394 }; 395 396 tsens_s2_p1: s2-p1@1fb { 397 reg = <0x1fb 0x1>; 398 bits = <0 6>; 399 }; 400 401 tsens_s2_p2: s2-p2@1fb { 402 reg = <0x1fb 0x2>; 403 bits = <6 6>; 404 }; 405 406 tsens_s3_p1: s3-p1@1fc { 407 reg = <0x1fc 0x2>; 408 bits = <4 6>; 409 }; 410 411 tsens_s3_p2: s3-p2@1fd { 412 reg = <0x1fd 0x1>; 413 bits = <2 6>; 414 }; 415 416 tsens_s4_p1: s4-p1@1fe { 417 reg = <0x1fe 0x1>; 418 bits = <0 6>; 419 }; 420 421 tsens_s4_p2: s4-p2@1fe { 422 reg = <0x1fe 0x2>; 423 bits = <6 6>; 424 }; 425 426 tsens_s5_p1: s5-p1@200 { 427 reg = <0x200 0x1>; 428 bits = <0 6>; 429 }; 430 431 tsens_s5_p2: s5-p2@200 { 432 reg = <0x200 0x2>; 433 bits = <6 6>; 434 }; 435 436 tsens_s6_p1: s6-p1@201 { 437 reg = <0x201 0x2>; 438 bits = <4 6>; 439 }; 440 441 tsens_s6_p2: s6-p2@202 { 442 reg = <0x202 0x1>; 443 bits = <2 6>; 444 }; 445 446 tsens_s7_p1: s7-p1@203 { 447 reg = <0x203 0x1>; 448 bits = <0 6>; 449 }; 450 451 tsens_s7_p2: s7-p2@203 { 452 reg = <0x203 0x2>; 453 bits = <6 6>; 454 }; 455 456 tsens_s8_p1: s8-p1@204 { 457 reg = <0x204 0x2>; 458 bits = <4 6>; 459 }; 460 461 tsens_s8_p2: s8-p2@205 { 462 reg = <0x205 0x1>; 463 bits = <2 6>; 464 }; 465 466 tsens_s9_p1: s9-p1@206 { 467 reg = <0x206 0x1>; 468 bits = <0 6>; 469 }; 470 471 tsens_s9_p2: s9-p2@206 { 472 reg = <0x206 0x2>; 473 bits = <6 6>; 474 }; 475 476 tsens_mode: mode@208 { 477 reg = <0x208 1>; 478 bits = <0 3>; 479 }; 480 481 tsens_base1: base1@208 { 482 reg = <0x208 2>; 483 bits = <3 8>; 484 }; 485 486 tsens_base2: base2@208 { 487 reg = <0x209 2>; 488 bits = <3 8>; 489 }; 490 491 cpr_efuse_quot_offset1: qoffset1@231 { 492 reg = <0x231 0x4>; 493 bits = <4 7>; 494 }; 495 cpr_efuse_quot_offset2: qoffset2@232 { 496 reg = <0x232 0x4>; 497 bits = <3 7>; 498 }; 499 cpr_efuse_quot_offset3: qoffset3@233 { 500 reg = <0x233 0x4>; 501 bits = <2 7>; 502 }; 503 cpr_efuse_init_voltage1: ivoltage1@229 { 504 reg = <0x229 0x4>; 505 bits = <4 6>; 506 }; 507 cpr_efuse_init_voltage2: ivoltage2@22a { 508 reg = <0x22a 0x4>; 509 bits = <2 6>; 510 }; 511 cpr_efuse_init_voltage3: ivoltage3@22b { 512 reg = <0x22b 0x4>; 513 bits = <0 6>; 514 }; 515 cpr_efuse_quot1: quot1@22b { 516 reg = <0x22b 0x4>; 517 bits = <6 12>; 518 }; 519 cpr_efuse_quot2: quot2@22d { 520 reg = <0x22d 0x4>; 521 bits = <2 12>; 522 }; 523 cpr_efuse_quot3: quot3@230 { 524 reg = <0x230 0x4>; 525 bits = <0 12>; 526 }; 527 cpr_efuse_ring1: ring1@228 { 528 reg = <0x228 0x4>; 529 bits = <0 3>; 530 }; 531 cpr_efuse_ring2: ring2@228 { 532 reg = <0x228 0x4>; 533 bits = <4 3>; 534 }; 535 cpr_efuse_ring3: ring3@229 { 536 reg = <0x229 0x4>; 537 bits = <0 3>; 538 }; 539 cpr_efuse_revision: revision@218 { 540 reg = <0x218 0x4>; 541 bits = <3 3>; 542 }; 543 }; 544 545 rng: rng@e3000 { 546 compatible = "qcom,prng-ee"; 547 reg = <0x000e3000 0x1000>; 548 clocks = <&gcc GCC_PRNG_AHB_CLK>; 549 clock-names = "core"; 550 }; 551 552 bimc: interconnect@400000 { 553 reg = <0x00400000 0x80000>; 554 compatible = "qcom,qcs404-bimc"; 555 #interconnect-cells = <1>; 556 clock-names = "bus", "bus_a"; 557 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 558 <&rpmcc RPM_SMD_BIMC_A_CLK>; 559 }; 560 561 tsens: thermal-sensor@4a9000 { 562 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 563 reg = <0x004a9000 0x1000>, /* TM */ 564 <0x004a8000 0x1000>; /* SROT */ 565 nvmem-cells = <&tsens_mode>, 566 <&tsens_base1>, <&tsens_base2>, 567 <&tsens_s0_p1>, <&tsens_s0_p2>, 568 <&tsens_s1_p1>, <&tsens_s1_p2>, 569 <&tsens_s2_p1>, <&tsens_s2_p2>, 570 <&tsens_s3_p1>, <&tsens_s3_p2>, 571 <&tsens_s4_p1>, <&tsens_s4_p2>, 572 <&tsens_s5_p1>, <&tsens_s5_p2>, 573 <&tsens_s6_p1>, <&tsens_s6_p2>, 574 <&tsens_s7_p1>, <&tsens_s7_p2>, 575 <&tsens_s8_p1>, <&tsens_s8_p2>, 576 <&tsens_s9_p1>, <&tsens_s9_p2>; 577 nvmem-cell-names = "mode", 578 "base1", "base2", 579 "s0_p1", "s0_p2", 580 "s1_p1", "s1_p2", 581 "s2_p1", "s2_p2", 582 "s3_p1", "s3_p2", 583 "s4_p1", "s4_p2", 584 "s5_p1", "s5_p2", 585 "s6_p1", "s6_p2", 586 "s7_p1", "s7_p2", 587 "s8_p1", "s8_p2", 588 "s9_p1", "s9_p2"; 589 #qcom,sensors = <10>; 590 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "uplow"; 592 #thermal-sensor-cells = <1>; 593 }; 594 595 pcnoc: interconnect@500000 { 596 reg = <0x00500000 0x15080>; 597 compatible = "qcom,qcs404-pcnoc"; 598 #interconnect-cells = <1>; 599 clock-names = "bus", "bus_a"; 600 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 601 <&rpmcc RPM_SMD_PNOC_A_CLK>; 602 }; 603 604 snoc: interconnect@580000 { 605 reg = <0x00580000 0x23080>; 606 compatible = "qcom,qcs404-snoc"; 607 #interconnect-cells = <1>; 608 clock-names = "bus", "bus_a"; 609 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 610 <&rpmcc RPM_SMD_SNOC_A_CLK>; 611 }; 612 613 remoteproc_cdsp: remoteproc@b00000 { 614 compatible = "qcom,qcs404-cdsp-pas"; 615 reg = <0x00b00000 0x4040>; 616 617 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 618 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 619 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 620 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 621 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 622 interrupt-names = "wdog", "fatal", "ready", 623 "handover", "stop-ack"; 624 625 clocks = <&xo_board>; 626 clock-names = "xo"; 627 628 /* 629 * If the node was using the PIL binding, then include properties: 630 * clocks = <&xo_board>, 631 * <&gcc GCC_CDSP_CFG_AHB_CLK>, 632 * <&gcc GCC_CDSP_TBU_CLK>, 633 * <&gcc GCC_BIMC_CDSP_CLK>, 634 * <&turingcc TURING_WRAPPER_AON_CLK>, 635 * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 636 * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 637 * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 638 * clock-names = "xo", 639 * "sway", 640 * "tbu", 641 * "bimc", 642 * "ahb_aon", 643 * "q6ss_slave", 644 * "q6ss_master", 645 * "q6_axim"; 646 * resets = <&gcc GCC_CDSP_RESTART>; 647 * reset-names = "restart"; 648 * qcom,halt-regs = <&tcsr 0x19004>; 649 */ 650 651 memory-region = <&cdsp_fw_mem>; 652 653 qcom,smem-states = <&cdsp_smp2p_out 0>; 654 qcom,smem-state-names = "stop"; 655 656 status = "disabled"; 657 658 glink-edge { 659 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 660 661 qcom,remote-pid = <5>; 662 mboxes = <&apcs_glb 12>; 663 664 label = "cdsp"; 665 }; 666 }; 667 668 usb3: usb@7678800 { 669 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 670 reg = <0x07678800 0x400>; 671 #address-cells = <1>; 672 #size-cells = <1>; 673 ranges; 674 clocks = <&gcc GCC_USB30_MASTER_CLK>, 675 <&gcc GCC_SYS_NOC_USB3_CLK>, 676 <&gcc GCC_USB30_SLEEP_CLK>, 677 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 678 clock-names = "core", "iface", "sleep", "mock_utmi"; 679 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 680 <&gcc GCC_USB30_MASTER_CLK>; 681 assigned-clock-rates = <19200000>, <200000000>; 682 status = "disabled"; 683 684 usb3_dwc3: usb@7580000 { 685 compatible = "snps,dwc3"; 686 reg = <0x07580000 0xcd00>; 687 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 688 phys = <&usb2_phy_prim>, <&usb3_phy>; 689 phy-names = "usb2-phy", "usb3-phy"; 690 snps,has-lpm-erratum; 691 snps,hird-threshold = /bits/ 8 <0x10>; 692 snps,usb3_lpm_capable; 693 dr_mode = "otg"; 694 }; 695 }; 696 697 usb2: usb@79b8800 { 698 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 699 reg = <0x079b8800 0x400>; 700 #address-cells = <1>; 701 #size-cells = <1>; 702 ranges; 703 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, 704 <&gcc GCC_PCNOC_USB2_CLK>, 705 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, 706 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 707 clock-names = "core", "iface", "sleep", "mock_utmi"; 708 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 709 <&gcc GCC_USB_HS_SYSTEM_CLK>; 710 assigned-clock-rates = <19200000>, <133333333>; 711 status = "disabled"; 712 713 usb@78c0000 { 714 compatible = "snps,dwc3"; 715 reg = <0x078c0000 0xcc00>; 716 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 717 phys = <&usb2_phy_sec>; 718 phy-names = "usb2-phy"; 719 snps,has-lpm-erratum; 720 snps,hird-threshold = /bits/ 8 <0x10>; 721 snps,usb3_lpm_capable; 722 dr_mode = "peripheral"; 723 }; 724 }; 725 726 tlmm: pinctrl@1000000 { 727 compatible = "qcom,qcs404-pinctrl"; 728 reg = <0x01000000 0x200000>, 729 <0x01300000 0x200000>, 730 <0x07b00000 0x200000>; 731 reg-names = "south", "north", "east"; 732 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 733 gpio-ranges = <&tlmm 0 0 120>; 734 gpio-controller; 735 #gpio-cells = <2>; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 739 blsp1_i2c0_default: blsp1-i2c0-default-state { 740 pins = "gpio32", "gpio33"; 741 function = "blsp_i2c0"; 742 }; 743 744 blsp1_i2c1_default: blsp1-i2c1-default-state { 745 pins = "gpio24", "gpio25"; 746 function = "blsp_i2c1"; 747 }; 748 749 blsp1_i2c2_default: blsp1-i2c2-default-state { 750 sda-pins { 751 pins = "gpio19"; 752 function = "blsp_i2c_sda_a2"; 753 }; 754 755 scl-pins { 756 pins = "gpio20"; 757 function = "blsp_i2c_scl_a2"; 758 }; 759 }; 760 761 blsp1_i2c3_default: blsp1-i2c3-default-state { 762 pins = "gpio84", "gpio85"; 763 function = "blsp_i2c3"; 764 }; 765 766 blsp1_i2c4_default: blsp1-i2c4-default-state { 767 pins = "gpio117", "gpio118"; 768 function = "blsp_i2c4"; 769 }; 770 771 blsp1_uart0_default: blsp1-uart0-default-state { 772 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 773 function = "blsp_uart0"; 774 }; 775 776 blsp1_uart1_default: blsp1-uart1-default-state { 777 pins = "gpio22", "gpio23"; 778 function = "blsp_uart1"; 779 }; 780 781 blsp1_uart2_default: blsp1-uart2-default-state { 782 rx-pins { 783 pins = "gpio18"; 784 function = "blsp_uart_rx_a2"; 785 }; 786 787 tx-pins { 788 pins = "gpio17"; 789 function = "blsp_uart_tx_a2"; 790 }; 791 }; 792 793 blsp1_uart3_default: blsp1-uart3-default-state { 794 cts-pins { 795 pins = "gpio84"; 796 function = "blsp_uart3"; 797 }; 798 799 rts-tx-pins { 800 pins = "gpio85", "gpio82"; 801 function = "blsp_uart3"; 802 }; 803 804 rx-pins { 805 pins = "gpio83"; 806 function = "blsp_uart3"; 807 }; 808 }; 809 810 blsp2_i2c0_default: blsp2-i2c0-default-state { 811 pins = "gpio28", "gpio29"; 812 function = "blsp_i2c5"; 813 }; 814 815 blsp1_spi0_default: blsp1-spi0-default-state { 816 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 817 function = "blsp_spi0"; 818 }; 819 820 blsp1_spi1_default: blsp1-spi1-default-state { 821 mosi-pins { 822 pins = "gpio22"; 823 function = "blsp_spi_mosi_a1"; 824 }; 825 826 miso-pins { 827 pins = "gpio23"; 828 function = "blsp_spi_miso_a1"; 829 }; 830 831 cs-n-pins { 832 pins = "gpio24"; 833 function = "blsp_spi_cs_n_a1"; 834 }; 835 836 clk-pins { 837 pins = "gpio25"; 838 function = "blsp_spi_clk_a1"; 839 }; 840 }; 841 842 blsp1_spi2_default: blsp1-spi2-default-state { 843 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 844 function = "blsp_spi2"; 845 }; 846 847 blsp1_spi3_default: blsp1-spi3-default-state { 848 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 849 function = "blsp_spi3"; 850 }; 851 852 blsp1_spi4_default: blsp1-spi4-default-state { 853 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 854 function = "blsp_spi4"; 855 }; 856 857 blsp2_spi0_default: blsp2-spi0-default-state { 858 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 859 function = "blsp_spi5"; 860 }; 861 862 blsp2_uart0_default: blsp2-uart0-default-state { 863 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 864 function = "blsp_uart5"; 865 }; 866 }; 867 868 gcc: clock-controller@1800000 { 869 compatible = "qcom,gcc-qcs404"; 870 reg = <0x01800000 0x80000>; 871 #clock-cells = <1>; 872 #reset-cells = <1>; 873 #power-domain-cells = <1>; 874 875 clocks = <&xo_board>, 876 <&sleep_clk>, 877 <&pcie_phy>, 878 <0>, 879 <0>, 880 <0>; 881 882 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 883 assigned-clock-rates = <19200000>; 884 }; 885 886 tcsr_mutex: hwlock@1905000 { 887 compatible = "qcom,tcsr-mutex"; 888 reg = <0x01905000 0x20000>; 889 #hwlock-cells = <1>; 890 }; 891 892 tcsr: syscon@1937000 { 893 compatible = "qcom,qcs404-tcsr", "syscon"; 894 reg = <0x01937000 0x25000>; 895 }; 896 897 sram@290000 { 898 compatible = "qcom,rpm-stats"; 899 reg = <0x00290000 0x10000>; 900 }; 901 902 spmi_bus: spmi@200f000 { 903 compatible = "qcom,spmi-pmic-arb"; 904 reg = <0x0200f000 0x001000>, 905 <0x02400000 0x800000>, 906 <0x02c00000 0x800000>, 907 <0x03800000 0x200000>, 908 <0x0200a000 0x002100>; 909 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 910 interrupt-names = "periph_irq"; 911 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 912 qcom,ee = <0>; 913 qcom,channel = <0>; 914 #address-cells = <2>; 915 #size-cells = <0>; 916 interrupt-controller; 917 #interrupt-cells = <4>; 918 }; 919 920 remoteproc_wcss: remoteproc@7400000 { 921 compatible = "qcom,qcs404-wcss-pas"; 922 reg = <0x07400000 0x4040>; 923 924 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 925 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 926 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 927 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 928 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 929 interrupt-names = "wdog", "fatal", "ready", 930 "handover", "stop-ack"; 931 932 clocks = <&xo_board>; 933 clock-names = "xo"; 934 935 memory-region = <&wlan_fw_mem>; 936 937 qcom,smem-states = <&wcss_smp2p_out 0>; 938 qcom,smem-state-names = "stop"; 939 940 status = "disabled"; 941 942 glink-edge { 943 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 944 945 qcom,remote-pid = <1>; 946 mboxes = <&apcs_glb 16>; 947 948 label = "wcss"; 949 }; 950 }; 951 952 pcie_phy: phy@7786000 { 953 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 954 reg = <0x07786000 0xb8>; 955 956 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 957 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 958 <&gcc GCC_PCIE_0_PIPE_ARES>; 959 reset-names = "phy", "pipe"; 960 961 clock-output-names = "pcie_0_pipe_clk"; 962 #clock-cells = <0>; 963 #phy-cells = <0>; 964 965 status = "disabled"; 966 }; 967 968 sdcc1: mmc@7804000 { 969 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 970 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 971 reg-names = "hc", "cqhci"; 972 973 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 975 interrupt-names = "hc_irq", "pwr_irq"; 976 977 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 978 <&gcc GCC_SDCC1_APPS_CLK>, 979 <&xo_board>; 980 clock-names = "iface", "core", "xo"; 981 982 status = "disabled"; 983 }; 984 985 blsp1_dma: dma-controller@7884000 { 986 compatible = "qcom,bam-v1.7.0"; 987 reg = <0x07884000 0x25000>; 988 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 990 clock-names = "bam_clk"; 991 #dma-cells = <1>; 992 qcom,ee = <0>; 993 status = "okay"; 994 }; 995 996 blsp1_uart0: serial@78af000 { 997 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 998 reg = <0x078af000 0x200>; 999 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1001 clock-names = "core", "iface"; 1002 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1003 dma-names = "tx", "rx"; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&blsp1_uart0_default>; 1006 status = "disabled"; 1007 }; 1008 1009 blsp1_uart1: serial@78b0000 { 1010 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1011 reg = <0x078b0000 0x200>; 1012 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1014 clock-names = "core", "iface"; 1015 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1016 dma-names = "tx", "rx"; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&blsp1_uart1_default>; 1019 status = "disabled"; 1020 }; 1021 1022 blsp1_uart2: serial@78b1000 { 1023 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1024 reg = <0x078b1000 0x200>; 1025 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1027 clock-names = "core", "iface"; 1028 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1029 dma-names = "tx", "rx"; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&blsp1_uart2_default>; 1032 status = "okay"; 1033 }; 1034 1035 ethernet: ethernet@7a80000 { 1036 compatible = "qcom,qcs404-ethqos"; 1037 reg = <0x07a80000 0x10000>, 1038 <0x07a96000 0x100>; 1039 reg-names = "stmmaceth", "rgmii"; 1040 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 1041 clocks = <&gcc GCC_ETH_AXI_CLK>, 1042 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 1043 <&gcc GCC_ETH_PTP_CLK>, 1044 <&gcc GCC_ETH_RGMII_CLK>; 1045 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1047 interrupt-names = "macirq", "eth_lpi"; 1048 1049 snps,tso; 1050 rx-fifo-depth = <4096>; 1051 tx-fifo-depth = <4096>; 1052 1053 status = "disabled"; 1054 }; 1055 1056 wifi: wifi@a000000 { 1057 compatible = "qcom,wcn3990-wifi"; 1058 reg = <0xa000000 0x800000>; 1059 reg-names = "membase"; 1060 memory-region = <&wlan_msa_mem>; 1061 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1073 status = "disabled"; 1074 }; 1075 1076 blsp1_uart3: serial@78b2000 { 1077 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1078 reg = <0x078b2000 0x200>; 1079 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1081 clock-names = "core", "iface"; 1082 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1083 dma-names = "tx", "rx"; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&blsp1_uart3_default>; 1086 status = "disabled"; 1087 }; 1088 1089 blsp1_i2c0: i2c@78b5000 { 1090 compatible = "qcom,i2c-qup-v2.2.1"; 1091 reg = <0x078b5000 0x600>; 1092 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, 1094 <&gcc GCC_BLSP1_AHB_CLK>; 1095 clock-names = "core", "iface"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&blsp1_i2c0_default>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 blsp1_spi0: spi@78b5000 { 1104 compatible = "qcom,spi-qup-v2.2.1"; 1105 reg = <0x078b5000 0x600>; 1106 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, 1108 <&gcc GCC_BLSP1_AHB_CLK>; 1109 clock-names = "core", "iface"; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&blsp1_spi0_default>; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 blsp1_i2c1: i2c@78b6000 { 1118 compatible = "qcom,i2c-qup-v2.2.1"; 1119 reg = <0x078b6000 0x600>; 1120 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1122 <&gcc GCC_BLSP1_AHB_CLK>; 1123 clock-names = "core", "iface"; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&blsp1_i2c1_default>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 status = "disabled"; 1129 }; 1130 1131 blsp1_spi1: spi@78b6000 { 1132 compatible = "qcom,spi-qup-v2.2.1"; 1133 reg = <0x078b6000 0x600>; 1134 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1136 <&gcc GCC_BLSP1_AHB_CLK>; 1137 clock-names = "core", "iface"; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&blsp1_spi1_default>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 blsp1_i2c2: i2c@78b7000 { 1146 compatible = "qcom,i2c-qup-v2.2.1"; 1147 reg = <0x078b7000 0x600>; 1148 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1150 <&gcc GCC_BLSP1_AHB_CLK>; 1151 clock-names = "core", "iface"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&blsp1_i2c2_default>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 blsp1_spi2: spi@78b7000 { 1160 compatible = "qcom,spi-qup-v2.2.1"; 1161 reg = <0x078b7000 0x600>; 1162 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1164 <&gcc GCC_BLSP1_AHB_CLK>; 1165 clock-names = "core", "iface"; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&blsp1_spi2_default>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 blsp1_i2c3: i2c@78b8000 { 1174 compatible = "qcom,i2c-qup-v2.2.1"; 1175 reg = <0x078b8000 0x600>; 1176 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1178 <&gcc GCC_BLSP1_AHB_CLK>; 1179 clock-names = "core", "iface"; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&blsp1_i2c3_default>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 blsp1_spi3: spi@78b8000 { 1188 compatible = "qcom,spi-qup-v2.2.1"; 1189 reg = <0x078b8000 0x600>; 1190 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1191 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1192 <&gcc GCC_BLSP1_AHB_CLK>; 1193 clock-names = "core", "iface"; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&blsp1_spi3_default>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 status = "disabled"; 1199 }; 1200 1201 blsp1_i2c4: i2c@78b9000 { 1202 compatible = "qcom,i2c-qup-v2.2.1"; 1203 reg = <0x078b9000 0x600>; 1204 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1206 <&gcc GCC_BLSP1_AHB_CLK>; 1207 clock-names = "core", "iface"; 1208 pinctrl-names = "default"; 1209 pinctrl-0 = <&blsp1_i2c4_default>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 status = "disabled"; 1213 }; 1214 1215 blsp1_spi4: spi@78b9000 { 1216 compatible = "qcom,spi-qup-v2.2.1"; 1217 reg = <0x078b9000 0x600>; 1218 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1220 <&gcc GCC_BLSP1_AHB_CLK>; 1221 clock-names = "core", "iface"; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&blsp1_spi4_default>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 status = "disabled"; 1227 }; 1228 1229 blsp2_dma: dma-controller@7ac4000 { 1230 compatible = "qcom,bam-v1.7.0"; 1231 reg = <0x07ac4000 0x17000>; 1232 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1234 clock-names = "bam_clk"; 1235 #dma-cells = <1>; 1236 qcom,ee = <0>; 1237 status = "disabled"; 1238 }; 1239 1240 blsp2_uart0: serial@7aef000 { 1241 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1242 reg = <0x07aef000 0x200>; 1243 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1245 clock-names = "core", "iface"; 1246 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1247 dma-names = "tx", "rx"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&blsp2_uart0_default>; 1250 status = "disabled"; 1251 }; 1252 1253 blsp2_i2c0: i2c@7af5000 { 1254 compatible = "qcom,i2c-qup-v2.2.1"; 1255 reg = <0x07af5000 0x600>; 1256 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, 1258 <&gcc GCC_BLSP2_AHB_CLK>; 1259 clock-names = "core", "iface"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&blsp2_i2c0_default>; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 1267 blsp2_spi0: spi@7af5000 { 1268 compatible = "qcom,spi-qup-v2.2.1"; 1269 reg = <0x07af5000 0x600>; 1270 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, 1272 <&gcc GCC_BLSP2_AHB_CLK>; 1273 clock-names = "core", "iface"; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&blsp2_spi0_default>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 status = "disabled"; 1279 }; 1280 1281 sram@8600000 { 1282 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; 1283 reg = <0x08600000 0x1000>; 1284 1285 #address-cells = <1>; 1286 #size-cells = <1>; 1287 1288 ranges = <0 0x08600000 0x1000>; 1289 1290 pil-reloc@94c { 1291 compatible = "qcom,pil-reloc-info"; 1292 reg = <0x94c 0xc8>; 1293 }; 1294 }; 1295 1296 intc: interrupt-controller@b000000 { 1297 compatible = "qcom,msm-qgic2"; 1298 interrupt-controller; 1299 #interrupt-cells = <3>; 1300 reg = <0x0b000000 0x1000>, 1301 <0x0b002000 0x1000>; 1302 }; 1303 1304 apcs_glb: mailbox@b011000 { 1305 compatible = "qcom,qcs404-apcs-apps-global", 1306 "qcom,msm8916-apcs-kpss-global", "syscon"; 1307 reg = <0x0b011000 0x1000>; 1308 #mbox-cells = <1>; 1309 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 1310 clock-names = "pll", "aux"; 1311 #clock-cells = <0>; 1312 }; 1313 1314 apcs_hfpll: clock-controller@b016000 { 1315 compatible = "qcom,hfpll"; 1316 reg = <0x0b016000 0x30>; 1317 #clock-cells = <0>; 1318 clock-output-names = "apcs_hfpll"; 1319 clocks = <&xo_board>; 1320 clock-names = "xo"; 1321 }; 1322 1323 watchdog@b017000 { 1324 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1325 reg = <0x0b017000 0x1000>; 1326 clocks = <&sleep_clk>; 1327 }; 1328 1329 cpr: power-controller@b018000 { 1330 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 1331 reg = <0x0b018000 0x1000>; 1332 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 1333 clocks = <&xo_board>; 1334 clock-names = "ref"; 1335 vdd-apc-supply = <&pms405_s3>; 1336 #power-domain-cells = <0>; 1337 operating-points-v2 = <&cpr_opp_table>; 1338 acc-syscon = <&tcsr>; 1339 1340 nvmem-cells = <&cpr_efuse_quot_offset1>, 1341 <&cpr_efuse_quot_offset2>, 1342 <&cpr_efuse_quot_offset3>, 1343 <&cpr_efuse_init_voltage1>, 1344 <&cpr_efuse_init_voltage2>, 1345 <&cpr_efuse_init_voltage3>, 1346 <&cpr_efuse_quot1>, 1347 <&cpr_efuse_quot2>, 1348 <&cpr_efuse_quot3>, 1349 <&cpr_efuse_ring1>, 1350 <&cpr_efuse_ring2>, 1351 <&cpr_efuse_ring3>, 1352 <&cpr_efuse_revision>; 1353 nvmem-cell-names = "cpr_quotient_offset1", 1354 "cpr_quotient_offset2", 1355 "cpr_quotient_offset3", 1356 "cpr_init_voltage1", 1357 "cpr_init_voltage2", 1358 "cpr_init_voltage3", 1359 "cpr_quotient1", 1360 "cpr_quotient2", 1361 "cpr_quotient3", 1362 "cpr_ring_osc1", 1363 "cpr_ring_osc2", 1364 "cpr_ring_osc3", 1365 "cpr_fuse_revision"; 1366 }; 1367 1368 timer@b120000 { 1369 #address-cells = <1>; 1370 #size-cells = <1>; 1371 ranges; 1372 compatible = "arm,armv7-timer-mem"; 1373 reg = <0x0b120000 0x1000>; 1374 clock-frequency = <19200000>; 1375 1376 frame@b121000 { 1377 frame-number = <0>; 1378 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1380 reg = <0x0b121000 0x1000>, 1381 <0x0b122000 0x1000>; 1382 }; 1383 1384 frame@b123000 { 1385 frame-number = <1>; 1386 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1387 reg = <0x0b123000 0x1000>; 1388 status = "disabled"; 1389 }; 1390 1391 frame@b124000 { 1392 frame-number = <2>; 1393 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1394 reg = <0x0b124000 0x1000>; 1395 status = "disabled"; 1396 }; 1397 1398 frame@b125000 { 1399 frame-number = <3>; 1400 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1401 reg = <0x0b125000 0x1000>; 1402 status = "disabled"; 1403 }; 1404 1405 frame@b126000 { 1406 frame-number = <4>; 1407 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1408 reg = <0x0b126000 0x1000>; 1409 status = "disabled"; 1410 }; 1411 1412 frame@b127000 { 1413 frame-number = <5>; 1414 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1415 reg = <0xb127000 0x1000>; 1416 status = "disabled"; 1417 }; 1418 1419 frame@b128000 { 1420 frame-number = <6>; 1421 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1422 reg = <0x0b128000 0x1000>; 1423 status = "disabled"; 1424 }; 1425 }; 1426 1427 remoteproc_adsp: remoteproc@c700000 { 1428 compatible = "qcom,qcs404-adsp-pas"; 1429 reg = <0x0c700000 0x4040>; 1430 1431 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 1432 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1433 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1434 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1435 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1436 interrupt-names = "wdog", "fatal", "ready", 1437 "handover", "stop-ack"; 1438 1439 clocks = <&xo_board>; 1440 clock-names = "xo"; 1441 1442 memory-region = <&adsp_fw_mem>; 1443 1444 qcom,smem-states = <&adsp_smp2p_out 0>; 1445 qcom,smem-state-names = "stop"; 1446 1447 status = "disabled"; 1448 1449 glink-edge { 1450 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1451 1452 qcom,remote-pid = <2>; 1453 mboxes = <&apcs_glb 8>; 1454 1455 label = "adsp"; 1456 }; 1457 }; 1458 1459 pcie: pci@10000000 { 1460 compatible = "qcom,pcie-qcs404"; 1461 reg = <0x10000000 0xf1d>, 1462 <0x10000f20 0xa8>, 1463 <0x07780000 0x2000>, 1464 <0x10001000 0x2000>; 1465 reg-names = "dbi", "elbi", "parf", "config"; 1466 device_type = "pci"; 1467 linux,pci-domain = <0>; 1468 bus-range = <0x00 0xff>; 1469 num-lanes = <1>; 1470 #address-cells = <3>; 1471 #size-cells = <2>; 1472 1473 ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ 1474 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ 1475 1476 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1477 interrupt-names = "msi"; 1478 #interrupt-cells = <1>; 1479 interrupt-map-mask = <0 0 0 0x7>; 1480 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1481 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1482 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1483 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1484 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1485 <&gcc GCC_PCIE_0_AUX_CLK>, 1486 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1487 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1488 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1489 1490 resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, 1491 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, 1492 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, 1493 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, 1494 <&gcc GCC_PCIE_0_BCR>, 1495 <&gcc GCC_PCIE_0_AHB_ARES>; 1496 reset-names = "axi_m", 1497 "axi_s", 1498 "axi_m_sticky", 1499 "pipe_sticky", 1500 "pwr", 1501 "ahb"; 1502 1503 phys = <&pcie_phy>; 1504 phy-names = "pciephy"; 1505 1506 status = "disabled"; 1507 }; 1508 }; 1509 1510 timer { 1511 compatible = "arm,armv8-timer"; 1512 interrupts = <GIC_PPI 2 0xff08>, 1513 <GIC_PPI 3 0xff08>, 1514 <GIC_PPI 4 0xff08>, 1515 <GIC_PPI 1 0xff08>; 1516 }; 1517 1518 smp2p-adsp { 1519 compatible = "qcom,smp2p"; 1520 qcom,smem = <443>, <429>; 1521 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1522 mboxes = <&apcs_glb 10>; 1523 qcom,local-pid = <0>; 1524 qcom,remote-pid = <2>; 1525 1526 adsp_smp2p_out: master-kernel { 1527 qcom,entry-name = "master-kernel"; 1528 #qcom,smem-state-cells = <1>; 1529 }; 1530 1531 adsp_smp2p_in: slave-kernel { 1532 qcom,entry-name = "slave-kernel"; 1533 interrupt-controller; 1534 #interrupt-cells = <2>; 1535 }; 1536 }; 1537 1538 smp2p-cdsp { 1539 compatible = "qcom,smp2p"; 1540 qcom,smem = <94>, <432>; 1541 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1542 mboxes = <&apcs_glb 14>; 1543 qcom,local-pid = <0>; 1544 qcom,remote-pid = <5>; 1545 1546 cdsp_smp2p_out: master-kernel { 1547 qcom,entry-name = "master-kernel"; 1548 #qcom,smem-state-cells = <1>; 1549 }; 1550 1551 cdsp_smp2p_in: slave-kernel { 1552 qcom,entry-name = "slave-kernel"; 1553 interrupt-controller; 1554 #interrupt-cells = <2>; 1555 }; 1556 }; 1557 1558 smp2p-wcss { 1559 compatible = "qcom,smp2p"; 1560 qcom,smem = <435>, <428>; 1561 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1562 mboxes = <&apcs_glb 18>; 1563 qcom,local-pid = <0>; 1564 qcom,remote-pid = <1>; 1565 1566 wcss_smp2p_out: master-kernel { 1567 qcom,entry-name = "master-kernel"; 1568 #qcom,smem-state-cells = <1>; 1569 }; 1570 1571 wcss_smp2p_in: slave-kernel { 1572 qcom,entry-name = "slave-kernel"; 1573 interrupt-controller; 1574 #interrupt-cells = <2>; 1575 }; 1576 }; 1577 1578 thermal-zones { 1579 aoss-thermal { 1580 polling-delay-passive = <250>; 1581 polling-delay = <1000>; 1582 1583 thermal-sensors = <&tsens 0>; 1584 1585 trips { 1586 aoss_alert0: trip-point0 { 1587 temperature = <105000>; 1588 hysteresis = <2000>; 1589 type = "hot"; 1590 }; 1591 }; 1592 }; 1593 1594 q6-hvx-thermal { 1595 polling-delay-passive = <250>; 1596 polling-delay = <1000>; 1597 1598 thermal-sensors = <&tsens 1>; 1599 1600 trips { 1601 q6_hvx_alert0: trip-point0 { 1602 temperature = <105000>; 1603 hysteresis = <2000>; 1604 type = "hot"; 1605 }; 1606 }; 1607 }; 1608 1609 lpass-thermal { 1610 polling-delay-passive = <250>; 1611 polling-delay = <1000>; 1612 1613 thermal-sensors = <&tsens 2>; 1614 1615 trips { 1616 lpass_alert0: trip-point0 { 1617 temperature = <105000>; 1618 hysteresis = <2000>; 1619 type = "hot"; 1620 }; 1621 }; 1622 }; 1623 1624 wlan-thermal { 1625 polling-delay-passive = <250>; 1626 polling-delay = <1000>; 1627 1628 thermal-sensors = <&tsens 3>; 1629 1630 trips { 1631 wlan_alert0: trip-point0 { 1632 temperature = <105000>; 1633 hysteresis = <2000>; 1634 type = "hot"; 1635 }; 1636 }; 1637 }; 1638 1639 cluster-thermal { 1640 polling-delay-passive = <250>; 1641 polling-delay = <1000>; 1642 1643 thermal-sensors = <&tsens 4>; 1644 1645 trips { 1646 cluster_alert0: trip-point0 { 1647 temperature = <95000>; 1648 hysteresis = <2000>; 1649 type = "hot"; 1650 }; 1651 cluster_alert1: trip-point1 { 1652 temperature = <105000>; 1653 hysteresis = <2000>; 1654 type = "passive"; 1655 }; 1656 cluster_crit: cluster-crit { 1657 temperature = <120000>; 1658 hysteresis = <2000>; 1659 type = "critical"; 1660 }; 1661 }; 1662 cooling-maps { 1663 map0 { 1664 trip = <&cluster_alert1>; 1665 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1666 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1667 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1668 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1669 }; 1670 }; 1671 }; 1672 1673 cpu0-thermal { 1674 polling-delay-passive = <250>; 1675 polling-delay = <1000>; 1676 1677 thermal-sensors = <&tsens 5>; 1678 1679 trips { 1680 cpu0_alert0: trip-point0 { 1681 temperature = <95000>; 1682 hysteresis = <2000>; 1683 type = "hot"; 1684 }; 1685 cpu0_alert1: trip-point1 { 1686 temperature = <105000>; 1687 hysteresis = <2000>; 1688 type = "passive"; 1689 }; 1690 cpu0_crit: cpu-crit { 1691 temperature = <120000>; 1692 hysteresis = <2000>; 1693 type = "critical"; 1694 }; 1695 }; 1696 cooling-maps { 1697 map0 { 1698 trip = <&cpu0_alert1>; 1699 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1700 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1701 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1702 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1703 }; 1704 }; 1705 }; 1706 1707 cpu1-thermal { 1708 polling-delay-passive = <250>; 1709 polling-delay = <1000>; 1710 1711 thermal-sensors = <&tsens 6>; 1712 1713 trips { 1714 cpu1_alert0: trip-point0 { 1715 temperature = <95000>; 1716 hysteresis = <2000>; 1717 type = "hot"; 1718 }; 1719 cpu1_alert1: trip-point1 { 1720 temperature = <105000>; 1721 hysteresis = <2000>; 1722 type = "passive"; 1723 }; 1724 cpu1_crit: cpu-crit { 1725 temperature = <120000>; 1726 hysteresis = <2000>; 1727 type = "critical"; 1728 }; 1729 }; 1730 cooling-maps { 1731 map0 { 1732 trip = <&cpu1_alert1>; 1733 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1734 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1735 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1736 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1737 }; 1738 }; 1739 }; 1740 1741 cpu2-thermal { 1742 polling-delay-passive = <250>; 1743 polling-delay = <1000>; 1744 1745 thermal-sensors = <&tsens 7>; 1746 1747 trips { 1748 cpu2_alert0: trip-point0 { 1749 temperature = <95000>; 1750 hysteresis = <2000>; 1751 type = "hot"; 1752 }; 1753 cpu2_alert1: trip-point1 { 1754 temperature = <105000>; 1755 hysteresis = <2000>; 1756 type = "passive"; 1757 }; 1758 cpu2_crit: cpu-crit { 1759 temperature = <120000>; 1760 hysteresis = <2000>; 1761 type = "critical"; 1762 }; 1763 }; 1764 cooling-maps { 1765 map0 { 1766 trip = <&cpu2_alert1>; 1767 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1768 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1769 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1770 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1771 }; 1772 }; 1773 }; 1774 1775 cpu3-thermal { 1776 polling-delay-passive = <250>; 1777 polling-delay = <1000>; 1778 1779 thermal-sensors = <&tsens 8>; 1780 1781 trips { 1782 cpu3_alert0: trip-point0 { 1783 temperature = <95000>; 1784 hysteresis = <2000>; 1785 type = "hot"; 1786 }; 1787 cpu3_alert1: trip-point1 { 1788 temperature = <105000>; 1789 hysteresis = <2000>; 1790 type = "passive"; 1791 }; 1792 cpu3_crit: cpu-crit { 1793 temperature = <120000>; 1794 hysteresis = <2000>; 1795 type = "critical"; 1796 }; 1797 }; 1798 cooling-maps { 1799 map0 { 1800 trip = <&cpu3_alert1>; 1801 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1802 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1803 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1804 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1805 }; 1806 }; 1807 }; 1808 1809 gpu-thermal { 1810 polling-delay-passive = <250>; 1811 polling-delay = <1000>; 1812 1813 thermal-sensors = <&tsens 9>; 1814 1815 trips { 1816 gpu_alert0: trip-point0 { 1817 temperature = <95000>; 1818 hysteresis = <2000>; 1819 type = "hot"; 1820 }; 1821 }; 1822 }; 1823 }; 1824}; 1825