1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-qcs404.h> 8#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32768>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x100>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 next-level-cache = <&L2_0>; 46 #cooling-cells = <2>; 47 clocks = <&apcs_glb>; 48 operating-points-v2 = <&cpu_opp_table>; 49 power-domains = <&cpr>; 50 power-domain-names = "cpr"; 51 }; 52 53 CPU1: cpu@101 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x101>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 next-level-cache = <&L2_0>; 60 #cooling-cells = <2>; 61 clocks = <&apcs_glb>; 62 operating-points-v2 = <&cpu_opp_table>; 63 power-domains = <&cpr>; 64 power-domain-names = "cpr"; 65 }; 66 67 CPU2: cpu@102 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x102>; 71 enable-method = "psci"; 72 cpu-idle-states = <&CPU_SLEEP_0>; 73 next-level-cache = <&L2_0>; 74 #cooling-cells = <2>; 75 clocks = <&apcs_glb>; 76 operating-points-v2 = <&cpu_opp_table>; 77 power-domains = <&cpr>; 78 power-domain-names = "cpr"; 79 }; 80 81 CPU3: cpu@103 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x103>; 85 enable-method = "psci"; 86 cpu-idle-states = <&CPU_SLEEP_0>; 87 next-level-cache = <&L2_0>; 88 #cooling-cells = <2>; 89 clocks = <&apcs_glb>; 90 operating-points-v2 = <&cpu_opp_table>; 91 power-domains = <&cpr>; 92 power-domain-names = "cpr"; 93 }; 94 95 L2_0: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 }; 99 100 idle-states { 101 entry-method = "psci"; 102 103 CPU_SLEEP_0: cpu-sleep-0 { 104 compatible = "arm,idle-state"; 105 idle-state-name = "standalone-power-collapse"; 106 arm,psci-suspend-param = <0x40000003>; 107 entry-latency-us = <125>; 108 exit-latency-us = <180>; 109 min-residency-us = <595>; 110 local-timer-stop; 111 }; 112 }; 113 }; 114 115 cpu_opp_table: opp-table-cpu { 116 compatible = "operating-points-v2-kryo-cpu"; 117 opp-shared; 118 119 opp-1094400000 { 120 opp-hz = /bits/ 64 <1094400000>; 121 required-opps = <&cpr_opp1>; 122 }; 123 opp-1248000000 { 124 opp-hz = /bits/ 64 <1248000000>; 125 required-opps = <&cpr_opp2>; 126 }; 127 opp-1401600000 { 128 opp-hz = /bits/ 64 <1401600000>; 129 required-opps = <&cpr_opp3>; 130 }; 131 }; 132 133 cpr_opp_table: opp-table-cpr { 134 compatible = "operating-points-v2-qcom-level"; 135 136 cpr_opp1: opp1 { 137 opp-level = <1>; 138 qcom,opp-fuse-level = <1>; 139 }; 140 cpr_opp2: opp2 { 141 opp-level = <2>; 142 qcom,opp-fuse-level = <2>; 143 }; 144 cpr_opp3: opp3 { 145 opp-level = <3>; 146 qcom,opp-fuse-level = <3>; 147 }; 148 }; 149 150 firmware { 151 scm: scm { 152 compatible = "qcom,scm-qcs404", "qcom,scm"; 153 #reset-cells = <1>; 154 }; 155 }; 156 157 memory@80000000 { 158 device_type = "memory"; 159 /* We expect the bootloader to fill in the size */ 160 reg = <0 0x80000000 0 0>; 161 }; 162 163 psci { 164 compatible = "arm,psci-1.0"; 165 method = "smc"; 166 }; 167 168 reserved-memory { 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 173 tz_apps_mem: memory@85900000 { 174 reg = <0 0x85900000 0 0x500000>; 175 no-map; 176 }; 177 178 xbl_mem: memory@85e00000 { 179 reg = <0 0x85e00000 0 0x100000>; 180 no-map; 181 }; 182 183 smem_region: memory@85f00000 { 184 reg = <0 0x85f00000 0 0x200000>; 185 no-map; 186 }; 187 188 tz_mem: memory@86100000 { 189 reg = <0 0x86100000 0 0x300000>; 190 no-map; 191 }; 192 193 wlan_fw_mem: memory@86400000 { 194 reg = <0 0x86400000 0 0x1100000>; 195 no-map; 196 }; 197 198 adsp_fw_mem: memory@87500000 { 199 reg = <0 0x87500000 0 0x1a00000>; 200 no-map; 201 }; 202 203 cdsp_fw_mem: memory@88f00000 { 204 reg = <0 0x88f00000 0 0x600000>; 205 no-map; 206 }; 207 208 wlan_msa_mem: memory@89500000 { 209 reg = <0 0x89500000 0 0x100000>; 210 no-map; 211 }; 212 213 uefi_mem: memory@9f800000 { 214 reg = <0 0x9f800000 0 0x800000>; 215 no-map; 216 }; 217 }; 218 219 rpm-glink { 220 compatible = "qcom,glink-rpm"; 221 222 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 223 qcom,rpm-msg-ram = <&rpm_msg_ram>; 224 mboxes = <&apcs_glb 0>; 225 226 rpm_requests: glink-channel { 227 compatible = "qcom,rpm-qcs404"; 228 qcom,glink-channels = "rpm_requests"; 229 230 rpmcc: clock-controller { 231 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; 232 #clock-cells = <1>; 233 }; 234 235 rpmpd: power-controller { 236 compatible = "qcom,qcs404-rpmpd"; 237 #power-domain-cells = <1>; 238 operating-points-v2 = <&rpmpd_opp_table>; 239 240 rpmpd_opp_table: opp-table { 241 compatible = "operating-points-v2"; 242 243 rpmpd_opp_ret: opp1 { 244 opp-level = <16>; 245 }; 246 247 rpmpd_opp_ret_plus: opp2 { 248 opp-level = <32>; 249 }; 250 251 rpmpd_opp_min_svs: opp3 { 252 opp-level = <48>; 253 }; 254 255 rpmpd_opp_low_svs: opp4 { 256 opp-level = <64>; 257 }; 258 259 rpmpd_opp_svs: opp5 { 260 opp-level = <128>; 261 }; 262 263 rpmpd_opp_svs_plus: opp6 { 264 opp-level = <192>; 265 }; 266 267 rpmpd_opp_nom: opp7 { 268 opp-level = <256>; 269 }; 270 271 rpmpd_opp_nom_plus: opp8 { 272 opp-level = <320>; 273 }; 274 275 rpmpd_opp_turbo: opp9 { 276 opp-level = <384>; 277 }; 278 279 rpmpd_opp_turbo_no_cpr: opp10 { 280 opp-level = <416>; 281 }; 282 283 rpmpd_opp_turbo_plus: opp11 { 284 opp-level = <512>; 285 }; 286 }; 287 }; 288 }; 289 }; 290 291 smem { 292 compatible = "qcom,smem"; 293 294 memory-region = <&smem_region>; 295 qcom,rpm-msg-ram = <&rpm_msg_ram>; 296 297 hwlocks = <&tcsr_mutex 3>; 298 }; 299 300 soc: soc@0 { 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0 0 0 0xffffffff>; 304 compatible = "simple-bus"; 305 306 turingcc: clock-controller@800000 { 307 compatible = "qcom,qcs404-turingcc"; 308 reg = <0x00800000 0x30000>; 309 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 310 311 #clock-cells = <1>; 312 #reset-cells = <1>; 313 314 status = "disabled"; 315 }; 316 317 rpm_msg_ram: sram@60000 { 318 compatible = "qcom,rpm-msg-ram"; 319 reg = <0x00060000 0x6000>; 320 }; 321 322 usb3_phy: phy@78000 { 323 compatible = "qcom,usb-ss-28nm-phy"; 324 reg = <0x00078000 0x400>; 325 #phy-cells = <0>; 326 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 327 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 328 <&gcc GCC_USB3_PHY_PIPE_CLK>; 329 clock-names = "ref", "ahb", "pipe"; 330 resets = <&gcc GCC_USB3_PHY_BCR>, 331 <&gcc GCC_USB3PHY_PHY_BCR>; 332 reset-names = "com", "phy"; 333 status = "disabled"; 334 }; 335 336 usb2_phy_prim: phy@7a000 { 337 compatible = "qcom,usb-hs-28nm-femtophy"; 338 reg = <0x0007a000 0x200>; 339 #phy-cells = <0>; 340 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 341 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 342 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 343 clock-names = "ref", "ahb", "sleep"; 344 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 345 <&gcc GCC_USB2A_PHY_BCR>; 346 reset-names = "phy", "por"; 347 status = "disabled"; 348 }; 349 350 usb2_phy_sec: phy@7c000 { 351 compatible = "qcom,usb-hs-28nm-femtophy"; 352 reg = <0x0007c000 0x200>; 353 #phy-cells = <0>; 354 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 355 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 356 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 357 clock-names = "ref", "ahb", "sleep"; 358 resets = <&gcc GCC_QUSB2_PHY_BCR>, 359 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 360 reset-names = "phy", "por"; 361 status = "disabled"; 362 }; 363 364 qfprom: qfprom@a4000 { 365 compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; 366 reg = <0x000a4000 0x1000>; 367 #address-cells = <1>; 368 #size-cells = <1>; 369 tsens_caldata: caldata@d0 { 370 reg = <0x1f8 0x14>; 371 }; 372 cpr_efuse_speedbin: speedbin@13c { 373 reg = <0x13c 0x4>; 374 bits = <2 3>; 375 }; 376 cpr_efuse_quot_offset1: qoffset1@231 { 377 reg = <0x231 0x4>; 378 bits = <4 7>; 379 }; 380 cpr_efuse_quot_offset2: qoffset2@232 { 381 reg = <0x232 0x4>; 382 bits = <3 7>; 383 }; 384 cpr_efuse_quot_offset3: qoffset3@233 { 385 reg = <0x233 0x4>; 386 bits = <2 7>; 387 }; 388 cpr_efuse_init_voltage1: ivoltage1@229 { 389 reg = <0x229 0x4>; 390 bits = <4 6>; 391 }; 392 cpr_efuse_init_voltage2: ivoltage2@22a { 393 reg = <0x22a 0x4>; 394 bits = <2 6>; 395 }; 396 cpr_efuse_init_voltage3: ivoltage3@22b { 397 reg = <0x22b 0x4>; 398 bits = <0 6>; 399 }; 400 cpr_efuse_quot1: quot1@22b { 401 reg = <0x22b 0x4>; 402 bits = <6 12>; 403 }; 404 cpr_efuse_quot2: quot2@22d { 405 reg = <0x22d 0x4>; 406 bits = <2 12>; 407 }; 408 cpr_efuse_quot3: quot3@230 { 409 reg = <0x230 0x4>; 410 bits = <0 12>; 411 }; 412 cpr_efuse_ring1: ring1@228 { 413 reg = <0x228 0x4>; 414 bits = <0 3>; 415 }; 416 cpr_efuse_ring2: ring2@228 { 417 reg = <0x228 0x4>; 418 bits = <4 3>; 419 }; 420 cpr_efuse_ring3: ring3@229 { 421 reg = <0x229 0x4>; 422 bits = <0 3>; 423 }; 424 cpr_efuse_revision: revision@218 { 425 reg = <0x218 0x4>; 426 bits = <3 3>; 427 }; 428 }; 429 430 rng: rng@e3000 { 431 compatible = "qcom,prng-ee"; 432 reg = <0x000e3000 0x1000>; 433 clocks = <&gcc GCC_PRNG_AHB_CLK>; 434 clock-names = "core"; 435 }; 436 437 bimc: interconnect@400000 { 438 reg = <0x00400000 0x80000>; 439 compatible = "qcom,qcs404-bimc"; 440 #interconnect-cells = <1>; 441 clock-names = "bus", "bus_a"; 442 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 443 <&rpmcc RPM_SMD_BIMC_A_CLK>; 444 }; 445 446 tsens: thermal-sensor@4a9000 { 447 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 448 reg = <0x004a9000 0x1000>, /* TM */ 449 <0x004a8000 0x1000>; /* SROT */ 450 nvmem-cells = <&tsens_caldata>; 451 nvmem-cell-names = "calib"; 452 #qcom,sensors = <10>; 453 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "uplow"; 455 #thermal-sensor-cells = <1>; 456 }; 457 458 pcnoc: interconnect@500000 { 459 reg = <0x00500000 0x15080>; 460 compatible = "qcom,qcs404-pcnoc"; 461 #interconnect-cells = <1>; 462 clock-names = "bus", "bus_a"; 463 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 464 <&rpmcc RPM_SMD_PNOC_A_CLK>; 465 }; 466 467 snoc: interconnect@580000 { 468 reg = <0x00580000 0x23080>; 469 compatible = "qcom,qcs404-snoc"; 470 #interconnect-cells = <1>; 471 clock-names = "bus", "bus_a"; 472 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 473 <&rpmcc RPM_SMD_SNOC_A_CLK>; 474 }; 475 476 remoteproc_cdsp: remoteproc@b00000 { 477 compatible = "qcom,qcs404-cdsp-pas"; 478 reg = <0x00b00000 0x4040>; 479 480 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 481 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 482 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 483 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 484 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 485 interrupt-names = "wdog", "fatal", "ready", 486 "handover", "stop-ack"; 487 488 clocks = <&xo_board>, 489 <&gcc GCC_CDSP_CFG_AHB_CLK>, 490 <&gcc GCC_CDSP_TBU_CLK>, 491 <&gcc GCC_BIMC_CDSP_CLK>, 492 <&turingcc TURING_WRAPPER_AON_CLK>, 493 <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 494 <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 495 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 496 clock-names = "xo", 497 "sway", 498 "tbu", 499 "bimc", 500 "ahb_aon", 501 "q6ss_slave", 502 "q6ss_master", 503 "q6_axim"; 504 505 resets = <&gcc GCC_CDSP_RESTART>; 506 reset-names = "restart"; 507 508 qcom,halt-regs = <&tcsr 0x19004>; 509 510 memory-region = <&cdsp_fw_mem>; 511 512 qcom,smem-states = <&cdsp_smp2p_out 0>; 513 qcom,smem-state-names = "stop"; 514 515 status = "disabled"; 516 517 glink-edge { 518 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 519 520 qcom,remote-pid = <5>; 521 mboxes = <&apcs_glb 12>; 522 523 label = "cdsp"; 524 }; 525 }; 526 527 usb3: usb@7678800 { 528 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 529 reg = <0x07678800 0x400>; 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ranges; 533 clocks = <&gcc GCC_USB30_MASTER_CLK>, 534 <&gcc GCC_SYS_NOC_USB3_CLK>, 535 <&gcc GCC_USB30_SLEEP_CLK>, 536 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 537 clock-names = "core", "iface", "sleep", "mock_utmi"; 538 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 539 <&gcc GCC_USB30_MASTER_CLK>; 540 assigned-clock-rates = <19200000>, <200000000>; 541 status = "disabled"; 542 543 usb3_dwc3: usb@7580000 { 544 compatible = "snps,dwc3"; 545 reg = <0x07580000 0xcd00>; 546 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 547 phys = <&usb2_phy_prim>, <&usb3_phy>; 548 phy-names = "usb2-phy", "usb3-phy"; 549 snps,has-lpm-erratum; 550 snps,hird-threshold = /bits/ 8 <0x10>; 551 snps,usb3_lpm_capable; 552 dr_mode = "otg"; 553 }; 554 }; 555 556 usb2: usb@79b8800 { 557 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 558 reg = <0x079b8800 0x400>; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 ranges; 562 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, 563 <&gcc GCC_PCNOC_USB2_CLK>, 564 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, 565 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 566 clock-names = "core", "iface", "sleep", "mock_utmi"; 567 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 568 <&gcc GCC_USB_HS_SYSTEM_CLK>; 569 assigned-clock-rates = <19200000>, <133333333>; 570 status = "disabled"; 571 572 usb@78c0000 { 573 compatible = "snps,dwc3"; 574 reg = <0x078c0000 0xcc00>; 575 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 576 phys = <&usb2_phy_sec>; 577 phy-names = "usb2-phy"; 578 snps,has-lpm-erratum; 579 snps,hird-threshold = /bits/ 8 <0x10>; 580 snps,usb3_lpm_capable; 581 dr_mode = "peripheral"; 582 }; 583 }; 584 585 tlmm: pinctrl@1000000 { 586 compatible = "qcom,qcs404-pinctrl"; 587 reg = <0x01000000 0x200000>, 588 <0x01300000 0x200000>, 589 <0x07b00000 0x200000>; 590 reg-names = "south", "north", "east"; 591 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 592 gpio-ranges = <&tlmm 0 0 120>; 593 gpio-controller; 594 #gpio-cells = <2>; 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 598 blsp1_i2c0_default: blsp1-i2c0-default-state { 599 pins = "gpio32", "gpio33"; 600 function = "blsp_i2c0"; 601 }; 602 603 blsp1_i2c1_default: blsp1-i2c1-default-state { 604 pins = "gpio24", "gpio25"; 605 function = "blsp_i2c1"; 606 }; 607 608 blsp1_i2c2_default: blsp1-i2c2-default-state { 609 sda-pins { 610 pins = "gpio19"; 611 function = "blsp_i2c_sda_a2"; 612 }; 613 614 scl-pins { 615 pins = "gpio20"; 616 function = "blsp_i2c_scl_a2"; 617 }; 618 }; 619 620 blsp1_i2c3_default: blsp1-i2c3-default-state { 621 pins = "gpio84", "gpio85"; 622 function = "blsp_i2c3"; 623 }; 624 625 blsp1_i2c4_default: blsp1-i2c4-default-state { 626 pins = "gpio117", "gpio118"; 627 function = "blsp_i2c4"; 628 }; 629 630 blsp1_uart0_default: blsp1-uart0-default-state { 631 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 632 function = "blsp_uart0"; 633 }; 634 635 blsp1_uart1_default: blsp1-uart1-default-state { 636 pins = "gpio22", "gpio23"; 637 function = "blsp_uart1"; 638 }; 639 640 blsp1_uart2_default: blsp1-uart2-default-state { 641 rx-pins { 642 pins = "gpio18"; 643 function = "blsp_uart_rx_a2"; 644 }; 645 646 tx-pins { 647 pins = "gpio17"; 648 function = "blsp_uart_tx_a2"; 649 }; 650 }; 651 652 blsp1_uart3_default: blsp1-uart3-default-state { 653 cts-pins { 654 pins = "gpio84"; 655 function = "blsp_uart3"; 656 }; 657 658 rts-tx-pins { 659 pins = "gpio85", "gpio82"; 660 function = "blsp_uart3"; 661 }; 662 663 rx-pins { 664 pins = "gpio83"; 665 function = "blsp_uart3"; 666 }; 667 }; 668 669 blsp2_i2c0_default: blsp2-i2c0-default-state { 670 pins = "gpio28", "gpio29"; 671 function = "blsp_i2c5"; 672 }; 673 674 blsp1_spi0_default: blsp1-spi0-default-state { 675 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 676 function = "blsp_spi0"; 677 }; 678 679 blsp1_spi1_default: blsp1-spi1-default-state { 680 mosi-pins { 681 pins = "gpio22"; 682 function = "blsp_spi_mosi_a1"; 683 }; 684 685 miso-pins { 686 pins = "gpio23"; 687 function = "blsp_spi_miso_a1"; 688 }; 689 690 cs-n-pins { 691 pins = "gpio24"; 692 function = "blsp_spi_cs_n_a1"; 693 }; 694 695 clk-pins { 696 pins = "gpio25"; 697 function = "blsp_spi_clk_a1"; 698 }; 699 }; 700 701 blsp1_spi2_default: blsp1-spi2-default-state { 702 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 703 function = "blsp_spi2"; 704 }; 705 706 blsp1_spi3_default: blsp1-spi3-default-state { 707 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 708 function = "blsp_spi3"; 709 }; 710 711 blsp1_spi4_default: blsp1-spi4-default-state { 712 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 713 function = "blsp_spi4"; 714 }; 715 716 blsp2_spi0_default: blsp2-spi0-default-state { 717 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 718 function = "blsp_spi5"; 719 }; 720 721 blsp2_uart0_default: blsp2-uart0-default-state { 722 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 723 function = "blsp_uart5"; 724 }; 725 }; 726 727 gcc: clock-controller@1800000 { 728 compatible = "qcom,gcc-qcs404"; 729 reg = <0x01800000 0x80000>; 730 #clock-cells = <1>; 731 #reset-cells = <1>; 732 733 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 734 assigned-clock-rates = <19200000>; 735 }; 736 737 tcsr_mutex: hwlock@1905000 { 738 compatible = "qcom,tcsr-mutex"; 739 reg = <0x01905000 0x20000>; 740 #hwlock-cells = <1>; 741 }; 742 743 tcsr: syscon@1937000 { 744 compatible = "qcom,qcs404-tcsr", "syscon"; 745 reg = <0x01937000 0x25000>; 746 }; 747 748 sram@290000 { 749 compatible = "qcom,rpm-stats"; 750 reg = <0x00290000 0x10000>; 751 }; 752 753 spmi_bus: spmi@200f000 { 754 compatible = "qcom,spmi-pmic-arb"; 755 reg = <0x0200f000 0x001000>, 756 <0x02400000 0x800000>, 757 <0x02c00000 0x800000>, 758 <0x03800000 0x200000>, 759 <0x0200a000 0x002100>; 760 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 761 interrupt-names = "periph_irq"; 762 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 763 qcom,ee = <0>; 764 qcom,channel = <0>; 765 #address-cells = <2>; 766 #size-cells = <0>; 767 interrupt-controller; 768 #interrupt-cells = <4>; 769 }; 770 771 remoteproc_wcss: remoteproc@7400000 { 772 compatible = "qcom,qcs404-wcss-pas"; 773 reg = <0x07400000 0x4040>; 774 775 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 776 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 777 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 778 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 779 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 780 interrupt-names = "wdog", "fatal", "ready", 781 "handover", "stop-ack"; 782 783 clocks = <&xo_board>; 784 clock-names = "xo"; 785 786 memory-region = <&wlan_fw_mem>; 787 788 qcom,smem-states = <&wcss_smp2p_out 0>; 789 qcom,smem-state-names = "stop"; 790 791 status = "disabled"; 792 793 glink-edge { 794 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 795 796 qcom,remote-pid = <1>; 797 mboxes = <&apcs_glb 16>; 798 799 label = "wcss"; 800 }; 801 }; 802 803 pcie_phy: phy@7786000 { 804 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 805 reg = <0x07786000 0xb8>; 806 807 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 808 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 809 <&gcc 21>; 810 reset-names = "phy", "pipe"; 811 812 clock-output-names = "pcie_0_pipe_clk"; 813 #phy-cells = <0>; 814 815 status = "disabled"; 816 }; 817 818 sdcc1: mmc@7804000 { 819 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 820 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 821 reg-names = "hc", "cqhci"; 822 823 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-names = "hc_irq", "pwr_irq"; 826 827 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 828 <&gcc GCC_SDCC1_APPS_CLK>, 829 <&xo_board>; 830 clock-names = "iface", "core", "xo"; 831 832 status = "disabled"; 833 }; 834 835 blsp1_dma: dma-controller@7884000 { 836 compatible = "qcom,bam-v1.7.0"; 837 reg = <0x07884000 0x25000>; 838 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 840 clock-names = "bam_clk"; 841 #dma-cells = <1>; 842 qcom,ee = <0>; 843 status = "okay"; 844 }; 845 846 blsp1_uart0: serial@78af000 { 847 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 848 reg = <0x078af000 0x200>; 849 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 851 clock-names = "core", "iface"; 852 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 853 dma-names = "tx", "rx"; 854 pinctrl-names = "default"; 855 pinctrl-0 = <&blsp1_uart0_default>; 856 status = "disabled"; 857 }; 858 859 blsp1_uart1: serial@78b0000 { 860 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 861 reg = <0x078b0000 0x200>; 862 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 864 clock-names = "core", "iface"; 865 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 866 dma-names = "tx", "rx"; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&blsp1_uart1_default>; 869 status = "disabled"; 870 }; 871 872 blsp1_uart2: serial@78b1000 { 873 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 874 reg = <0x078b1000 0x200>; 875 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 877 clock-names = "core", "iface"; 878 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 879 dma-names = "tx", "rx"; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&blsp1_uart2_default>; 882 status = "okay"; 883 }; 884 885 ethernet: ethernet@7a80000 { 886 compatible = "qcom,qcs404-ethqos"; 887 reg = <0x07a80000 0x10000>, 888 <0x07a96000 0x100>; 889 reg-names = "stmmaceth", "rgmii"; 890 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 891 clocks = <&gcc GCC_ETH_AXI_CLK>, 892 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 893 <&gcc GCC_ETH_PTP_CLK>, 894 <&gcc GCC_ETH_RGMII_CLK>; 895 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 897 interrupt-names = "macirq", "eth_lpi"; 898 899 snps,tso; 900 rx-fifo-depth = <4096>; 901 tx-fifo-depth = <4096>; 902 903 status = "disabled"; 904 }; 905 906 wifi: wifi@a000000 { 907 compatible = "qcom,wcn3990-wifi"; 908 reg = <0xa000000 0x800000>; 909 reg-names = "membase"; 910 memory-region = <&wlan_msa_mem>; 911 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 923 status = "disabled"; 924 }; 925 926 blsp1_uart3: serial@78b2000 { 927 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 928 reg = <0x078b2000 0x200>; 929 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 931 clock-names = "core", "iface"; 932 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 933 dma-names = "tx", "rx"; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&blsp1_uart3_default>; 936 status = "disabled"; 937 }; 938 939 blsp1_i2c0: i2c@78b5000 { 940 compatible = "qcom,i2c-qup-v2.2.1"; 941 reg = <0x078b5000 0x600>; 942 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, 944 <&gcc GCC_BLSP1_AHB_CLK>; 945 clock-names = "core", "iface"; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&blsp1_i2c0_default>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 }; 952 953 blsp1_spi0: spi@78b5000 { 954 compatible = "qcom,spi-qup-v2.2.1"; 955 reg = <0x078b5000 0x600>; 956 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, 958 <&gcc GCC_BLSP1_AHB_CLK>; 959 clock-names = "core", "iface"; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&blsp1_spi0_default>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 blsp1_i2c1: i2c@78b6000 { 968 compatible = "qcom,i2c-qup-v2.2.1"; 969 reg = <0x078b6000 0x600>; 970 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 972 <&gcc GCC_BLSP1_AHB_CLK>; 973 clock-names = "core", "iface"; 974 pinctrl-names = "default"; 975 pinctrl-0 = <&blsp1_i2c1_default>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 status = "disabled"; 979 }; 980 981 blsp1_spi1: spi@78b6000 { 982 compatible = "qcom,spi-qup-v2.2.1"; 983 reg = <0x078b6000 0x600>; 984 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 986 <&gcc GCC_BLSP1_AHB_CLK>; 987 clock-names = "core", "iface"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&blsp1_spi1_default>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 status = "disabled"; 993 }; 994 995 blsp1_i2c2: i2c@78b7000 { 996 compatible = "qcom,i2c-qup-v2.2.1"; 997 reg = <0x078b7000 0x600>; 998 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1000 <&gcc GCC_BLSP1_AHB_CLK>; 1001 clock-names = "core", "iface"; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&blsp1_i2c2_default>; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 status = "disabled"; 1007 }; 1008 1009 blsp1_spi2: spi@78b7000 { 1010 compatible = "qcom,spi-qup-v2.2.1"; 1011 reg = <0x078b7000 0x600>; 1012 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1014 <&gcc GCC_BLSP1_AHB_CLK>; 1015 clock-names = "core", "iface"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&blsp1_spi2_default>; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 status = "disabled"; 1021 }; 1022 1023 blsp1_i2c3: i2c@78b8000 { 1024 compatible = "qcom,i2c-qup-v2.2.1"; 1025 reg = <0x078b8000 0x600>; 1026 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1028 <&gcc GCC_BLSP1_AHB_CLK>; 1029 clock-names = "core", "iface"; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&blsp1_i2c3_default>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 blsp1_spi3: spi@78b8000 { 1038 compatible = "qcom,spi-qup-v2.2.1"; 1039 reg = <0x078b8000 0x600>; 1040 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1042 <&gcc GCC_BLSP1_AHB_CLK>; 1043 clock-names = "core", "iface"; 1044 pinctrl-names = "default"; 1045 pinctrl-0 = <&blsp1_spi3_default>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 blsp1_i2c4: i2c@78b9000 { 1052 compatible = "qcom,i2c-qup-v2.2.1"; 1053 reg = <0x078b9000 0x600>; 1054 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1056 <&gcc GCC_BLSP1_AHB_CLK>; 1057 clock-names = "core", "iface"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&blsp1_i2c4_default>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 status = "disabled"; 1063 }; 1064 1065 blsp1_spi4: spi@78b9000 { 1066 compatible = "qcom,spi-qup-v2.2.1"; 1067 reg = <0x078b9000 0x600>; 1068 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1070 <&gcc GCC_BLSP1_AHB_CLK>; 1071 clock-names = "core", "iface"; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&blsp1_spi4_default>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 blsp2_dma: dma-controller@7ac4000 { 1080 compatible = "qcom,bam-v1.7.0"; 1081 reg = <0x07ac4000 0x17000>; 1082 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1084 clock-names = "bam_clk"; 1085 #dma-cells = <1>; 1086 qcom,ee = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 blsp2_uart0: serial@7aef000 { 1091 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1092 reg = <0x07aef000 0x200>; 1093 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1095 clock-names = "core", "iface"; 1096 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1097 dma-names = "tx", "rx"; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&blsp2_uart0_default>; 1100 status = "disabled"; 1101 }; 1102 1103 blsp2_i2c0: i2c@7af5000 { 1104 compatible = "qcom,i2c-qup-v2.2.1"; 1105 reg = <0x07af5000 0x600>; 1106 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, 1108 <&gcc GCC_BLSP2_AHB_CLK>; 1109 clock-names = "core", "iface"; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&blsp2_i2c0_default>; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 blsp2_spi0: spi@7af5000 { 1118 compatible = "qcom,spi-qup-v2.2.1"; 1119 reg = <0x07af5000 0x600>; 1120 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, 1122 <&gcc GCC_BLSP2_AHB_CLK>; 1123 clock-names = "core", "iface"; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&blsp2_spi0_default>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 status = "disabled"; 1129 }; 1130 1131 sram@8600000 { 1132 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; 1133 reg = <0x08600000 0x1000>; 1134 1135 #address-cells = <1>; 1136 #size-cells = <1>; 1137 1138 ranges = <0 0x08600000 0x1000>; 1139 1140 pil-reloc@94c { 1141 compatible = "qcom,pil-reloc-info"; 1142 reg = <0x94c 0xc8>; 1143 }; 1144 }; 1145 1146 intc: interrupt-controller@b000000 { 1147 compatible = "qcom,msm-qgic2"; 1148 interrupt-controller; 1149 #interrupt-cells = <3>; 1150 reg = <0x0b000000 0x1000>, 1151 <0x0b002000 0x1000>; 1152 }; 1153 1154 apcs_glb: mailbox@b011000 { 1155 compatible = "qcom,qcs404-apcs-apps-global", "syscon"; 1156 reg = <0x0b011000 0x1000>; 1157 #mbox-cells = <1>; 1158 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 1159 clock-names = "pll", "aux"; 1160 #clock-cells = <0>; 1161 }; 1162 1163 apcs_hfpll: clock-controller@b016000 { 1164 compatible = "qcom,hfpll"; 1165 reg = <0x0b016000 0x30>; 1166 #clock-cells = <0>; 1167 clock-output-names = "apcs_hfpll"; 1168 clocks = <&xo_board>; 1169 clock-names = "xo"; 1170 }; 1171 1172 watchdog@b017000 { 1173 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1174 reg = <0x0b017000 0x1000>; 1175 clocks = <&sleep_clk>; 1176 }; 1177 1178 cpr: power-controller@b018000 { 1179 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 1180 reg = <0x0b018000 0x1000>; 1181 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 1182 clocks = <&xo_board>; 1183 clock-names = "ref"; 1184 vdd-apc-supply = <&pms405_s3>; 1185 #power-domain-cells = <0>; 1186 operating-points-v2 = <&cpr_opp_table>; 1187 acc-syscon = <&tcsr>; 1188 1189 nvmem-cells = <&cpr_efuse_quot_offset1>, 1190 <&cpr_efuse_quot_offset2>, 1191 <&cpr_efuse_quot_offset3>, 1192 <&cpr_efuse_init_voltage1>, 1193 <&cpr_efuse_init_voltage2>, 1194 <&cpr_efuse_init_voltage3>, 1195 <&cpr_efuse_quot1>, 1196 <&cpr_efuse_quot2>, 1197 <&cpr_efuse_quot3>, 1198 <&cpr_efuse_ring1>, 1199 <&cpr_efuse_ring2>, 1200 <&cpr_efuse_ring3>, 1201 <&cpr_efuse_revision>; 1202 nvmem-cell-names = "cpr_quotient_offset1", 1203 "cpr_quotient_offset2", 1204 "cpr_quotient_offset3", 1205 "cpr_init_voltage1", 1206 "cpr_init_voltage2", 1207 "cpr_init_voltage3", 1208 "cpr_quotient1", 1209 "cpr_quotient2", 1210 "cpr_quotient3", 1211 "cpr_ring_osc1", 1212 "cpr_ring_osc2", 1213 "cpr_ring_osc3", 1214 "cpr_fuse_revision"; 1215 }; 1216 1217 timer@b120000 { 1218 #address-cells = <1>; 1219 #size-cells = <1>; 1220 ranges; 1221 compatible = "arm,armv7-timer-mem"; 1222 reg = <0x0b120000 0x1000>; 1223 clock-frequency = <19200000>; 1224 1225 frame@b121000 { 1226 frame-number = <0>; 1227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1229 reg = <0x0b121000 0x1000>, 1230 <0x0b122000 0x1000>; 1231 }; 1232 1233 frame@b123000 { 1234 frame-number = <1>; 1235 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1236 reg = <0x0b123000 0x1000>; 1237 status = "disabled"; 1238 }; 1239 1240 frame@b124000 { 1241 frame-number = <2>; 1242 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1243 reg = <0x0b124000 0x1000>; 1244 status = "disabled"; 1245 }; 1246 1247 frame@b125000 { 1248 frame-number = <3>; 1249 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1250 reg = <0x0b125000 0x1000>; 1251 status = "disabled"; 1252 }; 1253 1254 frame@b126000 { 1255 frame-number = <4>; 1256 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1257 reg = <0x0b126000 0x1000>; 1258 status = "disabled"; 1259 }; 1260 1261 frame@b127000 { 1262 frame-number = <5>; 1263 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1264 reg = <0xb127000 0x1000>; 1265 status = "disabled"; 1266 }; 1267 1268 frame@b128000 { 1269 frame-number = <6>; 1270 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1271 reg = <0x0b128000 0x1000>; 1272 status = "disabled"; 1273 }; 1274 }; 1275 1276 remoteproc_adsp: remoteproc@c700000 { 1277 compatible = "qcom,qcs404-adsp-pas"; 1278 reg = <0x0c700000 0x4040>; 1279 1280 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 1281 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1282 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1283 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1284 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1285 interrupt-names = "wdog", "fatal", "ready", 1286 "handover", "stop-ack"; 1287 1288 clocks = <&xo_board>; 1289 clock-names = "xo"; 1290 1291 memory-region = <&adsp_fw_mem>; 1292 1293 qcom,smem-states = <&adsp_smp2p_out 0>; 1294 qcom,smem-state-names = "stop"; 1295 1296 status = "disabled"; 1297 1298 glink-edge { 1299 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1300 1301 qcom,remote-pid = <2>; 1302 mboxes = <&apcs_glb 8>; 1303 1304 label = "adsp"; 1305 }; 1306 }; 1307 1308 pcie: pci@10000000 { 1309 compatible = "qcom,pcie-qcs404"; 1310 reg = <0x10000000 0xf1d>, 1311 <0x10000f20 0xa8>, 1312 <0x07780000 0x2000>, 1313 <0x10001000 0x2000>; 1314 reg-names = "dbi", "elbi", "parf", "config"; 1315 device_type = "pci"; 1316 linux,pci-domain = <0>; 1317 bus-range = <0x00 0xff>; 1318 num-lanes = <1>; 1319 #address-cells = <3>; 1320 #size-cells = <2>; 1321 1322 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ 1323 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ 1324 1325 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1326 interrupt-names = "msi"; 1327 #interrupt-cells = <1>; 1328 interrupt-map-mask = <0 0 0 0x7>; 1329 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1330 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1331 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1332 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1333 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1334 <&gcc GCC_PCIE_0_AUX_CLK>, 1335 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1336 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1337 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1338 1339 resets = <&gcc 18>, 1340 <&gcc 17>, 1341 <&gcc 15>, 1342 <&gcc 19>, 1343 <&gcc GCC_PCIE_0_BCR>, 1344 <&gcc 16>; 1345 reset-names = "axi_m", 1346 "axi_s", 1347 "axi_m_sticky", 1348 "pipe_sticky", 1349 "pwr", 1350 "ahb"; 1351 1352 phys = <&pcie_phy>; 1353 phy-names = "pciephy"; 1354 1355 status = "disabled"; 1356 }; 1357 }; 1358 1359 timer { 1360 compatible = "arm,armv8-timer"; 1361 interrupts = <GIC_PPI 2 0xff08>, 1362 <GIC_PPI 3 0xff08>, 1363 <GIC_PPI 4 0xff08>, 1364 <GIC_PPI 1 0xff08>; 1365 }; 1366 1367 smp2p-adsp { 1368 compatible = "qcom,smp2p"; 1369 qcom,smem = <443>, <429>; 1370 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1371 mboxes = <&apcs_glb 10>; 1372 qcom,local-pid = <0>; 1373 qcom,remote-pid = <2>; 1374 1375 adsp_smp2p_out: master-kernel { 1376 qcom,entry-name = "master-kernel"; 1377 #qcom,smem-state-cells = <1>; 1378 }; 1379 1380 adsp_smp2p_in: slave-kernel { 1381 qcom,entry-name = "slave-kernel"; 1382 interrupt-controller; 1383 #interrupt-cells = <2>; 1384 }; 1385 }; 1386 1387 smp2p-cdsp { 1388 compatible = "qcom,smp2p"; 1389 qcom,smem = <94>, <432>; 1390 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1391 mboxes = <&apcs_glb 14>; 1392 qcom,local-pid = <0>; 1393 qcom,remote-pid = <5>; 1394 1395 cdsp_smp2p_out: master-kernel { 1396 qcom,entry-name = "master-kernel"; 1397 #qcom,smem-state-cells = <1>; 1398 }; 1399 1400 cdsp_smp2p_in: slave-kernel { 1401 qcom,entry-name = "slave-kernel"; 1402 interrupt-controller; 1403 #interrupt-cells = <2>; 1404 }; 1405 }; 1406 1407 smp2p-wcss { 1408 compatible = "qcom,smp2p"; 1409 qcom,smem = <435>, <428>; 1410 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1411 mboxes = <&apcs_glb 18>; 1412 qcom,local-pid = <0>; 1413 qcom,remote-pid = <1>; 1414 1415 wcss_smp2p_out: master-kernel { 1416 qcom,entry-name = "master-kernel"; 1417 #qcom,smem-state-cells = <1>; 1418 }; 1419 1420 wcss_smp2p_in: slave-kernel { 1421 qcom,entry-name = "slave-kernel"; 1422 interrupt-controller; 1423 #interrupt-cells = <2>; 1424 }; 1425 }; 1426 1427 thermal-zones { 1428 aoss-thermal { 1429 polling-delay-passive = <250>; 1430 polling-delay = <1000>; 1431 1432 thermal-sensors = <&tsens 0>; 1433 1434 trips { 1435 aoss_alert0: trip-point0 { 1436 temperature = <105000>; 1437 hysteresis = <2000>; 1438 type = "hot"; 1439 }; 1440 }; 1441 }; 1442 1443 q6-hvx-thermal { 1444 polling-delay-passive = <250>; 1445 polling-delay = <1000>; 1446 1447 thermal-sensors = <&tsens 1>; 1448 1449 trips { 1450 q6_hvx_alert0: trip-point0 { 1451 temperature = <105000>; 1452 hysteresis = <2000>; 1453 type = "hot"; 1454 }; 1455 }; 1456 }; 1457 1458 lpass-thermal { 1459 polling-delay-passive = <250>; 1460 polling-delay = <1000>; 1461 1462 thermal-sensors = <&tsens 2>; 1463 1464 trips { 1465 lpass_alert0: trip-point0 { 1466 temperature = <105000>; 1467 hysteresis = <2000>; 1468 type = "hot"; 1469 }; 1470 }; 1471 }; 1472 1473 wlan-thermal { 1474 polling-delay-passive = <250>; 1475 polling-delay = <1000>; 1476 1477 thermal-sensors = <&tsens 3>; 1478 1479 trips { 1480 wlan_alert0: trip-point0 { 1481 temperature = <105000>; 1482 hysteresis = <2000>; 1483 type = "hot"; 1484 }; 1485 }; 1486 }; 1487 1488 cluster-thermal { 1489 polling-delay-passive = <250>; 1490 polling-delay = <1000>; 1491 1492 thermal-sensors = <&tsens 4>; 1493 1494 trips { 1495 cluster_alert0: trip-point0 { 1496 temperature = <95000>; 1497 hysteresis = <2000>; 1498 type = "hot"; 1499 }; 1500 cluster_alert1: trip-point1 { 1501 temperature = <105000>; 1502 hysteresis = <2000>; 1503 type = "passive"; 1504 }; 1505 cluster_crit: cluster_crit { 1506 temperature = <120000>; 1507 hysteresis = <2000>; 1508 type = "critical"; 1509 }; 1510 }; 1511 cooling-maps { 1512 map0 { 1513 trip = <&cluster_alert1>; 1514 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1515 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1516 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1517 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1518 }; 1519 }; 1520 }; 1521 1522 cpu0-thermal { 1523 polling-delay-passive = <250>; 1524 polling-delay = <1000>; 1525 1526 thermal-sensors = <&tsens 5>; 1527 1528 trips { 1529 cpu0_alert0: trip-point0 { 1530 temperature = <95000>; 1531 hysteresis = <2000>; 1532 type = "hot"; 1533 }; 1534 cpu0_alert1: trip-point1 { 1535 temperature = <105000>; 1536 hysteresis = <2000>; 1537 type = "passive"; 1538 }; 1539 cpu0_crit: cpu_crit { 1540 temperature = <120000>; 1541 hysteresis = <2000>; 1542 type = "critical"; 1543 }; 1544 }; 1545 cooling-maps { 1546 map0 { 1547 trip = <&cpu0_alert1>; 1548 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1549 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1550 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1551 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1552 }; 1553 }; 1554 }; 1555 1556 cpu1-thermal { 1557 polling-delay-passive = <250>; 1558 polling-delay = <1000>; 1559 1560 thermal-sensors = <&tsens 6>; 1561 1562 trips { 1563 cpu1_alert0: trip-point0 { 1564 temperature = <95000>; 1565 hysteresis = <2000>; 1566 type = "hot"; 1567 }; 1568 cpu1_alert1: trip-point1 { 1569 temperature = <105000>; 1570 hysteresis = <2000>; 1571 type = "passive"; 1572 }; 1573 cpu1_crit: cpu_crit { 1574 temperature = <120000>; 1575 hysteresis = <2000>; 1576 type = "critical"; 1577 }; 1578 }; 1579 cooling-maps { 1580 map0 { 1581 trip = <&cpu1_alert1>; 1582 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1583 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1584 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1585 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1586 }; 1587 }; 1588 }; 1589 1590 cpu2-thermal { 1591 polling-delay-passive = <250>; 1592 polling-delay = <1000>; 1593 1594 thermal-sensors = <&tsens 7>; 1595 1596 trips { 1597 cpu2_alert0: trip-point0 { 1598 temperature = <95000>; 1599 hysteresis = <2000>; 1600 type = "hot"; 1601 }; 1602 cpu2_alert1: trip-point1 { 1603 temperature = <105000>; 1604 hysteresis = <2000>; 1605 type = "passive"; 1606 }; 1607 cpu2_crit: cpu_crit { 1608 temperature = <120000>; 1609 hysteresis = <2000>; 1610 type = "critical"; 1611 }; 1612 }; 1613 cooling-maps { 1614 map0 { 1615 trip = <&cpu2_alert1>; 1616 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1617 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1618 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1619 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1620 }; 1621 }; 1622 }; 1623 1624 cpu3-thermal { 1625 polling-delay-passive = <250>; 1626 polling-delay = <1000>; 1627 1628 thermal-sensors = <&tsens 8>; 1629 1630 trips { 1631 cpu3_alert0: trip-point0 { 1632 temperature = <95000>; 1633 hysteresis = <2000>; 1634 type = "hot"; 1635 }; 1636 cpu3_alert1: trip-point1 { 1637 temperature = <105000>; 1638 hysteresis = <2000>; 1639 type = "passive"; 1640 }; 1641 cpu3_crit: cpu_crit { 1642 temperature = <120000>; 1643 hysteresis = <2000>; 1644 type = "critical"; 1645 }; 1646 }; 1647 cooling-maps { 1648 map0 { 1649 trip = <&cpu3_alert1>; 1650 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1651 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1652 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1653 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1654 }; 1655 }; 1656 }; 1657 1658 gpu-thermal { 1659 polling-delay-passive = <250>; 1660 polling-delay = <1000>; 1661 1662 thermal-sensors = <&tsens 9>; 1663 1664 trips { 1665 gpu_alert0: trip-point0 { 1666 temperature = <95000>; 1667 hysteresis = <2000>; 1668 type = "hot"; 1669 }; 1670 }; 1671 }; 1672 }; 1673}; 1674