1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2018, Linaro Limited 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-qcs404.h> 6#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/thermal/thermal.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 }; 25 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <32768>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@100 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x100>; 41 enable-method = "psci"; 42 cpu-idle-states = <&CPU_SLEEP_0>; 43 next-level-cache = <&L2_0>; 44 #cooling-cells = <2>; 45 clocks = <&apcs_glb>; 46 operating-points-v2 = <&cpu_opp_table>; 47 power-domains = <&cpr>; 48 power-domain-names = "cpr"; 49 }; 50 51 CPU1: cpu@101 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x101>; 55 enable-method = "psci"; 56 cpu-idle-states = <&CPU_SLEEP_0>; 57 next-level-cache = <&L2_0>; 58 #cooling-cells = <2>; 59 clocks = <&apcs_glb>; 60 operating-points-v2 = <&cpu_opp_table>; 61 power-domains = <&cpr>; 62 power-domain-names = "cpr"; 63 }; 64 65 CPU2: cpu@102 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x102>; 69 enable-method = "psci"; 70 cpu-idle-states = <&CPU_SLEEP_0>; 71 next-level-cache = <&L2_0>; 72 #cooling-cells = <2>; 73 clocks = <&apcs_glb>; 74 operating-points-v2 = <&cpu_opp_table>; 75 power-domains = <&cpr>; 76 power-domain-names = "cpr"; 77 }; 78 79 CPU3: cpu@103 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x103>; 83 enable-method = "psci"; 84 cpu-idle-states = <&CPU_SLEEP_0>; 85 next-level-cache = <&L2_0>; 86 #cooling-cells = <2>; 87 clocks = <&apcs_glb>; 88 operating-points-v2 = <&cpu_opp_table>; 89 power-domains = <&cpr>; 90 power-domain-names = "cpr"; 91 }; 92 93 L2_0: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 }; 97 98 idle-states { 99 entry-method = "psci"; 100 101 CPU_SLEEP_0: cpu-sleep-0 { 102 compatible = "arm,idle-state"; 103 idle-state-name = "standalone-power-collapse"; 104 arm,psci-suspend-param = <0x40000003>; 105 entry-latency-us = <125>; 106 exit-latency-us = <180>; 107 min-residency-us = <595>; 108 local-timer-stop; 109 }; 110 }; 111 }; 112 113 cpu_opp_table: opp-table-cpu { 114 compatible = "operating-points-v2-kryo-cpu"; 115 opp-shared; 116 117 opp-1094400000 { 118 opp-hz = /bits/ 64 <1094400000>; 119 required-opps = <&cpr_opp1>; 120 }; 121 opp-1248000000 { 122 opp-hz = /bits/ 64 <1248000000>; 123 required-opps = <&cpr_opp2>; 124 }; 125 opp-1401600000 { 126 opp-hz = /bits/ 64 <1401600000>; 127 required-opps = <&cpr_opp3>; 128 }; 129 }; 130 131 cpr_opp_table: opp-table-cpr { 132 compatible = "operating-points-v2-qcom-level"; 133 134 cpr_opp1: opp1 { 135 opp-level = <1>; 136 qcom,opp-fuse-level = <1>; 137 }; 138 cpr_opp2: opp2 { 139 opp-level = <2>; 140 qcom,opp-fuse-level = <2>; 141 }; 142 cpr_opp3: opp3 { 143 opp-level = <3>; 144 qcom,opp-fuse-level = <3>; 145 }; 146 }; 147 148 firmware { 149 scm: scm { 150 compatible = "qcom,scm-qcs404", "qcom,scm"; 151 #reset-cells = <1>; 152 }; 153 }; 154 155 memory@80000000 { 156 device_type = "memory"; 157 /* We expect the bootloader to fill in the size */ 158 reg = <0 0x80000000 0 0>; 159 }; 160 161 psci { 162 compatible = "arm,psci-1.0"; 163 method = "smc"; 164 }; 165 166 reserved-memory { 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges; 170 171 tz_apps_mem: memory@85900000 { 172 reg = <0 0x85900000 0 0x500000>; 173 no-map; 174 }; 175 176 xbl_mem: memory@85e00000 { 177 reg = <0 0x85e00000 0 0x100000>; 178 no-map; 179 }; 180 181 smem_region: memory@85f00000 { 182 reg = <0 0x85f00000 0 0x200000>; 183 no-map; 184 }; 185 186 tz_mem: memory@86100000 { 187 reg = <0 0x86100000 0 0x300000>; 188 no-map; 189 }; 190 191 wlan_fw_mem: memory@86400000 { 192 reg = <0 0x86400000 0 0x1100000>; 193 no-map; 194 }; 195 196 adsp_fw_mem: memory@87500000 { 197 reg = <0 0x87500000 0 0x1a00000>; 198 no-map; 199 }; 200 201 cdsp_fw_mem: memory@88f00000 { 202 reg = <0 0x88f00000 0 0x600000>; 203 no-map; 204 }; 205 206 wlan_msa_mem: memory@89500000 { 207 reg = <0 0x89500000 0 0x100000>; 208 no-map; 209 }; 210 211 uefi_mem: memory@9f800000 { 212 reg = <0 0x9f800000 0 0x800000>; 213 no-map; 214 }; 215 }; 216 217 rpm-glink { 218 compatible = "qcom,glink-rpm"; 219 220 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 221 qcom,rpm-msg-ram = <&rpm_msg_ram>; 222 mboxes = <&apcs_glb 0>; 223 224 rpm_requests: glink-channel { 225 compatible = "qcom,rpm-qcs404"; 226 qcom,glink-channels = "rpm_requests"; 227 228 rpmcc: clock-controller { 229 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; 230 #clock-cells = <1>; 231 }; 232 233 rpmpd: power-controller { 234 compatible = "qcom,qcs404-rpmpd"; 235 #power-domain-cells = <1>; 236 operating-points-v2 = <&rpmpd_opp_table>; 237 238 rpmpd_opp_table: opp-table { 239 compatible = "operating-points-v2"; 240 241 rpmpd_opp_ret: opp1 { 242 opp-level = <16>; 243 }; 244 245 rpmpd_opp_ret_plus: opp2 { 246 opp-level = <32>; 247 }; 248 249 rpmpd_opp_min_svs: opp3 { 250 opp-level = <48>; 251 }; 252 253 rpmpd_opp_low_svs: opp4 { 254 opp-level = <64>; 255 }; 256 257 rpmpd_opp_svs: opp5 { 258 opp-level = <128>; 259 }; 260 261 rpmpd_opp_svs_plus: opp6 { 262 opp-level = <192>; 263 }; 264 265 rpmpd_opp_nom: opp7 { 266 opp-level = <256>; 267 }; 268 269 rpmpd_opp_nom_plus: opp8 { 270 opp-level = <320>; 271 }; 272 273 rpmpd_opp_turbo: opp9 { 274 opp-level = <384>; 275 }; 276 277 rpmpd_opp_turbo_no_cpr: opp10 { 278 opp-level = <416>; 279 }; 280 281 rpmpd_opp_turbo_plus: opp11 { 282 opp-level = <512>; 283 }; 284 }; 285 }; 286 }; 287 }; 288 289 smem { 290 compatible = "qcom,smem"; 291 292 memory-region = <&smem_region>; 293 qcom,rpm-msg-ram = <&rpm_msg_ram>; 294 295 hwlocks = <&tcsr_mutex 3>; 296 }; 297 298 soc: soc@0 { 299 #address-cells = <1>; 300 #size-cells = <1>; 301 ranges = <0 0 0 0xffffffff>; 302 compatible = "simple-bus"; 303 304 turingcc: clock-controller@800000 { 305 compatible = "qcom,qcs404-turingcc"; 306 reg = <0x00800000 0x30000>; 307 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 308 309 #clock-cells = <1>; 310 #reset-cells = <1>; 311 312 status = "disabled"; 313 }; 314 315 rpm_msg_ram: sram@60000 { 316 compatible = "qcom,rpm-msg-ram"; 317 reg = <0x00060000 0x6000>; 318 }; 319 320 usb3_phy: phy@78000 { 321 compatible = "qcom,usb-ss-28nm-phy"; 322 reg = <0x00078000 0x400>; 323 #phy-cells = <0>; 324 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 325 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 326 <&gcc GCC_USB3_PHY_PIPE_CLK>; 327 clock-names = "ref", "ahb", "pipe"; 328 resets = <&gcc GCC_USB3_PHY_BCR>, 329 <&gcc GCC_USB3PHY_PHY_BCR>; 330 reset-names = "com", "phy"; 331 status = "disabled"; 332 }; 333 334 usb2_phy_prim: phy@7a000 { 335 compatible = "qcom,usb-hs-28nm-femtophy"; 336 reg = <0x0007a000 0x200>; 337 #phy-cells = <0>; 338 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 339 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 340 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 341 clock-names = "ref", "ahb", "sleep"; 342 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 343 <&gcc GCC_USB2A_PHY_BCR>; 344 reset-names = "phy", "por"; 345 status = "disabled"; 346 }; 347 348 usb2_phy_sec: phy@7c000 { 349 compatible = "qcom,usb-hs-28nm-femtophy"; 350 reg = <0x0007c000 0x200>; 351 #phy-cells = <0>; 352 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 353 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 354 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 355 clock-names = "ref", "ahb", "sleep"; 356 resets = <&gcc GCC_QUSB2_PHY_BCR>, 357 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 358 reset-names = "phy", "por"; 359 status = "disabled"; 360 }; 361 362 qfprom: qfprom@a4000 { 363 compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; 364 reg = <0x000a4000 0x1000>; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 tsens_caldata: caldata@d0 { 368 reg = <0x1f8 0x14>; 369 }; 370 cpr_efuse_speedbin: speedbin@13c { 371 reg = <0x13c 0x4>; 372 bits = <2 3>; 373 }; 374 cpr_efuse_quot_offset1: qoffset1@231 { 375 reg = <0x231 0x4>; 376 bits = <4 7>; 377 }; 378 cpr_efuse_quot_offset2: qoffset2@232 { 379 reg = <0x232 0x4>; 380 bits = <3 7>; 381 }; 382 cpr_efuse_quot_offset3: qoffset3@233 { 383 reg = <0x233 0x4>; 384 bits = <2 7>; 385 }; 386 cpr_efuse_init_voltage1: ivoltage1@229 { 387 reg = <0x229 0x4>; 388 bits = <4 6>; 389 }; 390 cpr_efuse_init_voltage2: ivoltage2@22a { 391 reg = <0x22a 0x4>; 392 bits = <2 6>; 393 }; 394 cpr_efuse_init_voltage3: ivoltage3@22b { 395 reg = <0x22b 0x4>; 396 bits = <0 6>; 397 }; 398 cpr_efuse_quot1: quot1@22b { 399 reg = <0x22b 0x4>; 400 bits = <6 12>; 401 }; 402 cpr_efuse_quot2: quot2@22d { 403 reg = <0x22d 0x4>; 404 bits = <2 12>; 405 }; 406 cpr_efuse_quot3: quot3@230 { 407 reg = <0x230 0x4>; 408 bits = <0 12>; 409 }; 410 cpr_efuse_ring1: ring1@228 { 411 reg = <0x228 0x4>; 412 bits = <0 3>; 413 }; 414 cpr_efuse_ring2: ring2@228 { 415 reg = <0x228 0x4>; 416 bits = <4 3>; 417 }; 418 cpr_efuse_ring3: ring3@229 { 419 reg = <0x229 0x4>; 420 bits = <0 3>; 421 }; 422 cpr_efuse_revision: revision@218 { 423 reg = <0x218 0x4>; 424 bits = <3 3>; 425 }; 426 }; 427 428 rng: rng@e3000 { 429 compatible = "qcom,prng-ee"; 430 reg = <0x000e3000 0x1000>; 431 clocks = <&gcc GCC_PRNG_AHB_CLK>; 432 clock-names = "core"; 433 }; 434 435 bimc: interconnect@400000 { 436 reg = <0x00400000 0x80000>; 437 compatible = "qcom,qcs404-bimc"; 438 #interconnect-cells = <1>; 439 clock-names = "bus", "bus_a"; 440 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 441 <&rpmcc RPM_SMD_BIMC_A_CLK>; 442 }; 443 444 tsens: thermal-sensor@4a9000 { 445 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 446 reg = <0x004a9000 0x1000>, /* TM */ 447 <0x004a8000 0x1000>; /* SROT */ 448 nvmem-cells = <&tsens_caldata>; 449 nvmem-cell-names = "calib"; 450 #qcom,sensors = <10>; 451 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 452 interrupt-names = "uplow"; 453 #thermal-sensor-cells = <1>; 454 }; 455 456 pcnoc: interconnect@500000 { 457 reg = <0x00500000 0x15080>; 458 compatible = "qcom,qcs404-pcnoc"; 459 #interconnect-cells = <1>; 460 clock-names = "bus", "bus_a"; 461 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 462 <&rpmcc RPM_SMD_PNOC_A_CLK>; 463 }; 464 465 snoc: interconnect@580000 { 466 reg = <0x00580000 0x23080>; 467 compatible = "qcom,qcs404-snoc"; 468 #interconnect-cells = <1>; 469 clock-names = "bus", "bus_a"; 470 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 471 <&rpmcc RPM_SMD_SNOC_A_CLK>; 472 }; 473 474 remoteproc_cdsp: remoteproc@b00000 { 475 compatible = "qcom,qcs404-cdsp-pas"; 476 reg = <0x00b00000 0x4040>; 477 478 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 479 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 480 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 481 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 482 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 483 interrupt-names = "wdog", "fatal", "ready", 484 "handover", "stop-ack"; 485 486 clocks = <&xo_board>, 487 <&gcc GCC_CDSP_CFG_AHB_CLK>, 488 <&gcc GCC_CDSP_TBU_CLK>, 489 <&gcc GCC_BIMC_CDSP_CLK>, 490 <&turingcc TURING_WRAPPER_AON_CLK>, 491 <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 492 <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 493 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 494 clock-names = "xo", 495 "sway", 496 "tbu", 497 "bimc", 498 "ahb_aon", 499 "q6ss_slave", 500 "q6ss_master", 501 "q6_axim"; 502 503 resets = <&gcc GCC_CDSP_RESTART>; 504 reset-names = "restart"; 505 506 qcom,halt-regs = <&tcsr 0x19004>; 507 508 memory-region = <&cdsp_fw_mem>; 509 510 qcom,smem-states = <&cdsp_smp2p_out 0>; 511 qcom,smem-state-names = "stop"; 512 513 status = "disabled"; 514 515 glink-edge { 516 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 517 518 qcom,remote-pid = <5>; 519 mboxes = <&apcs_glb 12>; 520 521 label = "cdsp"; 522 }; 523 }; 524 525 usb3: usb@7678800 { 526 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 527 reg = <0x07678800 0x400>; 528 #address-cells = <1>; 529 #size-cells = <1>; 530 ranges; 531 clocks = <&gcc GCC_USB30_MASTER_CLK>, 532 <&gcc GCC_SYS_NOC_USB3_CLK>, 533 <&gcc GCC_USB30_SLEEP_CLK>, 534 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 535 clock-names = "core", "iface", "sleep", "mock_utmi"; 536 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 537 <&gcc GCC_USB30_MASTER_CLK>; 538 assigned-clock-rates = <19200000>, <200000000>; 539 status = "disabled"; 540 541 usb3_dwc3: usb@7580000 { 542 compatible = "snps,dwc3"; 543 reg = <0x07580000 0xcd00>; 544 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 545 phys = <&usb2_phy_prim>, <&usb3_phy>; 546 phy-names = "usb2-phy", "usb3-phy"; 547 snps,has-lpm-erratum; 548 snps,hird-threshold = /bits/ 8 <0x10>; 549 snps,usb3_lpm_capable; 550 dr_mode = "otg"; 551 }; 552 }; 553 554 usb2: usb@79b8800 { 555 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 556 reg = <0x079b8800 0x400>; 557 #address-cells = <1>; 558 #size-cells = <1>; 559 ranges; 560 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, 561 <&gcc GCC_PCNOC_USB2_CLK>, 562 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, 563 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 564 clock-names = "core", "iface", "sleep", "mock_utmi"; 565 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 566 <&gcc GCC_USB_HS_SYSTEM_CLK>; 567 assigned-clock-rates = <19200000>, <133333333>; 568 status = "disabled"; 569 570 usb@78c0000 { 571 compatible = "snps,dwc3"; 572 reg = <0x078c0000 0xcc00>; 573 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 574 phys = <&usb2_phy_sec>; 575 phy-names = "usb2-phy"; 576 snps,has-lpm-erratum; 577 snps,hird-threshold = /bits/ 8 <0x10>; 578 snps,usb3_lpm_capable; 579 dr_mode = "peripheral"; 580 }; 581 }; 582 583 tlmm: pinctrl@1000000 { 584 compatible = "qcom,qcs404-pinctrl"; 585 reg = <0x01000000 0x200000>, 586 <0x01300000 0x200000>, 587 <0x07b00000 0x200000>; 588 reg-names = "south", "north", "east"; 589 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 590 gpio-ranges = <&tlmm 0 0 120>; 591 gpio-controller; 592 #gpio-cells = <2>; 593 interrupt-controller; 594 #interrupt-cells = <2>; 595 596 blsp1_i2c0_default: blsp1-i2c0-default { 597 pins = "gpio32", "gpio33"; 598 function = "blsp_i2c0"; 599 }; 600 601 blsp1_i2c1_default: blsp1-i2c1-default { 602 pins = "gpio24", "gpio25"; 603 function = "blsp_i2c1"; 604 }; 605 606 blsp1_i2c2_default: blsp1-i2c2-default { 607 sda { 608 pins = "gpio19"; 609 function = "blsp_i2c_sda_a2"; 610 }; 611 612 scl { 613 pins = "gpio20"; 614 function = "blsp_i2c_scl_a2"; 615 }; 616 }; 617 618 blsp1_i2c3_default: blsp1-i2c3-default { 619 pins = "gpio84", "gpio85"; 620 function = "blsp_i2c3"; 621 }; 622 623 blsp1_i2c4_default: blsp1-i2c4-default { 624 pins = "gpio117", "gpio118"; 625 function = "blsp_i2c4"; 626 }; 627 628 blsp1_uart0_default: blsp1-uart0-default { 629 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 630 function = "blsp_uart0"; 631 }; 632 633 blsp1_uart1_default: blsp1-uart1-default { 634 pins = "gpio22", "gpio23"; 635 function = "blsp_uart1"; 636 }; 637 638 blsp1_uart2_default: blsp1-uart2-default { 639 rx { 640 pins = "gpio18"; 641 function = "blsp_uart_rx_a2"; 642 }; 643 644 tx { 645 pins = "gpio17"; 646 function = "blsp_uart_tx_a2"; 647 }; 648 }; 649 650 blsp1_uart3_default: blsp1-uart3-default { 651 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 652 function = "blsp_uart3"; 653 }; 654 655 blsp2_i2c0_default: blsp2-i2c0-default { 656 pins = "gpio28", "gpio29"; 657 function = "blsp_i2c5"; 658 }; 659 660 blsp1_spi0_default: blsp1-spi0-default { 661 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 662 function = "blsp_spi0"; 663 }; 664 665 blsp1_spi1_default: blsp1-spi1-default { 666 mosi { 667 pins = "gpio22"; 668 function = "blsp_spi_mosi_a1"; 669 }; 670 671 miso { 672 pins = "gpio23"; 673 function = "blsp_spi_miso_a1"; 674 }; 675 676 cs_n { 677 pins = "gpio24"; 678 function = "blsp_spi_cs_n_a1"; 679 }; 680 681 clk { 682 pins = "gpio25"; 683 function = "blsp_spi_clk_a1"; 684 }; 685 }; 686 687 blsp1_spi2_default: blsp1-spi2-default { 688 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 689 function = "blsp_spi2"; 690 }; 691 692 blsp1_spi3_default: blsp1-spi3-default { 693 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 694 function = "blsp_spi3"; 695 }; 696 697 blsp1_spi4_default: blsp1-spi4-default { 698 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 699 function = "blsp_spi4"; 700 }; 701 702 blsp2_spi0_default: blsp2-spi0-default { 703 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 704 function = "blsp_spi5"; 705 }; 706 707 blsp2_uart0_default: blsp2-uart0-default { 708 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 709 function = "blsp_uart5"; 710 }; 711 }; 712 713 gcc: clock-controller@1800000 { 714 compatible = "qcom,gcc-qcs404"; 715 reg = <0x01800000 0x80000>; 716 #clock-cells = <1>; 717 #reset-cells = <1>; 718 719 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 720 assigned-clock-rates = <19200000>; 721 }; 722 723 tcsr_mutex: hwlock@1905000 { 724 compatible = "qcom,tcsr-mutex"; 725 reg = <0x01905000 0x20000>; 726 #hwlock-cells = <1>; 727 }; 728 729 tcsr: syscon@1937000 { 730 compatible = "qcom,qcs404-tcsr", "syscon"; 731 reg = <0x01937000 0x25000>; 732 }; 733 734 sram@290000 { 735 compatible = "qcom,rpm-stats"; 736 reg = <0x00290000 0x10000>; 737 }; 738 739 spmi_bus: spmi@200f000 { 740 compatible = "qcom,spmi-pmic-arb"; 741 reg = <0x0200f000 0x001000>, 742 <0x02400000 0x800000>, 743 <0x02c00000 0x800000>, 744 <0x03800000 0x200000>, 745 <0x0200a000 0x002100>; 746 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 747 interrupt-names = "periph_irq"; 748 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 749 qcom,ee = <0>; 750 qcom,channel = <0>; 751 #address-cells = <2>; 752 #size-cells = <0>; 753 interrupt-controller; 754 #interrupt-cells = <4>; 755 }; 756 757 remoteproc_wcss: remoteproc@7400000 { 758 compatible = "qcom,qcs404-wcss-pas"; 759 reg = <0x07400000 0x4040>; 760 761 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 762 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 763 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 764 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 765 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 766 interrupt-names = "wdog", "fatal", "ready", 767 "handover", "stop-ack"; 768 769 clocks = <&xo_board>; 770 clock-names = "xo"; 771 772 memory-region = <&wlan_fw_mem>; 773 774 qcom,smem-states = <&wcss_smp2p_out 0>; 775 qcom,smem-state-names = "stop"; 776 777 status = "disabled"; 778 779 glink-edge { 780 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 781 782 qcom,remote-pid = <1>; 783 mboxes = <&apcs_glb 16>; 784 785 label = "wcss"; 786 }; 787 }; 788 789 pcie_phy: phy@7786000 { 790 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 791 reg = <0x07786000 0xb8>; 792 793 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 794 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 795 <&gcc 21>; 796 reset-names = "phy", "pipe"; 797 798 clock-output-names = "pcie_0_pipe_clk"; 799 #phy-cells = <0>; 800 801 status = "disabled"; 802 }; 803 804 sdcc1: mmc@7804000 { 805 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 806 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 807 reg-names = "hc", "cqhci"; 808 809 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 811 interrupt-names = "hc_irq", "pwr_irq"; 812 813 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 814 <&gcc GCC_SDCC1_APPS_CLK>, 815 <&xo_board>; 816 clock-names = "iface", "core", "xo"; 817 818 status = "disabled"; 819 }; 820 821 blsp1_dma: dma-controller@7884000 { 822 compatible = "qcom,bam-v1.7.0"; 823 reg = <0x07884000 0x25000>; 824 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 826 clock-names = "bam_clk"; 827 #dma-cells = <1>; 828 qcom,ee = <0>; 829 status = "okay"; 830 }; 831 832 blsp1_uart0: serial@78af000 { 833 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 834 reg = <0x078af000 0x200>; 835 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 837 clock-names = "core", "iface"; 838 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 839 dma-names = "tx", "rx"; 840 pinctrl-names = "default"; 841 pinctrl-0 = <&blsp1_uart0_default>; 842 status = "disabled"; 843 }; 844 845 blsp1_uart1: serial@78b0000 { 846 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 847 reg = <0x078b0000 0x200>; 848 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 850 clock-names = "core", "iface"; 851 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 852 dma-names = "tx", "rx"; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&blsp1_uart1_default>; 855 status = "disabled"; 856 }; 857 858 blsp1_uart2: serial@78b1000 { 859 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 860 reg = <0x078b1000 0x200>; 861 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 863 clock-names = "core", "iface"; 864 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 865 dma-names = "tx", "rx"; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&blsp1_uart2_default>; 868 status = "okay"; 869 }; 870 871 ethernet: ethernet@7a80000 { 872 compatible = "qcom,qcs404-ethqos"; 873 reg = <0x07a80000 0x10000>, 874 <0x07a96000 0x100>; 875 reg-names = "stmmaceth", "rgmii"; 876 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 877 clocks = <&gcc GCC_ETH_AXI_CLK>, 878 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 879 <&gcc GCC_ETH_PTP_CLK>, 880 <&gcc GCC_ETH_RGMII_CLK>; 881 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "macirq", "eth_lpi"; 884 885 snps,tso; 886 rx-fifo-depth = <4096>; 887 tx-fifo-depth = <4096>; 888 889 status = "disabled"; 890 }; 891 892 wifi: wifi@a000000 { 893 compatible = "qcom,wcn3990-wifi"; 894 reg = <0xa000000 0x800000>; 895 reg-names = "membase"; 896 memory-region = <&wlan_msa_mem>; 897 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 909 status = "disabled"; 910 }; 911 912 blsp1_uart3: serial@78b2000 { 913 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 914 reg = <0x078b2000 0x200>; 915 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 917 clock-names = "core", "iface"; 918 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 919 dma-names = "tx", "rx"; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&blsp1_uart3_default>; 922 status = "disabled"; 923 }; 924 925 blsp1_i2c0: i2c@78b5000 { 926 compatible = "qcom,i2c-qup-v2.2.1"; 927 reg = <0x078b5000 0x600>; 928 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, 930 <&gcc GCC_BLSP1_AHB_CLK>; 931 clock-names = "core", "iface"; 932 pinctrl-names = "default"; 933 pinctrl-0 = <&blsp1_i2c0_default>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 status = "disabled"; 937 }; 938 939 blsp1_spi0: spi@78b5000 { 940 compatible = "qcom,spi-qup-v2.2.1"; 941 reg = <0x078b5000 0x600>; 942 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, 944 <&gcc GCC_BLSP1_AHB_CLK>; 945 clock-names = "core", "iface"; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&blsp1_spi0_default>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 }; 952 953 blsp1_i2c1: i2c@78b6000 { 954 compatible = "qcom,i2c-qup-v2.2.1"; 955 reg = <0x078b6000 0x600>; 956 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 958 <&gcc GCC_BLSP1_AHB_CLK>; 959 clock-names = "core", "iface"; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&blsp1_i2c1_default>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 blsp1_spi1: spi@78b6000 { 968 compatible = "qcom,spi-qup-v2.2.1"; 969 reg = <0x078b6000 0x600>; 970 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 972 <&gcc GCC_BLSP1_AHB_CLK>; 973 clock-names = "core", "iface"; 974 pinctrl-names = "default"; 975 pinctrl-0 = <&blsp1_spi1_default>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 status = "disabled"; 979 }; 980 981 blsp1_i2c2: i2c@78b7000 { 982 compatible = "qcom,i2c-qup-v2.2.1"; 983 reg = <0x078b7000 0x600>; 984 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 986 <&gcc GCC_BLSP1_AHB_CLK>; 987 clock-names = "core", "iface"; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&blsp1_i2c2_default>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 status = "disabled"; 993 }; 994 995 blsp1_spi2: spi@78b7000 { 996 compatible = "qcom,spi-qup-v2.2.1"; 997 reg = <0x078b7000 0x600>; 998 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1000 <&gcc GCC_BLSP1_AHB_CLK>; 1001 clock-names = "core", "iface"; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&blsp1_spi2_default>; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 status = "disabled"; 1007 }; 1008 1009 blsp1_i2c3: i2c@78b8000 { 1010 compatible = "qcom,i2c-qup-v2.2.1"; 1011 reg = <0x078b8000 0x600>; 1012 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1014 <&gcc GCC_BLSP1_AHB_CLK>; 1015 clock-names = "core", "iface"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&blsp1_i2c3_default>; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 status = "disabled"; 1021 }; 1022 1023 blsp1_spi3: spi@78b8000 { 1024 compatible = "qcom,spi-qup-v2.2.1"; 1025 reg = <0x078b8000 0x600>; 1026 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1028 <&gcc GCC_BLSP1_AHB_CLK>; 1029 clock-names = "core", "iface"; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&blsp1_spi3_default>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 blsp1_i2c4: i2c@78b9000 { 1038 compatible = "qcom,i2c-qup-v2.2.1"; 1039 reg = <0x078b9000 0x600>; 1040 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1042 <&gcc GCC_BLSP1_AHB_CLK>; 1043 clock-names = "core", "iface"; 1044 pinctrl-names = "default"; 1045 pinctrl-0 = <&blsp1_i2c4_default>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 blsp1_spi4: spi@78b9000 { 1052 compatible = "qcom,spi-qup-v2.2.1"; 1053 reg = <0x078b9000 0x600>; 1054 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1056 <&gcc GCC_BLSP1_AHB_CLK>; 1057 clock-names = "core", "iface"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&blsp1_spi4_default>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 status = "disabled"; 1063 }; 1064 1065 blsp2_dma: dma-controller@7ac4000 { 1066 compatible = "qcom,bam-v1.7.0"; 1067 reg = <0x07ac4000 0x17000>; 1068 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1070 clock-names = "bam_clk"; 1071 #dma-cells = <1>; 1072 qcom,ee = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 blsp2_uart0: serial@7aef000 { 1077 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1078 reg = <0x07aef000 0x200>; 1079 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1081 clock-names = "core", "iface"; 1082 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1083 dma-names = "tx", "rx"; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&blsp2_uart0_default>; 1086 status = "disabled"; 1087 }; 1088 1089 blsp2_i2c0: i2c@7af5000 { 1090 compatible = "qcom,i2c-qup-v2.2.1"; 1091 reg = <0x07af5000 0x600>; 1092 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, 1094 <&gcc GCC_BLSP2_AHB_CLK>; 1095 clock-names = "core", "iface"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&blsp2_i2c0_default>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 status = "disabled"; 1101 }; 1102 1103 blsp2_spi0: spi@7af5000 { 1104 compatible = "qcom,spi-qup-v2.2.1"; 1105 reg = <0x07af5000 0x600>; 1106 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, 1108 <&gcc GCC_BLSP2_AHB_CLK>; 1109 clock-names = "core", "iface"; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&blsp2_spi0_default>; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 sram@8600000 { 1118 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; 1119 reg = <0x08600000 0x1000>; 1120 1121 #address-cells = <1>; 1122 #size-cells = <1>; 1123 1124 ranges = <0 0x08600000 0x1000>; 1125 1126 pil-reloc@94c { 1127 compatible = "qcom,pil-reloc-info"; 1128 reg = <0x94c 0xc8>; 1129 }; 1130 }; 1131 1132 intc: interrupt-controller@b000000 { 1133 compatible = "qcom,msm-qgic2"; 1134 interrupt-controller; 1135 #interrupt-cells = <3>; 1136 reg = <0x0b000000 0x1000>, 1137 <0x0b002000 0x1000>; 1138 }; 1139 1140 apcs_glb: mailbox@b011000 { 1141 compatible = "qcom,qcs404-apcs-apps-global", "syscon"; 1142 reg = <0x0b011000 0x1000>; 1143 #mbox-cells = <1>; 1144 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 1145 clock-names = "pll", "aux"; 1146 #clock-cells = <0>; 1147 }; 1148 1149 apcs_hfpll: clock-controller@b016000 { 1150 compatible = "qcom,hfpll"; 1151 reg = <0x0b016000 0x30>; 1152 #clock-cells = <0>; 1153 clock-output-names = "apcs_hfpll"; 1154 clocks = <&xo_board>; 1155 clock-names = "xo"; 1156 }; 1157 1158 watchdog@b017000 { 1159 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1160 reg = <0x0b017000 0x1000>; 1161 clocks = <&sleep_clk>; 1162 }; 1163 1164 cpr: power-controller@b018000 { 1165 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 1166 reg = <0x0b018000 0x1000>; 1167 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 1168 clocks = <&xo_board>; 1169 clock-names = "ref"; 1170 vdd-apc-supply = <&pms405_s3>; 1171 #power-domain-cells = <0>; 1172 operating-points-v2 = <&cpr_opp_table>; 1173 acc-syscon = <&tcsr>; 1174 1175 nvmem-cells = <&cpr_efuse_quot_offset1>, 1176 <&cpr_efuse_quot_offset2>, 1177 <&cpr_efuse_quot_offset3>, 1178 <&cpr_efuse_init_voltage1>, 1179 <&cpr_efuse_init_voltage2>, 1180 <&cpr_efuse_init_voltage3>, 1181 <&cpr_efuse_quot1>, 1182 <&cpr_efuse_quot2>, 1183 <&cpr_efuse_quot3>, 1184 <&cpr_efuse_ring1>, 1185 <&cpr_efuse_ring2>, 1186 <&cpr_efuse_ring3>, 1187 <&cpr_efuse_revision>; 1188 nvmem-cell-names = "cpr_quotient_offset1", 1189 "cpr_quotient_offset2", 1190 "cpr_quotient_offset3", 1191 "cpr_init_voltage1", 1192 "cpr_init_voltage2", 1193 "cpr_init_voltage3", 1194 "cpr_quotient1", 1195 "cpr_quotient2", 1196 "cpr_quotient3", 1197 "cpr_ring_osc1", 1198 "cpr_ring_osc2", 1199 "cpr_ring_osc3", 1200 "cpr_fuse_revision"; 1201 }; 1202 1203 timer@b120000 { 1204 #address-cells = <1>; 1205 #size-cells = <1>; 1206 ranges; 1207 compatible = "arm,armv7-timer-mem"; 1208 reg = <0x0b120000 0x1000>; 1209 clock-frequency = <19200000>; 1210 1211 frame@b121000 { 1212 frame-number = <0>; 1213 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1215 reg = <0x0b121000 0x1000>, 1216 <0x0b122000 0x1000>; 1217 }; 1218 1219 frame@b123000 { 1220 frame-number = <1>; 1221 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1222 reg = <0x0b123000 0x1000>; 1223 status = "disabled"; 1224 }; 1225 1226 frame@b124000 { 1227 frame-number = <2>; 1228 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1229 reg = <0x0b124000 0x1000>; 1230 status = "disabled"; 1231 }; 1232 1233 frame@b125000 { 1234 frame-number = <3>; 1235 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1236 reg = <0x0b125000 0x1000>; 1237 status = "disabled"; 1238 }; 1239 1240 frame@b126000 { 1241 frame-number = <4>; 1242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1243 reg = <0x0b126000 0x1000>; 1244 status = "disabled"; 1245 }; 1246 1247 frame@b127000 { 1248 frame-number = <5>; 1249 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1250 reg = <0xb127000 0x1000>; 1251 status = "disabled"; 1252 }; 1253 1254 frame@b128000 { 1255 frame-number = <6>; 1256 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1257 reg = <0x0b128000 0x1000>; 1258 status = "disabled"; 1259 }; 1260 }; 1261 1262 remoteproc_adsp: remoteproc@c700000 { 1263 compatible = "qcom,qcs404-adsp-pas"; 1264 reg = <0x0c700000 0x4040>; 1265 1266 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 1267 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1268 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1269 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1270 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1271 interrupt-names = "wdog", "fatal", "ready", 1272 "handover", "stop-ack"; 1273 1274 clocks = <&xo_board>; 1275 clock-names = "xo"; 1276 1277 memory-region = <&adsp_fw_mem>; 1278 1279 qcom,smem-states = <&adsp_smp2p_out 0>; 1280 qcom,smem-state-names = "stop"; 1281 1282 status = "disabled"; 1283 1284 glink-edge { 1285 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1286 1287 qcom,remote-pid = <2>; 1288 mboxes = <&apcs_glb 8>; 1289 1290 label = "adsp"; 1291 }; 1292 }; 1293 1294 pcie: pci@10000000 { 1295 compatible = "qcom,pcie-qcs404"; 1296 reg = <0x10000000 0xf1d>, 1297 <0x10000f20 0xa8>, 1298 <0x07780000 0x2000>, 1299 <0x10001000 0x2000>; 1300 reg-names = "dbi", "elbi", "parf", "config"; 1301 device_type = "pci"; 1302 linux,pci-domain = <0>; 1303 bus-range = <0x00 0xff>; 1304 num-lanes = <1>; 1305 #address-cells = <3>; 1306 #size-cells = <2>; 1307 1308 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ 1309 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ 1310 1311 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1312 interrupt-names = "msi"; 1313 #interrupt-cells = <1>; 1314 interrupt-map-mask = <0 0 0 0x7>; 1315 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1316 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1317 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1318 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1319 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1320 <&gcc GCC_PCIE_0_AUX_CLK>, 1321 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1322 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1323 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1324 1325 resets = <&gcc 18>, 1326 <&gcc 17>, 1327 <&gcc 15>, 1328 <&gcc 19>, 1329 <&gcc GCC_PCIE_0_BCR>, 1330 <&gcc 16>; 1331 reset-names = "axi_m", 1332 "axi_s", 1333 "axi_m_sticky", 1334 "pipe_sticky", 1335 "pwr", 1336 "ahb"; 1337 1338 phys = <&pcie_phy>; 1339 phy-names = "pciephy"; 1340 1341 status = "disabled"; 1342 }; 1343 }; 1344 1345 timer { 1346 compatible = "arm,armv8-timer"; 1347 interrupts = <GIC_PPI 2 0xff08>, 1348 <GIC_PPI 3 0xff08>, 1349 <GIC_PPI 4 0xff08>, 1350 <GIC_PPI 1 0xff08>; 1351 }; 1352 1353 smp2p-adsp { 1354 compatible = "qcom,smp2p"; 1355 qcom,smem = <443>, <429>; 1356 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1357 mboxes = <&apcs_glb 10>; 1358 qcom,local-pid = <0>; 1359 qcom,remote-pid = <2>; 1360 1361 adsp_smp2p_out: master-kernel { 1362 qcom,entry-name = "master-kernel"; 1363 #qcom,smem-state-cells = <1>; 1364 }; 1365 1366 adsp_smp2p_in: slave-kernel { 1367 qcom,entry-name = "slave-kernel"; 1368 interrupt-controller; 1369 #interrupt-cells = <2>; 1370 }; 1371 }; 1372 1373 smp2p-cdsp { 1374 compatible = "qcom,smp2p"; 1375 qcom,smem = <94>, <432>; 1376 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1377 mboxes = <&apcs_glb 14>; 1378 qcom,local-pid = <0>; 1379 qcom,remote-pid = <5>; 1380 1381 cdsp_smp2p_out: master-kernel { 1382 qcom,entry-name = "master-kernel"; 1383 #qcom,smem-state-cells = <1>; 1384 }; 1385 1386 cdsp_smp2p_in: slave-kernel { 1387 qcom,entry-name = "slave-kernel"; 1388 interrupt-controller; 1389 #interrupt-cells = <2>; 1390 }; 1391 }; 1392 1393 smp2p-wcss { 1394 compatible = "qcom,smp2p"; 1395 qcom,smem = <435>, <428>; 1396 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1397 mboxes = <&apcs_glb 18>; 1398 qcom,local-pid = <0>; 1399 qcom,remote-pid = <1>; 1400 1401 wcss_smp2p_out: master-kernel { 1402 qcom,entry-name = "master-kernel"; 1403 #qcom,smem-state-cells = <1>; 1404 }; 1405 1406 wcss_smp2p_in: slave-kernel { 1407 qcom,entry-name = "slave-kernel"; 1408 interrupt-controller; 1409 #interrupt-cells = <2>; 1410 }; 1411 }; 1412 1413 thermal-zones { 1414 aoss-thermal { 1415 polling-delay-passive = <250>; 1416 polling-delay = <1000>; 1417 1418 thermal-sensors = <&tsens 0>; 1419 1420 trips { 1421 aoss_alert0: trip-point0 { 1422 temperature = <105000>; 1423 hysteresis = <2000>; 1424 type = "hot"; 1425 }; 1426 }; 1427 }; 1428 1429 q6-hvx-thermal { 1430 polling-delay-passive = <250>; 1431 polling-delay = <1000>; 1432 1433 thermal-sensors = <&tsens 1>; 1434 1435 trips { 1436 q6_hvx_alert0: trip-point0 { 1437 temperature = <105000>; 1438 hysteresis = <2000>; 1439 type = "hot"; 1440 }; 1441 }; 1442 }; 1443 1444 lpass-thermal { 1445 polling-delay-passive = <250>; 1446 polling-delay = <1000>; 1447 1448 thermal-sensors = <&tsens 2>; 1449 1450 trips { 1451 lpass_alert0: trip-point0 { 1452 temperature = <105000>; 1453 hysteresis = <2000>; 1454 type = "hot"; 1455 }; 1456 }; 1457 }; 1458 1459 wlan-thermal { 1460 polling-delay-passive = <250>; 1461 polling-delay = <1000>; 1462 1463 thermal-sensors = <&tsens 3>; 1464 1465 trips { 1466 wlan_alert0: trip-point0 { 1467 temperature = <105000>; 1468 hysteresis = <2000>; 1469 type = "hot"; 1470 }; 1471 }; 1472 }; 1473 1474 cluster-thermal { 1475 polling-delay-passive = <250>; 1476 polling-delay = <1000>; 1477 1478 thermal-sensors = <&tsens 4>; 1479 1480 trips { 1481 cluster_alert0: trip-point0 { 1482 temperature = <95000>; 1483 hysteresis = <2000>; 1484 type = "hot"; 1485 }; 1486 cluster_alert1: trip-point1 { 1487 temperature = <105000>; 1488 hysteresis = <2000>; 1489 type = "passive"; 1490 }; 1491 cluster_crit: cluster_crit { 1492 temperature = <120000>; 1493 hysteresis = <2000>; 1494 type = "critical"; 1495 }; 1496 }; 1497 cooling-maps { 1498 map0 { 1499 trip = <&cluster_alert1>; 1500 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1501 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1502 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1503 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1504 }; 1505 }; 1506 }; 1507 1508 cpu0-thermal { 1509 polling-delay-passive = <250>; 1510 polling-delay = <1000>; 1511 1512 thermal-sensors = <&tsens 5>; 1513 1514 trips { 1515 cpu0_alert0: trip-point0 { 1516 temperature = <95000>; 1517 hysteresis = <2000>; 1518 type = "hot"; 1519 }; 1520 cpu0_alert1: trip-point1 { 1521 temperature = <105000>; 1522 hysteresis = <2000>; 1523 type = "passive"; 1524 }; 1525 cpu0_crit: cpu_crit { 1526 temperature = <120000>; 1527 hysteresis = <2000>; 1528 type = "critical"; 1529 }; 1530 }; 1531 cooling-maps { 1532 map0 { 1533 trip = <&cpu0_alert1>; 1534 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1535 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1536 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1537 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1538 }; 1539 }; 1540 }; 1541 1542 cpu1-thermal { 1543 polling-delay-passive = <250>; 1544 polling-delay = <1000>; 1545 1546 thermal-sensors = <&tsens 6>; 1547 1548 trips { 1549 cpu1_alert0: trip-point0 { 1550 temperature = <95000>; 1551 hysteresis = <2000>; 1552 type = "hot"; 1553 }; 1554 cpu1_alert1: trip-point1 { 1555 temperature = <105000>; 1556 hysteresis = <2000>; 1557 type = "passive"; 1558 }; 1559 cpu1_crit: cpu_crit { 1560 temperature = <120000>; 1561 hysteresis = <2000>; 1562 type = "critical"; 1563 }; 1564 }; 1565 cooling-maps { 1566 map0 { 1567 trip = <&cpu1_alert1>; 1568 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1569 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1570 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1571 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1572 }; 1573 }; 1574 }; 1575 1576 cpu2-thermal { 1577 polling-delay-passive = <250>; 1578 polling-delay = <1000>; 1579 1580 thermal-sensors = <&tsens 7>; 1581 1582 trips { 1583 cpu2_alert0: trip-point0 { 1584 temperature = <95000>; 1585 hysteresis = <2000>; 1586 type = "hot"; 1587 }; 1588 cpu2_alert1: trip-point1 { 1589 temperature = <105000>; 1590 hysteresis = <2000>; 1591 type = "passive"; 1592 }; 1593 cpu2_crit: cpu_crit { 1594 temperature = <120000>; 1595 hysteresis = <2000>; 1596 type = "critical"; 1597 }; 1598 }; 1599 cooling-maps { 1600 map0 { 1601 trip = <&cpu2_alert1>; 1602 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1603 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1604 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1605 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1606 }; 1607 }; 1608 }; 1609 1610 cpu3-thermal { 1611 polling-delay-passive = <250>; 1612 polling-delay = <1000>; 1613 1614 thermal-sensors = <&tsens 8>; 1615 1616 trips { 1617 cpu3_alert0: trip-point0 { 1618 temperature = <95000>; 1619 hysteresis = <2000>; 1620 type = "hot"; 1621 }; 1622 cpu3_alert1: trip-point1 { 1623 temperature = <105000>; 1624 hysteresis = <2000>; 1625 type = "passive"; 1626 }; 1627 cpu3_crit: cpu_crit { 1628 temperature = <120000>; 1629 hysteresis = <2000>; 1630 type = "critical"; 1631 }; 1632 }; 1633 cooling-maps { 1634 map0 { 1635 trip = <&cpu3_alert1>; 1636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1637 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1638 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1639 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1640 }; 1641 }; 1642 }; 1643 1644 gpu-thermal { 1645 polling-delay-passive = <250>; 1646 polling-delay = <1000>; 1647 1648 thermal-sensors = <&tsens 9>; 1649 1650 trips { 1651 gpu_alert0: trip-point0 { 1652 temperature = <95000>; 1653 hysteresis = <2000>; 1654 type = "hot"; 1655 }; 1656 }; 1657 }; 1658 }; 1659}; 1660