1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-qcs404.h> 8#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32768>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x100>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 next-level-cache = <&L2_0>; 46 #cooling-cells = <2>; 47 clocks = <&apcs_glb>; 48 operating-points-v2 = <&cpu_opp_table>; 49 power-domains = <&cpr>; 50 power-domain-names = "cpr"; 51 }; 52 53 CPU1: cpu@101 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x101>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 next-level-cache = <&L2_0>; 60 #cooling-cells = <2>; 61 clocks = <&apcs_glb>; 62 operating-points-v2 = <&cpu_opp_table>; 63 power-domains = <&cpr>; 64 power-domain-names = "cpr"; 65 }; 66 67 CPU2: cpu@102 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x102>; 71 enable-method = "psci"; 72 cpu-idle-states = <&CPU_SLEEP_0>; 73 next-level-cache = <&L2_0>; 74 #cooling-cells = <2>; 75 clocks = <&apcs_glb>; 76 operating-points-v2 = <&cpu_opp_table>; 77 power-domains = <&cpr>; 78 power-domain-names = "cpr"; 79 }; 80 81 CPU3: cpu@103 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x103>; 85 enable-method = "psci"; 86 cpu-idle-states = <&CPU_SLEEP_0>; 87 next-level-cache = <&L2_0>; 88 #cooling-cells = <2>; 89 clocks = <&apcs_glb>; 90 operating-points-v2 = <&cpu_opp_table>; 91 power-domains = <&cpr>; 92 power-domain-names = "cpr"; 93 }; 94 95 L2_0: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 }; 100 101 idle-states { 102 entry-method = "psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 idle-state-name = "standalone-power-collapse"; 107 arm,psci-suspend-param = <0x40000003>; 108 entry-latency-us = <125>; 109 exit-latency-us = <180>; 110 min-residency-us = <595>; 111 local-timer-stop; 112 }; 113 }; 114 }; 115 116 cpu_opp_table: opp-table-cpu { 117 compatible = "operating-points-v2-kryo-cpu"; 118 opp-shared; 119 120 opp-1094400000 { 121 opp-hz = /bits/ 64 <1094400000>; 122 required-opps = <&cpr_opp1>; 123 }; 124 opp-1248000000 { 125 opp-hz = /bits/ 64 <1248000000>; 126 required-opps = <&cpr_opp2>; 127 }; 128 opp-1401600000 { 129 opp-hz = /bits/ 64 <1401600000>; 130 required-opps = <&cpr_opp3>; 131 }; 132 }; 133 134 cpr_opp_table: opp-table-cpr { 135 compatible = "operating-points-v2-qcom-level"; 136 137 cpr_opp1: opp1 { 138 opp-level = <1>; 139 qcom,opp-fuse-level = <1>; 140 }; 141 cpr_opp2: opp2 { 142 opp-level = <2>; 143 qcom,opp-fuse-level = <2>; 144 }; 145 cpr_opp3: opp3 { 146 opp-level = <3>; 147 qcom,opp-fuse-level = <3>; 148 }; 149 }; 150 151 firmware { 152 scm: scm { 153 compatible = "qcom,scm-qcs404", "qcom,scm"; 154 #reset-cells = <1>; 155 }; 156 }; 157 158 memory@80000000 { 159 device_type = "memory"; 160 /* We expect the bootloader to fill in the size */ 161 reg = <0 0x80000000 0 0>; 162 }; 163 164 psci { 165 compatible = "arm,psci-1.0"; 166 method = "smc"; 167 }; 168 169 reserved-memory { 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges; 173 174 tz_apps_mem: memory@85900000 { 175 reg = <0 0x85900000 0 0x500000>; 176 no-map; 177 }; 178 179 xbl_mem: memory@85e00000 { 180 reg = <0 0x85e00000 0 0x100000>; 181 no-map; 182 }; 183 184 smem_region: memory@85f00000 { 185 reg = <0 0x85f00000 0 0x200000>; 186 no-map; 187 }; 188 189 tz_mem: memory@86100000 { 190 reg = <0 0x86100000 0 0x300000>; 191 no-map; 192 }; 193 194 wlan_fw_mem: memory@86400000 { 195 reg = <0 0x86400000 0 0x1100000>; 196 no-map; 197 }; 198 199 adsp_fw_mem: memory@87500000 { 200 reg = <0 0x87500000 0 0x1a00000>; 201 no-map; 202 }; 203 204 cdsp_fw_mem: memory@88f00000 { 205 reg = <0 0x88f00000 0 0x600000>; 206 no-map; 207 }; 208 209 wlan_msa_mem: memory@89500000 { 210 reg = <0 0x89500000 0 0x100000>; 211 no-map; 212 }; 213 214 uefi_mem: memory@9f800000 { 215 reg = <0 0x9f800000 0 0x800000>; 216 no-map; 217 }; 218 }; 219 220 rpm-glink { 221 compatible = "qcom,glink-rpm"; 222 223 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 224 qcom,rpm-msg-ram = <&rpm_msg_ram>; 225 mboxes = <&apcs_glb 0>; 226 227 rpm_requests: rpm-requests { 228 compatible = "qcom,rpm-qcs404"; 229 qcom,glink-channels = "rpm_requests"; 230 231 rpmcc: clock-controller { 232 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; 233 #clock-cells = <1>; 234 clocks = <&xo_board>; 235 clock-names = "xo"; 236 }; 237 238 rpmpd: power-controller { 239 compatible = "qcom,qcs404-rpmpd"; 240 #power-domain-cells = <1>; 241 operating-points-v2 = <&rpmpd_opp_table>; 242 243 rpmpd_opp_table: opp-table { 244 compatible = "operating-points-v2"; 245 246 rpmpd_opp_ret: opp1 { 247 opp-level = <16>; 248 }; 249 250 rpmpd_opp_ret_plus: opp2 { 251 opp-level = <32>; 252 }; 253 254 rpmpd_opp_min_svs: opp3 { 255 opp-level = <48>; 256 }; 257 258 rpmpd_opp_low_svs: opp4 { 259 opp-level = <64>; 260 }; 261 262 rpmpd_opp_svs: opp5 { 263 opp-level = <128>; 264 }; 265 266 rpmpd_opp_svs_plus: opp6 { 267 opp-level = <192>; 268 }; 269 270 rpmpd_opp_nom: opp7 { 271 opp-level = <256>; 272 }; 273 274 rpmpd_opp_nom_plus: opp8 { 275 opp-level = <320>; 276 }; 277 278 rpmpd_opp_turbo: opp9 { 279 opp-level = <384>; 280 }; 281 282 rpmpd_opp_turbo_no_cpr: opp10 { 283 opp-level = <416>; 284 }; 285 286 rpmpd_opp_turbo_plus: opp11 { 287 opp-level = <512>; 288 }; 289 }; 290 }; 291 }; 292 }; 293 294 smem { 295 compatible = "qcom,smem"; 296 297 memory-region = <&smem_region>; 298 qcom,rpm-msg-ram = <&rpm_msg_ram>; 299 300 hwlocks = <&tcsr_mutex 3>; 301 }; 302 303 soc: soc@0 { 304 #address-cells = <1>; 305 #size-cells = <1>; 306 ranges = <0 0 0 0xffffffff>; 307 compatible = "simple-bus"; 308 309 turingcc: clock-controller@800000 { 310 compatible = "qcom,qcs404-turingcc"; 311 reg = <0x00800000 0x30000>; 312 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 313 314 #clock-cells = <1>; 315 #reset-cells = <1>; 316 317 status = "disabled"; 318 }; 319 320 rpm_msg_ram: sram@60000 { 321 compatible = "qcom,rpm-msg-ram"; 322 reg = <0x00060000 0x6000>; 323 }; 324 325 usb3_phy: phy@78000 { 326 compatible = "qcom,usb-ss-28nm-phy"; 327 reg = <0x00078000 0x400>; 328 #phy-cells = <0>; 329 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 330 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 331 <&gcc GCC_USB3_PHY_PIPE_CLK>; 332 clock-names = "ref", "ahb", "pipe"; 333 resets = <&gcc GCC_USB3_PHY_BCR>, 334 <&gcc GCC_USB3PHY_PHY_BCR>; 335 reset-names = "com", "phy"; 336 status = "disabled"; 337 }; 338 339 usb2_phy_prim: phy@7a000 { 340 compatible = "qcom,usb-hs-28nm-femtophy"; 341 reg = <0x0007a000 0x200>; 342 #phy-cells = <0>; 343 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 344 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 345 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 346 clock-names = "ref", "ahb", "sleep"; 347 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 348 <&gcc GCC_USB2A_PHY_BCR>; 349 reset-names = "phy", "por"; 350 status = "disabled"; 351 }; 352 353 usb2_phy_sec: phy@7c000 { 354 compatible = "qcom,usb-hs-28nm-femtophy"; 355 reg = <0x0007c000 0x200>; 356 #phy-cells = <0>; 357 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 358 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 359 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 360 clock-names = "ref", "ahb", "sleep"; 361 resets = <&gcc GCC_QUSB2_PHY_BCR>, 362 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 363 reset-names = "phy", "por"; 364 status = "disabled"; 365 }; 366 367 qfprom: qfprom@a4000 { 368 compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; 369 reg = <0x000a4000 0x1000>; 370 #address-cells = <1>; 371 #size-cells = <1>; 372 cpr_efuse_speedbin: speedbin@13c { 373 reg = <0x13c 0x4>; 374 bits = <2 3>; 375 }; 376 377 tsens_s0_p1: s0-p1@1f8 { 378 reg = <0x1f8 0x1>; 379 bits = <0 6>; 380 }; 381 382 tsens_s0_p2: s0-p2@1f8 { 383 reg = <0x1f8 0x2>; 384 bits = <6 6>; 385 }; 386 387 tsens_s1_p1: s1-p1@1f9 { 388 reg = <0x1f9 0x2>; 389 bits = <4 6>; 390 }; 391 392 tsens_s1_p2: s1-p2@1fa { 393 reg = <0x1fa 0x1>; 394 bits = <2 6>; 395 }; 396 397 tsens_s2_p1: s2-p1@1fb { 398 reg = <0x1fb 0x1>; 399 bits = <0 6>; 400 }; 401 402 tsens_s2_p2: s2-p2@1fb { 403 reg = <0x1fb 0x2>; 404 bits = <6 6>; 405 }; 406 407 tsens_s3_p1: s3-p1@1fc { 408 reg = <0x1fc 0x2>; 409 bits = <4 6>; 410 }; 411 412 tsens_s3_p2: s3-p2@1fd { 413 reg = <0x1fd 0x1>; 414 bits = <2 6>; 415 }; 416 417 tsens_s4_p1: s4-p1@1fe { 418 reg = <0x1fe 0x1>; 419 bits = <0 6>; 420 }; 421 422 tsens_s4_p2: s4-p2@1fe { 423 reg = <0x1fe 0x2>; 424 bits = <6 6>; 425 }; 426 427 tsens_s5_p1: s5-p1@200 { 428 reg = <0x200 0x1>; 429 bits = <0 6>; 430 }; 431 432 tsens_s5_p2: s5-p2@200 { 433 reg = <0x200 0x2>; 434 bits = <6 6>; 435 }; 436 437 tsens_s6_p1: s6-p1@201 { 438 reg = <0x201 0x2>; 439 bits = <4 6>; 440 }; 441 442 tsens_s6_p2: s6-p2@202 { 443 reg = <0x202 0x1>; 444 bits = <2 6>; 445 }; 446 447 tsens_s7_p1: s7-p1@203 { 448 reg = <0x203 0x1>; 449 bits = <0 6>; 450 }; 451 452 tsens_s7_p2: s7-p2@203 { 453 reg = <0x203 0x2>; 454 bits = <6 6>; 455 }; 456 457 tsens_s8_p1: s8-p1@204 { 458 reg = <0x204 0x2>; 459 bits = <4 6>; 460 }; 461 462 tsens_s8_p2: s8-p2@205 { 463 reg = <0x205 0x1>; 464 bits = <2 6>; 465 }; 466 467 tsens_s9_p1: s9-p1@206 { 468 reg = <0x206 0x1>; 469 bits = <0 6>; 470 }; 471 472 tsens_s9_p2: s9-p2@206 { 473 reg = <0x206 0x2>; 474 bits = <6 6>; 475 }; 476 477 tsens_mode: mode@208 { 478 reg = <0x208 1>; 479 bits = <0 3>; 480 }; 481 482 tsens_base1: base1@208 { 483 reg = <0x208 2>; 484 bits = <3 8>; 485 }; 486 487 tsens_base2: base2@208 { 488 reg = <0x209 2>; 489 bits = <3 8>; 490 }; 491 492 cpr_efuse_quot_offset1: qoffset1@231 { 493 reg = <0x231 0x4>; 494 bits = <4 7>; 495 }; 496 cpr_efuse_quot_offset2: qoffset2@232 { 497 reg = <0x232 0x4>; 498 bits = <3 7>; 499 }; 500 cpr_efuse_quot_offset3: qoffset3@233 { 501 reg = <0x233 0x4>; 502 bits = <2 7>; 503 }; 504 cpr_efuse_init_voltage1: ivoltage1@229 { 505 reg = <0x229 0x4>; 506 bits = <4 6>; 507 }; 508 cpr_efuse_init_voltage2: ivoltage2@22a { 509 reg = <0x22a 0x4>; 510 bits = <2 6>; 511 }; 512 cpr_efuse_init_voltage3: ivoltage3@22b { 513 reg = <0x22b 0x4>; 514 bits = <0 6>; 515 }; 516 cpr_efuse_quot1: quot1@22b { 517 reg = <0x22b 0x4>; 518 bits = <6 12>; 519 }; 520 cpr_efuse_quot2: quot2@22d { 521 reg = <0x22d 0x4>; 522 bits = <2 12>; 523 }; 524 cpr_efuse_quot3: quot3@230 { 525 reg = <0x230 0x4>; 526 bits = <0 12>; 527 }; 528 cpr_efuse_ring1: ring1@228 { 529 reg = <0x228 0x4>; 530 bits = <0 3>; 531 }; 532 cpr_efuse_ring2: ring2@228 { 533 reg = <0x228 0x4>; 534 bits = <4 3>; 535 }; 536 cpr_efuse_ring3: ring3@229 { 537 reg = <0x229 0x4>; 538 bits = <0 3>; 539 }; 540 cpr_efuse_revision: revision@218 { 541 reg = <0x218 0x4>; 542 bits = <3 3>; 543 }; 544 }; 545 546 rng: rng@e3000 { 547 compatible = "qcom,prng-ee"; 548 reg = <0x000e3000 0x1000>; 549 clocks = <&gcc GCC_PRNG_AHB_CLK>; 550 clock-names = "core"; 551 }; 552 553 bimc: interconnect@400000 { 554 reg = <0x00400000 0x80000>; 555 compatible = "qcom,qcs404-bimc"; 556 #interconnect-cells = <1>; 557 clock-names = "bus", "bus_a"; 558 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 559 <&rpmcc RPM_SMD_BIMC_A_CLK>; 560 }; 561 562 tsens: thermal-sensor@4a9000 { 563 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 564 reg = <0x004a9000 0x1000>, /* TM */ 565 <0x004a8000 0x1000>; /* SROT */ 566 nvmem-cells = <&tsens_mode>, 567 <&tsens_base1>, <&tsens_base2>, 568 <&tsens_s0_p1>, <&tsens_s0_p2>, 569 <&tsens_s1_p1>, <&tsens_s1_p2>, 570 <&tsens_s2_p1>, <&tsens_s2_p2>, 571 <&tsens_s3_p1>, <&tsens_s3_p2>, 572 <&tsens_s4_p1>, <&tsens_s4_p2>, 573 <&tsens_s5_p1>, <&tsens_s5_p2>, 574 <&tsens_s6_p1>, <&tsens_s6_p2>, 575 <&tsens_s7_p1>, <&tsens_s7_p2>, 576 <&tsens_s8_p1>, <&tsens_s8_p2>, 577 <&tsens_s9_p1>, <&tsens_s9_p2>; 578 nvmem-cell-names = "mode", 579 "base1", "base2", 580 "s0_p1", "s0_p2", 581 "s1_p1", "s1_p2", 582 "s2_p1", "s2_p2", 583 "s3_p1", "s3_p2", 584 "s4_p1", "s4_p2", 585 "s5_p1", "s5_p2", 586 "s6_p1", "s6_p2", 587 "s7_p1", "s7_p2", 588 "s8_p1", "s8_p2", 589 "s9_p1", "s9_p2"; 590 #qcom,sensors = <10>; 591 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-names = "uplow"; 593 #thermal-sensor-cells = <1>; 594 }; 595 596 pcnoc: interconnect@500000 { 597 reg = <0x00500000 0x15080>; 598 compatible = "qcom,qcs404-pcnoc"; 599 #interconnect-cells = <1>; 600 clock-names = "bus", "bus_a"; 601 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 602 <&rpmcc RPM_SMD_PNOC_A_CLK>; 603 }; 604 605 snoc: interconnect@580000 { 606 reg = <0x00580000 0x23080>; 607 compatible = "qcom,qcs404-snoc"; 608 #interconnect-cells = <1>; 609 clock-names = "bus", "bus_a"; 610 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 611 <&rpmcc RPM_SMD_SNOC_A_CLK>; 612 }; 613 614 remoteproc_cdsp: remoteproc@b00000 { 615 compatible = "qcom,qcs404-cdsp-pas"; 616 reg = <0x00b00000 0x4040>; 617 618 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 619 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 620 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 621 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 622 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 623 interrupt-names = "wdog", "fatal", "ready", 624 "handover", "stop-ack"; 625 626 clocks = <&xo_board>; 627 clock-names = "xo"; 628 629 /* 630 * If the node was using the PIL binding, then include properties: 631 * clocks = <&xo_board>, 632 * <&gcc GCC_CDSP_CFG_AHB_CLK>, 633 * <&gcc GCC_CDSP_TBU_CLK>, 634 * <&gcc GCC_BIMC_CDSP_CLK>, 635 * <&turingcc TURING_WRAPPER_AON_CLK>, 636 * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 637 * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 638 * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 639 * clock-names = "xo", 640 * "sway", 641 * "tbu", 642 * "bimc", 643 * "ahb_aon", 644 * "q6ss_slave", 645 * "q6ss_master", 646 * "q6_axim"; 647 * resets = <&gcc GCC_CDSP_RESTART>; 648 * reset-names = "restart"; 649 * qcom,halt-regs = <&tcsr 0x19004>; 650 */ 651 652 memory-region = <&cdsp_fw_mem>; 653 654 qcom,smem-states = <&cdsp_smp2p_out 0>; 655 qcom,smem-state-names = "stop"; 656 657 status = "disabled"; 658 659 glink-edge { 660 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 661 662 qcom,remote-pid = <5>; 663 mboxes = <&apcs_glb 12>; 664 665 label = "cdsp"; 666 }; 667 }; 668 669 usb3: usb@7678800 { 670 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 671 reg = <0x07678800 0x400>; 672 #address-cells = <1>; 673 #size-cells = <1>; 674 ranges; 675 clocks = <&gcc GCC_USB30_MASTER_CLK>, 676 <&gcc GCC_SYS_NOC_USB3_CLK>, 677 <&gcc GCC_USB30_SLEEP_CLK>, 678 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 679 clock-names = "core", "iface", "sleep", "mock_utmi"; 680 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 681 <&gcc GCC_USB30_MASTER_CLK>; 682 assigned-clock-rates = <19200000>, <200000000>; 683 status = "disabled"; 684 685 usb3_dwc3: usb@7580000 { 686 compatible = "snps,dwc3"; 687 reg = <0x07580000 0xcd00>; 688 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 689 phys = <&usb2_phy_prim>, <&usb3_phy>; 690 phy-names = "usb2-phy", "usb3-phy"; 691 snps,has-lpm-erratum; 692 snps,hird-threshold = /bits/ 8 <0x10>; 693 snps,usb3_lpm_capable; 694 dr_mode = "otg"; 695 }; 696 }; 697 698 usb2: usb@79b8800 { 699 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 700 reg = <0x079b8800 0x400>; 701 #address-cells = <1>; 702 #size-cells = <1>; 703 ranges; 704 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, 705 <&gcc GCC_PCNOC_USB2_CLK>, 706 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, 707 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 708 clock-names = "core", "iface", "sleep", "mock_utmi"; 709 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 710 <&gcc GCC_USB_HS_SYSTEM_CLK>; 711 assigned-clock-rates = <19200000>, <133333333>; 712 status = "disabled"; 713 714 usb@78c0000 { 715 compatible = "snps,dwc3"; 716 reg = <0x078c0000 0xcc00>; 717 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 718 phys = <&usb2_phy_sec>; 719 phy-names = "usb2-phy"; 720 snps,has-lpm-erratum; 721 snps,hird-threshold = /bits/ 8 <0x10>; 722 snps,usb3_lpm_capable; 723 dr_mode = "peripheral"; 724 }; 725 }; 726 727 tlmm: pinctrl@1000000 { 728 compatible = "qcom,qcs404-pinctrl"; 729 reg = <0x01000000 0x200000>, 730 <0x01300000 0x200000>, 731 <0x07b00000 0x200000>; 732 reg-names = "south", "north", "east"; 733 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 734 gpio-ranges = <&tlmm 0 0 120>; 735 gpio-controller; 736 #gpio-cells = <2>; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 740 blsp1_i2c0_default: blsp1-i2c0-default-state { 741 pins = "gpio32", "gpio33"; 742 function = "blsp_i2c0"; 743 }; 744 745 blsp1_i2c1_default: blsp1-i2c1-default-state { 746 pins = "gpio24", "gpio25"; 747 function = "blsp_i2c1"; 748 }; 749 750 blsp1_i2c2_default: blsp1-i2c2-default-state { 751 sda-pins { 752 pins = "gpio19"; 753 function = "blsp_i2c_sda_a2"; 754 }; 755 756 scl-pins { 757 pins = "gpio20"; 758 function = "blsp_i2c_scl_a2"; 759 }; 760 }; 761 762 blsp1_i2c3_default: blsp1-i2c3-default-state { 763 pins = "gpio84", "gpio85"; 764 function = "blsp_i2c3"; 765 }; 766 767 blsp1_i2c4_default: blsp1-i2c4-default-state { 768 pins = "gpio117", "gpio118"; 769 function = "blsp_i2c4"; 770 }; 771 772 blsp1_uart0_default: blsp1-uart0-default-state { 773 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 774 function = "blsp_uart0"; 775 }; 776 777 blsp1_uart1_default: blsp1-uart1-default-state { 778 pins = "gpio22", "gpio23"; 779 function = "blsp_uart1"; 780 }; 781 782 blsp1_uart2_default: blsp1-uart2-default-state { 783 rx-pins { 784 pins = "gpio18"; 785 function = "blsp_uart_rx_a2"; 786 }; 787 788 tx-pins { 789 pins = "gpio17"; 790 function = "blsp_uart_tx_a2"; 791 }; 792 }; 793 794 blsp1_uart3_default: blsp1-uart3-default-state { 795 cts-pins { 796 pins = "gpio84"; 797 function = "blsp_uart3"; 798 }; 799 800 rts-tx-pins { 801 pins = "gpio85", "gpio82"; 802 function = "blsp_uart3"; 803 }; 804 805 rx-pins { 806 pins = "gpio83"; 807 function = "blsp_uart3"; 808 }; 809 }; 810 811 blsp2_i2c0_default: blsp2-i2c0-default-state { 812 pins = "gpio28", "gpio29"; 813 function = "blsp_i2c5"; 814 }; 815 816 blsp1_spi0_default: blsp1-spi0-default-state { 817 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 818 function = "blsp_spi0"; 819 }; 820 821 blsp1_spi1_default: blsp1-spi1-default-state { 822 mosi-pins { 823 pins = "gpio22"; 824 function = "blsp_spi_mosi_a1"; 825 }; 826 827 miso-pins { 828 pins = "gpio23"; 829 function = "blsp_spi_miso_a1"; 830 }; 831 832 cs-n-pins { 833 pins = "gpio24"; 834 function = "blsp_spi_cs_n_a1"; 835 }; 836 837 clk-pins { 838 pins = "gpio25"; 839 function = "blsp_spi_clk_a1"; 840 }; 841 }; 842 843 blsp1_spi2_default: blsp1-spi2-default-state { 844 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 845 function = "blsp_spi2"; 846 }; 847 848 blsp1_spi3_default: blsp1-spi3-default-state { 849 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 850 function = "blsp_spi3"; 851 }; 852 853 blsp1_spi4_default: blsp1-spi4-default-state { 854 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 855 function = "blsp_spi4"; 856 }; 857 858 blsp2_spi0_default: blsp2-spi0-default-state { 859 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 860 function = "blsp_spi5"; 861 }; 862 863 blsp2_uart0_default: blsp2-uart0-default-state { 864 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 865 function = "blsp_uart5"; 866 }; 867 }; 868 869 gcc: clock-controller@1800000 { 870 compatible = "qcom,gcc-qcs404"; 871 reg = <0x01800000 0x80000>; 872 #clock-cells = <1>; 873 #reset-cells = <1>; 874 #power-domain-cells = <1>; 875 876 clocks = <&xo_board>, 877 <&sleep_clk>, 878 <&pcie_phy>, 879 <0>, 880 <0>, 881 <0>; 882 883 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 884 assigned-clock-rates = <19200000>; 885 }; 886 887 tcsr_mutex: hwlock@1905000 { 888 compatible = "qcom,tcsr-mutex"; 889 reg = <0x01905000 0x20000>; 890 #hwlock-cells = <1>; 891 }; 892 893 tcsr: syscon@1937000 { 894 compatible = "qcom,qcs404-tcsr", "syscon"; 895 reg = <0x01937000 0x25000>; 896 }; 897 898 sram@290000 { 899 compatible = "qcom,rpm-stats"; 900 reg = <0x00290000 0x10000>; 901 }; 902 903 spmi_bus: spmi@200f000 { 904 compatible = "qcom,spmi-pmic-arb"; 905 reg = <0x0200f000 0x001000>, 906 <0x02400000 0x800000>, 907 <0x02c00000 0x800000>, 908 <0x03800000 0x200000>, 909 <0x0200a000 0x002100>; 910 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 911 interrupt-names = "periph_irq"; 912 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 913 qcom,ee = <0>; 914 qcom,channel = <0>; 915 #address-cells = <2>; 916 #size-cells = <0>; 917 interrupt-controller; 918 #interrupt-cells = <4>; 919 }; 920 921 remoteproc_wcss: remoteproc@7400000 { 922 compatible = "qcom,qcs404-wcss-pas"; 923 reg = <0x07400000 0x4040>; 924 925 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 926 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 927 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 928 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 929 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 930 interrupt-names = "wdog", "fatal", "ready", 931 "handover", "stop-ack"; 932 933 clocks = <&xo_board>; 934 clock-names = "xo"; 935 936 memory-region = <&wlan_fw_mem>; 937 938 qcom,smem-states = <&wcss_smp2p_out 0>; 939 qcom,smem-state-names = "stop"; 940 941 status = "disabled"; 942 943 glink-edge { 944 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 945 946 qcom,remote-pid = <1>; 947 mboxes = <&apcs_glb 16>; 948 949 label = "wcss"; 950 }; 951 }; 952 953 pcie_phy: phy@7786000 { 954 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 955 reg = <0x07786000 0xb8>; 956 957 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 958 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 959 <&gcc GCC_PCIE_0_PIPE_ARES>; 960 reset-names = "phy", "pipe"; 961 962 clock-output-names = "pcie_0_pipe_clk"; 963 #clock-cells = <0>; 964 #phy-cells = <0>; 965 966 status = "disabled"; 967 }; 968 969 sdcc1: mmc@7804000 { 970 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 971 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 972 reg-names = "hc", "cqhci"; 973 974 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 976 interrupt-names = "hc_irq", "pwr_irq"; 977 978 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 979 <&gcc GCC_SDCC1_APPS_CLK>, 980 <&xo_board>; 981 clock-names = "iface", "core", "xo"; 982 983 status = "disabled"; 984 }; 985 986 blsp1_dma: dma-controller@7884000 { 987 compatible = "qcom,bam-v1.7.0"; 988 reg = <0x07884000 0x25000>; 989 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 991 clock-names = "bam_clk"; 992 #dma-cells = <1>; 993 qcom,ee = <0>; 994 status = "okay"; 995 }; 996 997 blsp1_uart0: serial@78af000 { 998 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 999 reg = <0x078af000 0x200>; 1000 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1002 clock-names = "core", "iface"; 1003 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1004 dma-names = "tx", "rx"; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&blsp1_uart0_default>; 1007 status = "disabled"; 1008 }; 1009 1010 blsp1_uart1: serial@78b0000 { 1011 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1012 reg = <0x078b0000 0x200>; 1013 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1015 clock-names = "core", "iface"; 1016 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1017 dma-names = "tx", "rx"; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&blsp1_uart1_default>; 1020 status = "disabled"; 1021 }; 1022 1023 blsp1_uart2: serial@78b1000 { 1024 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1025 reg = <0x078b1000 0x200>; 1026 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1028 clock-names = "core", "iface"; 1029 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1030 dma-names = "tx", "rx"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&blsp1_uart2_default>; 1033 status = "okay"; 1034 }; 1035 1036 ethernet: ethernet@7a80000 { 1037 compatible = "qcom,qcs404-ethqos"; 1038 reg = <0x07a80000 0x10000>, 1039 <0x07a96000 0x100>; 1040 reg-names = "stmmaceth", "rgmii"; 1041 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 1042 clocks = <&gcc GCC_ETH_AXI_CLK>, 1043 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 1044 <&gcc GCC_ETH_PTP_CLK>, 1045 <&gcc GCC_ETH_RGMII_CLK>; 1046 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1048 interrupt-names = "macirq", "eth_lpi"; 1049 1050 snps,tso; 1051 rx-fifo-depth = <4096>; 1052 tx-fifo-depth = <4096>; 1053 1054 status = "disabled"; 1055 }; 1056 1057 wifi: wifi@a000000 { 1058 compatible = "qcom,wcn3990-wifi"; 1059 reg = <0xa000000 0x800000>; 1060 reg-names = "membase"; 1061 memory-region = <&wlan_msa_mem>; 1062 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1074 status = "disabled"; 1075 }; 1076 1077 blsp1_uart3: serial@78b2000 { 1078 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1079 reg = <0x078b2000 0x200>; 1080 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1082 clock-names = "core", "iface"; 1083 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1084 dma-names = "tx", "rx"; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&blsp1_uart3_default>; 1087 status = "disabled"; 1088 }; 1089 1090 blsp1_i2c0: i2c@78b5000 { 1091 compatible = "qcom,i2c-qup-v2.2.1"; 1092 reg = <0x078b5000 0x600>; 1093 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, 1095 <&gcc GCC_BLSP1_AHB_CLK>; 1096 clock-names = "core", "iface"; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&blsp1_i2c0_default>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 status = "disabled"; 1102 }; 1103 1104 blsp1_spi0: spi@78b5000 { 1105 compatible = "qcom,spi-qup-v2.2.1"; 1106 reg = <0x078b5000 0x600>; 1107 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, 1109 <&gcc GCC_BLSP1_AHB_CLK>; 1110 clock-names = "core", "iface"; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&blsp1_spi0_default>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 status = "disabled"; 1116 }; 1117 1118 blsp1_i2c1: i2c@78b6000 { 1119 compatible = "qcom,i2c-qup-v2.2.1"; 1120 reg = <0x078b6000 0x600>; 1121 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1123 <&gcc GCC_BLSP1_AHB_CLK>; 1124 clock-names = "core", "iface"; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&blsp1_i2c1_default>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 blsp1_spi1: spi@78b6000 { 1133 compatible = "qcom,spi-qup-v2.2.1"; 1134 reg = <0x078b6000 0x600>; 1135 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1137 <&gcc GCC_BLSP1_AHB_CLK>; 1138 clock-names = "core", "iface"; 1139 pinctrl-names = "default"; 1140 pinctrl-0 = <&blsp1_spi1_default>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 1146 blsp1_i2c2: i2c@78b7000 { 1147 compatible = "qcom,i2c-qup-v2.2.1"; 1148 reg = <0x078b7000 0x600>; 1149 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1151 <&gcc GCC_BLSP1_AHB_CLK>; 1152 clock-names = "core", "iface"; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&blsp1_i2c2_default>; 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 status = "disabled"; 1158 }; 1159 1160 blsp1_spi2: spi@78b7000 { 1161 compatible = "qcom,spi-qup-v2.2.1"; 1162 reg = <0x078b7000 0x600>; 1163 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1165 <&gcc GCC_BLSP1_AHB_CLK>; 1166 clock-names = "core", "iface"; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&blsp1_spi2_default>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 blsp1_i2c3: i2c@78b8000 { 1175 compatible = "qcom,i2c-qup-v2.2.1"; 1176 reg = <0x078b8000 0x600>; 1177 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1179 <&gcc GCC_BLSP1_AHB_CLK>; 1180 clock-names = "core", "iface"; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&blsp1_i2c3_default>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 status = "disabled"; 1186 }; 1187 1188 blsp1_spi3: spi@78b8000 { 1189 compatible = "qcom,spi-qup-v2.2.1"; 1190 reg = <0x078b8000 0x600>; 1191 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1193 <&gcc GCC_BLSP1_AHB_CLK>; 1194 clock-names = "core", "iface"; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&blsp1_spi3_default>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 status = "disabled"; 1200 }; 1201 1202 blsp1_i2c4: i2c@78b9000 { 1203 compatible = "qcom,i2c-qup-v2.2.1"; 1204 reg = <0x078b9000 0x600>; 1205 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1207 <&gcc GCC_BLSP1_AHB_CLK>; 1208 clock-names = "core", "iface"; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&blsp1_i2c4_default>; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 status = "disabled"; 1214 }; 1215 1216 blsp1_spi4: spi@78b9000 { 1217 compatible = "qcom,spi-qup-v2.2.1"; 1218 reg = <0x078b9000 0x600>; 1219 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1221 <&gcc GCC_BLSP1_AHB_CLK>; 1222 clock-names = "core", "iface"; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&blsp1_spi4_default>; 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 status = "disabled"; 1228 }; 1229 1230 blsp2_dma: dma-controller@7ac4000 { 1231 compatible = "qcom,bam-v1.7.0"; 1232 reg = <0x07ac4000 0x17000>; 1233 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1235 clock-names = "bam_clk"; 1236 #dma-cells = <1>; 1237 qcom,ee = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 blsp2_uart0: serial@7aef000 { 1242 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1243 reg = <0x07aef000 0x200>; 1244 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1246 clock-names = "core", "iface"; 1247 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1248 dma-names = "tx", "rx"; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&blsp2_uart0_default>; 1251 status = "disabled"; 1252 }; 1253 1254 blsp2_i2c0: i2c@7af5000 { 1255 compatible = "qcom,i2c-qup-v2.2.1"; 1256 reg = <0x07af5000 0x600>; 1257 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, 1259 <&gcc GCC_BLSP2_AHB_CLK>; 1260 clock-names = "core", "iface"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&blsp2_i2c0_default>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 status = "disabled"; 1266 }; 1267 1268 blsp2_spi0: spi@7af5000 { 1269 compatible = "qcom,spi-qup-v2.2.1"; 1270 reg = <0x07af5000 0x600>; 1271 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1272 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, 1273 <&gcc GCC_BLSP2_AHB_CLK>; 1274 clock-names = "core", "iface"; 1275 pinctrl-names = "default"; 1276 pinctrl-0 = <&blsp2_spi0_default>; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 status = "disabled"; 1280 }; 1281 1282 sram@8600000 { 1283 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; 1284 reg = <0x08600000 0x1000>; 1285 1286 #address-cells = <1>; 1287 #size-cells = <1>; 1288 1289 ranges = <0 0x08600000 0x1000>; 1290 1291 pil-reloc@94c { 1292 compatible = "qcom,pil-reloc-info"; 1293 reg = <0x94c 0xc8>; 1294 }; 1295 }; 1296 1297 intc: interrupt-controller@b000000 { 1298 compatible = "qcom,msm-qgic2"; 1299 interrupt-controller; 1300 #interrupt-cells = <3>; 1301 reg = <0x0b000000 0x1000>, 1302 <0x0b002000 0x1000>; 1303 }; 1304 1305 apcs_glb: mailbox@b011000 { 1306 compatible = "qcom,qcs404-apcs-apps-global", 1307 "qcom,msm8916-apcs-kpss-global", "syscon"; 1308 reg = <0x0b011000 0x1000>; 1309 #mbox-cells = <1>; 1310 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 1311 clock-names = "pll", "aux"; 1312 #clock-cells = <0>; 1313 }; 1314 1315 apcs_hfpll: clock-controller@b016000 { 1316 compatible = "qcom,hfpll"; 1317 reg = <0x0b016000 0x30>; 1318 #clock-cells = <0>; 1319 clock-output-names = "apcs_hfpll"; 1320 clocks = <&xo_board>; 1321 clock-names = "xo"; 1322 }; 1323 1324 watchdog@b017000 { 1325 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1326 reg = <0x0b017000 0x1000>; 1327 clocks = <&sleep_clk>; 1328 }; 1329 1330 cpr: power-controller@b018000 { 1331 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 1332 reg = <0x0b018000 0x1000>; 1333 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 1334 clocks = <&xo_board>; 1335 clock-names = "ref"; 1336 vdd-apc-supply = <&pms405_s3>; 1337 #power-domain-cells = <0>; 1338 operating-points-v2 = <&cpr_opp_table>; 1339 acc-syscon = <&tcsr>; 1340 1341 nvmem-cells = <&cpr_efuse_quot_offset1>, 1342 <&cpr_efuse_quot_offset2>, 1343 <&cpr_efuse_quot_offset3>, 1344 <&cpr_efuse_init_voltage1>, 1345 <&cpr_efuse_init_voltage2>, 1346 <&cpr_efuse_init_voltage3>, 1347 <&cpr_efuse_quot1>, 1348 <&cpr_efuse_quot2>, 1349 <&cpr_efuse_quot3>, 1350 <&cpr_efuse_ring1>, 1351 <&cpr_efuse_ring2>, 1352 <&cpr_efuse_ring3>, 1353 <&cpr_efuse_revision>; 1354 nvmem-cell-names = "cpr_quotient_offset1", 1355 "cpr_quotient_offset2", 1356 "cpr_quotient_offset3", 1357 "cpr_init_voltage1", 1358 "cpr_init_voltage2", 1359 "cpr_init_voltage3", 1360 "cpr_quotient1", 1361 "cpr_quotient2", 1362 "cpr_quotient3", 1363 "cpr_ring_osc1", 1364 "cpr_ring_osc2", 1365 "cpr_ring_osc3", 1366 "cpr_fuse_revision"; 1367 }; 1368 1369 timer@b120000 { 1370 #address-cells = <1>; 1371 #size-cells = <1>; 1372 ranges; 1373 compatible = "arm,armv7-timer-mem"; 1374 reg = <0x0b120000 0x1000>; 1375 clock-frequency = <19200000>; 1376 1377 frame@b121000 { 1378 frame-number = <0>; 1379 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1381 reg = <0x0b121000 0x1000>, 1382 <0x0b122000 0x1000>; 1383 }; 1384 1385 frame@b123000 { 1386 frame-number = <1>; 1387 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1388 reg = <0x0b123000 0x1000>; 1389 status = "disabled"; 1390 }; 1391 1392 frame@b124000 { 1393 frame-number = <2>; 1394 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1395 reg = <0x0b124000 0x1000>; 1396 status = "disabled"; 1397 }; 1398 1399 frame@b125000 { 1400 frame-number = <3>; 1401 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1402 reg = <0x0b125000 0x1000>; 1403 status = "disabled"; 1404 }; 1405 1406 frame@b126000 { 1407 frame-number = <4>; 1408 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1409 reg = <0x0b126000 0x1000>; 1410 status = "disabled"; 1411 }; 1412 1413 frame@b127000 { 1414 frame-number = <5>; 1415 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1416 reg = <0xb127000 0x1000>; 1417 status = "disabled"; 1418 }; 1419 1420 frame@b128000 { 1421 frame-number = <6>; 1422 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1423 reg = <0x0b128000 0x1000>; 1424 status = "disabled"; 1425 }; 1426 }; 1427 1428 remoteproc_adsp: remoteproc@c700000 { 1429 compatible = "qcom,qcs404-adsp-pas"; 1430 reg = <0x0c700000 0x4040>; 1431 1432 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 1433 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1434 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1435 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1436 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1437 interrupt-names = "wdog", "fatal", "ready", 1438 "handover", "stop-ack"; 1439 1440 clocks = <&xo_board>; 1441 clock-names = "xo"; 1442 1443 memory-region = <&adsp_fw_mem>; 1444 1445 qcom,smem-states = <&adsp_smp2p_out 0>; 1446 qcom,smem-state-names = "stop"; 1447 1448 status = "disabled"; 1449 1450 glink-edge { 1451 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1452 1453 qcom,remote-pid = <2>; 1454 mboxes = <&apcs_glb 8>; 1455 1456 label = "adsp"; 1457 }; 1458 }; 1459 1460 pcie: pci@10000000 { 1461 compatible = "qcom,pcie-qcs404"; 1462 reg = <0x10000000 0xf1d>, 1463 <0x10000f20 0xa8>, 1464 <0x07780000 0x2000>, 1465 <0x10001000 0x2000>; 1466 reg-names = "dbi", "elbi", "parf", "config"; 1467 device_type = "pci"; 1468 linux,pci-domain = <0>; 1469 bus-range = <0x00 0xff>; 1470 num-lanes = <1>; 1471 #address-cells = <3>; 1472 #size-cells = <2>; 1473 1474 ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ 1475 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ 1476 1477 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1478 interrupt-names = "msi"; 1479 #interrupt-cells = <1>; 1480 interrupt-map-mask = <0 0 0 0x7>; 1481 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1482 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1483 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1484 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1485 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1486 <&gcc GCC_PCIE_0_AUX_CLK>, 1487 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1488 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1489 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1490 1491 resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, 1492 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, 1493 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, 1494 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, 1495 <&gcc GCC_PCIE_0_BCR>, 1496 <&gcc GCC_PCIE_0_AHB_ARES>; 1497 reset-names = "axi_m", 1498 "axi_s", 1499 "axi_m_sticky", 1500 "pipe_sticky", 1501 "pwr", 1502 "ahb"; 1503 1504 phys = <&pcie_phy>; 1505 phy-names = "pciephy"; 1506 1507 status = "disabled"; 1508 }; 1509 }; 1510 1511 timer { 1512 compatible = "arm,armv8-timer"; 1513 interrupts = <GIC_PPI 2 0xff08>, 1514 <GIC_PPI 3 0xff08>, 1515 <GIC_PPI 4 0xff08>, 1516 <GIC_PPI 1 0xff08>; 1517 }; 1518 1519 smp2p-adsp { 1520 compatible = "qcom,smp2p"; 1521 qcom,smem = <443>, <429>; 1522 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1523 mboxes = <&apcs_glb 10>; 1524 qcom,local-pid = <0>; 1525 qcom,remote-pid = <2>; 1526 1527 adsp_smp2p_out: master-kernel { 1528 qcom,entry-name = "master-kernel"; 1529 #qcom,smem-state-cells = <1>; 1530 }; 1531 1532 adsp_smp2p_in: slave-kernel { 1533 qcom,entry-name = "slave-kernel"; 1534 interrupt-controller; 1535 #interrupt-cells = <2>; 1536 }; 1537 }; 1538 1539 smp2p-cdsp { 1540 compatible = "qcom,smp2p"; 1541 qcom,smem = <94>, <432>; 1542 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1543 mboxes = <&apcs_glb 14>; 1544 qcom,local-pid = <0>; 1545 qcom,remote-pid = <5>; 1546 1547 cdsp_smp2p_out: master-kernel { 1548 qcom,entry-name = "master-kernel"; 1549 #qcom,smem-state-cells = <1>; 1550 }; 1551 1552 cdsp_smp2p_in: slave-kernel { 1553 qcom,entry-name = "slave-kernel"; 1554 interrupt-controller; 1555 #interrupt-cells = <2>; 1556 }; 1557 }; 1558 1559 smp2p-wcss { 1560 compatible = "qcom,smp2p"; 1561 qcom,smem = <435>, <428>; 1562 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1563 mboxes = <&apcs_glb 18>; 1564 qcom,local-pid = <0>; 1565 qcom,remote-pid = <1>; 1566 1567 wcss_smp2p_out: master-kernel { 1568 qcom,entry-name = "master-kernel"; 1569 #qcom,smem-state-cells = <1>; 1570 }; 1571 1572 wcss_smp2p_in: slave-kernel { 1573 qcom,entry-name = "slave-kernel"; 1574 interrupt-controller; 1575 #interrupt-cells = <2>; 1576 }; 1577 }; 1578 1579 thermal-zones { 1580 aoss-thermal { 1581 polling-delay-passive = <250>; 1582 polling-delay = <1000>; 1583 1584 thermal-sensors = <&tsens 0>; 1585 1586 trips { 1587 aoss_alert0: trip-point0 { 1588 temperature = <105000>; 1589 hysteresis = <2000>; 1590 type = "hot"; 1591 }; 1592 }; 1593 }; 1594 1595 q6-hvx-thermal { 1596 polling-delay-passive = <250>; 1597 polling-delay = <1000>; 1598 1599 thermal-sensors = <&tsens 1>; 1600 1601 trips { 1602 q6_hvx_alert0: trip-point0 { 1603 temperature = <105000>; 1604 hysteresis = <2000>; 1605 type = "hot"; 1606 }; 1607 }; 1608 }; 1609 1610 lpass-thermal { 1611 polling-delay-passive = <250>; 1612 polling-delay = <1000>; 1613 1614 thermal-sensors = <&tsens 2>; 1615 1616 trips { 1617 lpass_alert0: trip-point0 { 1618 temperature = <105000>; 1619 hysteresis = <2000>; 1620 type = "hot"; 1621 }; 1622 }; 1623 }; 1624 1625 wlan-thermal { 1626 polling-delay-passive = <250>; 1627 polling-delay = <1000>; 1628 1629 thermal-sensors = <&tsens 3>; 1630 1631 trips { 1632 wlan_alert0: trip-point0 { 1633 temperature = <105000>; 1634 hysteresis = <2000>; 1635 type = "hot"; 1636 }; 1637 }; 1638 }; 1639 1640 cluster-thermal { 1641 polling-delay-passive = <250>; 1642 polling-delay = <1000>; 1643 1644 thermal-sensors = <&tsens 4>; 1645 1646 trips { 1647 cluster_alert0: trip-point0 { 1648 temperature = <95000>; 1649 hysteresis = <2000>; 1650 type = "hot"; 1651 }; 1652 cluster_alert1: trip-point1 { 1653 temperature = <105000>; 1654 hysteresis = <2000>; 1655 type = "passive"; 1656 }; 1657 cluster_crit: cluster-crit { 1658 temperature = <120000>; 1659 hysteresis = <2000>; 1660 type = "critical"; 1661 }; 1662 }; 1663 cooling-maps { 1664 map0 { 1665 trip = <&cluster_alert1>; 1666 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1667 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1668 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1669 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1670 }; 1671 }; 1672 }; 1673 1674 cpu0-thermal { 1675 polling-delay-passive = <250>; 1676 polling-delay = <1000>; 1677 1678 thermal-sensors = <&tsens 5>; 1679 1680 trips { 1681 cpu0_alert0: trip-point0 { 1682 temperature = <95000>; 1683 hysteresis = <2000>; 1684 type = "hot"; 1685 }; 1686 cpu0_alert1: trip-point1 { 1687 temperature = <105000>; 1688 hysteresis = <2000>; 1689 type = "passive"; 1690 }; 1691 cpu0_crit: cpu-crit { 1692 temperature = <120000>; 1693 hysteresis = <2000>; 1694 type = "critical"; 1695 }; 1696 }; 1697 cooling-maps { 1698 map0 { 1699 trip = <&cpu0_alert1>; 1700 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1701 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1702 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1703 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1704 }; 1705 }; 1706 }; 1707 1708 cpu1-thermal { 1709 polling-delay-passive = <250>; 1710 polling-delay = <1000>; 1711 1712 thermal-sensors = <&tsens 6>; 1713 1714 trips { 1715 cpu1_alert0: trip-point0 { 1716 temperature = <95000>; 1717 hysteresis = <2000>; 1718 type = "hot"; 1719 }; 1720 cpu1_alert1: trip-point1 { 1721 temperature = <105000>; 1722 hysteresis = <2000>; 1723 type = "passive"; 1724 }; 1725 cpu1_crit: cpu-crit { 1726 temperature = <120000>; 1727 hysteresis = <2000>; 1728 type = "critical"; 1729 }; 1730 }; 1731 cooling-maps { 1732 map0 { 1733 trip = <&cpu1_alert1>; 1734 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1735 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1736 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1737 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1738 }; 1739 }; 1740 }; 1741 1742 cpu2-thermal { 1743 polling-delay-passive = <250>; 1744 polling-delay = <1000>; 1745 1746 thermal-sensors = <&tsens 7>; 1747 1748 trips { 1749 cpu2_alert0: trip-point0 { 1750 temperature = <95000>; 1751 hysteresis = <2000>; 1752 type = "hot"; 1753 }; 1754 cpu2_alert1: trip-point1 { 1755 temperature = <105000>; 1756 hysteresis = <2000>; 1757 type = "passive"; 1758 }; 1759 cpu2_crit: cpu-crit { 1760 temperature = <120000>; 1761 hysteresis = <2000>; 1762 type = "critical"; 1763 }; 1764 }; 1765 cooling-maps { 1766 map0 { 1767 trip = <&cpu2_alert1>; 1768 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1769 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1770 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1771 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1772 }; 1773 }; 1774 }; 1775 1776 cpu3-thermal { 1777 polling-delay-passive = <250>; 1778 polling-delay = <1000>; 1779 1780 thermal-sensors = <&tsens 8>; 1781 1782 trips { 1783 cpu3_alert0: trip-point0 { 1784 temperature = <95000>; 1785 hysteresis = <2000>; 1786 type = "hot"; 1787 }; 1788 cpu3_alert1: trip-point1 { 1789 temperature = <105000>; 1790 hysteresis = <2000>; 1791 type = "passive"; 1792 }; 1793 cpu3_crit: cpu-crit { 1794 temperature = <120000>; 1795 hysteresis = <2000>; 1796 type = "critical"; 1797 }; 1798 }; 1799 cooling-maps { 1800 map0 { 1801 trip = <&cpu3_alert1>; 1802 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1803 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1804 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1805 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1806 }; 1807 }; 1808 }; 1809 1810 gpu-thermal { 1811 polling-delay-passive = <250>; 1812 polling-delay = <1000>; 1813 1814 thermal-sensors = <&tsens 9>; 1815 1816 trips { 1817 gpu_alert0: trip-point0 { 1818 temperature = <95000>; 1819 hysteresis = <2000>; 1820 type = "hot"; 1821 }; 1822 }; 1823 }; 1824 }; 1825}; 1826