1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2018, Linaro Limited 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-qcs404.h> 6#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/thermal/thermal.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 }; 25 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <32768>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@100 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x100>; 41 enable-method = "psci"; 42 cpu-idle-states = <&CPU_SLEEP_0>; 43 next-level-cache = <&L2_0>; 44 #cooling-cells = <2>; 45 }; 46 47 CPU1: cpu@101 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 reg = <0x101>; 51 enable-method = "psci"; 52 cpu-idle-states = <&CPU_SLEEP_0>; 53 next-level-cache = <&L2_0>; 54 #cooling-cells = <2>; 55 }; 56 57 CPU2: cpu@102 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x102>; 61 enable-method = "psci"; 62 cpu-idle-states = <&CPU_SLEEP_0>; 63 next-level-cache = <&L2_0>; 64 #cooling-cells = <2>; 65 }; 66 67 CPU3: cpu@103 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x103>; 71 enable-method = "psci"; 72 cpu-idle-states = <&CPU_SLEEP_0>; 73 next-level-cache = <&L2_0>; 74 #cooling-cells = <2>; 75 }; 76 77 L2_0: l2-cache { 78 compatible = "cache"; 79 cache-level = <2>; 80 }; 81 82 idle-states { 83 entry-method = "psci"; 84 85 CPU_SLEEP_0: cpu-sleep-0 { 86 compatible = "arm,idle-state"; 87 idle-state-name = "standalone-power-collapse"; 88 arm,psci-suspend-param = <0x40000003>; 89 entry-latency-us = <125>; 90 exit-latency-us = <180>; 91 min-residency-us = <595>; 92 local-timer-stop; 93 }; 94 }; 95 }; 96 97 firmware { 98 scm: scm { 99 compatible = "qcom,scm-qcs404", "qcom,scm"; 100 #reset-cells = <1>; 101 }; 102 }; 103 104 memory@80000000 { 105 device_type = "memory"; 106 /* We expect the bootloader to fill in the size */ 107 reg = <0 0x80000000 0 0>; 108 }; 109 110 psci { 111 compatible = "arm,psci-1.0"; 112 method = "smc"; 113 }; 114 115 reserved-memory { 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges; 119 120 tz_apps_mem: memory@85900000 { 121 reg = <0 0x85900000 0 0x500000>; 122 no-map; 123 }; 124 125 xbl_mem: memory@85e00000 { 126 reg = <0 0x85e00000 0 0x100000>; 127 no-map; 128 }; 129 130 smem_region: memory@85f00000 { 131 reg = <0 0x85f00000 0 0x200000>; 132 no-map; 133 }; 134 135 tz_mem: memory@86100000 { 136 reg = <0 0x86100000 0 0x300000>; 137 no-map; 138 }; 139 140 wlan_fw_mem: memory@86400000 { 141 reg = <0 0x86400000 0 0x1100000>; 142 no-map; 143 }; 144 145 adsp_fw_mem: memory@87500000 { 146 reg = <0 0x87500000 0 0x1a00000>; 147 no-map; 148 }; 149 150 cdsp_fw_mem: memory@88f00000 { 151 reg = <0 0x88f00000 0 0x600000>; 152 no-map; 153 }; 154 155 wlan_msa_mem: memory@89500000 { 156 reg = <0 0x89500000 0 0x100000>; 157 no-map; 158 }; 159 160 uefi_mem: memory@9f800000 { 161 reg = <0 0x9f800000 0 0x800000>; 162 no-map; 163 }; 164 }; 165 166 rpm-glink { 167 compatible = "qcom,glink-rpm"; 168 169 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 170 qcom,rpm-msg-ram = <&rpm_msg_ram>; 171 mboxes = <&apcs_glb 0>; 172 173 rpm_requests: glink-channel { 174 compatible = "qcom,rpm-qcs404"; 175 qcom,glink-channels = "rpm_requests"; 176 177 rpmcc: clock-controller { 178 compatible = "qcom,rpmcc-qcs404"; 179 #clock-cells = <1>; 180 }; 181 182 rpmpd: power-controller { 183 compatible = "qcom,qcs404-rpmpd"; 184 #power-domain-cells = <1>; 185 operating-points-v2 = <&rpmpd_opp_table>; 186 187 rpmpd_opp_table: opp-table { 188 compatible = "operating-points-v2"; 189 190 rpmpd_opp_ret: opp1 { 191 opp-level = <16>; 192 }; 193 194 rpmpd_opp_ret_plus: opp2 { 195 opp-level = <32>; 196 }; 197 198 rpmpd_opp_min_svs: opp3 { 199 opp-level = <48>; 200 }; 201 202 rpmpd_opp_low_svs: opp4 { 203 opp-level = <64>; 204 }; 205 206 rpmpd_opp_svs: opp5 { 207 opp-level = <128>; 208 }; 209 210 rpmpd_opp_svs_plus: opp6 { 211 opp-level = <192>; 212 }; 213 214 rpmpd_opp_nom: opp7 { 215 opp-level = <256>; 216 }; 217 218 rpmpd_opp_nom_plus: opp8 { 219 opp-level = <320>; 220 }; 221 222 rpmpd_opp_turbo: opp9 { 223 opp-level = <384>; 224 }; 225 226 rpmpd_opp_turbo_no_cpr: opp10 { 227 opp-level = <416>; 228 }; 229 230 rpmpd_opp_turbo_plus: opp11 { 231 opp-level = <512>; 232 }; 233 }; 234 }; 235 }; 236 }; 237 238 smem { 239 compatible = "qcom,smem"; 240 241 memory-region = <&smem_region>; 242 qcom,rpm-msg-ram = <&rpm_msg_ram>; 243 244 hwlocks = <&tcsr_mutex 3>; 245 }; 246 247 tcsr_mutex: hwlock { 248 compatible = "qcom,tcsr-mutex"; 249 syscon = <&tcsr_mutex_regs 0 0x1000>; 250 #hwlock-cells = <1>; 251 }; 252 253 soc: soc@0 { 254 #address-cells = <1>; 255 #size-cells = <1>; 256 ranges = <0 0 0 0xffffffff>; 257 compatible = "simple-bus"; 258 259 turingcc: clock-controller@800000 { 260 compatible = "qcom,qcs404-turingcc"; 261 reg = <0x00800000 0x30000>; 262 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 263 264 #clock-cells = <1>; 265 #reset-cells = <1>; 266 267 status = "disabled"; 268 }; 269 270 rpm_msg_ram: memory@60000 { 271 compatible = "qcom,rpm-msg-ram"; 272 reg = <0x00060000 0x6000>; 273 }; 274 275 qfprom: qfprom@a4000 { 276 compatible = "qcom,qfprom"; 277 reg = <0x000a4000 0x1000>; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 tsens_caldata: caldata@d0 { 281 reg = <0x1f8 0x14>; 282 }; 283 }; 284 285 rng: rng@e3000 { 286 compatible = "qcom,prng-ee"; 287 reg = <0x000e3000 0x1000>; 288 clocks = <&gcc GCC_PRNG_AHB_CLK>; 289 clock-names = "core"; 290 }; 291 292 bimc: interconnect@400000 { 293 reg = <0x00400000 0x80000>; 294 compatible = "qcom,qcs404-bimc"; 295 #interconnect-cells = <1>; 296 clock-names = "bus", "bus_a"; 297 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 298 <&rpmcc RPM_SMD_BIMC_A_CLK>; 299 }; 300 301 tsens: thermal-sensor@4a9000 { 302 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 303 reg = <0x004a9000 0x1000>, /* TM */ 304 <0x004a8000 0x1000>; /* SROT */ 305 nvmem-cells = <&tsens_caldata>; 306 nvmem-cell-names = "calib"; 307 #qcom,sensors = <10>; 308 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 309 interrupt-names = "uplow"; 310 #thermal-sensor-cells = <1>; 311 }; 312 313 pcnoc: interconnect@500000 { 314 reg = <0x00500000 0x15080>; 315 compatible = "qcom,qcs404-pcnoc"; 316 #interconnect-cells = <1>; 317 clock-names = "bus", "bus_a"; 318 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 319 <&rpmcc RPM_SMD_PNOC_A_CLK>; 320 }; 321 322 snoc: interconnect@580000 { 323 reg = <0x00580000 0x23080>; 324 compatible = "qcom,qcs404-snoc"; 325 #interconnect-cells = <1>; 326 clock-names = "bus", "bus_a"; 327 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 328 <&rpmcc RPM_SMD_SNOC_A_CLK>; 329 }; 330 331 remoteproc_cdsp: remoteproc@b00000 { 332 compatible = "qcom,qcs404-cdsp-pas"; 333 reg = <0x00b00000 0x4040>; 334 335 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 336 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 337 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 338 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 339 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 340 interrupt-names = "wdog", "fatal", "ready", 341 "handover", "stop-ack"; 342 343 clocks = <&xo_board>, 344 <&gcc GCC_CDSP_CFG_AHB_CLK>, 345 <&gcc GCC_CDSP_TBU_CLK>, 346 <&gcc GCC_BIMC_CDSP_CLK>, 347 <&turingcc TURING_WRAPPER_AON_CLK>, 348 <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 349 <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 350 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 351 clock-names = "xo", 352 "sway", 353 "tbu", 354 "bimc", 355 "ahb_aon", 356 "q6ss_slave", 357 "q6ss_master", 358 "q6_axim"; 359 360 resets = <&gcc GCC_CDSP_RESTART>; 361 reset-names = "restart"; 362 363 qcom,halt-regs = <&tcsr 0x19004>; 364 365 memory-region = <&cdsp_fw_mem>; 366 367 qcom,smem-states = <&cdsp_smp2p_out 0>; 368 qcom,smem-state-names = "stop"; 369 370 status = "disabled"; 371 372 glink-edge { 373 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 374 375 qcom,remote-pid = <5>; 376 mboxes = <&apcs_glb 12>; 377 378 label = "cdsp"; 379 }; 380 }; 381 382 tlmm: pinctrl@1000000 { 383 compatible = "qcom,qcs404-pinctrl"; 384 reg = <0x01000000 0x200000>, 385 <0x01300000 0x200000>, 386 <0x07b00000 0x200000>; 387 reg-names = "south", "north", "east"; 388 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 389 gpio-ranges = <&tlmm 0 0 120>; 390 gpio-controller; 391 #gpio-cells = <2>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 395 blsp1_i2c0_default: blsp1-i2c0-default { 396 pins = "gpio32", "gpio33"; 397 function = "blsp_i2c0"; 398 }; 399 400 blsp1_i2c1_default: blsp1-i2c1-default { 401 pins = "gpio24", "gpio25"; 402 function = "blsp_i2c1"; 403 }; 404 405 blsp1_i2c2_default: blsp1-i2c2-default { 406 sda { 407 pins = "gpio19"; 408 function = "blsp_i2c_sda_a2"; 409 }; 410 411 scl { 412 pins = "gpio20"; 413 function = "blsp_i2c_scl_a2"; 414 }; 415 }; 416 417 blsp1_i2c3_default: blsp1-i2c3-default { 418 pins = "gpio84", "gpio85"; 419 function = "blsp_i2c3"; 420 }; 421 422 blsp1_i2c4_default: blsp1-i2c4-default { 423 pins = "gpio117", "gpio118"; 424 function = "blsp_i2c4"; 425 }; 426 427 blsp1_uart0_default: blsp1-uart0-default { 428 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 429 function = "blsp_uart0"; 430 }; 431 432 blsp1_uart1_default: blsp1-uart1-default { 433 pins = "gpio22", "gpio23"; 434 function = "blsp_uart1"; 435 }; 436 437 blsp1_uart2_default: blsp1-uart2-default { 438 rx { 439 pins = "gpio18"; 440 function = "blsp_uart_rx_a2"; 441 }; 442 443 tx { 444 pins = "gpio17"; 445 function = "blsp_uart_tx_a2"; 446 }; 447 }; 448 449 blsp1_uart3_default: blsp1-uart3-default { 450 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 451 function = "blsp_uart3"; 452 }; 453 454 blsp2_i2c0_default: blsp2-i2c0-default { 455 pins = "gpio28", "gpio29"; 456 function = "blsp_i2c5"; 457 }; 458 459 blsp1_spi0_default: blsp1-spi0-default { 460 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 461 function = "blsp_spi0"; 462 }; 463 464 blsp1_spi1_default: blsp1-spi1-default { 465 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 466 function = "blsp_spi1"; 467 }; 468 469 blsp1_spi2_default: blsp1-spi2-default { 470 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 471 function = "blsp_spi2"; 472 }; 473 474 blsp1_spi3_default: blsp1-spi3-default { 475 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 476 function = "blsp_spi3"; 477 }; 478 479 blsp1_spi4_default: blsp1-spi4-default { 480 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 481 function = "blsp_spi4"; 482 }; 483 484 blsp2_spi0_default: blsp2-spi0-default { 485 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 486 function = "blsp_spi5"; 487 }; 488 489 blsp2_uart0_default: blsp2-uart0-default { 490 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 491 function = "blsp_uart5"; 492 }; 493 }; 494 495 gcc: clock-controller@1800000 { 496 compatible = "qcom,gcc-qcs404"; 497 reg = <0x01800000 0x80000>; 498 #clock-cells = <1>; 499 #reset-cells = <1>; 500 501 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 502 assigned-clock-rates = <19200000>; 503 }; 504 505 tcsr_mutex_regs: syscon@1905000 { 506 compatible = "syscon"; 507 reg = <0x01905000 0x20000>; 508 }; 509 510 tcsr: syscon@1937000 { 511 compatible = "syscon"; 512 reg = <0x01937000 0x25000>; 513 }; 514 515 spmi_bus: spmi@200f000 { 516 compatible = "qcom,spmi-pmic-arb"; 517 reg = <0x0200f000 0x001000>, 518 <0x02400000 0x800000>, 519 <0x02c00000 0x800000>, 520 <0x03800000 0x200000>, 521 <0x0200a000 0x002100>; 522 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 523 interrupt-names = "periph_irq"; 524 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 525 qcom,ee = <0>; 526 qcom,channel = <0>; 527 #address-cells = <2>; 528 #size-cells = <0>; 529 interrupt-controller; 530 #interrupt-cells = <4>; 531 }; 532 533 remoteproc_wcss: remoteproc@7400000 { 534 compatible = "qcom,qcs404-wcss-pas"; 535 reg = <0x07400000 0x4040>; 536 537 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 538 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 539 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 540 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 541 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 542 interrupt-names = "wdog", "fatal", "ready", 543 "handover", "stop-ack"; 544 545 clocks = <&xo_board>; 546 clock-names = "xo"; 547 548 memory-region = <&wlan_fw_mem>; 549 550 qcom,smem-states = <&wcss_smp2p_out 0>; 551 qcom,smem-state-names = "stop"; 552 553 status = "disabled"; 554 555 glink-edge { 556 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 557 558 qcom,remote-pid = <1>; 559 mboxes = <&apcs_glb 16>; 560 561 label = "wcss"; 562 }; 563 }; 564 565 pcie_phy: phy@7786000 { 566 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 567 reg = <0x07786000 0xb8>; 568 569 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 570 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 571 <&gcc 21>; 572 reset-names = "phy", "pipe"; 573 574 clock-output-names = "pcie_0_pipe_clk"; 575 #phy-cells = <0>; 576 577 status = "disabled"; 578 }; 579 580 sdcc1: sdcc@7804000 { 581 compatible = "qcom,sdhci-msm-v5"; 582 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 583 reg-names = "hc_mem", "cmdq_mem"; 584 585 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "hc_irq", "pwr_irq"; 588 589 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 590 <&gcc GCC_SDCC1_AHB_CLK>, 591 <&xo_board>; 592 clock-names = "core", "iface", "xo"; 593 594 status = "disabled"; 595 }; 596 597 blsp1_dma: dma@7884000 { 598 compatible = "qcom,bam-v1.7.0"; 599 reg = <0x07884000 0x25000>; 600 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 602 clock-names = "bam_clk"; 603 #dma-cells = <1>; 604 qcom,ee = <0>; 605 status = "okay"; 606 }; 607 608 blsp1_uart0: serial@78af000 { 609 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 610 reg = <0x078af000 0x200>; 611 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 613 clock-names = "core", "iface"; 614 dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; 615 dma-names = "rx", "tx"; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&blsp1_uart0_default>; 618 status = "disabled"; 619 }; 620 621 blsp1_uart1: serial@78b0000 { 622 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 623 reg = <0x078b0000 0x200>; 624 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 626 clock-names = "core", "iface"; 627 dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; 628 dma-names = "rx", "tx"; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&blsp1_uart1_default>; 631 status = "disabled"; 632 }; 633 634 blsp1_uart2: serial@78b1000 { 635 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 636 reg = <0x078b1000 0x200>; 637 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 639 clock-names = "core", "iface"; 640 dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; 641 dma-names = "rx", "tx"; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&blsp1_uart2_default>; 644 status = "okay"; 645 }; 646 647 ethernet: ethernet@7a80000 { 648 compatible = "qcom,qcs404-ethqos"; 649 reg = <0x07a80000 0x10000>, 650 <0x07a96000 0x100>; 651 reg-names = "stmmaceth", "rgmii"; 652 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 653 clocks = <&gcc GCC_ETH_AXI_CLK>, 654 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 655 <&gcc GCC_ETH_PTP_CLK>, 656 <&gcc GCC_ETH_RGMII_CLK>; 657 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 659 interrupt-names = "macirq", "eth_lpi"; 660 661 snps,tso; 662 rx-fifo-depth = <4096>; 663 tx-fifo-depth = <4096>; 664 665 status = "disabled"; 666 }; 667 668 wifi: wifi@a000000 { 669 compatible = "qcom,wcn3990-wifi"; 670 reg = <0xa000000 0x800000>; 671 reg-names = "membase"; 672 memory-region = <&wlan_msa_mem>; 673 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 685 status = "disabled"; 686 }; 687 688 blsp1_uart3: serial@78b2000 { 689 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 690 reg = <0x078b2000 0x200>; 691 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 693 clock-names = "core", "iface"; 694 dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; 695 dma-names = "rx", "tx"; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&blsp1_uart3_default>; 698 status = "disabled"; 699 }; 700 701 blsp1_i2c0: i2c@78b5000 { 702 compatible = "qcom,i2c-qup-v2.2.1"; 703 reg = <0x078b5000 0x600>; 704 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 706 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; 707 clock-names = "iface", "core"; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&blsp1_i2c0_default>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 blsp1_spi0: spi@78b5000 { 716 compatible = "qcom,spi-qup-v2.2.1"; 717 reg = <0x078b5000 0x600>; 718 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 720 <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; 721 clock-names = "iface", "core"; 722 pinctrl-names = "default"; 723 pinctrl-0 = <&blsp1_spi0_default>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 status = "disabled"; 727 }; 728 729 blsp1_i2c1: i2c@78b6000 { 730 compatible = "qcom,i2c-qup-v2.2.1"; 731 reg = <0x078b6000 0x600>; 732 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 734 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 735 clock-names = "iface", "core"; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&blsp1_i2c1_default>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 status = "disabled"; 741 }; 742 743 blsp1_spi1: spi@78b6000 { 744 compatible = "qcom,spi-qup-v2.2.1"; 745 reg = <0x078b6000 0x600>; 746 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 748 <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; 749 clock-names = "iface", "core"; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&blsp1_spi1_default>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 757 blsp1_i2c2: i2c@78b7000 { 758 compatible = "qcom,i2c-qup-v2.2.1"; 759 reg = <0x078b7000 0x600>; 760 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 762 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 763 clock-names = "iface", "core"; 764 pinctrl-names = "default"; 765 pinctrl-0 = <&blsp1_i2c2_default>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 status = "disabled"; 769 }; 770 771 blsp1_spi2: spi@78b7000 { 772 compatible = "qcom,spi-qup-v2.2.1"; 773 reg = <0x078b7000 0x600>; 774 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 776 <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; 777 clock-names = "iface", "core"; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&blsp1_spi2_default>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 status = "disabled"; 783 }; 784 785 blsp1_i2c3: i2c@78b8000 { 786 compatible = "qcom,i2c-qup-v2.2.1"; 787 reg = <0x078b8000 0x600>; 788 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 790 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 791 clock-names = "iface", "core"; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&blsp1_i2c3_default>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 status = "disabled"; 797 }; 798 799 blsp1_spi3: spi@78b8000 { 800 compatible = "qcom,spi-qup-v2.2.1"; 801 reg = <0x078b8000 0x600>; 802 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 804 <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; 805 clock-names = "iface", "core"; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&blsp1_spi3_default>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 status = "disabled"; 811 }; 812 813 blsp1_i2c4: i2c@78b9000 { 814 compatible = "qcom,i2c-qup-v2.2.1"; 815 reg = <0x078b9000 0x600>; 816 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 818 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 819 clock-names = "iface", "core"; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&blsp1_i2c4_default>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 status = "disabled"; 825 }; 826 827 blsp1_spi4: spi@78b9000 { 828 compatible = "qcom,spi-qup-v2.2.1"; 829 reg = <0x078b9000 0x600>; 830 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 832 <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; 833 clock-names = "iface", "core"; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&blsp1_spi4_default>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 blsp2_dma: dma@7ac4000 { 842 compatible = "qcom,bam-v1.7.0"; 843 reg = <0x07ac4000 0x17000>; 844 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 846 clock-names = "bam_clk"; 847 #dma-cells = <1>; 848 qcom,ee = <0>; 849 status = "disabled"; 850 }; 851 852 blsp2_uart0: serial@7aef000 { 853 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 854 reg = <0x07aef000 0x200>; 855 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 857 clock-names = "core", "iface"; 858 dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; 859 dma-names = "rx", "tx"; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&blsp2_uart0_default>; 862 status = "disabled"; 863 }; 864 865 blsp2_i2c0: i2c@7af5000 { 866 compatible = "qcom,i2c-qup-v2.2.1"; 867 reg = <0x07af5000 0x600>; 868 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 870 <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; 871 clock-names = "iface", "core"; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&blsp2_i2c0_default>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 status = "disabled"; 877 }; 878 879 blsp2_spi0: spi@7af5000 { 880 compatible = "qcom,spi-qup-v2.2.1"; 881 reg = <0x07af5000 0x600>; 882 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 884 <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; 885 clock-names = "iface", "core"; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&blsp2_spi0_default>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 status = "disabled"; 891 }; 892 893 intc: interrupt-controller@b000000 { 894 compatible = "qcom,msm-qgic2"; 895 interrupt-controller; 896 #interrupt-cells = <3>; 897 reg = <0x0b000000 0x1000>, 898 <0x0b002000 0x1000>; 899 }; 900 901 apcs_glb: mailbox@b011000 { 902 compatible = "qcom,qcs404-apcs-apps-global", "syscon"; 903 reg = <0x0b011000 0x1000>; 904 #mbox-cells = <1>; 905 }; 906 907 watchdog@b017000 { 908 compatible = "qcom,kpss-wdt"; 909 reg = <0x0b017000 0x1000>; 910 clocks = <&sleep_clk>; 911 }; 912 913 timer@b120000 { 914 #address-cells = <1>; 915 #size-cells = <1>; 916 ranges; 917 compatible = "arm,armv7-timer-mem"; 918 reg = <0x0b120000 0x1000>; 919 clock-frequency = <19200000>; 920 921 frame@b121000 { 922 frame-number = <0>; 923 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 925 reg = <0x0b121000 0x1000>, 926 <0x0b122000 0x1000>; 927 }; 928 929 frame@b123000 { 930 frame-number = <1>; 931 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 932 reg = <0x0b123000 0x1000>; 933 status = "disabled"; 934 }; 935 936 frame@b124000 { 937 frame-number = <2>; 938 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 939 reg = <0x0b124000 0x1000>; 940 status = "disabled"; 941 }; 942 943 frame@b125000 { 944 frame-number = <3>; 945 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 946 reg = <0x0b125000 0x1000>; 947 status = "disabled"; 948 }; 949 950 frame@b126000 { 951 frame-number = <4>; 952 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 953 reg = <0x0b126000 0x1000>; 954 status = "disabled"; 955 }; 956 957 frame@b127000 { 958 frame-number = <5>; 959 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 960 reg = <0xb127000 0x1000>; 961 status = "disabled"; 962 }; 963 964 frame@b128000 { 965 frame-number = <6>; 966 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 967 reg = <0x0b128000 0x1000>; 968 status = "disabled"; 969 }; 970 }; 971 972 remoteproc_adsp: remoteproc@c700000 { 973 compatible = "qcom,qcs404-adsp-pas"; 974 reg = <0x0c700000 0x4040>; 975 976 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 977 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 978 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 979 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 980 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 981 interrupt-names = "wdog", "fatal", "ready", 982 "handover", "stop-ack"; 983 984 clocks = <&xo_board>; 985 clock-names = "xo"; 986 987 memory-region = <&adsp_fw_mem>; 988 989 qcom,smem-states = <&adsp_smp2p_out 0>; 990 qcom,smem-state-names = "stop"; 991 992 status = "disabled"; 993 994 glink-edge { 995 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 996 997 qcom,remote-pid = <2>; 998 mboxes = <&apcs_glb 8>; 999 1000 label = "adsp"; 1001 }; 1002 }; 1003 1004 pcie: pci@10000000 { 1005 compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; 1006 reg = <0x10000000 0xf1d>, 1007 <0x10000f20 0xa8>, 1008 <0x07780000 0x2000>, 1009 <0x10001000 0x2000>; 1010 reg-names = "dbi", "elbi", "parf", "config"; 1011 device_type = "pci"; 1012 linux,pci-domain = <0>; 1013 bus-range = <0x00 0xff>; 1014 num-lanes = <1>; 1015 #address-cells = <3>; 1016 #size-cells = <2>; 1017 1018 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ 1019 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ 1020 1021 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1022 interrupt-names = "msi"; 1023 #interrupt-cells = <1>; 1024 interrupt-map-mask = <0 0 0 0x7>; 1025 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1026 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1027 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1028 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1029 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1030 <&gcc GCC_PCIE_0_AUX_CLK>, 1031 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1032 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1033 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1034 1035 resets = <&gcc 18>, 1036 <&gcc 17>, 1037 <&gcc 15>, 1038 <&gcc 19>, 1039 <&gcc GCC_PCIE_0_BCR>, 1040 <&gcc 16>; 1041 reset-names = "axi_m", 1042 "axi_s", 1043 "axi_m_sticky", 1044 "pipe_sticky", 1045 "pwr", 1046 "ahb"; 1047 1048 phys = <&pcie_phy>; 1049 phy-names = "pciephy"; 1050 1051 status = "disabled"; 1052 }; 1053 }; 1054 1055 timer { 1056 compatible = "arm,armv8-timer"; 1057 interrupts = <GIC_PPI 2 0xff08>, 1058 <GIC_PPI 3 0xff08>, 1059 <GIC_PPI 4 0xff08>, 1060 <GIC_PPI 1 0xff08>; 1061 }; 1062 1063 smp2p-adsp { 1064 compatible = "qcom,smp2p"; 1065 qcom,smem = <443>, <429>; 1066 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1067 mboxes = <&apcs_glb 10>; 1068 qcom,local-pid = <0>; 1069 qcom,remote-pid = <2>; 1070 1071 adsp_smp2p_out: master-kernel { 1072 qcom,entry-name = "master-kernel"; 1073 #qcom,smem-state-cells = <1>; 1074 }; 1075 1076 adsp_smp2p_in: slave-kernel { 1077 qcom,entry-name = "slave-kernel"; 1078 interrupt-controller; 1079 #interrupt-cells = <2>; 1080 }; 1081 }; 1082 1083 smp2p-cdsp { 1084 compatible = "qcom,smp2p"; 1085 qcom,smem = <94>, <432>; 1086 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1087 mboxes = <&apcs_glb 14>; 1088 qcom,local-pid = <0>; 1089 qcom,remote-pid = <5>; 1090 1091 cdsp_smp2p_out: master-kernel { 1092 qcom,entry-name = "master-kernel"; 1093 #qcom,smem-state-cells = <1>; 1094 }; 1095 1096 cdsp_smp2p_in: slave-kernel { 1097 qcom,entry-name = "slave-kernel"; 1098 interrupt-controller; 1099 #interrupt-cells = <2>; 1100 }; 1101 }; 1102 1103 smp2p-wcss { 1104 compatible = "qcom,smp2p"; 1105 qcom,smem = <435>, <428>; 1106 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1107 mboxes = <&apcs_glb 18>; 1108 qcom,local-pid = <0>; 1109 qcom,remote-pid = <1>; 1110 1111 wcss_smp2p_out: master-kernel { 1112 qcom,entry-name = "master-kernel"; 1113 #qcom,smem-state-cells = <1>; 1114 }; 1115 1116 wcss_smp2p_in: slave-kernel { 1117 qcom,entry-name = "slave-kernel"; 1118 interrupt-controller; 1119 #interrupt-cells = <2>; 1120 }; 1121 }; 1122 1123 thermal-zones { 1124 aoss-thermal { 1125 polling-delay-passive = <250>; 1126 polling-delay = <1000>; 1127 1128 thermal-sensors = <&tsens 0>; 1129 1130 trips { 1131 aoss_alert0: trip-point0 { 1132 temperature = <105000>; 1133 hysteresis = <2000>; 1134 type = "hot"; 1135 }; 1136 }; 1137 }; 1138 1139 q6-hvx-thermal { 1140 polling-delay-passive = <250>; 1141 polling-delay = <1000>; 1142 1143 thermal-sensors = <&tsens 1>; 1144 1145 trips { 1146 q6_hvx_alert0: trip-point0 { 1147 temperature = <105000>; 1148 hysteresis = <2000>; 1149 type = "hot"; 1150 }; 1151 }; 1152 }; 1153 1154 lpass-thermal { 1155 polling-delay-passive = <250>; 1156 polling-delay = <1000>; 1157 1158 thermal-sensors = <&tsens 2>; 1159 1160 trips { 1161 lpass_alert0: trip-point0 { 1162 temperature = <105000>; 1163 hysteresis = <2000>; 1164 type = "hot"; 1165 }; 1166 }; 1167 }; 1168 1169 wlan-thermal { 1170 polling-delay-passive = <250>; 1171 polling-delay = <1000>; 1172 1173 thermal-sensors = <&tsens 3>; 1174 1175 trips { 1176 wlan_alert0: trip-point0 { 1177 temperature = <105000>; 1178 hysteresis = <2000>; 1179 type = "hot"; 1180 }; 1181 }; 1182 }; 1183 1184 cluster-thermal { 1185 polling-delay-passive = <250>; 1186 polling-delay = <1000>; 1187 1188 thermal-sensors = <&tsens 4>; 1189 1190 trips { 1191 cluster_alert0: trip-point0 { 1192 temperature = <95000>; 1193 hysteresis = <2000>; 1194 type = "hot"; 1195 }; 1196 cluster_alert1: trip-point1 { 1197 temperature = <105000>; 1198 hysteresis = <2000>; 1199 type = "passive"; 1200 }; 1201 cluster_crit: cluster_crit { 1202 temperature = <120000>; 1203 hysteresis = <2000>; 1204 type = "critical"; 1205 }; 1206 }; 1207 cooling-maps { 1208 map0 { 1209 trip = <&cluster_alert1>; 1210 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1211 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1212 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1213 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1214 }; 1215 }; 1216 }; 1217 1218 cpu0-thermal { 1219 polling-delay-passive = <250>; 1220 polling-delay = <1000>; 1221 1222 thermal-sensors = <&tsens 5>; 1223 1224 trips { 1225 cpu0_alert0: trip-point0 { 1226 temperature = <95000>; 1227 hysteresis = <2000>; 1228 type = "hot"; 1229 }; 1230 cpu0_alert1: trip-point1 { 1231 temperature = <105000>; 1232 hysteresis = <2000>; 1233 type = "passive"; 1234 }; 1235 cpu0_crit: cpu_crit { 1236 temperature = <120000>; 1237 hysteresis = <2000>; 1238 type = "critical"; 1239 }; 1240 }; 1241 cooling-maps { 1242 map0 { 1243 trip = <&cpu0_alert1>; 1244 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1245 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1246 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1247 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1248 }; 1249 }; 1250 }; 1251 1252 cpu1-thermal { 1253 polling-delay-passive = <250>; 1254 polling-delay = <1000>; 1255 1256 thermal-sensors = <&tsens 6>; 1257 1258 trips { 1259 cpu1_alert0: trip-point0 { 1260 temperature = <95000>; 1261 hysteresis = <2000>; 1262 type = "hot"; 1263 }; 1264 cpu1_alert1: trip-point1 { 1265 temperature = <105000>; 1266 hysteresis = <2000>; 1267 type = "passive"; 1268 }; 1269 cpu1_crit: cpu_crit { 1270 temperature = <120000>; 1271 hysteresis = <2000>; 1272 type = "critical"; 1273 }; 1274 }; 1275 cooling-maps { 1276 map0 { 1277 trip = <&cpu1_alert1>; 1278 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1279 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1280 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1281 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1282 }; 1283 }; 1284 }; 1285 1286 cpu2-thermal { 1287 polling-delay-passive = <250>; 1288 polling-delay = <1000>; 1289 1290 thermal-sensors = <&tsens 7>; 1291 1292 trips { 1293 cpu2_alert0: trip-point0 { 1294 temperature = <95000>; 1295 hysteresis = <2000>; 1296 type = "hot"; 1297 }; 1298 cpu2_alert1: trip-point1 { 1299 temperature = <105000>; 1300 hysteresis = <2000>; 1301 type = "passive"; 1302 }; 1303 cpu2_crit: cpu_crit { 1304 temperature = <120000>; 1305 hysteresis = <2000>; 1306 type = "critical"; 1307 }; 1308 }; 1309 cooling-maps { 1310 map0 { 1311 trip = <&cpu2_alert1>; 1312 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1313 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1314 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1315 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1316 }; 1317 }; 1318 }; 1319 1320 cpu3-thermal { 1321 polling-delay-passive = <250>; 1322 polling-delay = <1000>; 1323 1324 thermal-sensors = <&tsens 8>; 1325 1326 trips { 1327 cpu3_alert0: trip-point0 { 1328 temperature = <95000>; 1329 hysteresis = <2000>; 1330 type = "hot"; 1331 }; 1332 cpu3_alert1: trip-point1 { 1333 temperature = <105000>; 1334 hysteresis = <2000>; 1335 type = "passive"; 1336 }; 1337 cpu3_crit: cpu_crit { 1338 temperature = <120000>; 1339 hysteresis = <2000>; 1340 type = "critical"; 1341 }; 1342 }; 1343 cooling-maps { 1344 map0 { 1345 trip = <&cpu3_alert1>; 1346 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1347 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1348 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1349 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1350 }; 1351 }; 1352 }; 1353 1354 gpu-thermal { 1355 polling-delay-passive = <250>; 1356 polling-delay = <1000>; 1357 1358 thermal-sensors = <&tsens 9>; 1359 1360 trips { 1361 gpu_alert0: trip-point0 { 1362 temperature = <95000>; 1363 hysteresis = <2000>; 1364 type = "hot"; 1365 }; 1366 }; 1367 }; 1368 }; 1369}; 1370