1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2018, Linaro Limited 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-qcs404.h> 6 7/ { 8 interrupt-parent = <&intc>; 9 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 chosen { }; 14 15 clocks { 16 xo_board: xo-board { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <19200000>; 20 }; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 CPU0: cpu@100 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a53"; 30 reg = <0x100>; 31 enable-method = "psci"; 32 next-level-cache = <&L2_0>; 33 }; 34 35 CPU1: cpu@101 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x101>; 39 enable-method = "psci"; 40 next-level-cache = <&L2_0>; 41 }; 42 43 CPU2: cpu@102 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x102>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU3: cpu@103 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x103>; 55 enable-method = "psci"; 56 next-level-cache = <&L2_0>; 57 }; 58 59 L2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 }; 63 }; 64 65 firmware { 66 scm: scm { 67 compatible = "qcom,scm-qcs404", "qcom,scm"; 68 #reset-cells = <1>; 69 }; 70 }; 71 72 memory@80000000 { 73 device_type = "memory"; 74 /* We expect the bootloader to fill in the size */ 75 reg = <0 0x80000000 0 0>; 76 }; 77 78 psci { 79 compatible = "arm,psci-1.0"; 80 method = "smc"; 81 }; 82 83 remoteproc_adsp: remoteproc-adsp { 84 compatible = "qcom,qcs404-adsp-pas"; 85 86 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 87 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 88 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 89 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 90 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 91 interrupt-names = "wdog", "fatal", "ready", 92 "handover", "stop-ack"; 93 94 clocks = <&xo_board>; 95 clock-names = "xo"; 96 97 memory-region = <&adsp_fw_mem>; 98 99 qcom,smem-states = <&adsp_smp2p_out 0>; 100 qcom,smem-state-names = "stop"; 101 102 status = "disabled"; 103 104 glink-edge { 105 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 106 107 qcom,remote-pid = <2>; 108 mboxes = <&apcs_glb 8>; 109 110 label = "adsp"; 111 }; 112 }; 113 114 remoteproc_cdsp: remoteproc-cdsp { 115 compatible = "qcom,qcs404-cdsp-pas"; 116 117 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 118 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 119 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 120 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 121 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 122 interrupt-names = "wdog", "fatal", "ready", 123 "handover", "stop-ack"; 124 125 clocks = <&xo_board>; 126 clock-names = "xo"; 127 128 memory-region = <&cdsp_fw_mem>; 129 130 qcom,smem-states = <&cdsp_smp2p_out 0>; 131 qcom,smem-state-names = "stop"; 132 133 status = "disabled"; 134 135 glink-edge { 136 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 137 138 qcom,remote-pid = <5>; 139 mboxes = <&apcs_glb 12>; 140 141 label = "cdsp"; 142 }; 143 }; 144 145 remoteproc_wcss: remoteproc-wcss { 146 compatible = "qcom,qcs404-wcss-pas"; 147 148 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 149 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 150 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 151 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 152 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 153 interrupt-names = "wdog", "fatal", "ready", 154 "handover", "stop-ack"; 155 156 clocks = <&xo_board>; 157 clock-names = "xo"; 158 159 memory-region = <&wlan_fw_mem>; 160 161 qcom,smem-states = <&wcss_smp2p_out 0>; 162 qcom,smem-state-names = "stop"; 163 164 status = "disabled"; 165 166 glink-edge { 167 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 168 169 qcom,remote-pid = <1>; 170 mboxes = <&apcs_glb 16>; 171 172 label = "wcss"; 173 }; 174 }; 175 176 reserved-memory { 177 #address-cells = <2>; 178 #size-cells = <2>; 179 ranges; 180 181 memory@85600000 { 182 reg = <0 0x85600000 0 0x90000>; 183 no-map; 184 }; 185 186 smem_region: memory@85f00000 { 187 reg = <0 0x85f00000 0 0x200000>; 188 no-map; 189 }; 190 191 memory@86100000 { 192 reg = <0 0x86100000 0 0x300000>; 193 no-map; 194 }; 195 196 wlan_fw_mem: memory@86400000 { 197 reg = <0 0x86400000 0 0x1c00000>; 198 no-map; 199 }; 200 201 adsp_fw_mem: memory@88000000 { 202 reg = <0 0x88000000 0 0x1a00000>; 203 no-map; 204 }; 205 206 cdsp_fw_mem: memory@89a00000 { 207 reg = <0 0x89a00000 0 0x600000>; 208 no-map; 209 }; 210 211 wlan_msa_mem: memory@8a000000 { 212 reg = <0 0x8a000000 0 0x100000>; 213 no-map; 214 }; 215 }; 216 217 rpm-glink { 218 compatible = "qcom,glink-rpm"; 219 220 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 221 qcom,rpm-msg-ram = <&rpm_msg_ram>; 222 mboxes = <&apcs_glb 0>; 223 224 rpm_requests: glink-channel { 225 compatible = "qcom,rpm-qcs404"; 226 qcom,glink-channels = "rpm_requests"; 227 }; 228 }; 229 230 smem { 231 compatible = "qcom,smem"; 232 233 memory-region = <&smem_region>; 234 qcom,rpm-msg-ram = <&rpm_msg_ram>; 235 236 hwlocks = <&tcsr_mutex 3>; 237 }; 238 239 tcsr_mutex: hwlock { 240 compatible = "qcom,tcsr-mutex"; 241 syscon = <&tcsr_mutex_regs 0 0x1000>; 242 #hwlock-cells = <1>; 243 }; 244 245 soc: soc@0 { 246 #address-cells = <1>; 247 #size-cells = <1>; 248 ranges = <0 0 0 0xffffffff>; 249 compatible = "simple-bus"; 250 251 rpm_msg_ram: memory@60000 { 252 compatible = "qcom,rpm-msg-ram"; 253 reg = <0x00060000 0x6000>; 254 }; 255 256 rng: rng@e3000 { 257 compatible = "qcom,prng-ee"; 258 reg = <0x000e3000 0x1000>; 259 clocks = <&gcc GCC_PRNG_AHB_CLK>; 260 clock-names = "core"; 261 }; 262 263 tlmm: pinctrl@1000000 { 264 compatible = "qcom,qcs404-pinctrl"; 265 reg = <0x01000000 0x200000>, 266 <0x01300000 0x200000>, 267 <0x07b00000 0x200000>; 268 reg-names = "south", "north", "east"; 269 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 270 gpio-ranges = <&tlmm 0 0 120>; 271 gpio-controller; 272 #gpio-cells = <2>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 }; 276 277 gcc: clock-controller@1800000 { 278 compatible = "qcom,gcc-qcs404"; 279 reg = <0x01800000 0x80000>; 280 #clock-cells = <1>; 281 282 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 283 assigned-clock-rates = <19200000>; 284 }; 285 286 tcsr_mutex_regs: syscon@1905000 { 287 compatible = "syscon"; 288 reg = <0x01905000 0x20000>; 289 }; 290 291 spmi_bus: spmi@200f000 { 292 compatible = "qcom,spmi-pmic-arb"; 293 reg = <0x0200f000 0x001000>, 294 <0x02400000 0x800000>, 295 <0x02c00000 0x800000>, 296 <0x03800000 0x200000>, 297 <0x0200a000 0x002100>; 298 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 299 interrupt-names = "periph_irq"; 300 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 301 qcom,ee = <0>; 302 qcom,channel = <0>; 303 #address-cells = <2>; 304 #size-cells = <0>; 305 interrupt-controller; 306 #interrupt-cells = <4>; 307 }; 308 309 sdcc1: sdcc@7804000 { 310 compatible = "qcom,sdhci-msm-v5"; 311 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 312 reg-names = "hc_mem", "cmdq_mem"; 313 314 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 316 interrupt-names = "hc_irq", "pwr_irq"; 317 318 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 319 <&gcc GCC_SDCC1_AHB_CLK>, 320 <&xo_board>; 321 clock-names = "core", "iface", "xo"; 322 323 status = "disabled"; 324 }; 325 326 blsp1_dma: dma@7884000 { 327 compatible = "qcom,bam-v1.7.0"; 328 reg = <0x07884000 0x25000>; 329 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 331 clock-names = "bam_clk"; 332 #dma-cells = <1>; 333 qcom,controlled-remotely = <1>; 334 qcom,ee = <0>; 335 status = "okay"; 336 }; 337 338 blsp1_uart2: serial@78b1000 { 339 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 340 reg = <0x078b1000 0x200>; 341 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 343 clock-names = "core", "iface"; 344 dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; 345 dma-names = "rx", "tx"; 346 status = "okay"; 347 }; 348 349 intc: interrupt-controller@b000000 { 350 compatible = "qcom,msm-qgic2"; 351 interrupt-controller; 352 #interrupt-cells = <3>; 353 reg = <0x0b000000 0x1000>, 354 <0x0b002000 0x1000>; 355 }; 356 357 apcs_glb: mailbox@b011000 { 358 compatible = "qcom,qcs404-apcs-apps-global", "syscon"; 359 reg = <0x0b011000 0x1000>; 360 #mbox-cells = <1>; 361 }; 362 363 timer@b120000 { 364 #address-cells = <1>; 365 #size-cells = <1>; 366 ranges; 367 compatible = "arm,armv7-timer-mem"; 368 reg = <0x0b120000 0x1000>; 369 clock-frequency = <19200000>; 370 371 frame@b121000 { 372 frame-number = <0>; 373 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 375 reg = <0x0b121000 0x1000>, 376 <0x0b122000 0x1000>; 377 }; 378 379 frame@b123000 { 380 frame-number = <1>; 381 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 382 reg = <0x0b123000 0x1000>; 383 status = "disabled"; 384 }; 385 386 frame@b124000 { 387 frame-number = <2>; 388 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 389 reg = <0x0b124000 0x1000>; 390 status = "disabled"; 391 }; 392 393 frame@b125000 { 394 frame-number = <3>; 395 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 396 reg = <0x0b125000 0x1000>; 397 status = "disabled"; 398 }; 399 400 frame@b126000 { 401 frame-number = <4>; 402 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 403 reg = <0x0b126000 0x1000>; 404 status = "disabled"; 405 }; 406 407 frame@b127000 { 408 frame-number = <5>; 409 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 410 reg = <0xb127000 0x1000>; 411 status = "disabled"; 412 }; 413 414 frame@b128000 { 415 frame-number = <6>; 416 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 417 reg = <0x0b128000 0x1000>; 418 status = "disabled"; 419 }; 420 }; 421 }; 422 423 timer { 424 compatible = "arm,armv8-timer"; 425 interrupts = <GIC_PPI 2 0xff08>, 426 <GIC_PPI 3 0xff08>, 427 <GIC_PPI 4 0xff08>, 428 <GIC_PPI 1 0xff08>; 429 }; 430 431 smp2p-adsp { 432 compatible = "qcom,smp2p"; 433 qcom,smem = <443>, <429>; 434 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 435 mboxes = <&apcs_glb 10>; 436 qcom,local-pid = <0>; 437 qcom,remote-pid = <2>; 438 439 adsp_smp2p_out: master-kernel { 440 qcom,entry-name = "master-kernel"; 441 #qcom,smem-state-cells = <1>; 442 }; 443 444 adsp_smp2p_in: slave-kernel { 445 qcom,entry-name = "slave-kernel"; 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 }; 449 }; 450 451 smp2p-cdsp { 452 compatible = "qcom,smp2p"; 453 qcom,smem = <94>, <432>; 454 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 455 mboxes = <&apcs_glb 14>; 456 qcom,local-pid = <0>; 457 qcom,remote-pid = <5>; 458 459 cdsp_smp2p_out: master-kernel { 460 qcom,entry-name = "master-kernel"; 461 #qcom,smem-state-cells = <1>; 462 }; 463 464 cdsp_smp2p_in: slave-kernel { 465 qcom,entry-name = "slave-kernel"; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 }; 469 }; 470 471 smp2p-wcss { 472 compatible = "qcom,smp2p"; 473 qcom,smem = <435>, <428>; 474 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 475 mboxes = <&apcs_glb 18>; 476 qcom,local-pid = <0>; 477 qcom,remote-pid = <1>; 478 479 wcss_smp2p_out: master-kernel { 480 qcom,entry-name = "master-kernel"; 481 #qcom,smem-state-cells = <1>; 482 }; 483 484 wcss_smp2p_in: slave-kernel { 485 qcom,entry-name = "slave-kernel"; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 }; 489 }; 490}; 491