xref: /openbmc/linux/arch/arm64/boot/dts/qcom/qcs404.dtsi (revision 67779ca2)

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
#include <dt-bindings/clock/qcom,rpmcc.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&L2_0>;
		};

		CPU1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&L2_0>;
		};

		CPU3: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				idle-state-name = "standalone-power-collapse";
				arm,psci-suspend-param = <0x40000003>;
				entry-latency-us = <125>;
				exit-latency-us = <180>;
				min-residency-us = <595>;
				local-timer-stop;
			};
		};
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm-qcs404", "qcom,scm";
			#reset-cells = <1>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0 0x80000000 0 0>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		memory@85600000 {
			reg = <0 0x85600000 0 0x90000>;
			no-map;
		};

		smem_region: memory@85f00000 {
			reg = <0 0x85f00000 0 0x200000>;
			no-map;
		};

		memory@86100000 {
			reg = <0 0x86100000 0 0x300000>;
			no-map;
		};

		wlan_fw_mem: memory@86400000 {
			reg = <0 0x86400000 0 0x1c00000>;
			no-map;
		};

		adsp_fw_mem: memory@88000000 {
			reg = <0 0x88000000 0 0x1a00000>;
			no-map;
		};

		cdsp_fw_mem: memory@89a00000 {
			reg = <0 0x89a00000 0 0x600000>;
			no-map;
		};

		wlan_msa_mem: memory@8a000000 {
			reg = <0 0x8a000000 0 0x100000>;
			no-map;
		};
	};

	rpm-glink {
		compatible = "qcom,glink-rpm";

		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		mboxes = <&apcs_glb 0>;

		rpm_requests: glink-channel {
			compatible = "qcom,rpm-qcs404";
			qcom,glink-channels = "rpm_requests";

			rpmcc: clock-controller {
				compatible = "qcom,rpmcc-qcs404";
				#clock-cells = <1>;
			};
		};
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x1000>;
		#hwlock-cells = <1>;
	};

	soc: soc@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		turingcc: clock-controller@800000 {
			compatible = "qcom,qcs404-turingcc";
			reg = <0x00800000 0x30000>;
			clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;

			#clock-cells = <1>;
			#reset-cells = <1>;

			status = "disabled";
		};

		rpm_msg_ram: memory@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x00060000 0x6000>;
		};

		rng: rng@e3000 {
			compatible = "qcom,prng-ee";
			reg = <0x000e3000 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		remoteproc_cdsp: remoteproc@b00000 {
			compatible = "qcom,qcs404-cdsp-pas";
			reg = <0x00b00000 0x4040>;

			interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&xo_board>,
				 <&gcc GCC_CDSP_CFG_AHB_CLK>,
				 <&gcc GCC_CDSP_TBU_CLK>,
				 <&gcc GCC_BIMC_CDSP_CLK>,
				 <&turingcc TURING_WRAPPER_AON_CLK>,
				 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
				 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
				 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
			clock-names = "xo",
				      "sway",
				      "tbu",
				      "bimc",
				      "ahb_aon",
				      "q6ss_slave",
				      "q6ss_master",
				      "q6_axim";

			resets = <&gcc GCC_CDSP_RESTART>;
			reset-names = "restart";

			qcom,halt-regs = <&tcsr 0x19004>;

			memory-region = <&cdsp_fw_mem>;

			qcom,smem-states = <&cdsp_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;

				qcom,remote-pid = <5>;
				mboxes = <&apcs_glb 12>;

				label = "cdsp";
			};
		};

		tlmm: pinctrl@1000000 {
			compatible = "qcom,qcs404-pinctrl";
			reg = <0x01000000 0x200000>,
			      <0x01300000 0x200000>,
			      <0x07b00000 0x200000>;
			reg-names = "south", "north", "east";
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-ranges = <&tlmm 0 0 120>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;

			blsp1_i2c0_default: blsp1-i2c0-default {
				pins = "gpio32", "gpio33";
				function = "blsp_i2c0";
			};

			blsp1_i2c1_default: blsp1-i2c1-default {
				pins = "gpio24", "gpio25";
				function = "blsp_i2c1";
			};

			blsp1_i2c2_default: blsp1-i2c2-default {
				sda {
					pins = "gpio19";
					function = "blsp_i2c_sda_a2";
				};

				scl {
					pins = "gpio20";
					function = "blsp_i2c_scl_a2";
				};
			};

			blsp1_i2c3_default: blsp1-i2c3-default {
				pins = "gpio84", "gpio85";
				function = "blsp_i2c3";
			};

			blsp1_i2c4_default: blsp1-i2c4-default {
				pins = "gpio117", "gpio118";
				function = "blsp_i2c4";
			};

			blsp1_uart0_default: blsp1-uart0-default {
				pins = "gpio30", "gpio31", "gpio32", "gpio33";
				function = "blsp_uart0";
			};

			blsp1_uart1_default: blsp1-uart1-default {
				pins = "gpio22", "gpio23";
				function = "blsp_uart1";
			};

			blsp1_uart2_default: blsp1-uart2-default {
				rx {
					pins = "gpio18";
					function = "blsp_uart_rx_a2";
				};

				tx {
					pins = "gpio17";
					function = "blsp_uart_tx_a2";
				};
			};

			blsp1_uart3_default: blsp1-uart3-default {
				pins = "gpio82", "gpio83", "gpio84", "gpio85";
				function = "blsp_uart3";
			};

			blsp2_i2c0_default: blsp2-i2c0-default {
				pins = "gpio28", "gpio29";
				function = "blsp_i2c5";
			};

			blsp1_spi0_default: blsp1-spi0-default {
				pins = "gpio30", "gpio31", "gpio32", "gpio33";
				function = "blsp_spi0";
			};

			blsp1_spi1_default: blsp1-spi1-default {
				pins = "gpio22", "gpio23", "gpio24", "gpio25";
				function = "blsp_spi1";
			};

			blsp1_spi2_default: blsp1-spi2-default {
				pins = "gpio17", "gpio18", "gpio19", "gpio20";
				function = "blsp_spi2";
			};

			blsp1_spi3_default: blsp1-spi3-default {
				pins = "gpio82", "gpio83", "gpio84", "gpio85";
				function = "blsp_spi3";
			};

			blsp1_spi4_default: blsp1-spi4-default {
				pins = "gpio37", "gpio38", "gpio117", "gpio118";
				function = "blsp_spi4";
			};

			blsp2_spi0_default: blsp2-spi0-default {
				pins = "gpio26", "gpio27", "gpio28", "gpio29";
				function = "blsp_spi5";
			};

			blsp2_uart0_default: blsp2-uart0-default {
				pins = "gpio26", "gpio27", "gpio28", "gpio29";
				function = "blsp_uart5";
			};
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-qcs404";
			reg = <0x01800000 0x80000>;
			#clock-cells = <1>;

			assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
			assigned-clock-rates = <19200000>;
		};

		tcsr_mutex_regs: syscon@1905000 {
			compatible = "syscon";
			reg = <0x01905000 0x20000>;
		};

		tcsr: syscon@1937000 {
			compatible = "syscon";
			reg = <0x01937000 0x25000>;
		};

		spmi_bus: spmi@200f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x0200f000 0x001000>,
			      <0x02400000 0x800000>,
			      <0x02c00000 0x800000>,
			      <0x03800000 0x200000>,
			      <0x0200a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		remoteproc_wcss: remoteproc@7400000 {
			compatible = "qcom,qcs404-wcss-pas";
			reg = <0x07400000 0x4040>;

			interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
					      <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&xo_board>;
			clock-names = "xo";

			memory-region = <&wlan_fw_mem>;

			qcom,smem-states = <&wcss_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

				qcom,remote-pid = <1>;
				mboxes = <&apcs_glb 16>;

				label = "wcss";
			};
		};

		sdcc1: sdcc@7804000 {
			compatible = "qcom,sdhci-msm-v5";
			reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
			reg-names = "hc_mem", "cmdq_mem";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";

			status = "disabled";
		};

		blsp1_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x25000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "okay";
		};

		blsp1_uart0: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
			dma-names = "rx", "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_uart0_default>;
			status = "disabled";
		};

		blsp1_uart1: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
			dma-names = "rx", "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_uart1_default>;
			status = "disabled";
		};

		blsp1_uart2: serial@78b1000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b1000 0x200>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
			dma-names = "rx", "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_uart2_default>;
			status = "okay";
		};

		ethernet: ethernet@7a80000 {
			compatible = "qcom,qcs404-ethqos";
			reg = <0x07a80000 0x10000>,
				<0x07a96000 0x100>;
			reg-names = "stmmaceth", "rgmii";
			clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
			clocks = <&gcc GCC_ETH_AXI_CLK>,
				<&gcc GCC_ETH_SLAVE_AHB_CLK>,
				<&gcc GCC_ETH_PTP_CLK>,
				<&gcc GCC_ETH_RGMII_CLK>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "eth_lpi";

			snps,tso;
			rx-fifo-depth = <4096>;
			tx-fifo-depth = <4096>;

			status = "disabled";
		};

		wifi: wifi@a000000 {
			compatible = "qcom,wcn3990-wifi";
			reg = <0xa000000 0x800000>;
			reg-names = "membase";
			memory-region = <&wlan_msa_mem>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		blsp1_uart3: serial@78b2000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b2000 0x200>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
			dma-names = "rx", "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_uart3_default>;
			status = "disabled";
		};

		blsp1_i2c0: i2c@78b5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c0_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_spi0: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi0_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c1: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c1_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_spi1: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi1_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c2: i2c@78b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c2_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_spi2: spi@78b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi2_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c3: i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b8000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c3_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_spi3: spi@78b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b8000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi3_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c4: i2c@78b9000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b9000 0x600>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c4_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_spi4: spi@78b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b9000 0x600>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_spi4_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_dma: dma@7ac4000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07ac4000 0x17000>;
			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp2_uart0: serial@7aef000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x07aef000 0x200>;
			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
			dma-names = "rx", "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_uart0_default>;
			status = "disabled";
		};

		blsp2_i2c0: i2c@7af5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x07af5000 0x600>;
			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
				 <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_i2c0_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_spi0: spi@7af5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x07af5000 0x600>;
			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
				 <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_spi0_default>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>,
			      <0x0b002000 0x1000>;
		};

		apcs_glb: mailbox@b011000 {
			compatible = "qcom,qcs404-apcs-apps-global", "syscon";
			reg = <0x0b011000 0x1000>;
			#mbox-cells = <1>;
		};

		timer@b120000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x0b120000 0x1000>;
			clock-frequency = <19200000>;

			frame@b121000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b121000 0x1000>,
				      <0x0b122000 0x1000>;
			};

			frame@b123000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b123000 0x1000>;
				status = "disabled";
			};

			frame@b124000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b124000 0x1000>;
				status = "disabled";
			};

			frame@b125000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b125000 0x1000>;
				status = "disabled";
			};

			frame@b126000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b126000 0x1000>;
				status = "disabled";
			};

			frame@b127000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb127000 0x1000>;
				status = "disabled";
			};

			frame@b128000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b128000 0x1000>;
				status = "disabled";
			};
		};

		remoteproc_adsp: remoteproc@c700000 {
			compatible = "qcom,qcs404-adsp-pas";
			reg = <0x0c700000 0x4040>;

			interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&xo_board>;
			clock-names = "xo";

			memory-region = <&adsp_fw_mem>;

			qcom,smem-states = <&adsp_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;

				qcom,remote-pid = <2>;
				mboxes = <&apcs_glb 8>;

				label = "adsp";
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 0xff08>,
			     <GIC_PPI 3 0xff08>,
			     <GIC_PPI 4 0xff08>,
			     <GIC_PPI 1 0xff08>;
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 10>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-wcss {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 18>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		wcss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		wcss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};
};