1b4d82f4dSVinod Koul// SPDX-License-Identifier: GPL-2.0 2b4d82f4dSVinod Koul// Copyright (c) 2018, Linaro Limited 3b4d82f4dSVinod Koul 4b4d82f4dSVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 5b4d82f4dSVinod Koul#include <dt-bindings/clock/qcom,gcc-qcs404.h> 60b0c3390SBjorn Andersson#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 7bf75731dSBjorn Andersson#include <dt-bindings/clock/qcom,rpmcc.h> 811f61210SBjorn Andersson#include <dt-bindings/power/qcom-rpmpd.h> 9f48cee32SAmit Kucheria#include <dt-bindings/thermal/thermal.h> 10b4d82f4dSVinod Koul 11b4d82f4dSVinod Koul/ { 12b4d82f4dSVinod Koul interrupt-parent = <&intc>; 13b4d82f4dSVinod Koul 14b4d82f4dSVinod Koul #address-cells = <2>; 15b4d82f4dSVinod Koul #size-cells = <2>; 16b4d82f4dSVinod Koul 17b4d82f4dSVinod Koul chosen { }; 18b4d82f4dSVinod Koul 19b4d82f4dSVinod Koul clocks { 20b4d82f4dSVinod Koul xo_board: xo-board { 21b4d82f4dSVinod Koul compatible = "fixed-clock"; 22b4d82f4dSVinod Koul #clock-cells = <0>; 23b4d82f4dSVinod Koul clock-frequency = <19200000>; 24b4d82f4dSVinod Koul }; 2510c71fd1SJorge Ramirez-Ortiz 2610c71fd1SJorge Ramirez-Ortiz sleep_clk: sleep-clk { 2710c71fd1SJorge Ramirez-Ortiz compatible = "fixed-clock"; 2810c71fd1SJorge Ramirez-Ortiz #clock-cells = <0>; 2910c71fd1SJorge Ramirez-Ortiz clock-frequency = <32768>; 3010c71fd1SJorge Ramirez-Ortiz }; 31b4d82f4dSVinod Koul }; 32b4d82f4dSVinod Koul 33b4d82f4dSVinod Koul cpus { 34b4d82f4dSVinod Koul #address-cells = <1>; 35b4d82f4dSVinod Koul #size-cells = <0>; 36b4d82f4dSVinod Koul 37b4d82f4dSVinod Koul CPU0: cpu@100 { 38b4d82f4dSVinod Koul device_type = "cpu"; 39b4d82f4dSVinod Koul compatible = "arm,cortex-a53"; 40b4d82f4dSVinod Koul reg = <0x100>; 41b4d82f4dSVinod Koul enable-method = "psci"; 4245ea8f32SNiklas Cassel cpu-idle-states = <&CPU_SLEEP_0>; 43b4d82f4dSVinod Koul next-level-cache = <&L2_0>; 44f48cee32SAmit Kucheria #cooling-cells = <2>; 45cbccc6bcSJorge Ramirez-Ortiz clocks = <&apcs_glb>; 46cbccc6bcSJorge Ramirez-Ortiz operating-points-v2 = <&cpu_opp_table>; 4704aadcaaSNiklas Cassel power-domains = <&cpr>; 4804aadcaaSNiklas Cassel power-domain-names = "cpr"; 49b4d82f4dSVinod Koul }; 50b4d82f4dSVinod Koul 51b4d82f4dSVinod Koul CPU1: cpu@101 { 52b4d82f4dSVinod Koul device_type = "cpu"; 53b4d82f4dSVinod Koul compatible = "arm,cortex-a53"; 54b4d82f4dSVinod Koul reg = <0x101>; 55b4d82f4dSVinod Koul enable-method = "psci"; 5645ea8f32SNiklas Cassel cpu-idle-states = <&CPU_SLEEP_0>; 57b4d82f4dSVinod Koul next-level-cache = <&L2_0>; 58f48cee32SAmit Kucheria #cooling-cells = <2>; 59cbccc6bcSJorge Ramirez-Ortiz clocks = <&apcs_glb>; 60cbccc6bcSJorge Ramirez-Ortiz operating-points-v2 = <&cpu_opp_table>; 6104aadcaaSNiklas Cassel power-domains = <&cpr>; 6204aadcaaSNiklas Cassel power-domain-names = "cpr"; 63b4d82f4dSVinod Koul }; 64b4d82f4dSVinod Koul 65b4d82f4dSVinod Koul CPU2: cpu@102 { 66b4d82f4dSVinod Koul device_type = "cpu"; 67b4d82f4dSVinod Koul compatible = "arm,cortex-a53"; 68b4d82f4dSVinod Koul reg = <0x102>; 69b4d82f4dSVinod Koul enable-method = "psci"; 7045ea8f32SNiklas Cassel cpu-idle-states = <&CPU_SLEEP_0>; 71b4d82f4dSVinod Koul next-level-cache = <&L2_0>; 72f48cee32SAmit Kucheria #cooling-cells = <2>; 73cbccc6bcSJorge Ramirez-Ortiz clocks = <&apcs_glb>; 74cbccc6bcSJorge Ramirez-Ortiz operating-points-v2 = <&cpu_opp_table>; 7504aadcaaSNiklas Cassel power-domains = <&cpr>; 7604aadcaaSNiklas Cassel power-domain-names = "cpr"; 77b4d82f4dSVinod Koul }; 78b4d82f4dSVinod Koul 79b4d82f4dSVinod Koul CPU3: cpu@103 { 80b4d82f4dSVinod Koul device_type = "cpu"; 81b4d82f4dSVinod Koul compatible = "arm,cortex-a53"; 82b4d82f4dSVinod Koul reg = <0x103>; 83b4d82f4dSVinod Koul enable-method = "psci"; 8445ea8f32SNiklas Cassel cpu-idle-states = <&CPU_SLEEP_0>; 85b4d82f4dSVinod Koul next-level-cache = <&L2_0>; 86f48cee32SAmit Kucheria #cooling-cells = <2>; 87cbccc6bcSJorge Ramirez-Ortiz clocks = <&apcs_glb>; 88cbccc6bcSJorge Ramirez-Ortiz operating-points-v2 = <&cpu_opp_table>; 8904aadcaaSNiklas Cassel power-domains = <&cpr>; 9004aadcaaSNiklas Cassel power-domain-names = "cpr"; 91b4d82f4dSVinod Koul }; 92b4d82f4dSVinod Koul 93b4d82f4dSVinod Koul L2_0: l2-cache { 94b4d82f4dSVinod Koul compatible = "cache"; 95b4d82f4dSVinod Koul cache-level = <2>; 96b4d82f4dSVinod Koul }; 9745ea8f32SNiklas Cassel 9845ea8f32SNiklas Cassel idle-states { 9945ea8f32SNiklas Cassel entry-method = "psci"; 10045ea8f32SNiklas Cassel 10145ea8f32SNiklas Cassel CPU_SLEEP_0: cpu-sleep-0 { 10245ea8f32SNiklas Cassel compatible = "arm,idle-state"; 10345ea8f32SNiklas Cassel idle-state-name = "standalone-power-collapse"; 10445ea8f32SNiklas Cassel arm,psci-suspend-param = <0x40000003>; 10545ea8f32SNiklas Cassel entry-latency-us = <125>; 10645ea8f32SNiklas Cassel exit-latency-us = <180>; 10745ea8f32SNiklas Cassel min-residency-us = <595>; 10845ea8f32SNiklas Cassel local-timer-stop; 10945ea8f32SNiklas Cassel }; 11045ea8f32SNiklas Cassel }; 111b4d82f4dSVinod Koul }; 112b4d82f4dSVinod Koul 113cbccc6bcSJorge Ramirez-Ortiz cpu_opp_table: cpu-opp-table { 11404aadcaaSNiklas Cassel compatible = "operating-points-v2-kryo-cpu"; 115cbccc6bcSJorge Ramirez-Ortiz opp-shared; 116cbccc6bcSJorge Ramirez-Ortiz 117cbccc6bcSJorge Ramirez-Ortiz opp-1094400000 { 118cbccc6bcSJorge Ramirez-Ortiz opp-hz = /bits/ 64 <1094400000>; 11904aadcaaSNiklas Cassel required-opps = <&cpr_opp1>; 120cbccc6bcSJorge Ramirez-Ortiz }; 121cbccc6bcSJorge Ramirez-Ortiz opp-1248000000 { 122cbccc6bcSJorge Ramirez-Ortiz opp-hz = /bits/ 64 <1248000000>; 12304aadcaaSNiklas Cassel required-opps = <&cpr_opp2>; 124cbccc6bcSJorge Ramirez-Ortiz }; 125cbccc6bcSJorge Ramirez-Ortiz opp-1401600000 { 126cbccc6bcSJorge Ramirez-Ortiz opp-hz = /bits/ 64 <1401600000>; 12704aadcaaSNiklas Cassel required-opps = <&cpr_opp3>; 12804aadcaaSNiklas Cassel }; 12904aadcaaSNiklas Cassel }; 13004aadcaaSNiklas Cassel 13104aadcaaSNiklas Cassel cpr_opp_table: cpr-opp-table { 13204aadcaaSNiklas Cassel compatible = "operating-points-v2-qcom-level"; 13304aadcaaSNiklas Cassel 13404aadcaaSNiklas Cassel cpr_opp1: opp1 { 13504aadcaaSNiklas Cassel opp-level = <1>; 13604aadcaaSNiklas Cassel qcom,opp-fuse-level = <1>; 13704aadcaaSNiklas Cassel }; 13804aadcaaSNiklas Cassel cpr_opp2: opp2 { 13904aadcaaSNiklas Cassel opp-level = <2>; 14004aadcaaSNiklas Cassel qcom,opp-fuse-level = <2>; 14104aadcaaSNiklas Cassel }; 14204aadcaaSNiklas Cassel cpr_opp3: opp3 { 14304aadcaaSNiklas Cassel opp-level = <3>; 14404aadcaaSNiklas Cassel qcom,opp-fuse-level = <3>; 145cbccc6bcSJorge Ramirez-Ortiz }; 146cbccc6bcSJorge Ramirez-Ortiz }; 147cbccc6bcSJorge Ramirez-Ortiz 148e7fd184fSBjorn Andersson firmware { 149e7fd184fSBjorn Andersson scm: scm { 150e7fd184fSBjorn Andersson compatible = "qcom,scm-qcs404", "qcom,scm"; 151e7fd184fSBjorn Andersson #reset-cells = <1>; 152e7fd184fSBjorn Andersson }; 153e7fd184fSBjorn Andersson }; 154e7fd184fSBjorn Andersson 155b4d82f4dSVinod Koul memory@80000000 { 156b4d82f4dSVinod Koul device_type = "memory"; 157b4d82f4dSVinod Koul /* We expect the bootloader to fill in the size */ 158b4d82f4dSVinod Koul reg = <0 0x80000000 0 0>; 159b4d82f4dSVinod Koul }; 160b4d82f4dSVinod Koul 161b4d82f4dSVinod Koul psci { 162b4d82f4dSVinod Koul compatible = "arm,psci-1.0"; 163b4d82f4dSVinod Koul method = "smc"; 164b4d82f4dSVinod Koul }; 165b4d82f4dSVinod Koul 166d59117abSBjorn Andersson reserved-memory { 167d59117abSBjorn Andersson #address-cells = <2>; 168d59117abSBjorn Andersson #size-cells = <2>; 169d59117abSBjorn Andersson ranges; 170d59117abSBjorn Andersson 171a87fa5bcSBjorn Andersson tz_apps_mem: memory@85900000 { 172a87fa5bcSBjorn Andersson reg = <0 0x85900000 0 0x500000>; 173a87fa5bcSBjorn Andersson no-map; 174a87fa5bcSBjorn Andersson }; 175a87fa5bcSBjorn Andersson 176a87fa5bcSBjorn Andersson xbl_mem: memory@85e00000 { 177a87fa5bcSBjorn Andersson reg = <0 0x85e00000 0 0x100000>; 178d59117abSBjorn Andersson no-map; 179d59117abSBjorn Andersson }; 180d59117abSBjorn Andersson 181d59117abSBjorn Andersson smem_region: memory@85f00000 { 182d59117abSBjorn Andersson reg = <0 0x85f00000 0 0x200000>; 183d59117abSBjorn Andersson no-map; 184d59117abSBjorn Andersson }; 185d59117abSBjorn Andersson 186a87fa5bcSBjorn Andersson tz_mem: memory@86100000 { 187d59117abSBjorn Andersson reg = <0 0x86100000 0 0x300000>; 188d59117abSBjorn Andersson no-map; 189d59117abSBjorn Andersson }; 190d59117abSBjorn Andersson 191d59117abSBjorn Andersson wlan_fw_mem: memory@86400000 { 192a87fa5bcSBjorn Andersson reg = <0 0x86400000 0 0x1100000>; 193d59117abSBjorn Andersson no-map; 194d59117abSBjorn Andersson }; 195d59117abSBjorn Andersson 196a87fa5bcSBjorn Andersson adsp_fw_mem: memory@87500000 { 197a87fa5bcSBjorn Andersson reg = <0 0x87500000 0 0x1a00000>; 198d59117abSBjorn Andersson no-map; 199d59117abSBjorn Andersson }; 200d59117abSBjorn Andersson 201a87fa5bcSBjorn Andersson cdsp_fw_mem: memory@88f00000 { 202a87fa5bcSBjorn Andersson reg = <0 0x88f00000 0 0x600000>; 203d59117abSBjorn Andersson no-map; 204d59117abSBjorn Andersson }; 205d59117abSBjorn Andersson 206a87fa5bcSBjorn Andersson wlan_msa_mem: memory@89500000 { 207a87fa5bcSBjorn Andersson reg = <0 0x89500000 0 0x100000>; 208a87fa5bcSBjorn Andersson no-map; 209a87fa5bcSBjorn Andersson }; 210a87fa5bcSBjorn Andersson 211a87fa5bcSBjorn Andersson uefi_mem: memory@9f800000 { 212a87fa5bcSBjorn Andersson reg = <0 0x9f800000 0 0x800000>; 213d59117abSBjorn Andersson no-map; 214d59117abSBjorn Andersson }; 215d59117abSBjorn Andersson }; 216d59117abSBjorn Andersson 2177fc7089dSBjorn Andersson rpm-glink { 2187fc7089dSBjorn Andersson compatible = "qcom,glink-rpm"; 2197fc7089dSBjorn Andersson 2207fc7089dSBjorn Andersson interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 2217fc7089dSBjorn Andersson qcom,rpm-msg-ram = <&rpm_msg_ram>; 2227fc7089dSBjorn Andersson mboxes = <&apcs_glb 0>; 2237fc7089dSBjorn Andersson 2247fc7089dSBjorn Andersson rpm_requests: glink-channel { 2257fc7089dSBjorn Andersson compatible = "qcom,rpm-qcs404"; 2267fc7089dSBjorn Andersson qcom,glink-channels = "rpm_requests"; 227bf75731dSBjorn Andersson 228bf75731dSBjorn Andersson rpmcc: clock-controller { 229bf75731dSBjorn Andersson compatible = "qcom,rpmcc-qcs404"; 230bf75731dSBjorn Andersson #clock-cells = <1>; 231bf75731dSBjorn Andersson }; 23211f61210SBjorn Andersson 23311f61210SBjorn Andersson rpmpd: power-controller { 23411f61210SBjorn Andersson compatible = "qcom,qcs404-rpmpd"; 23511f61210SBjorn Andersson #power-domain-cells = <1>; 23611f61210SBjorn Andersson operating-points-v2 = <&rpmpd_opp_table>; 23711f61210SBjorn Andersson 23811f61210SBjorn Andersson rpmpd_opp_table: opp-table { 23911f61210SBjorn Andersson compatible = "operating-points-v2"; 24011f61210SBjorn Andersson 24111f61210SBjorn Andersson rpmpd_opp_ret: opp1 { 24211f61210SBjorn Andersson opp-level = <16>; 24311f61210SBjorn Andersson }; 24411f61210SBjorn Andersson 24511f61210SBjorn Andersson rpmpd_opp_ret_plus: opp2 { 24611f61210SBjorn Andersson opp-level = <32>; 24711f61210SBjorn Andersson }; 24811f61210SBjorn Andersson 24911f61210SBjorn Andersson rpmpd_opp_min_svs: opp3 { 25011f61210SBjorn Andersson opp-level = <48>; 25111f61210SBjorn Andersson }; 25211f61210SBjorn Andersson 25311f61210SBjorn Andersson rpmpd_opp_low_svs: opp4 { 25411f61210SBjorn Andersson opp-level = <64>; 25511f61210SBjorn Andersson }; 25611f61210SBjorn Andersson 25711f61210SBjorn Andersson rpmpd_opp_svs: opp5 { 25811f61210SBjorn Andersson opp-level = <128>; 25911f61210SBjorn Andersson }; 26011f61210SBjorn Andersson 26111f61210SBjorn Andersson rpmpd_opp_svs_plus: opp6 { 26211f61210SBjorn Andersson opp-level = <192>; 26311f61210SBjorn Andersson }; 26411f61210SBjorn Andersson 26511f61210SBjorn Andersson rpmpd_opp_nom: opp7 { 26611f61210SBjorn Andersson opp-level = <256>; 26711f61210SBjorn Andersson }; 26811f61210SBjorn Andersson 26911f61210SBjorn Andersson rpmpd_opp_nom_plus: opp8 { 27011f61210SBjorn Andersson opp-level = <320>; 27111f61210SBjorn Andersson }; 27211f61210SBjorn Andersson 27311f61210SBjorn Andersson rpmpd_opp_turbo: opp9 { 27411f61210SBjorn Andersson opp-level = <384>; 27511f61210SBjorn Andersson }; 27611f61210SBjorn Andersson 27711f61210SBjorn Andersson rpmpd_opp_turbo_no_cpr: opp10 { 27811f61210SBjorn Andersson opp-level = <416>; 27911f61210SBjorn Andersson }; 28011f61210SBjorn Andersson 28111f61210SBjorn Andersson rpmpd_opp_turbo_plus: opp11 { 28211f61210SBjorn Andersson opp-level = <512>; 28311f61210SBjorn Andersson }; 28411f61210SBjorn Andersson }; 28511f61210SBjorn Andersson }; 2867fc7089dSBjorn Andersson }; 2877fc7089dSBjorn Andersson }; 2887fc7089dSBjorn Andersson 2897fc7089dSBjorn Andersson smem { 2907fc7089dSBjorn Andersson compatible = "qcom,smem"; 2917fc7089dSBjorn Andersson 2927fc7089dSBjorn Andersson memory-region = <&smem_region>; 2937fc7089dSBjorn Andersson qcom,rpm-msg-ram = <&rpm_msg_ram>; 2947fc7089dSBjorn Andersson 2957fc7089dSBjorn Andersson hwlocks = <&tcsr_mutex 3>; 2967fc7089dSBjorn Andersson }; 2977fc7089dSBjorn Andersson 2987fc7089dSBjorn Andersson tcsr_mutex: hwlock { 2997fc7089dSBjorn Andersson compatible = "qcom,tcsr-mutex"; 3007fc7089dSBjorn Andersson syscon = <&tcsr_mutex_regs 0 0x1000>; 3017fc7089dSBjorn Andersson #hwlock-cells = <1>; 3027fc7089dSBjorn Andersson }; 3037fc7089dSBjorn Andersson 304b4d82f4dSVinod Koul soc: soc@0 { 305b4d82f4dSVinod Koul #address-cells = <1>; 306b4d82f4dSVinod Koul #size-cells = <1>; 307b4d82f4dSVinod Koul ranges = <0 0 0 0xffffffff>; 308b4d82f4dSVinod Koul compatible = "simple-bus"; 309b4d82f4dSVinod Koul 3100b0c3390SBjorn Andersson turingcc: clock-controller@800000 { 3110b0c3390SBjorn Andersson compatible = "qcom,qcs404-turingcc"; 3120b0c3390SBjorn Andersson reg = <0x00800000 0x30000>; 3130b0c3390SBjorn Andersson clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 3140b0c3390SBjorn Andersson 3150b0c3390SBjorn Andersson #clock-cells = <1>; 3160b0c3390SBjorn Andersson #reset-cells = <1>; 3170b0c3390SBjorn Andersson 3180b0c3390SBjorn Andersson status = "disabled"; 3190b0c3390SBjorn Andersson }; 3200b0c3390SBjorn Andersson 3217fc7089dSBjorn Andersson rpm_msg_ram: memory@60000 { 3227fc7089dSBjorn Andersson compatible = "qcom,rpm-msg-ram"; 3237fc7089dSBjorn Andersson reg = <0x00060000 0x6000>; 3247fc7089dSBjorn Andersson }; 3257fc7089dSBjorn Andersson 32664cf50d0SAmit Kucheria qfprom: qfprom@a4000 { 32764cf50d0SAmit Kucheria compatible = "qcom,qfprom"; 32864cf50d0SAmit Kucheria reg = <0x000a4000 0x1000>; 32964cf50d0SAmit Kucheria #address-cells = <1>; 33064cf50d0SAmit Kucheria #size-cells = <1>; 33164cf50d0SAmit Kucheria tsens_caldata: caldata@d0 { 33264cf50d0SAmit Kucheria reg = <0x1f8 0x14>; 33364cf50d0SAmit Kucheria }; 33404aadcaaSNiklas Cassel cpr_efuse_speedbin: speedbin@13c { 33504aadcaaSNiklas Cassel reg = <0x13c 0x4>; 33604aadcaaSNiklas Cassel bits = <2 3>; 33704aadcaaSNiklas Cassel }; 33804aadcaaSNiklas Cassel cpr_efuse_quot_offset1: qoffset1@231 { 33904aadcaaSNiklas Cassel reg = <0x231 0x4>; 34004aadcaaSNiklas Cassel bits = <4 7>; 34104aadcaaSNiklas Cassel }; 34204aadcaaSNiklas Cassel cpr_efuse_quot_offset2: qoffset2@232 { 34304aadcaaSNiklas Cassel reg = <0x232 0x4>; 34404aadcaaSNiklas Cassel bits = <3 7>; 34504aadcaaSNiklas Cassel }; 34604aadcaaSNiklas Cassel cpr_efuse_quot_offset3: qoffset3@233 { 34704aadcaaSNiklas Cassel reg = <0x233 0x4>; 34804aadcaaSNiklas Cassel bits = <2 7>; 34904aadcaaSNiklas Cassel }; 35004aadcaaSNiklas Cassel cpr_efuse_init_voltage1: ivoltage1@229 { 35104aadcaaSNiklas Cassel reg = <0x229 0x4>; 35204aadcaaSNiklas Cassel bits = <4 6>; 35304aadcaaSNiklas Cassel }; 35404aadcaaSNiklas Cassel cpr_efuse_init_voltage2: ivoltage2@22a { 35504aadcaaSNiklas Cassel reg = <0x22a 0x4>; 35604aadcaaSNiklas Cassel bits = <2 6>; 35704aadcaaSNiklas Cassel }; 35804aadcaaSNiklas Cassel cpr_efuse_init_voltage3: ivoltage3@22b { 35904aadcaaSNiklas Cassel reg = <0x22b 0x4>; 36004aadcaaSNiklas Cassel bits = <0 6>; 36104aadcaaSNiklas Cassel }; 36204aadcaaSNiklas Cassel cpr_efuse_quot1: quot1@22b { 36304aadcaaSNiklas Cassel reg = <0x22b 0x4>; 36404aadcaaSNiklas Cassel bits = <6 12>; 36504aadcaaSNiklas Cassel }; 36604aadcaaSNiklas Cassel cpr_efuse_quot2: quot2@22d { 36704aadcaaSNiklas Cassel reg = <0x22d 0x4>; 36804aadcaaSNiklas Cassel bits = <2 12>; 36904aadcaaSNiklas Cassel }; 37004aadcaaSNiklas Cassel cpr_efuse_quot3: quot3@230 { 37104aadcaaSNiklas Cassel reg = <0x230 0x4>; 37204aadcaaSNiklas Cassel bits = <0 12>; 37304aadcaaSNiklas Cassel }; 37404aadcaaSNiklas Cassel cpr_efuse_ring1: ring1@228 { 37504aadcaaSNiklas Cassel reg = <0x228 0x4>; 37604aadcaaSNiklas Cassel bits = <0 3>; 37704aadcaaSNiklas Cassel }; 37804aadcaaSNiklas Cassel cpr_efuse_ring2: ring2@228 { 37904aadcaaSNiklas Cassel reg = <0x228 0x4>; 38004aadcaaSNiklas Cassel bits = <4 3>; 38104aadcaaSNiklas Cassel }; 38204aadcaaSNiklas Cassel cpr_efuse_ring3: ring3@229 { 38304aadcaaSNiklas Cassel reg = <0x229 0x4>; 38404aadcaaSNiklas Cassel bits = <0 3>; 38504aadcaaSNiklas Cassel }; 38604aadcaaSNiklas Cassel cpr_efuse_revision: revision@218 { 38704aadcaaSNiklas Cassel reg = <0x218 0x4>; 38804aadcaaSNiklas Cassel bits = <3 3>; 38904aadcaaSNiklas Cassel }; 39064cf50d0SAmit Kucheria }; 39164cf50d0SAmit Kucheria 392df96c65cSVinod Koul rng: rng@e3000 { 393df96c65cSVinod Koul compatible = "qcom,prng-ee"; 394df96c65cSVinod Koul reg = <0x000e3000 0x1000>; 395df96c65cSVinod Koul clocks = <&gcc GCC_PRNG_AHB_CLK>; 396df96c65cSVinod Koul clock-names = "core"; 397df96c65cSVinod Koul }; 398df96c65cSVinod Koul 399668c7603SGeorgi Djakov bimc: interconnect@400000 { 400668c7603SGeorgi Djakov reg = <0x00400000 0x80000>; 401668c7603SGeorgi Djakov compatible = "qcom,qcs404-bimc"; 402668c7603SGeorgi Djakov #interconnect-cells = <1>; 403668c7603SGeorgi Djakov clock-names = "bus", "bus_a"; 404668c7603SGeorgi Djakov clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 405668c7603SGeorgi Djakov <&rpmcc RPM_SMD_BIMC_A_CLK>; 406668c7603SGeorgi Djakov }; 407668c7603SGeorgi Djakov 40864cf50d0SAmit Kucheria tsens: thermal-sensor@4a9000 { 40964cf50d0SAmit Kucheria compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 41064cf50d0SAmit Kucheria reg = <0x004a9000 0x1000>, /* TM */ 41164cf50d0SAmit Kucheria <0x004a8000 0x1000>; /* SROT */ 41264cf50d0SAmit Kucheria nvmem-cells = <&tsens_caldata>; 41364cf50d0SAmit Kucheria nvmem-cell-names = "calib"; 41464cf50d0SAmit Kucheria #qcom,sensors = <10>; 415e51f7ff4SAmit Kucheria interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 416e51f7ff4SAmit Kucheria interrupt-names = "uplow"; 41764cf50d0SAmit Kucheria #thermal-sensor-cells = <1>; 41864cf50d0SAmit Kucheria }; 41964cf50d0SAmit Kucheria 420668c7603SGeorgi Djakov pcnoc: interconnect@500000 { 421668c7603SGeorgi Djakov reg = <0x00500000 0x15080>; 422668c7603SGeorgi Djakov compatible = "qcom,qcs404-pcnoc"; 423668c7603SGeorgi Djakov #interconnect-cells = <1>; 424668c7603SGeorgi Djakov clock-names = "bus", "bus_a"; 425668c7603SGeorgi Djakov clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 426668c7603SGeorgi Djakov <&rpmcc RPM_SMD_PNOC_A_CLK>; 427668c7603SGeorgi Djakov }; 428668c7603SGeorgi Djakov 429668c7603SGeorgi Djakov snoc: interconnect@580000 { 430668c7603SGeorgi Djakov reg = <0x00580000 0x23080>; 431668c7603SGeorgi Djakov compatible = "qcom,qcs404-snoc"; 432668c7603SGeorgi Djakov #interconnect-cells = <1>; 433668c7603SGeorgi Djakov clock-names = "bus", "bus_a"; 434668c7603SGeorgi Djakov clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 435668c7603SGeorgi Djakov <&rpmcc RPM_SMD_SNOC_A_CLK>; 436668c7603SGeorgi Djakov }; 437668c7603SGeorgi Djakov 438f4dd04a8SBjorn Andersson remoteproc_cdsp: remoteproc@b00000 { 439f4dd04a8SBjorn Andersson compatible = "qcom,qcs404-cdsp-pas"; 440f4dd04a8SBjorn Andersson reg = <0x00b00000 0x4040>; 441f4dd04a8SBjorn Andersson 442f4dd04a8SBjorn Andersson interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 443f4dd04a8SBjorn Andersson <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 444f4dd04a8SBjorn Andersson <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 445f4dd04a8SBjorn Andersson <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 446f4dd04a8SBjorn Andersson <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 447f4dd04a8SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 448f4dd04a8SBjorn Andersson "handover", "stop-ack"; 449f4dd04a8SBjorn Andersson 450f4dd04a8SBjorn Andersson clocks = <&xo_board>, 451f4dd04a8SBjorn Andersson <&gcc GCC_CDSP_CFG_AHB_CLK>, 452f4dd04a8SBjorn Andersson <&gcc GCC_CDSP_TBU_CLK>, 453f4dd04a8SBjorn Andersson <&gcc GCC_BIMC_CDSP_CLK>, 454f4dd04a8SBjorn Andersson <&turingcc TURING_WRAPPER_AON_CLK>, 455f4dd04a8SBjorn Andersson <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 456f4dd04a8SBjorn Andersson <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 457f4dd04a8SBjorn Andersson <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 458f4dd04a8SBjorn Andersson clock-names = "xo", 459f4dd04a8SBjorn Andersson "sway", 460f4dd04a8SBjorn Andersson "tbu", 461f4dd04a8SBjorn Andersson "bimc", 462f4dd04a8SBjorn Andersson "ahb_aon", 463f4dd04a8SBjorn Andersson "q6ss_slave", 464f4dd04a8SBjorn Andersson "q6ss_master", 465f4dd04a8SBjorn Andersson "q6_axim"; 466f4dd04a8SBjorn Andersson 467f4dd04a8SBjorn Andersson resets = <&gcc GCC_CDSP_RESTART>; 468f4dd04a8SBjorn Andersson reset-names = "restart"; 469f4dd04a8SBjorn Andersson 470f4dd04a8SBjorn Andersson qcom,halt-regs = <&tcsr 0x19004>; 471f4dd04a8SBjorn Andersson 472f4dd04a8SBjorn Andersson memory-region = <&cdsp_fw_mem>; 473f4dd04a8SBjorn Andersson 474f4dd04a8SBjorn Andersson qcom,smem-states = <&cdsp_smp2p_out 0>; 475f4dd04a8SBjorn Andersson qcom,smem-state-names = "stop"; 476f4dd04a8SBjorn Andersson 477f4dd04a8SBjorn Andersson status = "disabled"; 478f4dd04a8SBjorn Andersson 479f4dd04a8SBjorn Andersson glink-edge { 480f4dd04a8SBjorn Andersson interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 481f4dd04a8SBjorn Andersson 482f4dd04a8SBjorn Andersson qcom,remote-pid = <5>; 483f4dd04a8SBjorn Andersson mboxes = <&apcs_glb 12>; 484f4dd04a8SBjorn Andersson 485f4dd04a8SBjorn Andersson label = "cdsp"; 486f4dd04a8SBjorn Andersson }; 487f4dd04a8SBjorn Andersson }; 488f4dd04a8SBjorn Andersson 48975f6e6d9SBjorn Andersson tlmm: pinctrl@1000000 { 49075f6e6d9SBjorn Andersson compatible = "qcom,qcs404-pinctrl"; 49175f6e6d9SBjorn Andersson reg = <0x01000000 0x200000>, 49275f6e6d9SBjorn Andersson <0x01300000 0x200000>, 49375f6e6d9SBjorn Andersson <0x07b00000 0x200000>; 49475f6e6d9SBjorn Andersson reg-names = "south", "north", "east"; 49575f6e6d9SBjorn Andersson interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 49675f6e6d9SBjorn Andersson gpio-ranges = <&tlmm 0 0 120>; 49775f6e6d9SBjorn Andersson gpio-controller; 49875f6e6d9SBjorn Andersson #gpio-cells = <2>; 49975f6e6d9SBjorn Andersson interrupt-controller; 50075f6e6d9SBjorn Andersson #interrupt-cells = <2>; 5015bb9ab94SBjorn Andersson 502734e6d02SBjorn Andersson blsp1_i2c0_default: blsp1-i2c0-default { 503734e6d02SBjorn Andersson pins = "gpio32", "gpio33"; 504734e6d02SBjorn Andersson function = "blsp_i2c0"; 505734e6d02SBjorn Andersson }; 506734e6d02SBjorn Andersson 507734e6d02SBjorn Andersson blsp1_i2c1_default: blsp1-i2c1-default { 508734e6d02SBjorn Andersson pins = "gpio24", "gpio25"; 509734e6d02SBjorn Andersson function = "blsp_i2c1"; 510734e6d02SBjorn Andersson }; 511734e6d02SBjorn Andersson 512734e6d02SBjorn Andersson blsp1_i2c2_default: blsp1-i2c2-default { 513734e6d02SBjorn Andersson sda { 514734e6d02SBjorn Andersson pins = "gpio19"; 515734e6d02SBjorn Andersson function = "blsp_i2c_sda_a2"; 516734e6d02SBjorn Andersson }; 517734e6d02SBjorn Andersson 518734e6d02SBjorn Andersson scl { 519734e6d02SBjorn Andersson pins = "gpio20"; 520734e6d02SBjorn Andersson function = "blsp_i2c_scl_a2"; 521734e6d02SBjorn Andersson }; 522734e6d02SBjorn Andersson }; 523734e6d02SBjorn Andersson 524734e6d02SBjorn Andersson blsp1_i2c3_default: blsp1-i2c3-default { 525734e6d02SBjorn Andersson pins = "gpio84", "gpio85"; 526734e6d02SBjorn Andersson function = "blsp_i2c3"; 527734e6d02SBjorn Andersson }; 528734e6d02SBjorn Andersson 529734e6d02SBjorn Andersson blsp1_i2c4_default: blsp1-i2c4-default { 530734e6d02SBjorn Andersson pins = "gpio117", "gpio118"; 531734e6d02SBjorn Andersson function = "blsp_i2c4"; 532734e6d02SBjorn Andersson }; 533734e6d02SBjorn Andersson 534bf9aa8a4SBjorn Andersson blsp1_uart0_default: blsp1-uart0-default { 535bf9aa8a4SBjorn Andersson pins = "gpio30", "gpio31", "gpio32", "gpio33"; 536bf9aa8a4SBjorn Andersson function = "blsp_uart0"; 537bf9aa8a4SBjorn Andersson }; 538bf9aa8a4SBjorn Andersson 539bf9aa8a4SBjorn Andersson blsp1_uart1_default: blsp1-uart1-default { 540bf9aa8a4SBjorn Andersson pins = "gpio22", "gpio23"; 541bf9aa8a4SBjorn Andersson function = "blsp_uart1"; 542bf9aa8a4SBjorn Andersson }; 543bf9aa8a4SBjorn Andersson 5445bb9ab94SBjorn Andersson blsp1_uart2_default: blsp1-uart2-default { 5455bb9ab94SBjorn Andersson rx { 5465bb9ab94SBjorn Andersson pins = "gpio18"; 5475bb9ab94SBjorn Andersson function = "blsp_uart_rx_a2"; 5485bb9ab94SBjorn Andersson }; 5495bb9ab94SBjorn Andersson 5505bb9ab94SBjorn Andersson tx { 5515bb9ab94SBjorn Andersson pins = "gpio17"; 5525bb9ab94SBjorn Andersson function = "blsp_uart_tx_a2"; 5535bb9ab94SBjorn Andersson }; 5545bb9ab94SBjorn Andersson }; 555bf9aa8a4SBjorn Andersson 556bf9aa8a4SBjorn Andersson blsp1_uart3_default: blsp1-uart3-default { 557bf9aa8a4SBjorn Andersson pins = "gpio82", "gpio83", "gpio84", "gpio85"; 558bf9aa8a4SBjorn Andersson function = "blsp_uart3"; 559bf9aa8a4SBjorn Andersson }; 560bf9aa8a4SBjorn Andersson 561734e6d02SBjorn Andersson blsp2_i2c0_default: blsp2-i2c0-default { 562734e6d02SBjorn Andersson pins = "gpio28", "gpio29"; 563734e6d02SBjorn Andersson function = "blsp_i2c5"; 564734e6d02SBjorn Andersson }; 565734e6d02SBjorn Andersson 566734e6d02SBjorn Andersson blsp1_spi0_default: blsp1-spi0-default { 567734e6d02SBjorn Andersson pins = "gpio30", "gpio31", "gpio32", "gpio33"; 568734e6d02SBjorn Andersson function = "blsp_spi0"; 569734e6d02SBjorn Andersson }; 570734e6d02SBjorn Andersson 571734e6d02SBjorn Andersson blsp1_spi1_default: blsp1-spi1-default { 572734e6d02SBjorn Andersson pins = "gpio22", "gpio23", "gpio24", "gpio25"; 573734e6d02SBjorn Andersson function = "blsp_spi1"; 574734e6d02SBjorn Andersson }; 575734e6d02SBjorn Andersson 576734e6d02SBjorn Andersson blsp1_spi2_default: blsp1-spi2-default { 577734e6d02SBjorn Andersson pins = "gpio17", "gpio18", "gpio19", "gpio20"; 578734e6d02SBjorn Andersson function = "blsp_spi2"; 579734e6d02SBjorn Andersson }; 580734e6d02SBjorn Andersson 581734e6d02SBjorn Andersson blsp1_spi3_default: blsp1-spi3-default { 582734e6d02SBjorn Andersson pins = "gpio82", "gpio83", "gpio84", "gpio85"; 583734e6d02SBjorn Andersson function = "blsp_spi3"; 584734e6d02SBjorn Andersson }; 585734e6d02SBjorn Andersson 586734e6d02SBjorn Andersson blsp1_spi4_default: blsp1-spi4-default { 587734e6d02SBjorn Andersson pins = "gpio37", "gpio38", "gpio117", "gpio118"; 588734e6d02SBjorn Andersson function = "blsp_spi4"; 589734e6d02SBjorn Andersson }; 590734e6d02SBjorn Andersson 591734e6d02SBjorn Andersson blsp2_spi0_default: blsp2-spi0-default { 592734e6d02SBjorn Andersson pins = "gpio26", "gpio27", "gpio28", "gpio29"; 593734e6d02SBjorn Andersson function = "blsp_spi5"; 594734e6d02SBjorn Andersson }; 595734e6d02SBjorn Andersson 596bf9aa8a4SBjorn Andersson blsp2_uart0_default: blsp2-uart0-default { 597bf9aa8a4SBjorn Andersson pins = "gpio26", "gpio27", "gpio28", "gpio29"; 598bf9aa8a4SBjorn Andersson function = "blsp_uart5"; 599bf9aa8a4SBjorn Andersson }; 60075f6e6d9SBjorn Andersson }; 60175f6e6d9SBjorn Andersson 602b4d82f4dSVinod Koul gcc: clock-controller@1800000 { 603b4d82f4dSVinod Koul compatible = "qcom,gcc-qcs404"; 604b4d82f4dSVinod Koul reg = <0x01800000 0x80000>; 605b4d82f4dSVinod Koul #clock-cells = <1>; 6064b2c7ea8SAndy Gross #reset-cells = <1>; 607b4d82f4dSVinod Koul 608b4d82f4dSVinod Koul assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 609b4d82f4dSVinod Koul assigned-clock-rates = <19200000>; 610b4d82f4dSVinod Koul }; 611b4d82f4dSVinod Koul 6127fc7089dSBjorn Andersson tcsr_mutex_regs: syscon@1905000 { 6137fc7089dSBjorn Andersson compatible = "syscon"; 6147fc7089dSBjorn Andersson reg = <0x01905000 0x20000>; 6157fc7089dSBjorn Andersson }; 6167fc7089dSBjorn Andersson 617560ad5e7SBjorn Andersson tcsr: syscon@1937000 { 618560ad5e7SBjorn Andersson compatible = "syscon"; 619560ad5e7SBjorn Andersson reg = <0x01937000 0x25000>; 620560ad5e7SBjorn Andersson }; 621560ad5e7SBjorn Andersson 6221a94b65bSVinod Koul spmi_bus: spmi@200f000 { 6231a94b65bSVinod Koul compatible = "qcom,spmi-pmic-arb"; 6241a94b65bSVinod Koul reg = <0x0200f000 0x001000>, 6251a94b65bSVinod Koul <0x02400000 0x800000>, 6261a94b65bSVinod Koul <0x02c00000 0x800000>, 6271a94b65bSVinod Koul <0x03800000 0x200000>, 6281a94b65bSVinod Koul <0x0200a000 0x002100>; 6291a94b65bSVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 6301a94b65bSVinod Koul interrupt-names = "periph_irq"; 6311a94b65bSVinod Koul interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 6321a94b65bSVinod Koul qcom,ee = <0>; 6331a94b65bSVinod Koul qcom,channel = <0>; 6341a94b65bSVinod Koul #address-cells = <2>; 6351a94b65bSVinod Koul #size-cells = <0>; 6361a94b65bSVinod Koul interrupt-controller; 6371a94b65bSVinod Koul #interrupt-cells = <4>; 6381a94b65bSVinod Koul }; 6391a94b65bSVinod Koul 64067779ca2SBjorn Andersson remoteproc_wcss: remoteproc@7400000 { 64167779ca2SBjorn Andersson compatible = "qcom,qcs404-wcss-pas"; 64267779ca2SBjorn Andersson reg = <0x07400000 0x4040>; 64367779ca2SBjorn Andersson 64467779ca2SBjorn Andersson interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 64567779ca2SBjorn Andersson <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 64667779ca2SBjorn Andersson <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 64767779ca2SBjorn Andersson <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 64867779ca2SBjorn Andersson <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 64967779ca2SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 65067779ca2SBjorn Andersson "handover", "stop-ack"; 65167779ca2SBjorn Andersson 65267779ca2SBjorn Andersson clocks = <&xo_board>; 65367779ca2SBjorn Andersson clock-names = "xo"; 65467779ca2SBjorn Andersson 65567779ca2SBjorn Andersson memory-region = <&wlan_fw_mem>; 65667779ca2SBjorn Andersson 65767779ca2SBjorn Andersson qcom,smem-states = <&wcss_smp2p_out 0>; 65867779ca2SBjorn Andersson qcom,smem-state-names = "stop"; 65967779ca2SBjorn Andersson 66067779ca2SBjorn Andersson status = "disabled"; 66167779ca2SBjorn Andersson 66267779ca2SBjorn Andersson glink-edge { 66367779ca2SBjorn Andersson interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 66467779ca2SBjorn Andersson 66567779ca2SBjorn Andersson qcom,remote-pid = <1>; 66667779ca2SBjorn Andersson mboxes = <&apcs_glb 16>; 66767779ca2SBjorn Andersson 66867779ca2SBjorn Andersson label = "wcss"; 66967779ca2SBjorn Andersson }; 67067779ca2SBjorn Andersson }; 67167779ca2SBjorn Andersson 672431f6464SBjorn Andersson pcie_phy: phy@7786000 { 673431f6464SBjorn Andersson compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 674431f6464SBjorn Andersson reg = <0x07786000 0xb8>; 675431f6464SBjorn Andersson 676431f6464SBjorn Andersson clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 677431f6464SBjorn Andersson resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 678431f6464SBjorn Andersson <&gcc 21>; 679431f6464SBjorn Andersson reset-names = "phy", "pipe"; 680431f6464SBjorn Andersson 681431f6464SBjorn Andersson clock-output-names = "pcie_0_pipe_clk"; 682431f6464SBjorn Andersson #phy-cells = <0>; 683431f6464SBjorn Andersson 684431f6464SBjorn Andersson status = "disabled"; 685431f6464SBjorn Andersson }; 686431f6464SBjorn Andersson 6877241ab94SBjorn Andersson sdcc1: sdcc@7804000 { 688f8c84813SDouglas Anderson compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 6897241ab94SBjorn Andersson reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 690557a2abaSVeerabhadrarao Badiganti reg-names = "hc", "cqhci"; 6917241ab94SBjorn Andersson 6927241ab94SBjorn Andersson interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 6937241ab94SBjorn Andersson <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 6947241ab94SBjorn Andersson interrupt-names = "hc_irq", "pwr_irq"; 6957241ab94SBjorn Andersson 6967241ab94SBjorn Andersson clocks = <&gcc GCC_SDCC1_APPS_CLK>, 6977241ab94SBjorn Andersson <&gcc GCC_SDCC1_AHB_CLK>, 6987241ab94SBjorn Andersson <&xo_board>; 6997241ab94SBjorn Andersson clock-names = "core", "iface", "xo"; 7007241ab94SBjorn Andersson 7017241ab94SBjorn Andersson status = "disabled"; 7027241ab94SBjorn Andersson }; 7037241ab94SBjorn Andersson 704e77c5206SVinod Koul blsp1_dma: dma@7884000 { 705e77c5206SVinod Koul compatible = "qcom,bam-v1.7.0"; 706e77c5206SVinod Koul reg = <0x07884000 0x25000>; 707e77c5206SVinod Koul interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 708e77c5206SVinod Koul clocks = <&gcc GCC_BLSP1_AHB_CLK>; 709e77c5206SVinod Koul clock-names = "bam_clk"; 710e77c5206SVinod Koul #dma-cells = <1>; 711e77c5206SVinod Koul qcom,ee = <0>; 712e77c5206SVinod Koul status = "okay"; 713e77c5206SVinod Koul }; 714e77c5206SVinod Koul 715bf9aa8a4SBjorn Andersson blsp1_uart0: serial@78af000 { 716bf9aa8a4SBjorn Andersson compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 717bf9aa8a4SBjorn Andersson reg = <0x078af000 0x200>; 718bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 719bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 720bf9aa8a4SBjorn Andersson clock-names = "core", "iface"; 721bf9aa8a4SBjorn Andersson dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; 722bf9aa8a4SBjorn Andersson dma-names = "rx", "tx"; 723bf9aa8a4SBjorn Andersson pinctrl-names = "default"; 724bf9aa8a4SBjorn Andersson pinctrl-0 = <&blsp1_uart0_default>; 725bf9aa8a4SBjorn Andersson status = "disabled"; 726bf9aa8a4SBjorn Andersson }; 727bf9aa8a4SBjorn Andersson 728bf9aa8a4SBjorn Andersson blsp1_uart1: serial@78b0000 { 729bf9aa8a4SBjorn Andersson compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 730bf9aa8a4SBjorn Andersson reg = <0x078b0000 0x200>; 731bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 732bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 733bf9aa8a4SBjorn Andersson clock-names = "core", "iface"; 734bf9aa8a4SBjorn Andersson dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; 735bf9aa8a4SBjorn Andersson dma-names = "rx", "tx"; 736bf9aa8a4SBjorn Andersson pinctrl-names = "default"; 737bf9aa8a4SBjorn Andersson pinctrl-0 = <&blsp1_uart1_default>; 738bf9aa8a4SBjorn Andersson status = "disabled"; 739bf9aa8a4SBjorn Andersson }; 740bf9aa8a4SBjorn Andersson 741b4d82f4dSVinod Koul blsp1_uart2: serial@78b1000 { 742b4d82f4dSVinod Koul compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 743b4d82f4dSVinod Koul reg = <0x078b1000 0x200>; 744b4d82f4dSVinod Koul interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 745b4d82f4dSVinod Koul clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 746b4d82f4dSVinod Koul clock-names = "core", "iface"; 747aec2a765SVinod Koul dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; 748aec2a765SVinod Koul dma-names = "rx", "tx"; 7495bb9ab94SBjorn Andersson pinctrl-names = "default"; 7505bb9ab94SBjorn Andersson pinctrl-0 = <&blsp1_uart2_default>; 751b4d82f4dSVinod Koul status = "okay"; 752b4d82f4dSVinod Koul }; 753b4d82f4dSVinod Koul 7544dfa70eaSVinod Koul ethernet: ethernet@7a80000 { 7554dfa70eaSVinod Koul compatible = "qcom,qcs404-ethqos"; 7564dfa70eaSVinod Koul reg = <0x07a80000 0x10000>, 7574dfa70eaSVinod Koul <0x07a96000 0x100>; 7584dfa70eaSVinod Koul reg-names = "stmmaceth", "rgmii"; 7594dfa70eaSVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 7604dfa70eaSVinod Koul clocks = <&gcc GCC_ETH_AXI_CLK>, 7614dfa70eaSVinod Koul <&gcc GCC_ETH_SLAVE_AHB_CLK>, 7624dfa70eaSVinod Koul <&gcc GCC_ETH_PTP_CLK>, 7634dfa70eaSVinod Koul <&gcc GCC_ETH_RGMII_CLK>; 7644dfa70eaSVinod Koul interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 7654dfa70eaSVinod Koul <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 7664dfa70eaSVinod Koul interrupt-names = "macirq", "eth_lpi"; 7674dfa70eaSVinod Koul 7684dfa70eaSVinod Koul snps,tso; 7694dfa70eaSVinod Koul rx-fifo-depth = <4096>; 7704dfa70eaSVinod Koul tx-fifo-depth = <4096>; 7714dfa70eaSVinod Koul 7724dfa70eaSVinod Koul status = "disabled"; 7734dfa70eaSVinod Koul }; 7744dfa70eaSVinod Koul 7754bbbca1eSGovind Singh wifi: wifi@a000000 { 7764bbbca1eSGovind Singh compatible = "qcom,wcn3990-wifi"; 7774bbbca1eSGovind Singh reg = <0xa000000 0x800000>; 7784bbbca1eSGovind Singh reg-names = "membase"; 7794bbbca1eSGovind Singh memory-region = <&wlan_msa_mem>; 7804bbbca1eSGovind Singh interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 7814bbbca1eSGovind Singh <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 7824bbbca1eSGovind Singh <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 7834bbbca1eSGovind Singh <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 7844bbbca1eSGovind Singh <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 7854bbbca1eSGovind Singh <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 7864bbbca1eSGovind Singh <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 7874bbbca1eSGovind Singh <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 7884bbbca1eSGovind Singh <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 7894bbbca1eSGovind Singh <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 7904bbbca1eSGovind Singh <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 7914bbbca1eSGovind Singh <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 7924bbbca1eSGovind Singh status = "disabled"; 7934bbbca1eSGovind Singh }; 7944bbbca1eSGovind Singh 795bf9aa8a4SBjorn Andersson blsp1_uart3: serial@78b2000 { 796bf9aa8a4SBjorn Andersson compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 797bf9aa8a4SBjorn Andersson reg = <0x078b2000 0x200>; 798bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 799bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 800bf9aa8a4SBjorn Andersson clock-names = "core", "iface"; 801bf9aa8a4SBjorn Andersson dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; 802bf9aa8a4SBjorn Andersson dma-names = "rx", "tx"; 803bf9aa8a4SBjorn Andersson pinctrl-names = "default"; 804bf9aa8a4SBjorn Andersson pinctrl-0 = <&blsp1_uart3_default>; 805bf9aa8a4SBjorn Andersson status = "disabled"; 806bf9aa8a4SBjorn Andersson }; 807bf9aa8a4SBjorn Andersson 808734e6d02SBjorn Andersson blsp1_i2c0: i2c@78b5000 { 809734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 810734e6d02SBjorn Andersson reg = <0x078b5000 0x600>; 811734e6d02SBjorn Andersson interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 812734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 813734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; 814734e6d02SBjorn Andersson clock-names = "iface", "core"; 815734e6d02SBjorn Andersson pinctrl-names = "default"; 816734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c0_default>; 817734e6d02SBjorn Andersson #address-cells = <1>; 818734e6d02SBjorn Andersson #size-cells = <0>; 819734e6d02SBjorn Andersson status = "disabled"; 820734e6d02SBjorn Andersson }; 821734e6d02SBjorn Andersson 822734e6d02SBjorn Andersson blsp1_spi0: spi@78b5000 { 823734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 824734e6d02SBjorn Andersson reg = <0x078b5000 0x600>; 825734e6d02SBjorn Andersson interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 826734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 827734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; 828734e6d02SBjorn Andersson clock-names = "iface", "core"; 829734e6d02SBjorn Andersson pinctrl-names = "default"; 830734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi0_default>; 831734e6d02SBjorn Andersson #address-cells = <1>; 832734e6d02SBjorn Andersson #size-cells = <0>; 833734e6d02SBjorn Andersson status = "disabled"; 834734e6d02SBjorn Andersson }; 835734e6d02SBjorn Andersson 836734e6d02SBjorn Andersson blsp1_i2c1: i2c@78b6000 { 837734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 838734e6d02SBjorn Andersson reg = <0x078b6000 0x600>; 839734e6d02SBjorn Andersson interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 840734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 841734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 842734e6d02SBjorn Andersson clock-names = "iface", "core"; 843734e6d02SBjorn Andersson pinctrl-names = "default"; 844734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c1_default>; 845734e6d02SBjorn Andersson #address-cells = <1>; 846734e6d02SBjorn Andersson #size-cells = <0>; 847734e6d02SBjorn Andersson status = "disabled"; 848734e6d02SBjorn Andersson }; 849734e6d02SBjorn Andersson 850734e6d02SBjorn Andersson blsp1_spi1: spi@78b6000 { 851734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 852734e6d02SBjorn Andersson reg = <0x078b6000 0x600>; 853734e6d02SBjorn Andersson interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 854734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 855734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; 856734e6d02SBjorn Andersson clock-names = "iface", "core"; 857734e6d02SBjorn Andersson pinctrl-names = "default"; 858734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi1_default>; 859734e6d02SBjorn Andersson #address-cells = <1>; 860734e6d02SBjorn Andersson #size-cells = <0>; 861734e6d02SBjorn Andersson status = "disabled"; 862734e6d02SBjorn Andersson }; 863734e6d02SBjorn Andersson 864734e6d02SBjorn Andersson blsp1_i2c2: i2c@78b7000 { 865734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 866734e6d02SBjorn Andersson reg = <0x078b7000 0x600>; 867734e6d02SBjorn Andersson interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 868734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 869734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 870734e6d02SBjorn Andersson clock-names = "iface", "core"; 871734e6d02SBjorn Andersson pinctrl-names = "default"; 872734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c2_default>; 873734e6d02SBjorn Andersson #address-cells = <1>; 874734e6d02SBjorn Andersson #size-cells = <0>; 875734e6d02SBjorn Andersson status = "disabled"; 876734e6d02SBjorn Andersson }; 877734e6d02SBjorn Andersson 878734e6d02SBjorn Andersson blsp1_spi2: spi@78b7000 { 879734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 880734e6d02SBjorn Andersson reg = <0x078b7000 0x600>; 881734e6d02SBjorn Andersson interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 882734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 883734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; 884734e6d02SBjorn Andersson clock-names = "iface", "core"; 885734e6d02SBjorn Andersson pinctrl-names = "default"; 886734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi2_default>; 887734e6d02SBjorn Andersson #address-cells = <1>; 888734e6d02SBjorn Andersson #size-cells = <0>; 889734e6d02SBjorn Andersson status = "disabled"; 890734e6d02SBjorn Andersson }; 891734e6d02SBjorn Andersson 892734e6d02SBjorn Andersson blsp1_i2c3: i2c@78b8000 { 893734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 894734e6d02SBjorn Andersson reg = <0x078b8000 0x600>; 895734e6d02SBjorn Andersson interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 896734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 897734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 898734e6d02SBjorn Andersson clock-names = "iface", "core"; 899734e6d02SBjorn Andersson pinctrl-names = "default"; 900734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c3_default>; 901734e6d02SBjorn Andersson #address-cells = <1>; 902734e6d02SBjorn Andersson #size-cells = <0>; 903734e6d02SBjorn Andersson status = "disabled"; 904734e6d02SBjorn Andersson }; 905734e6d02SBjorn Andersson 906734e6d02SBjorn Andersson blsp1_spi3: spi@78b8000 { 907734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 908734e6d02SBjorn Andersson reg = <0x078b8000 0x600>; 909734e6d02SBjorn Andersson interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 910734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 911734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; 912734e6d02SBjorn Andersson clock-names = "iface", "core"; 913734e6d02SBjorn Andersson pinctrl-names = "default"; 914734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi3_default>; 915734e6d02SBjorn Andersson #address-cells = <1>; 916734e6d02SBjorn Andersson #size-cells = <0>; 917734e6d02SBjorn Andersson status = "disabled"; 918734e6d02SBjorn Andersson }; 919734e6d02SBjorn Andersson 920734e6d02SBjorn Andersson blsp1_i2c4: i2c@78b9000 { 921734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 922734e6d02SBjorn Andersson reg = <0x078b9000 0x600>; 923734e6d02SBjorn Andersson interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 924734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 925734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 926734e6d02SBjorn Andersson clock-names = "iface", "core"; 927734e6d02SBjorn Andersson pinctrl-names = "default"; 928734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c4_default>; 929734e6d02SBjorn Andersson #address-cells = <1>; 930734e6d02SBjorn Andersson #size-cells = <0>; 931734e6d02SBjorn Andersson status = "disabled"; 932734e6d02SBjorn Andersson }; 933734e6d02SBjorn Andersson 934734e6d02SBjorn Andersson blsp1_spi4: spi@78b9000 { 935734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 936734e6d02SBjorn Andersson reg = <0x078b9000 0x600>; 937734e6d02SBjorn Andersson interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 938734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 939734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; 940734e6d02SBjorn Andersson clock-names = "iface", "core"; 941734e6d02SBjorn Andersson pinctrl-names = "default"; 942734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi4_default>; 943734e6d02SBjorn Andersson #address-cells = <1>; 944734e6d02SBjorn Andersson #size-cells = <0>; 945734e6d02SBjorn Andersson status = "disabled"; 946734e6d02SBjorn Andersson }; 947734e6d02SBjorn Andersson 948bf9aa8a4SBjorn Andersson blsp2_dma: dma@7ac4000 { 949bf9aa8a4SBjorn Andersson compatible = "qcom,bam-v1.7.0"; 950bf9aa8a4SBjorn Andersson reg = <0x07ac4000 0x17000>; 951bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 952bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP2_AHB_CLK>; 953bf9aa8a4SBjorn Andersson clock-names = "bam_clk"; 954bf9aa8a4SBjorn Andersson #dma-cells = <1>; 955bf9aa8a4SBjorn Andersson qcom,ee = <0>; 956bf9aa8a4SBjorn Andersson status = "disabled"; 957bf9aa8a4SBjorn Andersson }; 958bf9aa8a4SBjorn Andersson 959bf9aa8a4SBjorn Andersson blsp2_uart0: serial@7aef000 { 960bf9aa8a4SBjorn Andersson compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 961bf9aa8a4SBjorn Andersson reg = <0x07aef000 0x200>; 962bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 963bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 964bf9aa8a4SBjorn Andersson clock-names = "core", "iface"; 965bf9aa8a4SBjorn Andersson dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; 966bf9aa8a4SBjorn Andersson dma-names = "rx", "tx"; 967bf9aa8a4SBjorn Andersson pinctrl-names = "default"; 968bf9aa8a4SBjorn Andersson pinctrl-0 = <&blsp2_uart0_default>; 969bf9aa8a4SBjorn Andersson status = "disabled"; 970bf9aa8a4SBjorn Andersson }; 971bf9aa8a4SBjorn Andersson 972734e6d02SBjorn Andersson blsp2_i2c0: i2c@7af5000 { 973734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 974734e6d02SBjorn Andersson reg = <0x07af5000 0x600>; 975734e6d02SBjorn Andersson interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 976734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP2_AHB_CLK>, 977734e6d02SBjorn Andersson <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; 978734e6d02SBjorn Andersson clock-names = "iface", "core"; 979734e6d02SBjorn Andersson pinctrl-names = "default"; 980734e6d02SBjorn Andersson pinctrl-0 = <&blsp2_i2c0_default>; 981734e6d02SBjorn Andersson #address-cells = <1>; 982734e6d02SBjorn Andersson #size-cells = <0>; 983734e6d02SBjorn Andersson status = "disabled"; 984734e6d02SBjorn Andersson }; 985734e6d02SBjorn Andersson 986734e6d02SBjorn Andersson blsp2_spi0: spi@7af5000 { 987734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 988734e6d02SBjorn Andersson reg = <0x07af5000 0x600>; 989734e6d02SBjorn Andersson interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 990734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP2_AHB_CLK>, 991734e6d02SBjorn Andersson <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; 992734e6d02SBjorn Andersson clock-names = "iface", "core"; 993734e6d02SBjorn Andersson pinctrl-names = "default"; 994734e6d02SBjorn Andersson pinctrl-0 = <&blsp2_spi0_default>; 995734e6d02SBjorn Andersson #address-cells = <1>; 996734e6d02SBjorn Andersson #size-cells = <0>; 997734e6d02SBjorn Andersson status = "disabled"; 998734e6d02SBjorn Andersson }; 999734e6d02SBjorn Andersson 1000b4d82f4dSVinod Koul intc: interrupt-controller@b000000 { 1001b4d82f4dSVinod Koul compatible = "qcom,msm-qgic2"; 1002b4d82f4dSVinod Koul interrupt-controller; 1003b4d82f4dSVinod Koul #interrupt-cells = <3>; 1004b4d82f4dSVinod Koul reg = <0x0b000000 0x1000>, 1005b4d82f4dSVinod Koul <0x0b002000 0x1000>; 1006b4d82f4dSVinod Koul }; 1007b4d82f4dSVinod Koul 10087fc7089dSBjorn Andersson apcs_glb: mailbox@b011000 { 10097fc7089dSBjorn Andersson compatible = "qcom,qcs404-apcs-apps-global", "syscon"; 10107fc7089dSBjorn Andersson reg = <0x0b011000 0x1000>; 10117fc7089dSBjorn Andersson #mbox-cells = <1>; 101201163a20SJorge Ramirez-Ortiz clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 101301163a20SJorge Ramirez-Ortiz clock-names = "pll", "aux"; 101401163a20SJorge Ramirez-Ortiz #clock-cells = <0>; 10157fc7089dSBjorn Andersson }; 10167fc7089dSBjorn Andersson 101740b3d940SJorge Ramirez-Ortiz apcs_hfpll: clock-controller@b016000 { 101840b3d940SJorge Ramirez-Ortiz compatible = "qcom,hfpll"; 101940b3d940SJorge Ramirez-Ortiz reg = <0x0b016000 0x30>; 102040b3d940SJorge Ramirez-Ortiz #clock-cells = <0>; 102140b3d940SJorge Ramirez-Ortiz clock-output-names = "apcs_hfpll"; 102240b3d940SJorge Ramirez-Ortiz clocks = <&xo_board>; 102340b3d940SJorge Ramirez-Ortiz clock-names = "xo"; 102440b3d940SJorge Ramirez-Ortiz }; 102540b3d940SJorge Ramirez-Ortiz 10268a250aa6SJorge Ramirez-Ortiz watchdog@b017000 { 10279692d9ffSSai Prakash Ranjan compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 10288a250aa6SJorge Ramirez-Ortiz reg = <0x0b017000 0x1000>; 10298a250aa6SJorge Ramirez-Ortiz clocks = <&sleep_clk>; 10308a250aa6SJorge Ramirez-Ortiz }; 10318a250aa6SJorge Ramirez-Ortiz 103204aadcaaSNiklas Cassel cpr: power-controller@b018000 { 103304aadcaaSNiklas Cassel compatible = "qcom,qcs404-cpr", "qcom,cpr"; 103404aadcaaSNiklas Cassel reg = <0x0b018000 0x1000>; 103504aadcaaSNiklas Cassel interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 103604aadcaaSNiklas Cassel clocks = <&xo_board>; 103704aadcaaSNiklas Cassel clock-names = "ref"; 103804aadcaaSNiklas Cassel vdd-apc-supply = <&pms405_s3>; 103904aadcaaSNiklas Cassel #power-domain-cells = <0>; 104004aadcaaSNiklas Cassel operating-points-v2 = <&cpr_opp_table>; 104104aadcaaSNiklas Cassel acc-syscon = <&tcsr>; 104204aadcaaSNiklas Cassel 104304aadcaaSNiklas Cassel nvmem-cells = <&cpr_efuse_quot_offset1>, 104404aadcaaSNiklas Cassel <&cpr_efuse_quot_offset2>, 104504aadcaaSNiklas Cassel <&cpr_efuse_quot_offset3>, 104604aadcaaSNiklas Cassel <&cpr_efuse_init_voltage1>, 104704aadcaaSNiklas Cassel <&cpr_efuse_init_voltage2>, 104804aadcaaSNiklas Cassel <&cpr_efuse_init_voltage3>, 104904aadcaaSNiklas Cassel <&cpr_efuse_quot1>, 105004aadcaaSNiklas Cassel <&cpr_efuse_quot2>, 105104aadcaaSNiklas Cassel <&cpr_efuse_quot3>, 105204aadcaaSNiklas Cassel <&cpr_efuse_ring1>, 105304aadcaaSNiklas Cassel <&cpr_efuse_ring2>, 105404aadcaaSNiklas Cassel <&cpr_efuse_ring3>, 105504aadcaaSNiklas Cassel <&cpr_efuse_revision>; 105604aadcaaSNiklas Cassel nvmem-cell-names = "cpr_quotient_offset1", 105704aadcaaSNiklas Cassel "cpr_quotient_offset2", 105804aadcaaSNiklas Cassel "cpr_quotient_offset3", 105904aadcaaSNiklas Cassel "cpr_init_voltage1", 106004aadcaaSNiklas Cassel "cpr_init_voltage2", 106104aadcaaSNiklas Cassel "cpr_init_voltage3", 106204aadcaaSNiklas Cassel "cpr_quotient1", 106304aadcaaSNiklas Cassel "cpr_quotient2", 106404aadcaaSNiklas Cassel "cpr_quotient3", 106504aadcaaSNiklas Cassel "cpr_ring_osc1", 106604aadcaaSNiklas Cassel "cpr_ring_osc2", 106704aadcaaSNiklas Cassel "cpr_ring_osc3", 106804aadcaaSNiklas Cassel "cpr_fuse_revision"; 106904aadcaaSNiklas Cassel }; 107004aadcaaSNiklas Cassel 1071b4d82f4dSVinod Koul timer@b120000 { 1072b4d82f4dSVinod Koul #address-cells = <1>; 1073b4d82f4dSVinod Koul #size-cells = <1>; 1074b4d82f4dSVinod Koul ranges; 1075b4d82f4dSVinod Koul compatible = "arm,armv7-timer-mem"; 1076b4d82f4dSVinod Koul reg = <0x0b120000 0x1000>; 1077b4d82f4dSVinod Koul clock-frequency = <19200000>; 1078b4d82f4dSVinod Koul 1079b4d82f4dSVinod Koul frame@b121000 { 1080b4d82f4dSVinod Koul frame-number = <0>; 1081b4d82f4dSVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1082b4d82f4dSVinod Koul <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1083b4d82f4dSVinod Koul reg = <0x0b121000 0x1000>, 1084b4d82f4dSVinod Koul <0x0b122000 0x1000>; 1085b4d82f4dSVinod Koul }; 1086b4d82f4dSVinod Koul 1087b4d82f4dSVinod Koul frame@b123000 { 1088b4d82f4dSVinod Koul frame-number = <1>; 1089b4d82f4dSVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1090b4d82f4dSVinod Koul reg = <0x0b123000 0x1000>; 1091b4d82f4dSVinod Koul status = "disabled"; 1092b4d82f4dSVinod Koul }; 1093b4d82f4dSVinod Koul 1094b4d82f4dSVinod Koul frame@b124000 { 1095b4d82f4dSVinod Koul frame-number = <2>; 1096b4d82f4dSVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1097b4d82f4dSVinod Koul reg = <0x0b124000 0x1000>; 1098b4d82f4dSVinod Koul status = "disabled"; 1099b4d82f4dSVinod Koul }; 1100b4d82f4dSVinod Koul 1101b4d82f4dSVinod Koul frame@b125000 { 1102b4d82f4dSVinod Koul frame-number = <3>; 1103b4d82f4dSVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1104b4d82f4dSVinod Koul reg = <0x0b125000 0x1000>; 1105b4d82f4dSVinod Koul status = "disabled"; 1106b4d82f4dSVinod Koul }; 1107b4d82f4dSVinod Koul 1108b4d82f4dSVinod Koul frame@b126000 { 1109b4d82f4dSVinod Koul frame-number = <4>; 1110b4d82f4dSVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1111b4d82f4dSVinod Koul reg = <0x0b126000 0x1000>; 1112b4d82f4dSVinod Koul status = "disabled"; 1113b4d82f4dSVinod Koul }; 1114b4d82f4dSVinod Koul 1115b4d82f4dSVinod Koul frame@b127000 { 1116b4d82f4dSVinod Koul frame-number = <5>; 1117b4d82f4dSVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1118b4d82f4dSVinod Koul reg = <0xb127000 0x1000>; 1119b4d82f4dSVinod Koul status = "disabled"; 1120b4d82f4dSVinod Koul }; 1121b4d82f4dSVinod Koul 1122b4d82f4dSVinod Koul frame@b128000 { 1123b4d82f4dSVinod Koul frame-number = <6>; 1124b4d82f4dSVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1125b4d82f4dSVinod Koul reg = <0x0b128000 0x1000>; 1126b4d82f4dSVinod Koul status = "disabled"; 1127b4d82f4dSVinod Koul }; 1128b4d82f4dSVinod Koul }; 112967779ca2SBjorn Andersson 113067779ca2SBjorn Andersson remoteproc_adsp: remoteproc@c700000 { 113167779ca2SBjorn Andersson compatible = "qcom,qcs404-adsp-pas"; 113267779ca2SBjorn Andersson reg = <0x0c700000 0x4040>; 113367779ca2SBjorn Andersson 113467779ca2SBjorn Andersson interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 113567779ca2SBjorn Andersson <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 113667779ca2SBjorn Andersson <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 113767779ca2SBjorn Andersson <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 113867779ca2SBjorn Andersson <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 113967779ca2SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 114067779ca2SBjorn Andersson "handover", "stop-ack"; 114167779ca2SBjorn Andersson 114267779ca2SBjorn Andersson clocks = <&xo_board>; 114367779ca2SBjorn Andersson clock-names = "xo"; 114467779ca2SBjorn Andersson 114567779ca2SBjorn Andersson memory-region = <&adsp_fw_mem>; 114667779ca2SBjorn Andersson 114767779ca2SBjorn Andersson qcom,smem-states = <&adsp_smp2p_out 0>; 114867779ca2SBjorn Andersson qcom,smem-state-names = "stop"; 114967779ca2SBjorn Andersson 115067779ca2SBjorn Andersson status = "disabled"; 115167779ca2SBjorn Andersson 115267779ca2SBjorn Andersson glink-edge { 115367779ca2SBjorn Andersson interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 115467779ca2SBjorn Andersson 115567779ca2SBjorn Andersson qcom,remote-pid = <2>; 115667779ca2SBjorn Andersson mboxes = <&apcs_glb 8>; 115767779ca2SBjorn Andersson 115867779ca2SBjorn Andersson label = "adsp"; 115967779ca2SBjorn Andersson }; 116067779ca2SBjorn Andersson }; 1161431f6464SBjorn Andersson 1162431f6464SBjorn Andersson pcie: pci@10000000 { 1163431f6464SBjorn Andersson compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; 1164431f6464SBjorn Andersson reg = <0x10000000 0xf1d>, 1165431f6464SBjorn Andersson <0x10000f20 0xa8>, 1166431f6464SBjorn Andersson <0x07780000 0x2000>, 1167431f6464SBjorn Andersson <0x10001000 0x2000>; 1168431f6464SBjorn Andersson reg-names = "dbi", "elbi", "parf", "config"; 1169431f6464SBjorn Andersson device_type = "pci"; 1170431f6464SBjorn Andersson linux,pci-domain = <0>; 1171431f6464SBjorn Andersson bus-range = <0x00 0xff>; 1172431f6464SBjorn Andersson num-lanes = <1>; 1173431f6464SBjorn Andersson #address-cells = <3>; 1174431f6464SBjorn Andersson #size-cells = <2>; 1175431f6464SBjorn Andersson 1176431f6464SBjorn Andersson ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ 1177431f6464SBjorn Andersson <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ 1178431f6464SBjorn Andersson 1179431f6464SBjorn Andersson interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1180431f6464SBjorn Andersson interrupt-names = "msi"; 1181431f6464SBjorn Andersson #interrupt-cells = <1>; 1182431f6464SBjorn Andersson interrupt-map-mask = <0 0 0 0x7>; 1183431f6464SBjorn Andersson interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1184431f6464SBjorn Andersson <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1185431f6464SBjorn Andersson <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1186431f6464SBjorn Andersson <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1187431f6464SBjorn Andersson clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1188431f6464SBjorn Andersson <&gcc GCC_PCIE_0_AUX_CLK>, 1189431f6464SBjorn Andersson <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1190431f6464SBjorn Andersson <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1191431f6464SBjorn Andersson clock-names = "iface", "aux", "master_bus", "slave_bus"; 1192431f6464SBjorn Andersson 1193431f6464SBjorn Andersson resets = <&gcc 18>, 1194431f6464SBjorn Andersson <&gcc 17>, 1195431f6464SBjorn Andersson <&gcc 15>, 1196431f6464SBjorn Andersson <&gcc 19>, 1197431f6464SBjorn Andersson <&gcc GCC_PCIE_0_BCR>, 1198431f6464SBjorn Andersson <&gcc 16>; 1199431f6464SBjorn Andersson reset-names = "axi_m", 1200431f6464SBjorn Andersson "axi_s", 1201431f6464SBjorn Andersson "axi_m_sticky", 1202431f6464SBjorn Andersson "pipe_sticky", 1203431f6464SBjorn Andersson "pwr", 1204431f6464SBjorn Andersson "ahb"; 1205431f6464SBjorn Andersson 1206431f6464SBjorn Andersson phys = <&pcie_phy>; 1207431f6464SBjorn Andersson phy-names = "pciephy"; 1208431f6464SBjorn Andersson 1209431f6464SBjorn Andersson status = "disabled"; 1210431f6464SBjorn Andersson }; 1211b4d82f4dSVinod Koul }; 1212b4d82f4dSVinod Koul 1213b4d82f4dSVinod Koul timer { 1214b4d82f4dSVinod Koul compatible = "arm,armv8-timer"; 1215b4d82f4dSVinod Koul interrupts = <GIC_PPI 2 0xff08>, 1216b4d82f4dSVinod Koul <GIC_PPI 3 0xff08>, 1217b4d82f4dSVinod Koul <GIC_PPI 4 0xff08>, 1218b4d82f4dSVinod Koul <GIC_PPI 1 0xff08>; 1219b4d82f4dSVinod Koul }; 1220afdfb0b3SVinod Koul 1221afdfb0b3SVinod Koul smp2p-adsp { 1222afdfb0b3SVinod Koul compatible = "qcom,smp2p"; 1223afdfb0b3SVinod Koul qcom,smem = <443>, <429>; 1224afdfb0b3SVinod Koul interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1225afdfb0b3SVinod Koul mboxes = <&apcs_glb 10>; 1226afdfb0b3SVinod Koul qcom,local-pid = <0>; 1227afdfb0b3SVinod Koul qcom,remote-pid = <2>; 1228afdfb0b3SVinod Koul 1229afdfb0b3SVinod Koul adsp_smp2p_out: master-kernel { 1230afdfb0b3SVinod Koul qcom,entry-name = "master-kernel"; 1231afdfb0b3SVinod Koul #qcom,smem-state-cells = <1>; 1232afdfb0b3SVinod Koul }; 1233afdfb0b3SVinod Koul 1234afdfb0b3SVinod Koul adsp_smp2p_in: slave-kernel { 1235afdfb0b3SVinod Koul qcom,entry-name = "slave-kernel"; 1236afdfb0b3SVinod Koul interrupt-controller; 1237afdfb0b3SVinod Koul #interrupt-cells = <2>; 1238afdfb0b3SVinod Koul }; 1239afdfb0b3SVinod Koul }; 1240afdfb0b3SVinod Koul 1241afdfb0b3SVinod Koul smp2p-cdsp { 1242afdfb0b3SVinod Koul compatible = "qcom,smp2p"; 1243afdfb0b3SVinod Koul qcom,smem = <94>, <432>; 1244afdfb0b3SVinod Koul interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1245afdfb0b3SVinod Koul mboxes = <&apcs_glb 14>; 1246afdfb0b3SVinod Koul qcom,local-pid = <0>; 1247afdfb0b3SVinod Koul qcom,remote-pid = <5>; 1248afdfb0b3SVinod Koul 1249afdfb0b3SVinod Koul cdsp_smp2p_out: master-kernel { 1250afdfb0b3SVinod Koul qcom,entry-name = "master-kernel"; 1251afdfb0b3SVinod Koul #qcom,smem-state-cells = <1>; 1252afdfb0b3SVinod Koul }; 1253afdfb0b3SVinod Koul 1254afdfb0b3SVinod Koul cdsp_smp2p_in: slave-kernel { 1255afdfb0b3SVinod Koul qcom,entry-name = "slave-kernel"; 1256afdfb0b3SVinod Koul interrupt-controller; 1257afdfb0b3SVinod Koul #interrupt-cells = <2>; 1258afdfb0b3SVinod Koul }; 1259afdfb0b3SVinod Koul }; 1260afdfb0b3SVinod Koul 1261afdfb0b3SVinod Koul smp2p-wcss { 1262afdfb0b3SVinod Koul compatible = "qcom,smp2p"; 1263afdfb0b3SVinod Koul qcom,smem = <435>, <428>; 1264afdfb0b3SVinod Koul interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1265afdfb0b3SVinod Koul mboxes = <&apcs_glb 18>; 1266afdfb0b3SVinod Koul qcom,local-pid = <0>; 1267afdfb0b3SVinod Koul qcom,remote-pid = <1>; 1268afdfb0b3SVinod Koul 1269afdfb0b3SVinod Koul wcss_smp2p_out: master-kernel { 1270afdfb0b3SVinod Koul qcom,entry-name = "master-kernel"; 1271afdfb0b3SVinod Koul #qcom,smem-state-cells = <1>; 1272afdfb0b3SVinod Koul }; 1273afdfb0b3SVinod Koul 1274afdfb0b3SVinod Koul wcss_smp2p_in: slave-kernel { 1275afdfb0b3SVinod Koul qcom,entry-name = "slave-kernel"; 1276afdfb0b3SVinod Koul interrupt-controller; 1277afdfb0b3SVinod Koul #interrupt-cells = <2>; 1278afdfb0b3SVinod Koul }; 1279afdfb0b3SVinod Koul }; 1280f48cee32SAmit Kucheria 1281f48cee32SAmit Kucheria thermal-zones { 1282f48cee32SAmit Kucheria aoss-thermal { 1283f48cee32SAmit Kucheria polling-delay-passive = <250>; 1284f48cee32SAmit Kucheria polling-delay = <1000>; 1285f48cee32SAmit Kucheria 1286f48cee32SAmit Kucheria thermal-sensors = <&tsens 0>; 1287f48cee32SAmit Kucheria 1288f48cee32SAmit Kucheria trips { 1289e8c48eb0SVinod Koul aoss_alert0: trip-point0 { 1290f48cee32SAmit Kucheria temperature = <105000>; 1291f48cee32SAmit Kucheria hysteresis = <2000>; 1292f48cee32SAmit Kucheria type = "hot"; 1293f48cee32SAmit Kucheria }; 1294f48cee32SAmit Kucheria }; 1295f48cee32SAmit Kucheria }; 1296f48cee32SAmit Kucheria 1297f48cee32SAmit Kucheria q6-hvx-thermal { 1298f48cee32SAmit Kucheria polling-delay-passive = <250>; 1299f48cee32SAmit Kucheria polling-delay = <1000>; 1300f48cee32SAmit Kucheria 1301f48cee32SAmit Kucheria thermal-sensors = <&tsens 1>; 1302f48cee32SAmit Kucheria 1303f48cee32SAmit Kucheria trips { 1304e8c48eb0SVinod Koul q6_hvx_alert0: trip-point0 { 1305f48cee32SAmit Kucheria temperature = <105000>; 1306f48cee32SAmit Kucheria hysteresis = <2000>; 1307f48cee32SAmit Kucheria type = "hot"; 1308f48cee32SAmit Kucheria }; 1309f48cee32SAmit Kucheria }; 1310f48cee32SAmit Kucheria }; 1311f48cee32SAmit Kucheria 1312f48cee32SAmit Kucheria lpass-thermal { 1313f48cee32SAmit Kucheria polling-delay-passive = <250>; 1314f48cee32SAmit Kucheria polling-delay = <1000>; 1315f48cee32SAmit Kucheria 1316f48cee32SAmit Kucheria thermal-sensors = <&tsens 2>; 1317f48cee32SAmit Kucheria 1318f48cee32SAmit Kucheria trips { 1319e8c48eb0SVinod Koul lpass_alert0: trip-point0 { 1320f48cee32SAmit Kucheria temperature = <105000>; 1321f48cee32SAmit Kucheria hysteresis = <2000>; 1322f48cee32SAmit Kucheria type = "hot"; 1323f48cee32SAmit Kucheria }; 1324f48cee32SAmit Kucheria }; 1325f48cee32SAmit Kucheria }; 1326f48cee32SAmit Kucheria 1327f48cee32SAmit Kucheria wlan-thermal { 1328f48cee32SAmit Kucheria polling-delay-passive = <250>; 1329f48cee32SAmit Kucheria polling-delay = <1000>; 1330f48cee32SAmit Kucheria 1331f48cee32SAmit Kucheria thermal-sensors = <&tsens 3>; 1332f48cee32SAmit Kucheria 1333f48cee32SAmit Kucheria trips { 1334e8c48eb0SVinod Koul wlan_alert0: trip-point0 { 1335f48cee32SAmit Kucheria temperature = <105000>; 1336f48cee32SAmit Kucheria hysteresis = <2000>; 1337f48cee32SAmit Kucheria type = "hot"; 1338f48cee32SAmit Kucheria }; 1339f48cee32SAmit Kucheria }; 1340f48cee32SAmit Kucheria }; 1341f48cee32SAmit Kucheria 1342f48cee32SAmit Kucheria cluster-thermal { 1343f48cee32SAmit Kucheria polling-delay-passive = <250>; 1344f48cee32SAmit Kucheria polling-delay = <1000>; 1345f48cee32SAmit Kucheria 1346f48cee32SAmit Kucheria thermal-sensors = <&tsens 4>; 1347f48cee32SAmit Kucheria 1348f48cee32SAmit Kucheria trips { 1349e8c48eb0SVinod Koul cluster_alert0: trip-point0 { 1350f48cee32SAmit Kucheria temperature = <95000>; 1351f48cee32SAmit Kucheria hysteresis = <2000>; 1352f48cee32SAmit Kucheria type = "hot"; 1353f48cee32SAmit Kucheria }; 1354e8c48eb0SVinod Koul cluster_alert1: trip-point1 { 1355f48cee32SAmit Kucheria temperature = <105000>; 1356f48cee32SAmit Kucheria hysteresis = <2000>; 1357f48cee32SAmit Kucheria type = "passive"; 1358f48cee32SAmit Kucheria }; 1359f48cee32SAmit Kucheria cluster_crit: cluster_crit { 1360f48cee32SAmit Kucheria temperature = <120000>; 1361f48cee32SAmit Kucheria hysteresis = <2000>; 1362f48cee32SAmit Kucheria type = "critical"; 1363f48cee32SAmit Kucheria }; 1364f48cee32SAmit Kucheria }; 1365f48cee32SAmit Kucheria cooling-maps { 1366f48cee32SAmit Kucheria map0 { 1367f48cee32SAmit Kucheria trip = <&cluster_alert1>; 1368f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1369f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1370f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1371f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1372f48cee32SAmit Kucheria }; 1373f48cee32SAmit Kucheria }; 1374f48cee32SAmit Kucheria }; 1375f48cee32SAmit Kucheria 1376f48cee32SAmit Kucheria cpu0-thermal { 1377f48cee32SAmit Kucheria polling-delay-passive = <250>; 1378f48cee32SAmit Kucheria polling-delay = <1000>; 1379f48cee32SAmit Kucheria 1380f48cee32SAmit Kucheria thermal-sensors = <&tsens 5>; 1381f48cee32SAmit Kucheria 1382f48cee32SAmit Kucheria trips { 1383e8c48eb0SVinod Koul cpu0_alert0: trip-point0 { 1384f48cee32SAmit Kucheria temperature = <95000>; 1385f48cee32SAmit Kucheria hysteresis = <2000>; 1386f48cee32SAmit Kucheria type = "hot"; 1387f48cee32SAmit Kucheria }; 1388e8c48eb0SVinod Koul cpu0_alert1: trip-point1 { 1389f48cee32SAmit Kucheria temperature = <105000>; 1390f48cee32SAmit Kucheria hysteresis = <2000>; 1391f48cee32SAmit Kucheria type = "passive"; 1392f48cee32SAmit Kucheria }; 1393f48cee32SAmit Kucheria cpu0_crit: cpu_crit { 1394f48cee32SAmit Kucheria temperature = <120000>; 1395f48cee32SAmit Kucheria hysteresis = <2000>; 1396f48cee32SAmit Kucheria type = "critical"; 1397f48cee32SAmit Kucheria }; 1398f48cee32SAmit Kucheria }; 1399f48cee32SAmit Kucheria cooling-maps { 1400f48cee32SAmit Kucheria map0 { 1401f48cee32SAmit Kucheria trip = <&cpu0_alert1>; 1402f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1403f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1404f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1405f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1406f48cee32SAmit Kucheria }; 1407f48cee32SAmit Kucheria }; 1408f48cee32SAmit Kucheria }; 1409f48cee32SAmit Kucheria 1410f48cee32SAmit Kucheria cpu1-thermal { 1411f48cee32SAmit Kucheria polling-delay-passive = <250>; 1412f48cee32SAmit Kucheria polling-delay = <1000>; 1413f48cee32SAmit Kucheria 1414f48cee32SAmit Kucheria thermal-sensors = <&tsens 6>; 1415f48cee32SAmit Kucheria 1416f48cee32SAmit Kucheria trips { 1417e8c48eb0SVinod Koul cpu1_alert0: trip-point0 { 1418f48cee32SAmit Kucheria temperature = <95000>; 1419f48cee32SAmit Kucheria hysteresis = <2000>; 1420f48cee32SAmit Kucheria type = "hot"; 1421f48cee32SAmit Kucheria }; 1422e8c48eb0SVinod Koul cpu1_alert1: trip-point1 { 1423f48cee32SAmit Kucheria temperature = <105000>; 1424f48cee32SAmit Kucheria hysteresis = <2000>; 1425f48cee32SAmit Kucheria type = "passive"; 1426f48cee32SAmit Kucheria }; 1427f48cee32SAmit Kucheria cpu1_crit: cpu_crit { 1428f48cee32SAmit Kucheria temperature = <120000>; 1429f48cee32SAmit Kucheria hysteresis = <2000>; 1430f48cee32SAmit Kucheria type = "critical"; 1431f48cee32SAmit Kucheria }; 1432f48cee32SAmit Kucheria }; 1433f48cee32SAmit Kucheria cooling-maps { 1434f48cee32SAmit Kucheria map0 { 1435f48cee32SAmit Kucheria trip = <&cpu1_alert1>; 1436f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1437f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1438f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1439f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1440f48cee32SAmit Kucheria }; 1441f48cee32SAmit Kucheria }; 1442f48cee32SAmit Kucheria }; 1443f48cee32SAmit Kucheria 1444f48cee32SAmit Kucheria cpu2-thermal { 1445f48cee32SAmit Kucheria polling-delay-passive = <250>; 1446f48cee32SAmit Kucheria polling-delay = <1000>; 1447f48cee32SAmit Kucheria 1448f48cee32SAmit Kucheria thermal-sensors = <&tsens 7>; 1449f48cee32SAmit Kucheria 1450f48cee32SAmit Kucheria trips { 1451e8c48eb0SVinod Koul cpu2_alert0: trip-point0 { 1452f48cee32SAmit Kucheria temperature = <95000>; 1453f48cee32SAmit Kucheria hysteresis = <2000>; 1454f48cee32SAmit Kucheria type = "hot"; 1455f48cee32SAmit Kucheria }; 1456e8c48eb0SVinod Koul cpu2_alert1: trip-point1 { 1457f48cee32SAmit Kucheria temperature = <105000>; 1458f48cee32SAmit Kucheria hysteresis = <2000>; 1459f48cee32SAmit Kucheria type = "passive"; 1460f48cee32SAmit Kucheria }; 1461f48cee32SAmit Kucheria cpu2_crit: cpu_crit { 1462f48cee32SAmit Kucheria temperature = <120000>; 1463f48cee32SAmit Kucheria hysteresis = <2000>; 1464f48cee32SAmit Kucheria type = "critical"; 1465f48cee32SAmit Kucheria }; 1466f48cee32SAmit Kucheria }; 1467f48cee32SAmit Kucheria cooling-maps { 1468f48cee32SAmit Kucheria map0 { 1469f48cee32SAmit Kucheria trip = <&cpu2_alert1>; 1470f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1471f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1472f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1473f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1474f48cee32SAmit Kucheria }; 1475f48cee32SAmit Kucheria }; 1476f48cee32SAmit Kucheria }; 1477f48cee32SAmit Kucheria 1478f48cee32SAmit Kucheria cpu3-thermal { 1479f48cee32SAmit Kucheria polling-delay-passive = <250>; 1480f48cee32SAmit Kucheria polling-delay = <1000>; 1481f48cee32SAmit Kucheria 1482f48cee32SAmit Kucheria thermal-sensors = <&tsens 8>; 1483f48cee32SAmit Kucheria 1484f48cee32SAmit Kucheria trips { 1485e8c48eb0SVinod Koul cpu3_alert0: trip-point0 { 1486f48cee32SAmit Kucheria temperature = <95000>; 1487f48cee32SAmit Kucheria hysteresis = <2000>; 1488f48cee32SAmit Kucheria type = "hot"; 1489f48cee32SAmit Kucheria }; 1490e8c48eb0SVinod Koul cpu3_alert1: trip-point1 { 1491f48cee32SAmit Kucheria temperature = <105000>; 1492f48cee32SAmit Kucheria hysteresis = <2000>; 1493f48cee32SAmit Kucheria type = "passive"; 1494f48cee32SAmit Kucheria }; 1495f48cee32SAmit Kucheria cpu3_crit: cpu_crit { 1496f48cee32SAmit Kucheria temperature = <120000>; 1497f48cee32SAmit Kucheria hysteresis = <2000>; 1498f48cee32SAmit Kucheria type = "critical"; 1499f48cee32SAmit Kucheria }; 1500f48cee32SAmit Kucheria }; 1501f48cee32SAmit Kucheria cooling-maps { 1502f48cee32SAmit Kucheria map0 { 1503f48cee32SAmit Kucheria trip = <&cpu3_alert1>; 1504f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1505f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1506f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1507f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1508f48cee32SAmit Kucheria }; 1509f48cee32SAmit Kucheria }; 1510f48cee32SAmit Kucheria }; 1511f48cee32SAmit Kucheria 1512f48cee32SAmit Kucheria gpu-thermal { 1513f48cee32SAmit Kucheria polling-delay-passive = <250>; 1514f48cee32SAmit Kucheria polling-delay = <1000>; 1515f48cee32SAmit Kucheria 1516f48cee32SAmit Kucheria thermal-sensors = <&tsens 9>; 1517f48cee32SAmit Kucheria 1518f48cee32SAmit Kucheria trips { 1519e8c48eb0SVinod Koul gpu_alert0: trip-point0 { 1520f48cee32SAmit Kucheria temperature = <95000>; 1521f48cee32SAmit Kucheria hysteresis = <2000>; 1522f48cee32SAmit Kucheria type = "hot"; 1523f48cee32SAmit Kucheria }; 1524f48cee32SAmit Kucheria }; 1525f48cee32SAmit Kucheria }; 1526f48cee32SAmit Kucheria }; 1527b4d82f4dSVinod Koul}; 1528