1b4d82f4dSVinod Koul// SPDX-License-Identifier: GPL-2.0 2b4d82f4dSVinod Koul// Copyright (c) 2018, Linaro Limited 3b4d82f4dSVinod Koul 4b4d82f4dSVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 5b4d82f4dSVinod Koul#include <dt-bindings/clock/qcom,gcc-qcs404.h> 60b0c3390SBjorn Andersson#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 7bf75731dSBjorn Andersson#include <dt-bindings/clock/qcom,rpmcc.h> 811f61210SBjorn Andersson#include <dt-bindings/power/qcom-rpmpd.h> 9f48cee32SAmit Kucheria#include <dt-bindings/thermal/thermal.h> 10b4d82f4dSVinod Koul 11b4d82f4dSVinod Koul/ { 12b4d82f4dSVinod Koul interrupt-parent = <&intc>; 13b4d82f4dSVinod Koul 14b4d82f4dSVinod Koul #address-cells = <2>; 15b4d82f4dSVinod Koul #size-cells = <2>; 16b4d82f4dSVinod Koul 17b4d82f4dSVinod Koul chosen { }; 18b4d82f4dSVinod Koul 19b4d82f4dSVinod Koul clocks { 20b4d82f4dSVinod Koul xo_board: xo-board { 21b4d82f4dSVinod Koul compatible = "fixed-clock"; 22b4d82f4dSVinod Koul #clock-cells = <0>; 23b4d82f4dSVinod Koul clock-frequency = <19200000>; 24b4d82f4dSVinod Koul }; 2510c71fd1SJorge Ramirez-Ortiz 2610c71fd1SJorge Ramirez-Ortiz sleep_clk: sleep-clk { 2710c71fd1SJorge Ramirez-Ortiz compatible = "fixed-clock"; 2810c71fd1SJorge Ramirez-Ortiz #clock-cells = <0>; 2910c71fd1SJorge Ramirez-Ortiz clock-frequency = <32768>; 3010c71fd1SJorge Ramirez-Ortiz }; 31b4d82f4dSVinod Koul }; 32b4d82f4dSVinod Koul 33b4d82f4dSVinod Koul cpus { 34b4d82f4dSVinod Koul #address-cells = <1>; 35b4d82f4dSVinod Koul #size-cells = <0>; 36b4d82f4dSVinod Koul 37b4d82f4dSVinod Koul CPU0: cpu@100 { 38b4d82f4dSVinod Koul device_type = "cpu"; 39b4d82f4dSVinod Koul compatible = "arm,cortex-a53"; 40b4d82f4dSVinod Koul reg = <0x100>; 41b4d82f4dSVinod Koul enable-method = "psci"; 4245ea8f32SNiklas Cassel cpu-idle-states = <&CPU_SLEEP_0>; 43b4d82f4dSVinod Koul next-level-cache = <&L2_0>; 44f48cee32SAmit Kucheria #cooling-cells = <2>; 45cbccc6bcSJorge Ramirez-Ortiz clocks = <&apcs_glb>; 46cbccc6bcSJorge Ramirez-Ortiz operating-points-v2 = <&cpu_opp_table>; 4704aadcaaSNiklas Cassel power-domains = <&cpr>; 4804aadcaaSNiklas Cassel power-domain-names = "cpr"; 49b4d82f4dSVinod Koul }; 50b4d82f4dSVinod Koul 51b4d82f4dSVinod Koul CPU1: cpu@101 { 52b4d82f4dSVinod Koul device_type = "cpu"; 53b4d82f4dSVinod Koul compatible = "arm,cortex-a53"; 54b4d82f4dSVinod Koul reg = <0x101>; 55b4d82f4dSVinod Koul enable-method = "psci"; 5645ea8f32SNiklas Cassel cpu-idle-states = <&CPU_SLEEP_0>; 57b4d82f4dSVinod Koul next-level-cache = <&L2_0>; 58f48cee32SAmit Kucheria #cooling-cells = <2>; 59cbccc6bcSJorge Ramirez-Ortiz clocks = <&apcs_glb>; 60cbccc6bcSJorge Ramirez-Ortiz operating-points-v2 = <&cpu_opp_table>; 6104aadcaaSNiklas Cassel power-domains = <&cpr>; 6204aadcaaSNiklas Cassel power-domain-names = "cpr"; 63b4d82f4dSVinod Koul }; 64b4d82f4dSVinod Koul 65b4d82f4dSVinod Koul CPU2: cpu@102 { 66b4d82f4dSVinod Koul device_type = "cpu"; 67b4d82f4dSVinod Koul compatible = "arm,cortex-a53"; 68b4d82f4dSVinod Koul reg = <0x102>; 69b4d82f4dSVinod Koul enable-method = "psci"; 7045ea8f32SNiklas Cassel cpu-idle-states = <&CPU_SLEEP_0>; 71b4d82f4dSVinod Koul next-level-cache = <&L2_0>; 72f48cee32SAmit Kucheria #cooling-cells = <2>; 73cbccc6bcSJorge Ramirez-Ortiz clocks = <&apcs_glb>; 74cbccc6bcSJorge Ramirez-Ortiz operating-points-v2 = <&cpu_opp_table>; 7504aadcaaSNiklas Cassel power-domains = <&cpr>; 7604aadcaaSNiklas Cassel power-domain-names = "cpr"; 77b4d82f4dSVinod Koul }; 78b4d82f4dSVinod Koul 79b4d82f4dSVinod Koul CPU3: cpu@103 { 80b4d82f4dSVinod Koul device_type = "cpu"; 81b4d82f4dSVinod Koul compatible = "arm,cortex-a53"; 82b4d82f4dSVinod Koul reg = <0x103>; 83b4d82f4dSVinod Koul enable-method = "psci"; 8445ea8f32SNiklas Cassel cpu-idle-states = <&CPU_SLEEP_0>; 85b4d82f4dSVinod Koul next-level-cache = <&L2_0>; 86f48cee32SAmit Kucheria #cooling-cells = <2>; 87cbccc6bcSJorge Ramirez-Ortiz clocks = <&apcs_glb>; 88cbccc6bcSJorge Ramirez-Ortiz operating-points-v2 = <&cpu_opp_table>; 8904aadcaaSNiklas Cassel power-domains = <&cpr>; 9004aadcaaSNiklas Cassel power-domain-names = "cpr"; 91b4d82f4dSVinod Koul }; 92b4d82f4dSVinod Koul 93b4d82f4dSVinod Koul L2_0: l2-cache { 94b4d82f4dSVinod Koul compatible = "cache"; 95b4d82f4dSVinod Koul cache-level = <2>; 96b4d82f4dSVinod Koul }; 9745ea8f32SNiklas Cassel 9845ea8f32SNiklas Cassel idle-states { 9945ea8f32SNiklas Cassel entry-method = "psci"; 10045ea8f32SNiklas Cassel 10145ea8f32SNiklas Cassel CPU_SLEEP_0: cpu-sleep-0 { 10245ea8f32SNiklas Cassel compatible = "arm,idle-state"; 10345ea8f32SNiklas Cassel idle-state-name = "standalone-power-collapse"; 10445ea8f32SNiklas Cassel arm,psci-suspend-param = <0x40000003>; 10545ea8f32SNiklas Cassel entry-latency-us = <125>; 10645ea8f32SNiklas Cassel exit-latency-us = <180>; 10745ea8f32SNiklas Cassel min-residency-us = <595>; 10845ea8f32SNiklas Cassel local-timer-stop; 10945ea8f32SNiklas Cassel }; 11045ea8f32SNiklas Cassel }; 111b4d82f4dSVinod Koul }; 112b4d82f4dSVinod Koul 113b7072cc5SYassine Oudjana cpu_opp_table: opp-table-cpu { 11404aadcaaSNiklas Cassel compatible = "operating-points-v2-kryo-cpu"; 115cbccc6bcSJorge Ramirez-Ortiz opp-shared; 116cbccc6bcSJorge Ramirez-Ortiz 117cbccc6bcSJorge Ramirez-Ortiz opp-1094400000 { 118cbccc6bcSJorge Ramirez-Ortiz opp-hz = /bits/ 64 <1094400000>; 11904aadcaaSNiklas Cassel required-opps = <&cpr_opp1>; 120cbccc6bcSJorge Ramirez-Ortiz }; 121cbccc6bcSJorge Ramirez-Ortiz opp-1248000000 { 122cbccc6bcSJorge Ramirez-Ortiz opp-hz = /bits/ 64 <1248000000>; 12304aadcaaSNiklas Cassel required-opps = <&cpr_opp2>; 124cbccc6bcSJorge Ramirez-Ortiz }; 125cbccc6bcSJorge Ramirez-Ortiz opp-1401600000 { 126cbccc6bcSJorge Ramirez-Ortiz opp-hz = /bits/ 64 <1401600000>; 12704aadcaaSNiklas Cassel required-opps = <&cpr_opp3>; 12804aadcaaSNiklas Cassel }; 12904aadcaaSNiklas Cassel }; 13004aadcaaSNiklas Cassel 131b7072cc5SYassine Oudjana cpr_opp_table: opp-table-cpr { 13204aadcaaSNiklas Cassel compatible = "operating-points-v2-qcom-level"; 13304aadcaaSNiklas Cassel 13404aadcaaSNiklas Cassel cpr_opp1: opp1 { 13504aadcaaSNiklas Cassel opp-level = <1>; 13604aadcaaSNiklas Cassel qcom,opp-fuse-level = <1>; 13704aadcaaSNiklas Cassel }; 13804aadcaaSNiklas Cassel cpr_opp2: opp2 { 13904aadcaaSNiklas Cassel opp-level = <2>; 14004aadcaaSNiklas Cassel qcom,opp-fuse-level = <2>; 14104aadcaaSNiklas Cassel }; 14204aadcaaSNiklas Cassel cpr_opp3: opp3 { 14304aadcaaSNiklas Cassel opp-level = <3>; 14404aadcaaSNiklas Cassel qcom,opp-fuse-level = <3>; 145cbccc6bcSJorge Ramirez-Ortiz }; 146cbccc6bcSJorge Ramirez-Ortiz }; 147cbccc6bcSJorge Ramirez-Ortiz 148e7fd184fSBjorn Andersson firmware { 149e7fd184fSBjorn Andersson scm: scm { 150e7fd184fSBjorn Andersson compatible = "qcom,scm-qcs404", "qcom,scm"; 151e7fd184fSBjorn Andersson #reset-cells = <1>; 152e7fd184fSBjorn Andersson }; 153e7fd184fSBjorn Andersson }; 154e7fd184fSBjorn Andersson 155b4d82f4dSVinod Koul memory@80000000 { 156b4d82f4dSVinod Koul device_type = "memory"; 157b4d82f4dSVinod Koul /* We expect the bootloader to fill in the size */ 158b4d82f4dSVinod Koul reg = <0 0x80000000 0 0>; 159b4d82f4dSVinod Koul }; 160b4d82f4dSVinod Koul 161b4d82f4dSVinod Koul psci { 162b4d82f4dSVinod Koul compatible = "arm,psci-1.0"; 163b4d82f4dSVinod Koul method = "smc"; 164b4d82f4dSVinod Koul }; 165b4d82f4dSVinod Koul 166d59117abSBjorn Andersson reserved-memory { 167d59117abSBjorn Andersson #address-cells = <2>; 168d59117abSBjorn Andersson #size-cells = <2>; 169d59117abSBjorn Andersson ranges; 170d59117abSBjorn Andersson 171a87fa5bcSBjorn Andersson tz_apps_mem: memory@85900000 { 172a87fa5bcSBjorn Andersson reg = <0 0x85900000 0 0x500000>; 173a87fa5bcSBjorn Andersson no-map; 174a87fa5bcSBjorn Andersson }; 175a87fa5bcSBjorn Andersson 176a87fa5bcSBjorn Andersson xbl_mem: memory@85e00000 { 177a87fa5bcSBjorn Andersson reg = <0 0x85e00000 0 0x100000>; 178d59117abSBjorn Andersson no-map; 179d59117abSBjorn Andersson }; 180d59117abSBjorn Andersson 181d59117abSBjorn Andersson smem_region: memory@85f00000 { 182d59117abSBjorn Andersson reg = <0 0x85f00000 0 0x200000>; 183d59117abSBjorn Andersson no-map; 184d59117abSBjorn Andersson }; 185d59117abSBjorn Andersson 186a87fa5bcSBjorn Andersson tz_mem: memory@86100000 { 187d59117abSBjorn Andersson reg = <0 0x86100000 0 0x300000>; 188d59117abSBjorn Andersson no-map; 189d59117abSBjorn Andersson }; 190d59117abSBjorn Andersson 191d59117abSBjorn Andersson wlan_fw_mem: memory@86400000 { 192a87fa5bcSBjorn Andersson reg = <0 0x86400000 0 0x1100000>; 193d59117abSBjorn Andersson no-map; 194d59117abSBjorn Andersson }; 195d59117abSBjorn Andersson 196a87fa5bcSBjorn Andersson adsp_fw_mem: memory@87500000 { 197a87fa5bcSBjorn Andersson reg = <0 0x87500000 0 0x1a00000>; 198d59117abSBjorn Andersson no-map; 199d59117abSBjorn Andersson }; 200d59117abSBjorn Andersson 201a87fa5bcSBjorn Andersson cdsp_fw_mem: memory@88f00000 { 202a87fa5bcSBjorn Andersson reg = <0 0x88f00000 0 0x600000>; 203d59117abSBjorn Andersson no-map; 204d59117abSBjorn Andersson }; 205d59117abSBjorn Andersson 206a87fa5bcSBjorn Andersson wlan_msa_mem: memory@89500000 { 207a87fa5bcSBjorn Andersson reg = <0 0x89500000 0 0x100000>; 208a87fa5bcSBjorn Andersson no-map; 209a87fa5bcSBjorn Andersson }; 210a87fa5bcSBjorn Andersson 211a87fa5bcSBjorn Andersson uefi_mem: memory@9f800000 { 212a87fa5bcSBjorn Andersson reg = <0 0x9f800000 0 0x800000>; 213d59117abSBjorn Andersson no-map; 214d59117abSBjorn Andersson }; 215d59117abSBjorn Andersson }; 216d59117abSBjorn Andersson 2177fc7089dSBjorn Andersson rpm-glink { 2187fc7089dSBjorn Andersson compatible = "qcom,glink-rpm"; 2197fc7089dSBjorn Andersson 2207fc7089dSBjorn Andersson interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 2217fc7089dSBjorn Andersson qcom,rpm-msg-ram = <&rpm_msg_ram>; 2227fc7089dSBjorn Andersson mboxes = <&apcs_glb 0>; 2237fc7089dSBjorn Andersson 2247fc7089dSBjorn Andersson rpm_requests: glink-channel { 2257fc7089dSBjorn Andersson compatible = "qcom,rpm-qcs404"; 2267fc7089dSBjorn Andersson qcom,glink-channels = "rpm_requests"; 227bf75731dSBjorn Andersson 228bf75731dSBjorn Andersson rpmcc: clock-controller { 229bf75731dSBjorn Andersson compatible = "qcom,rpmcc-qcs404"; 230bf75731dSBjorn Andersson #clock-cells = <1>; 231bf75731dSBjorn Andersson }; 23211f61210SBjorn Andersson 23311f61210SBjorn Andersson rpmpd: power-controller { 23411f61210SBjorn Andersson compatible = "qcom,qcs404-rpmpd"; 23511f61210SBjorn Andersson #power-domain-cells = <1>; 23611f61210SBjorn Andersson operating-points-v2 = <&rpmpd_opp_table>; 23711f61210SBjorn Andersson 23811f61210SBjorn Andersson rpmpd_opp_table: opp-table { 23911f61210SBjorn Andersson compatible = "operating-points-v2"; 24011f61210SBjorn Andersson 24111f61210SBjorn Andersson rpmpd_opp_ret: opp1 { 24211f61210SBjorn Andersson opp-level = <16>; 24311f61210SBjorn Andersson }; 24411f61210SBjorn Andersson 24511f61210SBjorn Andersson rpmpd_opp_ret_plus: opp2 { 24611f61210SBjorn Andersson opp-level = <32>; 24711f61210SBjorn Andersson }; 24811f61210SBjorn Andersson 24911f61210SBjorn Andersson rpmpd_opp_min_svs: opp3 { 25011f61210SBjorn Andersson opp-level = <48>; 25111f61210SBjorn Andersson }; 25211f61210SBjorn Andersson 25311f61210SBjorn Andersson rpmpd_opp_low_svs: opp4 { 25411f61210SBjorn Andersson opp-level = <64>; 25511f61210SBjorn Andersson }; 25611f61210SBjorn Andersson 25711f61210SBjorn Andersson rpmpd_opp_svs: opp5 { 25811f61210SBjorn Andersson opp-level = <128>; 25911f61210SBjorn Andersson }; 26011f61210SBjorn Andersson 26111f61210SBjorn Andersson rpmpd_opp_svs_plus: opp6 { 26211f61210SBjorn Andersson opp-level = <192>; 26311f61210SBjorn Andersson }; 26411f61210SBjorn Andersson 26511f61210SBjorn Andersson rpmpd_opp_nom: opp7 { 26611f61210SBjorn Andersson opp-level = <256>; 26711f61210SBjorn Andersson }; 26811f61210SBjorn Andersson 26911f61210SBjorn Andersson rpmpd_opp_nom_plus: opp8 { 27011f61210SBjorn Andersson opp-level = <320>; 27111f61210SBjorn Andersson }; 27211f61210SBjorn Andersson 27311f61210SBjorn Andersson rpmpd_opp_turbo: opp9 { 27411f61210SBjorn Andersson opp-level = <384>; 27511f61210SBjorn Andersson }; 27611f61210SBjorn Andersson 27711f61210SBjorn Andersson rpmpd_opp_turbo_no_cpr: opp10 { 27811f61210SBjorn Andersson opp-level = <416>; 27911f61210SBjorn Andersson }; 28011f61210SBjorn Andersson 28111f61210SBjorn Andersson rpmpd_opp_turbo_plus: opp11 { 28211f61210SBjorn Andersson opp-level = <512>; 28311f61210SBjorn Andersson }; 28411f61210SBjorn Andersson }; 28511f61210SBjorn Andersson }; 2867fc7089dSBjorn Andersson }; 2877fc7089dSBjorn Andersson }; 2887fc7089dSBjorn Andersson 2897fc7089dSBjorn Andersson smem { 2907fc7089dSBjorn Andersson compatible = "qcom,smem"; 2917fc7089dSBjorn Andersson 2927fc7089dSBjorn Andersson memory-region = <&smem_region>; 2937fc7089dSBjorn Andersson qcom,rpm-msg-ram = <&rpm_msg_ram>; 2947fc7089dSBjorn Andersson 2957fc7089dSBjorn Andersson hwlocks = <&tcsr_mutex 3>; 2967fc7089dSBjorn Andersson }; 2977fc7089dSBjorn Andersson 2987fc7089dSBjorn Andersson tcsr_mutex: hwlock { 2997fc7089dSBjorn Andersson compatible = "qcom,tcsr-mutex"; 3007fc7089dSBjorn Andersson syscon = <&tcsr_mutex_regs 0 0x1000>; 3017fc7089dSBjorn Andersson #hwlock-cells = <1>; 3027fc7089dSBjorn Andersson }; 3037fc7089dSBjorn Andersson 304b4d82f4dSVinod Koul soc: soc@0 { 305b4d82f4dSVinod Koul #address-cells = <1>; 306b4d82f4dSVinod Koul #size-cells = <1>; 307b4d82f4dSVinod Koul ranges = <0 0 0 0xffffffff>; 308b4d82f4dSVinod Koul compatible = "simple-bus"; 309b4d82f4dSVinod Koul 3100b0c3390SBjorn Andersson turingcc: clock-controller@800000 { 3110b0c3390SBjorn Andersson compatible = "qcom,qcs404-turingcc"; 3120b0c3390SBjorn Andersson reg = <0x00800000 0x30000>; 3130b0c3390SBjorn Andersson clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 3140b0c3390SBjorn Andersson 3150b0c3390SBjorn Andersson #clock-cells = <1>; 3160b0c3390SBjorn Andersson #reset-cells = <1>; 3170b0c3390SBjorn Andersson 3180b0c3390SBjorn Andersson status = "disabled"; 3190b0c3390SBjorn Andersson }; 3200b0c3390SBjorn Andersson 321179811beSStephan Gerhold rpm_msg_ram: sram@60000 { 3227fc7089dSBjorn Andersson compatible = "qcom,rpm-msg-ram"; 3237fc7089dSBjorn Andersson reg = <0x00060000 0x6000>; 3247fc7089dSBjorn Andersson }; 3257fc7089dSBjorn Andersson 3269375e7d7SBjorn Andersson usb3_phy: phy@78000 { 3279375e7d7SBjorn Andersson compatible = "qcom,usb-ss-28nm-phy"; 3289375e7d7SBjorn Andersson reg = <0x00078000 0x400>; 3299375e7d7SBjorn Andersson #phy-cells = <0>; 3309375e7d7SBjorn Andersson clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 3319375e7d7SBjorn Andersson <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 3329375e7d7SBjorn Andersson <&gcc GCC_USB3_PHY_PIPE_CLK>; 3339375e7d7SBjorn Andersson clock-names = "ref", "ahb", "pipe"; 3349375e7d7SBjorn Andersson resets = <&gcc GCC_USB3_PHY_BCR>, 3359375e7d7SBjorn Andersson <&gcc GCC_USB3PHY_PHY_BCR>; 3369375e7d7SBjorn Andersson reset-names = "com", "phy"; 3379375e7d7SBjorn Andersson status = "disabled"; 3389375e7d7SBjorn Andersson }; 3399375e7d7SBjorn Andersson 3409375e7d7SBjorn Andersson usb2_phy_prim: phy@7a000 { 3419375e7d7SBjorn Andersson compatible = "qcom,usb-hs-28nm-femtophy"; 3429375e7d7SBjorn Andersson reg = <0x0007a000 0x200>; 3439375e7d7SBjorn Andersson #phy-cells = <0>; 3449375e7d7SBjorn Andersson clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 3459375e7d7SBjorn Andersson <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 3469375e7d7SBjorn Andersson <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 3479375e7d7SBjorn Andersson clock-names = "ref", "ahb", "sleep"; 3489375e7d7SBjorn Andersson resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 3499375e7d7SBjorn Andersson <&gcc GCC_USB2A_PHY_BCR>; 3509375e7d7SBjorn Andersson reset-names = "phy", "por"; 3519375e7d7SBjorn Andersson status = "disabled"; 3529375e7d7SBjorn Andersson }; 3539375e7d7SBjorn Andersson 3549375e7d7SBjorn Andersson usb2_phy_sec: phy@7c000 { 3559375e7d7SBjorn Andersson compatible = "qcom,usb-hs-28nm-femtophy"; 3569375e7d7SBjorn Andersson reg = <0x0007c000 0x200>; 3579375e7d7SBjorn Andersson #phy-cells = <0>; 3589375e7d7SBjorn Andersson clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 3599375e7d7SBjorn Andersson <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 3609375e7d7SBjorn Andersson <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 3619375e7d7SBjorn Andersson clock-names = "ref", "ahb", "sleep"; 3629375e7d7SBjorn Andersson resets = <&gcc GCC_QUSB2_PHY_BCR>, 3639375e7d7SBjorn Andersson <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 3649375e7d7SBjorn Andersson reset-names = "phy", "por"; 3659375e7d7SBjorn Andersson status = "disabled"; 3669375e7d7SBjorn Andersson }; 3679375e7d7SBjorn Andersson 36864cf50d0SAmit Kucheria qfprom: qfprom@a4000 { 36964cf50d0SAmit Kucheria compatible = "qcom,qfprom"; 37064cf50d0SAmit Kucheria reg = <0x000a4000 0x1000>; 37164cf50d0SAmit Kucheria #address-cells = <1>; 37264cf50d0SAmit Kucheria #size-cells = <1>; 37364cf50d0SAmit Kucheria tsens_caldata: caldata@d0 { 37464cf50d0SAmit Kucheria reg = <0x1f8 0x14>; 37564cf50d0SAmit Kucheria }; 37604aadcaaSNiklas Cassel cpr_efuse_speedbin: speedbin@13c { 37704aadcaaSNiklas Cassel reg = <0x13c 0x4>; 37804aadcaaSNiklas Cassel bits = <2 3>; 37904aadcaaSNiklas Cassel }; 38004aadcaaSNiklas Cassel cpr_efuse_quot_offset1: qoffset1@231 { 38104aadcaaSNiklas Cassel reg = <0x231 0x4>; 38204aadcaaSNiklas Cassel bits = <4 7>; 38304aadcaaSNiklas Cassel }; 38404aadcaaSNiklas Cassel cpr_efuse_quot_offset2: qoffset2@232 { 38504aadcaaSNiklas Cassel reg = <0x232 0x4>; 38604aadcaaSNiklas Cassel bits = <3 7>; 38704aadcaaSNiklas Cassel }; 38804aadcaaSNiklas Cassel cpr_efuse_quot_offset3: qoffset3@233 { 38904aadcaaSNiklas Cassel reg = <0x233 0x4>; 39004aadcaaSNiklas Cassel bits = <2 7>; 39104aadcaaSNiklas Cassel }; 39204aadcaaSNiklas Cassel cpr_efuse_init_voltage1: ivoltage1@229 { 39304aadcaaSNiklas Cassel reg = <0x229 0x4>; 39404aadcaaSNiklas Cassel bits = <4 6>; 39504aadcaaSNiklas Cassel }; 39604aadcaaSNiklas Cassel cpr_efuse_init_voltage2: ivoltage2@22a { 39704aadcaaSNiklas Cassel reg = <0x22a 0x4>; 39804aadcaaSNiklas Cassel bits = <2 6>; 39904aadcaaSNiklas Cassel }; 40004aadcaaSNiklas Cassel cpr_efuse_init_voltage3: ivoltage3@22b { 40104aadcaaSNiklas Cassel reg = <0x22b 0x4>; 40204aadcaaSNiklas Cassel bits = <0 6>; 40304aadcaaSNiklas Cassel }; 40404aadcaaSNiklas Cassel cpr_efuse_quot1: quot1@22b { 40504aadcaaSNiklas Cassel reg = <0x22b 0x4>; 40604aadcaaSNiklas Cassel bits = <6 12>; 40704aadcaaSNiklas Cassel }; 40804aadcaaSNiklas Cassel cpr_efuse_quot2: quot2@22d { 40904aadcaaSNiklas Cassel reg = <0x22d 0x4>; 41004aadcaaSNiklas Cassel bits = <2 12>; 41104aadcaaSNiklas Cassel }; 41204aadcaaSNiklas Cassel cpr_efuse_quot3: quot3@230 { 41304aadcaaSNiklas Cassel reg = <0x230 0x4>; 41404aadcaaSNiklas Cassel bits = <0 12>; 41504aadcaaSNiklas Cassel }; 41604aadcaaSNiklas Cassel cpr_efuse_ring1: ring1@228 { 41704aadcaaSNiklas Cassel reg = <0x228 0x4>; 41804aadcaaSNiklas Cassel bits = <0 3>; 41904aadcaaSNiklas Cassel }; 42004aadcaaSNiklas Cassel cpr_efuse_ring2: ring2@228 { 42104aadcaaSNiklas Cassel reg = <0x228 0x4>; 42204aadcaaSNiklas Cassel bits = <4 3>; 42304aadcaaSNiklas Cassel }; 42404aadcaaSNiklas Cassel cpr_efuse_ring3: ring3@229 { 42504aadcaaSNiklas Cassel reg = <0x229 0x4>; 42604aadcaaSNiklas Cassel bits = <0 3>; 42704aadcaaSNiklas Cassel }; 42804aadcaaSNiklas Cassel cpr_efuse_revision: revision@218 { 42904aadcaaSNiklas Cassel reg = <0x218 0x4>; 43004aadcaaSNiklas Cassel bits = <3 3>; 43104aadcaaSNiklas Cassel }; 43264cf50d0SAmit Kucheria }; 43364cf50d0SAmit Kucheria 434df96c65cSVinod Koul rng: rng@e3000 { 435df96c65cSVinod Koul compatible = "qcom,prng-ee"; 436df96c65cSVinod Koul reg = <0x000e3000 0x1000>; 437df96c65cSVinod Koul clocks = <&gcc GCC_PRNG_AHB_CLK>; 438df96c65cSVinod Koul clock-names = "core"; 439df96c65cSVinod Koul }; 440df96c65cSVinod Koul 441668c7603SGeorgi Djakov bimc: interconnect@400000 { 442668c7603SGeorgi Djakov reg = <0x00400000 0x80000>; 443668c7603SGeorgi Djakov compatible = "qcom,qcs404-bimc"; 444668c7603SGeorgi Djakov #interconnect-cells = <1>; 445668c7603SGeorgi Djakov clock-names = "bus", "bus_a"; 446668c7603SGeorgi Djakov clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 447668c7603SGeorgi Djakov <&rpmcc RPM_SMD_BIMC_A_CLK>; 448668c7603SGeorgi Djakov }; 449668c7603SGeorgi Djakov 45064cf50d0SAmit Kucheria tsens: thermal-sensor@4a9000 { 45164cf50d0SAmit Kucheria compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 45264cf50d0SAmit Kucheria reg = <0x004a9000 0x1000>, /* TM */ 45364cf50d0SAmit Kucheria <0x004a8000 0x1000>; /* SROT */ 45464cf50d0SAmit Kucheria nvmem-cells = <&tsens_caldata>; 45564cf50d0SAmit Kucheria nvmem-cell-names = "calib"; 45664cf50d0SAmit Kucheria #qcom,sensors = <10>; 457e51f7ff4SAmit Kucheria interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 458e51f7ff4SAmit Kucheria interrupt-names = "uplow"; 45964cf50d0SAmit Kucheria #thermal-sensor-cells = <1>; 46064cf50d0SAmit Kucheria }; 46164cf50d0SAmit Kucheria 462668c7603SGeorgi Djakov pcnoc: interconnect@500000 { 463668c7603SGeorgi Djakov reg = <0x00500000 0x15080>; 464668c7603SGeorgi Djakov compatible = "qcom,qcs404-pcnoc"; 465668c7603SGeorgi Djakov #interconnect-cells = <1>; 466668c7603SGeorgi Djakov clock-names = "bus", "bus_a"; 467668c7603SGeorgi Djakov clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 468668c7603SGeorgi Djakov <&rpmcc RPM_SMD_PNOC_A_CLK>; 469668c7603SGeorgi Djakov }; 470668c7603SGeorgi Djakov 471668c7603SGeorgi Djakov snoc: interconnect@580000 { 472668c7603SGeorgi Djakov reg = <0x00580000 0x23080>; 473668c7603SGeorgi Djakov compatible = "qcom,qcs404-snoc"; 474668c7603SGeorgi Djakov #interconnect-cells = <1>; 475668c7603SGeorgi Djakov clock-names = "bus", "bus_a"; 476668c7603SGeorgi Djakov clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 477668c7603SGeorgi Djakov <&rpmcc RPM_SMD_SNOC_A_CLK>; 478668c7603SGeorgi Djakov }; 479668c7603SGeorgi Djakov 480f4dd04a8SBjorn Andersson remoteproc_cdsp: remoteproc@b00000 { 481f4dd04a8SBjorn Andersson compatible = "qcom,qcs404-cdsp-pas"; 482f4dd04a8SBjorn Andersson reg = <0x00b00000 0x4040>; 483f4dd04a8SBjorn Andersson 484f4dd04a8SBjorn Andersson interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 485f4dd04a8SBjorn Andersson <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 486f4dd04a8SBjorn Andersson <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 487f4dd04a8SBjorn Andersson <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 488f4dd04a8SBjorn Andersson <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 489f4dd04a8SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 490f4dd04a8SBjorn Andersson "handover", "stop-ack"; 491f4dd04a8SBjorn Andersson 492f4dd04a8SBjorn Andersson clocks = <&xo_board>, 493f4dd04a8SBjorn Andersson <&gcc GCC_CDSP_CFG_AHB_CLK>, 494f4dd04a8SBjorn Andersson <&gcc GCC_CDSP_TBU_CLK>, 495f4dd04a8SBjorn Andersson <&gcc GCC_BIMC_CDSP_CLK>, 496f4dd04a8SBjorn Andersson <&turingcc TURING_WRAPPER_AON_CLK>, 497f4dd04a8SBjorn Andersson <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 498f4dd04a8SBjorn Andersson <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 499f4dd04a8SBjorn Andersson <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 500f4dd04a8SBjorn Andersson clock-names = "xo", 501f4dd04a8SBjorn Andersson "sway", 502f4dd04a8SBjorn Andersson "tbu", 503f4dd04a8SBjorn Andersson "bimc", 504f4dd04a8SBjorn Andersson "ahb_aon", 505f4dd04a8SBjorn Andersson "q6ss_slave", 506f4dd04a8SBjorn Andersson "q6ss_master", 507f4dd04a8SBjorn Andersson "q6_axim"; 508f4dd04a8SBjorn Andersson 509f4dd04a8SBjorn Andersson resets = <&gcc GCC_CDSP_RESTART>; 510f4dd04a8SBjorn Andersson reset-names = "restart"; 511f4dd04a8SBjorn Andersson 512f4dd04a8SBjorn Andersson qcom,halt-regs = <&tcsr 0x19004>; 513f4dd04a8SBjorn Andersson 514f4dd04a8SBjorn Andersson memory-region = <&cdsp_fw_mem>; 515f4dd04a8SBjorn Andersson 516f4dd04a8SBjorn Andersson qcom,smem-states = <&cdsp_smp2p_out 0>; 517f4dd04a8SBjorn Andersson qcom,smem-state-names = "stop"; 518f4dd04a8SBjorn Andersson 519f4dd04a8SBjorn Andersson status = "disabled"; 520f4dd04a8SBjorn Andersson 521f4dd04a8SBjorn Andersson glink-edge { 522f4dd04a8SBjorn Andersson interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 523f4dd04a8SBjorn Andersson 524f4dd04a8SBjorn Andersson qcom,remote-pid = <5>; 525f4dd04a8SBjorn Andersson mboxes = <&apcs_glb 12>; 526f4dd04a8SBjorn Andersson 527f4dd04a8SBjorn Andersson label = "cdsp"; 528f4dd04a8SBjorn Andersson }; 529f4dd04a8SBjorn Andersson }; 530f4dd04a8SBjorn Andersson 5319375e7d7SBjorn Andersson usb3: usb@7678800 { 5329375e7d7SBjorn Andersson compatible = "qcom,dwc3"; 5339375e7d7SBjorn Andersson reg = <0x07678800 0x400>; 5349375e7d7SBjorn Andersson #address-cells = <1>; 5359375e7d7SBjorn Andersson #size-cells = <1>; 5369375e7d7SBjorn Andersson ranges; 5379375e7d7SBjorn Andersson clocks = <&gcc GCC_USB30_MASTER_CLK>, 5389375e7d7SBjorn Andersson <&gcc GCC_SYS_NOC_USB3_CLK>, 5399375e7d7SBjorn Andersson <&gcc GCC_USB30_SLEEP_CLK>, 5409375e7d7SBjorn Andersson <&gcc GCC_USB30_MOCK_UTMI_CLK>; 5419375e7d7SBjorn Andersson clock-names = "core", "iface", "sleep", "mock_utmi"; 5429375e7d7SBjorn Andersson assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5439375e7d7SBjorn Andersson <&gcc GCC_USB30_MASTER_CLK>; 5449375e7d7SBjorn Andersson assigned-clock-rates = <19200000>, <200000000>; 5459375e7d7SBjorn Andersson status = "disabled"; 5469375e7d7SBjorn Andersson 5471f958f3dSGreg Kroah-Hartman dwc3@7580000 { 5489375e7d7SBjorn Andersson compatible = "snps,dwc3"; 5499375e7d7SBjorn Andersson reg = <0x07580000 0xcd00>; 5509375e7d7SBjorn Andersson interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 5519375e7d7SBjorn Andersson phys = <&usb2_phy_sec>, <&usb3_phy>; 5529375e7d7SBjorn Andersson phy-names = "usb2-phy", "usb3-phy"; 5539375e7d7SBjorn Andersson snps,has-lpm-erratum; 5549375e7d7SBjorn Andersson snps,hird-threshold = /bits/ 8 <0x10>; 5559375e7d7SBjorn Andersson snps,usb3_lpm_capable; 5569375e7d7SBjorn Andersson dr_mode = "otg"; 5579375e7d7SBjorn Andersson }; 5589375e7d7SBjorn Andersson }; 5599375e7d7SBjorn Andersson 5609375e7d7SBjorn Andersson usb2: usb@79b8800 { 5619375e7d7SBjorn Andersson compatible = "qcom,dwc3"; 5629375e7d7SBjorn Andersson reg = <0x079b8800 0x400>; 5639375e7d7SBjorn Andersson #address-cells = <1>; 5649375e7d7SBjorn Andersson #size-cells = <1>; 5659375e7d7SBjorn Andersson ranges; 5669375e7d7SBjorn Andersson clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, 5679375e7d7SBjorn Andersson <&gcc GCC_PCNOC_USB2_CLK>, 5689375e7d7SBjorn Andersson <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, 5699375e7d7SBjorn Andersson <&gcc GCC_USB20_MOCK_UTMI_CLK>; 5709375e7d7SBjorn Andersson clock-names = "core", "iface", "sleep", "mock_utmi"; 5719375e7d7SBjorn Andersson assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5729375e7d7SBjorn Andersson <&gcc GCC_USB_HS_SYSTEM_CLK>; 5739375e7d7SBjorn Andersson assigned-clock-rates = <19200000>, <133333333>; 5749375e7d7SBjorn Andersson status = "disabled"; 5759375e7d7SBjorn Andersson 5761f958f3dSGreg Kroah-Hartman dwc3@78c0000 { 5779375e7d7SBjorn Andersson compatible = "snps,dwc3"; 5789375e7d7SBjorn Andersson reg = <0x078c0000 0xcc00>; 5799375e7d7SBjorn Andersson interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 5809375e7d7SBjorn Andersson phys = <&usb2_phy_prim>; 5819375e7d7SBjorn Andersson phy-names = "usb2-phy"; 5829375e7d7SBjorn Andersson snps,has-lpm-erratum; 5839375e7d7SBjorn Andersson snps,hird-threshold = /bits/ 8 <0x10>; 5849375e7d7SBjorn Andersson snps,usb3_lpm_capable; 5859375e7d7SBjorn Andersson dr_mode = "peripheral"; 5869375e7d7SBjorn Andersson }; 5879375e7d7SBjorn Andersson }; 5889375e7d7SBjorn Andersson 58975f6e6d9SBjorn Andersson tlmm: pinctrl@1000000 { 59075f6e6d9SBjorn Andersson compatible = "qcom,qcs404-pinctrl"; 59175f6e6d9SBjorn Andersson reg = <0x01000000 0x200000>, 59275f6e6d9SBjorn Andersson <0x01300000 0x200000>, 59375f6e6d9SBjorn Andersson <0x07b00000 0x200000>; 59475f6e6d9SBjorn Andersson reg-names = "south", "north", "east"; 59575f6e6d9SBjorn Andersson interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 59675f6e6d9SBjorn Andersson gpio-ranges = <&tlmm 0 0 120>; 59775f6e6d9SBjorn Andersson gpio-controller; 59875f6e6d9SBjorn Andersson #gpio-cells = <2>; 59975f6e6d9SBjorn Andersson interrupt-controller; 60075f6e6d9SBjorn Andersson #interrupt-cells = <2>; 6015bb9ab94SBjorn Andersson 602734e6d02SBjorn Andersson blsp1_i2c0_default: blsp1-i2c0-default { 603734e6d02SBjorn Andersson pins = "gpio32", "gpio33"; 604734e6d02SBjorn Andersson function = "blsp_i2c0"; 605734e6d02SBjorn Andersson }; 606734e6d02SBjorn Andersson 607734e6d02SBjorn Andersson blsp1_i2c1_default: blsp1-i2c1-default { 608734e6d02SBjorn Andersson pins = "gpio24", "gpio25"; 609734e6d02SBjorn Andersson function = "blsp_i2c1"; 610734e6d02SBjorn Andersson }; 611734e6d02SBjorn Andersson 612734e6d02SBjorn Andersson blsp1_i2c2_default: blsp1-i2c2-default { 613734e6d02SBjorn Andersson sda { 614734e6d02SBjorn Andersson pins = "gpio19"; 615734e6d02SBjorn Andersson function = "blsp_i2c_sda_a2"; 616734e6d02SBjorn Andersson }; 617734e6d02SBjorn Andersson 618734e6d02SBjorn Andersson scl { 619734e6d02SBjorn Andersson pins = "gpio20"; 620734e6d02SBjorn Andersson function = "blsp_i2c_scl_a2"; 621734e6d02SBjorn Andersson }; 622734e6d02SBjorn Andersson }; 623734e6d02SBjorn Andersson 624734e6d02SBjorn Andersson blsp1_i2c3_default: blsp1-i2c3-default { 625734e6d02SBjorn Andersson pins = "gpio84", "gpio85"; 626734e6d02SBjorn Andersson function = "blsp_i2c3"; 627734e6d02SBjorn Andersson }; 628734e6d02SBjorn Andersson 629734e6d02SBjorn Andersson blsp1_i2c4_default: blsp1-i2c4-default { 630734e6d02SBjorn Andersson pins = "gpio117", "gpio118"; 631734e6d02SBjorn Andersson function = "blsp_i2c4"; 632734e6d02SBjorn Andersson }; 633734e6d02SBjorn Andersson 634bf9aa8a4SBjorn Andersson blsp1_uart0_default: blsp1-uart0-default { 635bf9aa8a4SBjorn Andersson pins = "gpio30", "gpio31", "gpio32", "gpio33"; 636bf9aa8a4SBjorn Andersson function = "blsp_uart0"; 637bf9aa8a4SBjorn Andersson }; 638bf9aa8a4SBjorn Andersson 639bf9aa8a4SBjorn Andersson blsp1_uart1_default: blsp1-uart1-default { 640bf9aa8a4SBjorn Andersson pins = "gpio22", "gpio23"; 641bf9aa8a4SBjorn Andersson function = "blsp_uart1"; 642bf9aa8a4SBjorn Andersson }; 643bf9aa8a4SBjorn Andersson 6445bb9ab94SBjorn Andersson blsp1_uart2_default: blsp1-uart2-default { 6455bb9ab94SBjorn Andersson rx { 6465bb9ab94SBjorn Andersson pins = "gpio18"; 6475bb9ab94SBjorn Andersson function = "blsp_uart_rx_a2"; 6485bb9ab94SBjorn Andersson }; 6495bb9ab94SBjorn Andersson 6505bb9ab94SBjorn Andersson tx { 6515bb9ab94SBjorn Andersson pins = "gpio17"; 6525bb9ab94SBjorn Andersson function = "blsp_uart_tx_a2"; 6535bb9ab94SBjorn Andersson }; 6545bb9ab94SBjorn Andersson }; 655bf9aa8a4SBjorn Andersson 656bf9aa8a4SBjorn Andersson blsp1_uart3_default: blsp1-uart3-default { 657bf9aa8a4SBjorn Andersson pins = "gpio82", "gpio83", "gpio84", "gpio85"; 658bf9aa8a4SBjorn Andersson function = "blsp_uart3"; 659bf9aa8a4SBjorn Andersson }; 660bf9aa8a4SBjorn Andersson 661734e6d02SBjorn Andersson blsp2_i2c0_default: blsp2-i2c0-default { 662734e6d02SBjorn Andersson pins = "gpio28", "gpio29"; 663734e6d02SBjorn Andersson function = "blsp_i2c5"; 664734e6d02SBjorn Andersson }; 665734e6d02SBjorn Andersson 666734e6d02SBjorn Andersson blsp1_spi0_default: blsp1-spi0-default { 667734e6d02SBjorn Andersson pins = "gpio30", "gpio31", "gpio32", "gpio33"; 668734e6d02SBjorn Andersson function = "blsp_spi0"; 669734e6d02SBjorn Andersson }; 670734e6d02SBjorn Andersson 671734e6d02SBjorn Andersson blsp1_spi1_default: blsp1-spi1-default { 672734e6d02SBjorn Andersson pins = "gpio22", "gpio23", "gpio24", "gpio25"; 673734e6d02SBjorn Andersson function = "blsp_spi1"; 674734e6d02SBjorn Andersson }; 675734e6d02SBjorn Andersson 676734e6d02SBjorn Andersson blsp1_spi2_default: blsp1-spi2-default { 677734e6d02SBjorn Andersson pins = "gpio17", "gpio18", "gpio19", "gpio20"; 678734e6d02SBjorn Andersson function = "blsp_spi2"; 679734e6d02SBjorn Andersson }; 680734e6d02SBjorn Andersson 681734e6d02SBjorn Andersson blsp1_spi3_default: blsp1-spi3-default { 682734e6d02SBjorn Andersson pins = "gpio82", "gpio83", "gpio84", "gpio85"; 683734e6d02SBjorn Andersson function = "blsp_spi3"; 684734e6d02SBjorn Andersson }; 685734e6d02SBjorn Andersson 686734e6d02SBjorn Andersson blsp1_spi4_default: blsp1-spi4-default { 687734e6d02SBjorn Andersson pins = "gpio37", "gpio38", "gpio117", "gpio118"; 688734e6d02SBjorn Andersson function = "blsp_spi4"; 689734e6d02SBjorn Andersson }; 690734e6d02SBjorn Andersson 691734e6d02SBjorn Andersson blsp2_spi0_default: blsp2-spi0-default { 692734e6d02SBjorn Andersson pins = "gpio26", "gpio27", "gpio28", "gpio29"; 693734e6d02SBjorn Andersson function = "blsp_spi5"; 694734e6d02SBjorn Andersson }; 695734e6d02SBjorn Andersson 696bf9aa8a4SBjorn Andersson blsp2_uart0_default: blsp2-uart0-default { 697bf9aa8a4SBjorn Andersson pins = "gpio26", "gpio27", "gpio28", "gpio29"; 698bf9aa8a4SBjorn Andersson function = "blsp_uart5"; 699bf9aa8a4SBjorn Andersson }; 70075f6e6d9SBjorn Andersson }; 70175f6e6d9SBjorn Andersson 702b4d82f4dSVinod Koul gcc: clock-controller@1800000 { 703b4d82f4dSVinod Koul compatible = "qcom,gcc-qcs404"; 704b4d82f4dSVinod Koul reg = <0x01800000 0x80000>; 705b4d82f4dSVinod Koul #clock-cells = <1>; 7064b2c7ea8SAndy Gross #reset-cells = <1>; 707b4d82f4dSVinod Koul 708b4d82f4dSVinod Koul assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 709b4d82f4dSVinod Koul assigned-clock-rates = <19200000>; 710b4d82f4dSVinod Koul }; 711b4d82f4dSVinod Koul 7127fc7089dSBjorn Andersson tcsr_mutex_regs: syscon@1905000 { 7137fc7089dSBjorn Andersson compatible = "syscon"; 7147fc7089dSBjorn Andersson reg = <0x01905000 0x20000>; 7157fc7089dSBjorn Andersson }; 7167fc7089dSBjorn Andersson 717560ad5e7SBjorn Andersson tcsr: syscon@1937000 { 718560ad5e7SBjorn Andersson compatible = "syscon"; 719560ad5e7SBjorn Andersson reg = <0x01937000 0x25000>; 720560ad5e7SBjorn Andersson }; 721560ad5e7SBjorn Andersson 722290bc684SMaulik Shah sram@290000 { 723290bc684SMaulik Shah compatible = "qcom,rpm-stats"; 724290bc684SMaulik Shah reg = <0x00290000 0x10000>; 725290bc684SMaulik Shah }; 726290bc684SMaulik Shah 7271a94b65bSVinod Koul spmi_bus: spmi@200f000 { 7281a94b65bSVinod Koul compatible = "qcom,spmi-pmic-arb"; 7291a94b65bSVinod Koul reg = <0x0200f000 0x001000>, 7301a94b65bSVinod Koul <0x02400000 0x800000>, 7311a94b65bSVinod Koul <0x02c00000 0x800000>, 7321a94b65bSVinod Koul <0x03800000 0x200000>, 7331a94b65bSVinod Koul <0x0200a000 0x002100>; 7341a94b65bSVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 7351a94b65bSVinod Koul interrupt-names = "periph_irq"; 7361a94b65bSVinod Koul interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 7371a94b65bSVinod Koul qcom,ee = <0>; 7381a94b65bSVinod Koul qcom,channel = <0>; 7391a94b65bSVinod Koul #address-cells = <2>; 7401a94b65bSVinod Koul #size-cells = <0>; 7411a94b65bSVinod Koul interrupt-controller; 7421a94b65bSVinod Koul #interrupt-cells = <4>; 7431a94b65bSVinod Koul }; 7441a94b65bSVinod Koul 74567779ca2SBjorn Andersson remoteproc_wcss: remoteproc@7400000 { 74667779ca2SBjorn Andersson compatible = "qcom,qcs404-wcss-pas"; 74767779ca2SBjorn Andersson reg = <0x07400000 0x4040>; 74867779ca2SBjorn Andersson 74967779ca2SBjorn Andersson interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 75067779ca2SBjorn Andersson <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 75167779ca2SBjorn Andersson <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 75267779ca2SBjorn Andersson <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 75367779ca2SBjorn Andersson <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 75467779ca2SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 75567779ca2SBjorn Andersson "handover", "stop-ack"; 75667779ca2SBjorn Andersson 75767779ca2SBjorn Andersson clocks = <&xo_board>; 75867779ca2SBjorn Andersson clock-names = "xo"; 75967779ca2SBjorn Andersson 76067779ca2SBjorn Andersson memory-region = <&wlan_fw_mem>; 76167779ca2SBjorn Andersson 76267779ca2SBjorn Andersson qcom,smem-states = <&wcss_smp2p_out 0>; 76367779ca2SBjorn Andersson qcom,smem-state-names = "stop"; 76467779ca2SBjorn Andersson 76567779ca2SBjorn Andersson status = "disabled"; 76667779ca2SBjorn Andersson 76767779ca2SBjorn Andersson glink-edge { 76867779ca2SBjorn Andersson interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 76967779ca2SBjorn Andersson 77067779ca2SBjorn Andersson qcom,remote-pid = <1>; 77167779ca2SBjorn Andersson mboxes = <&apcs_glb 16>; 77267779ca2SBjorn Andersson 77367779ca2SBjorn Andersson label = "wcss"; 77467779ca2SBjorn Andersson }; 77567779ca2SBjorn Andersson }; 77667779ca2SBjorn Andersson 777431f6464SBjorn Andersson pcie_phy: phy@7786000 { 778431f6464SBjorn Andersson compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 779431f6464SBjorn Andersson reg = <0x07786000 0xb8>; 780431f6464SBjorn Andersson 781431f6464SBjorn Andersson clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 782431f6464SBjorn Andersson resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 783431f6464SBjorn Andersson <&gcc 21>; 784431f6464SBjorn Andersson reset-names = "phy", "pipe"; 785431f6464SBjorn Andersson 786431f6464SBjorn Andersson clock-output-names = "pcie_0_pipe_clk"; 787431f6464SBjorn Andersson #phy-cells = <0>; 788431f6464SBjorn Andersson 789431f6464SBjorn Andersson status = "disabled"; 790431f6464SBjorn Andersson }; 791431f6464SBjorn Andersson 7927241ab94SBjorn Andersson sdcc1: sdcc@7804000 { 793f8c84813SDouglas Anderson compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 7947241ab94SBjorn Andersson reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 795557a2abaSVeerabhadrarao Badiganti reg-names = "hc", "cqhci"; 7967241ab94SBjorn Andersson 7977241ab94SBjorn Andersson interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 7987241ab94SBjorn Andersson <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 7997241ab94SBjorn Andersson interrupt-names = "hc_irq", "pwr_irq"; 8007241ab94SBjorn Andersson 8017241ab94SBjorn Andersson clocks = <&gcc GCC_SDCC1_APPS_CLK>, 8027241ab94SBjorn Andersson <&gcc GCC_SDCC1_AHB_CLK>, 8037241ab94SBjorn Andersson <&xo_board>; 8047241ab94SBjorn Andersson clock-names = "core", "iface", "xo"; 8057241ab94SBjorn Andersson 8067241ab94SBjorn Andersson status = "disabled"; 8077241ab94SBjorn Andersson }; 8087241ab94SBjorn Andersson 8096bd61ef4SVinod Koul blsp1_dma: dma-controller@7884000 { 810e77c5206SVinod Koul compatible = "qcom,bam-v1.7.0"; 811e77c5206SVinod Koul reg = <0x07884000 0x25000>; 812e77c5206SVinod Koul interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 813e77c5206SVinod Koul clocks = <&gcc GCC_BLSP1_AHB_CLK>; 814e77c5206SVinod Koul clock-names = "bam_clk"; 815e77c5206SVinod Koul #dma-cells = <1>; 816e77c5206SVinod Koul qcom,ee = <0>; 817e77c5206SVinod Koul status = "okay"; 818e77c5206SVinod Koul }; 819e77c5206SVinod Koul 820bf9aa8a4SBjorn Andersson blsp1_uart0: serial@78af000 { 821bf9aa8a4SBjorn Andersson compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 822bf9aa8a4SBjorn Andersson reg = <0x078af000 0x200>; 823bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 824bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 825bf9aa8a4SBjorn Andersson clock-names = "core", "iface"; 826*0e1b27f4SKrzysztof Kozlowski dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 827*0e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 828bf9aa8a4SBjorn Andersson pinctrl-names = "default"; 829bf9aa8a4SBjorn Andersson pinctrl-0 = <&blsp1_uart0_default>; 830bf9aa8a4SBjorn Andersson status = "disabled"; 831bf9aa8a4SBjorn Andersson }; 832bf9aa8a4SBjorn Andersson 833bf9aa8a4SBjorn Andersson blsp1_uart1: serial@78b0000 { 834bf9aa8a4SBjorn Andersson compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 835bf9aa8a4SBjorn Andersson reg = <0x078b0000 0x200>; 836bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 837bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 838bf9aa8a4SBjorn Andersson clock-names = "core", "iface"; 839*0e1b27f4SKrzysztof Kozlowski dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 840*0e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 841bf9aa8a4SBjorn Andersson pinctrl-names = "default"; 842bf9aa8a4SBjorn Andersson pinctrl-0 = <&blsp1_uart1_default>; 843bf9aa8a4SBjorn Andersson status = "disabled"; 844bf9aa8a4SBjorn Andersson }; 845bf9aa8a4SBjorn Andersson 846b4d82f4dSVinod Koul blsp1_uart2: serial@78b1000 { 847b4d82f4dSVinod Koul compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 848b4d82f4dSVinod Koul reg = <0x078b1000 0x200>; 849b4d82f4dSVinod Koul interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 850b4d82f4dSVinod Koul clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 851b4d82f4dSVinod Koul clock-names = "core", "iface"; 852*0e1b27f4SKrzysztof Kozlowski dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 853*0e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 8545bb9ab94SBjorn Andersson pinctrl-names = "default"; 8555bb9ab94SBjorn Andersson pinctrl-0 = <&blsp1_uart2_default>; 856b4d82f4dSVinod Koul status = "okay"; 857b4d82f4dSVinod Koul }; 858b4d82f4dSVinod Koul 8594dfa70eaSVinod Koul ethernet: ethernet@7a80000 { 8604dfa70eaSVinod Koul compatible = "qcom,qcs404-ethqos"; 8614dfa70eaSVinod Koul reg = <0x07a80000 0x10000>, 8624dfa70eaSVinod Koul <0x07a96000 0x100>; 8634dfa70eaSVinod Koul reg-names = "stmmaceth", "rgmii"; 8644dfa70eaSVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 8654dfa70eaSVinod Koul clocks = <&gcc GCC_ETH_AXI_CLK>, 8664dfa70eaSVinod Koul <&gcc GCC_ETH_SLAVE_AHB_CLK>, 8674dfa70eaSVinod Koul <&gcc GCC_ETH_PTP_CLK>, 8684dfa70eaSVinod Koul <&gcc GCC_ETH_RGMII_CLK>; 8694dfa70eaSVinod Koul interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 8704dfa70eaSVinod Koul <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 8714dfa70eaSVinod Koul interrupt-names = "macirq", "eth_lpi"; 8724dfa70eaSVinod Koul 8734dfa70eaSVinod Koul snps,tso; 8744dfa70eaSVinod Koul rx-fifo-depth = <4096>; 8754dfa70eaSVinod Koul tx-fifo-depth = <4096>; 8764dfa70eaSVinod Koul 8774dfa70eaSVinod Koul status = "disabled"; 8784dfa70eaSVinod Koul }; 8794dfa70eaSVinod Koul 8804bbbca1eSGovind Singh wifi: wifi@a000000 { 8814bbbca1eSGovind Singh compatible = "qcom,wcn3990-wifi"; 8824bbbca1eSGovind Singh reg = <0xa000000 0x800000>; 8834bbbca1eSGovind Singh reg-names = "membase"; 8844bbbca1eSGovind Singh memory-region = <&wlan_msa_mem>; 8854bbbca1eSGovind Singh interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 8864bbbca1eSGovind Singh <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 8874bbbca1eSGovind Singh <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 8884bbbca1eSGovind Singh <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 8894bbbca1eSGovind Singh <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 8904bbbca1eSGovind Singh <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 8914bbbca1eSGovind Singh <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 8924bbbca1eSGovind Singh <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 8934bbbca1eSGovind Singh <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 8944bbbca1eSGovind Singh <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 8954bbbca1eSGovind Singh <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 8964bbbca1eSGovind Singh <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 8974bbbca1eSGovind Singh status = "disabled"; 8984bbbca1eSGovind Singh }; 8994bbbca1eSGovind Singh 900bf9aa8a4SBjorn Andersson blsp1_uart3: serial@78b2000 { 901bf9aa8a4SBjorn Andersson compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 902bf9aa8a4SBjorn Andersson reg = <0x078b2000 0x200>; 903bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 904bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 905bf9aa8a4SBjorn Andersson clock-names = "core", "iface"; 906*0e1b27f4SKrzysztof Kozlowski dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 907*0e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 908bf9aa8a4SBjorn Andersson pinctrl-names = "default"; 909bf9aa8a4SBjorn Andersson pinctrl-0 = <&blsp1_uart3_default>; 910bf9aa8a4SBjorn Andersson status = "disabled"; 911bf9aa8a4SBjorn Andersson }; 912bf9aa8a4SBjorn Andersson 913734e6d02SBjorn Andersson blsp1_i2c0: i2c@78b5000 { 914734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 915734e6d02SBjorn Andersson reg = <0x078b5000 0x600>; 916734e6d02SBjorn Andersson interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 917734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 918734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; 919734e6d02SBjorn Andersson clock-names = "iface", "core"; 920734e6d02SBjorn Andersson pinctrl-names = "default"; 921734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c0_default>; 922734e6d02SBjorn Andersson #address-cells = <1>; 923734e6d02SBjorn Andersson #size-cells = <0>; 924734e6d02SBjorn Andersson status = "disabled"; 925734e6d02SBjorn Andersson }; 926734e6d02SBjorn Andersson 927734e6d02SBjorn Andersson blsp1_spi0: spi@78b5000 { 928734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 929734e6d02SBjorn Andersson reg = <0x078b5000 0x600>; 930734e6d02SBjorn Andersson interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 931734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 932734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; 933734e6d02SBjorn Andersson clock-names = "iface", "core"; 934734e6d02SBjorn Andersson pinctrl-names = "default"; 935734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi0_default>; 936734e6d02SBjorn Andersson #address-cells = <1>; 937734e6d02SBjorn Andersson #size-cells = <0>; 938734e6d02SBjorn Andersson status = "disabled"; 939734e6d02SBjorn Andersson }; 940734e6d02SBjorn Andersson 941734e6d02SBjorn Andersson blsp1_i2c1: i2c@78b6000 { 942734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 943734e6d02SBjorn Andersson reg = <0x078b6000 0x600>; 944734e6d02SBjorn Andersson interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 945734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 946734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 947734e6d02SBjorn Andersson clock-names = "iface", "core"; 948734e6d02SBjorn Andersson pinctrl-names = "default"; 949734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c1_default>; 950734e6d02SBjorn Andersson #address-cells = <1>; 951734e6d02SBjorn Andersson #size-cells = <0>; 952734e6d02SBjorn Andersson status = "disabled"; 953734e6d02SBjorn Andersson }; 954734e6d02SBjorn Andersson 955734e6d02SBjorn Andersson blsp1_spi1: spi@78b6000 { 956734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 957734e6d02SBjorn Andersson reg = <0x078b6000 0x600>; 958734e6d02SBjorn Andersson interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 959734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 960734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; 961734e6d02SBjorn Andersson clock-names = "iface", "core"; 962734e6d02SBjorn Andersson pinctrl-names = "default"; 963734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi1_default>; 964734e6d02SBjorn Andersson #address-cells = <1>; 965734e6d02SBjorn Andersson #size-cells = <0>; 966734e6d02SBjorn Andersson status = "disabled"; 967734e6d02SBjorn Andersson }; 968734e6d02SBjorn Andersson 969734e6d02SBjorn Andersson blsp1_i2c2: i2c@78b7000 { 970734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 971734e6d02SBjorn Andersson reg = <0x078b7000 0x600>; 972734e6d02SBjorn Andersson interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 973734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 974734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 975734e6d02SBjorn Andersson clock-names = "iface", "core"; 976734e6d02SBjorn Andersson pinctrl-names = "default"; 977734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c2_default>; 978734e6d02SBjorn Andersson #address-cells = <1>; 979734e6d02SBjorn Andersson #size-cells = <0>; 980734e6d02SBjorn Andersson status = "disabled"; 981734e6d02SBjorn Andersson }; 982734e6d02SBjorn Andersson 983734e6d02SBjorn Andersson blsp1_spi2: spi@78b7000 { 984734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 985734e6d02SBjorn Andersson reg = <0x078b7000 0x600>; 986734e6d02SBjorn Andersson interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 987734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 988734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; 989734e6d02SBjorn Andersson clock-names = "iface", "core"; 990734e6d02SBjorn Andersson pinctrl-names = "default"; 991734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi2_default>; 992734e6d02SBjorn Andersson #address-cells = <1>; 993734e6d02SBjorn Andersson #size-cells = <0>; 994734e6d02SBjorn Andersson status = "disabled"; 995734e6d02SBjorn Andersson }; 996734e6d02SBjorn Andersson 997734e6d02SBjorn Andersson blsp1_i2c3: i2c@78b8000 { 998734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 999734e6d02SBjorn Andersson reg = <0x078b8000 0x600>; 1000734e6d02SBjorn Andersson interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1001734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1002734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 1003734e6d02SBjorn Andersson clock-names = "iface", "core"; 1004734e6d02SBjorn Andersson pinctrl-names = "default"; 1005734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c3_default>; 1006734e6d02SBjorn Andersson #address-cells = <1>; 1007734e6d02SBjorn Andersson #size-cells = <0>; 1008734e6d02SBjorn Andersson status = "disabled"; 1009734e6d02SBjorn Andersson }; 1010734e6d02SBjorn Andersson 1011734e6d02SBjorn Andersson blsp1_spi3: spi@78b8000 { 1012734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 1013734e6d02SBjorn Andersson reg = <0x078b8000 0x600>; 1014734e6d02SBjorn Andersson interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1015734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1016734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; 1017734e6d02SBjorn Andersson clock-names = "iface", "core"; 1018734e6d02SBjorn Andersson pinctrl-names = "default"; 1019734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi3_default>; 1020734e6d02SBjorn Andersson #address-cells = <1>; 1021734e6d02SBjorn Andersson #size-cells = <0>; 1022734e6d02SBjorn Andersson status = "disabled"; 1023734e6d02SBjorn Andersson }; 1024734e6d02SBjorn Andersson 1025734e6d02SBjorn Andersson blsp1_i2c4: i2c@78b9000 { 1026734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 1027734e6d02SBjorn Andersson reg = <0x078b9000 0x600>; 1028734e6d02SBjorn Andersson interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1029734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1030734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 1031734e6d02SBjorn Andersson clock-names = "iface", "core"; 1032734e6d02SBjorn Andersson pinctrl-names = "default"; 1033734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_i2c4_default>; 1034734e6d02SBjorn Andersson #address-cells = <1>; 1035734e6d02SBjorn Andersson #size-cells = <0>; 1036734e6d02SBjorn Andersson status = "disabled"; 1037734e6d02SBjorn Andersson }; 1038734e6d02SBjorn Andersson 1039734e6d02SBjorn Andersson blsp1_spi4: spi@78b9000 { 1040734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 1041734e6d02SBjorn Andersson reg = <0x078b9000 0x600>; 1042734e6d02SBjorn Andersson interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1043734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1044734e6d02SBjorn Andersson <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; 1045734e6d02SBjorn Andersson clock-names = "iface", "core"; 1046734e6d02SBjorn Andersson pinctrl-names = "default"; 1047734e6d02SBjorn Andersson pinctrl-0 = <&blsp1_spi4_default>; 1048734e6d02SBjorn Andersson #address-cells = <1>; 1049734e6d02SBjorn Andersson #size-cells = <0>; 1050734e6d02SBjorn Andersson status = "disabled"; 1051734e6d02SBjorn Andersson }; 1052734e6d02SBjorn Andersson 10536bd61ef4SVinod Koul blsp2_dma: dma-controller@7ac4000 { 1054bf9aa8a4SBjorn Andersson compatible = "qcom,bam-v1.7.0"; 1055bf9aa8a4SBjorn Andersson reg = <0x07ac4000 0x17000>; 1056bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1057bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1058bf9aa8a4SBjorn Andersson clock-names = "bam_clk"; 1059bf9aa8a4SBjorn Andersson #dma-cells = <1>; 1060bf9aa8a4SBjorn Andersson qcom,ee = <0>; 1061bf9aa8a4SBjorn Andersson status = "disabled"; 1062bf9aa8a4SBjorn Andersson }; 1063bf9aa8a4SBjorn Andersson 1064bf9aa8a4SBjorn Andersson blsp2_uart0: serial@7aef000 { 1065bf9aa8a4SBjorn Andersson compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1066bf9aa8a4SBjorn Andersson reg = <0x07aef000 0x200>; 1067bf9aa8a4SBjorn Andersson interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1068bf9aa8a4SBjorn Andersson clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1069bf9aa8a4SBjorn Andersson clock-names = "core", "iface"; 1070*0e1b27f4SKrzysztof Kozlowski dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1071*0e1b27f4SKrzysztof Kozlowski dma-names = "tx", "rx"; 1072bf9aa8a4SBjorn Andersson pinctrl-names = "default"; 1073bf9aa8a4SBjorn Andersson pinctrl-0 = <&blsp2_uart0_default>; 1074bf9aa8a4SBjorn Andersson status = "disabled"; 1075bf9aa8a4SBjorn Andersson }; 1076bf9aa8a4SBjorn Andersson 1077734e6d02SBjorn Andersson blsp2_i2c0: i2c@7af5000 { 1078734e6d02SBjorn Andersson compatible = "qcom,i2c-qup-v2.2.1"; 1079734e6d02SBjorn Andersson reg = <0x07af5000 0x600>; 1080734e6d02SBjorn Andersson interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1081734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1082734e6d02SBjorn Andersson <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; 1083734e6d02SBjorn Andersson clock-names = "iface", "core"; 1084734e6d02SBjorn Andersson pinctrl-names = "default"; 1085734e6d02SBjorn Andersson pinctrl-0 = <&blsp2_i2c0_default>; 1086734e6d02SBjorn Andersson #address-cells = <1>; 1087734e6d02SBjorn Andersson #size-cells = <0>; 1088734e6d02SBjorn Andersson status = "disabled"; 1089734e6d02SBjorn Andersson }; 1090734e6d02SBjorn Andersson 1091734e6d02SBjorn Andersson blsp2_spi0: spi@7af5000 { 1092734e6d02SBjorn Andersson compatible = "qcom,spi-qup-v2.2.1"; 1093734e6d02SBjorn Andersson reg = <0x07af5000 0x600>; 1094734e6d02SBjorn Andersson interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1095734e6d02SBjorn Andersson clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1096734e6d02SBjorn Andersson <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; 1097734e6d02SBjorn Andersson clock-names = "iface", "core"; 1098734e6d02SBjorn Andersson pinctrl-names = "default"; 1099734e6d02SBjorn Andersson pinctrl-0 = <&blsp2_spi0_default>; 1100734e6d02SBjorn Andersson #address-cells = <1>; 1101734e6d02SBjorn Andersson #size-cells = <0>; 1102734e6d02SBjorn Andersson status = "disabled"; 1103734e6d02SBjorn Andersson }; 1104734e6d02SBjorn Andersson 1105809cc579SBjorn Andersson imem@8600000 { 1106809cc579SBjorn Andersson compatible = "simple-mfd"; 1107809cc579SBjorn Andersson reg = <0x08600000 0x1000>; 1108809cc579SBjorn Andersson 1109809cc579SBjorn Andersson #address-cells = <1>; 1110809cc579SBjorn Andersson #size-cells = <1>; 1111809cc579SBjorn Andersson 1112809cc579SBjorn Andersson ranges = <0 0x08600000 0x1000>; 1113809cc579SBjorn Andersson 1114809cc579SBjorn Andersson pil-reloc@94c { 1115809cc579SBjorn Andersson compatible = "qcom,pil-reloc-info"; 1116809cc579SBjorn Andersson reg = <0x94c 0xc8>; 1117809cc579SBjorn Andersson }; 1118809cc579SBjorn Andersson }; 1119809cc579SBjorn Andersson 1120b4d82f4dSVinod Koul intc: interrupt-controller@b000000 { 1121b4d82f4dSVinod Koul compatible = "qcom,msm-qgic2"; 1122b4d82f4dSVinod Koul interrupt-controller; 1123b4d82f4dSVinod Koul #interrupt-cells = <3>; 1124b4d82f4dSVinod Koul reg = <0x0b000000 0x1000>, 1125b4d82f4dSVinod Koul <0x0b002000 0x1000>; 1126b4d82f4dSVinod Koul }; 1127b4d82f4dSVinod Koul 11287fc7089dSBjorn Andersson apcs_glb: mailbox@b011000 { 11297fc7089dSBjorn Andersson compatible = "qcom,qcs404-apcs-apps-global", "syscon"; 11307fc7089dSBjorn Andersson reg = <0x0b011000 0x1000>; 11317fc7089dSBjorn Andersson #mbox-cells = <1>; 113201163a20SJorge Ramirez-Ortiz clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 113301163a20SJorge Ramirez-Ortiz clock-names = "pll", "aux"; 113401163a20SJorge Ramirez-Ortiz #clock-cells = <0>; 11357fc7089dSBjorn Andersson }; 11367fc7089dSBjorn Andersson 113740b3d940SJorge Ramirez-Ortiz apcs_hfpll: clock-controller@b016000 { 113840b3d940SJorge Ramirez-Ortiz compatible = "qcom,hfpll"; 113940b3d940SJorge Ramirez-Ortiz reg = <0x0b016000 0x30>; 114040b3d940SJorge Ramirez-Ortiz #clock-cells = <0>; 114140b3d940SJorge Ramirez-Ortiz clock-output-names = "apcs_hfpll"; 114240b3d940SJorge Ramirez-Ortiz clocks = <&xo_board>; 114340b3d940SJorge Ramirez-Ortiz clock-names = "xo"; 114440b3d940SJorge Ramirez-Ortiz }; 114540b3d940SJorge Ramirez-Ortiz 11468a250aa6SJorge Ramirez-Ortiz watchdog@b017000 { 11479692d9ffSSai Prakash Ranjan compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 11488a250aa6SJorge Ramirez-Ortiz reg = <0x0b017000 0x1000>; 11498a250aa6SJorge Ramirez-Ortiz clocks = <&sleep_clk>; 11508a250aa6SJorge Ramirez-Ortiz }; 11518a250aa6SJorge Ramirez-Ortiz 115204aadcaaSNiklas Cassel cpr: power-controller@b018000 { 115304aadcaaSNiklas Cassel compatible = "qcom,qcs404-cpr", "qcom,cpr"; 115404aadcaaSNiklas Cassel reg = <0x0b018000 0x1000>; 115504aadcaaSNiklas Cassel interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 115604aadcaaSNiklas Cassel clocks = <&xo_board>; 115704aadcaaSNiklas Cassel clock-names = "ref"; 115804aadcaaSNiklas Cassel vdd-apc-supply = <&pms405_s3>; 115904aadcaaSNiklas Cassel #power-domain-cells = <0>; 116004aadcaaSNiklas Cassel operating-points-v2 = <&cpr_opp_table>; 116104aadcaaSNiklas Cassel acc-syscon = <&tcsr>; 116204aadcaaSNiklas Cassel 116304aadcaaSNiklas Cassel nvmem-cells = <&cpr_efuse_quot_offset1>, 116404aadcaaSNiklas Cassel <&cpr_efuse_quot_offset2>, 116504aadcaaSNiklas Cassel <&cpr_efuse_quot_offset3>, 116604aadcaaSNiklas Cassel <&cpr_efuse_init_voltage1>, 116704aadcaaSNiklas Cassel <&cpr_efuse_init_voltage2>, 116804aadcaaSNiklas Cassel <&cpr_efuse_init_voltage3>, 116904aadcaaSNiklas Cassel <&cpr_efuse_quot1>, 117004aadcaaSNiklas Cassel <&cpr_efuse_quot2>, 117104aadcaaSNiklas Cassel <&cpr_efuse_quot3>, 117204aadcaaSNiklas Cassel <&cpr_efuse_ring1>, 117304aadcaaSNiklas Cassel <&cpr_efuse_ring2>, 117404aadcaaSNiklas Cassel <&cpr_efuse_ring3>, 117504aadcaaSNiklas Cassel <&cpr_efuse_revision>; 117604aadcaaSNiklas Cassel nvmem-cell-names = "cpr_quotient_offset1", 117704aadcaaSNiklas Cassel "cpr_quotient_offset2", 117804aadcaaSNiklas Cassel "cpr_quotient_offset3", 117904aadcaaSNiklas Cassel "cpr_init_voltage1", 118004aadcaaSNiklas Cassel "cpr_init_voltage2", 118104aadcaaSNiklas Cassel "cpr_init_voltage3", 118204aadcaaSNiklas Cassel "cpr_quotient1", 118304aadcaaSNiklas Cassel "cpr_quotient2", 118404aadcaaSNiklas Cassel "cpr_quotient3", 118504aadcaaSNiklas Cassel "cpr_ring_osc1", 118604aadcaaSNiklas Cassel "cpr_ring_osc2", 118704aadcaaSNiklas Cassel "cpr_ring_osc3", 118804aadcaaSNiklas Cassel "cpr_fuse_revision"; 118904aadcaaSNiklas Cassel }; 119004aadcaaSNiklas Cassel 1191b4d82f4dSVinod Koul timer@b120000 { 1192b4d82f4dSVinod Koul #address-cells = <1>; 1193b4d82f4dSVinod Koul #size-cells = <1>; 1194b4d82f4dSVinod Koul ranges; 1195b4d82f4dSVinod Koul compatible = "arm,armv7-timer-mem"; 1196b4d82f4dSVinod Koul reg = <0x0b120000 0x1000>; 1197b4d82f4dSVinod Koul clock-frequency = <19200000>; 1198b4d82f4dSVinod Koul 1199b4d82f4dSVinod Koul frame@b121000 { 1200b4d82f4dSVinod Koul frame-number = <0>; 1201b4d82f4dSVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1202b4d82f4dSVinod Koul <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1203b4d82f4dSVinod Koul reg = <0x0b121000 0x1000>, 1204b4d82f4dSVinod Koul <0x0b122000 0x1000>; 1205b4d82f4dSVinod Koul }; 1206b4d82f4dSVinod Koul 1207b4d82f4dSVinod Koul frame@b123000 { 1208b4d82f4dSVinod Koul frame-number = <1>; 1209b4d82f4dSVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1210b4d82f4dSVinod Koul reg = <0x0b123000 0x1000>; 1211b4d82f4dSVinod Koul status = "disabled"; 1212b4d82f4dSVinod Koul }; 1213b4d82f4dSVinod Koul 1214b4d82f4dSVinod Koul frame@b124000 { 1215b4d82f4dSVinod Koul frame-number = <2>; 1216b4d82f4dSVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1217b4d82f4dSVinod Koul reg = <0x0b124000 0x1000>; 1218b4d82f4dSVinod Koul status = "disabled"; 1219b4d82f4dSVinod Koul }; 1220b4d82f4dSVinod Koul 1221b4d82f4dSVinod Koul frame@b125000 { 1222b4d82f4dSVinod Koul frame-number = <3>; 1223b4d82f4dSVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1224b4d82f4dSVinod Koul reg = <0x0b125000 0x1000>; 1225b4d82f4dSVinod Koul status = "disabled"; 1226b4d82f4dSVinod Koul }; 1227b4d82f4dSVinod Koul 1228b4d82f4dSVinod Koul frame@b126000 { 1229b4d82f4dSVinod Koul frame-number = <4>; 1230b4d82f4dSVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1231b4d82f4dSVinod Koul reg = <0x0b126000 0x1000>; 1232b4d82f4dSVinod Koul status = "disabled"; 1233b4d82f4dSVinod Koul }; 1234b4d82f4dSVinod Koul 1235b4d82f4dSVinod Koul frame@b127000 { 1236b4d82f4dSVinod Koul frame-number = <5>; 1237b4d82f4dSVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1238b4d82f4dSVinod Koul reg = <0xb127000 0x1000>; 1239b4d82f4dSVinod Koul status = "disabled"; 1240b4d82f4dSVinod Koul }; 1241b4d82f4dSVinod Koul 1242b4d82f4dSVinod Koul frame@b128000 { 1243b4d82f4dSVinod Koul frame-number = <6>; 1244b4d82f4dSVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1245b4d82f4dSVinod Koul reg = <0x0b128000 0x1000>; 1246b4d82f4dSVinod Koul status = "disabled"; 1247b4d82f4dSVinod Koul }; 1248b4d82f4dSVinod Koul }; 124967779ca2SBjorn Andersson 125067779ca2SBjorn Andersson remoteproc_adsp: remoteproc@c700000 { 125167779ca2SBjorn Andersson compatible = "qcom,qcs404-adsp-pas"; 125267779ca2SBjorn Andersson reg = <0x0c700000 0x4040>; 125367779ca2SBjorn Andersson 125467779ca2SBjorn Andersson interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 125567779ca2SBjorn Andersson <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 125667779ca2SBjorn Andersson <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 125767779ca2SBjorn Andersson <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 125867779ca2SBjorn Andersson <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 125967779ca2SBjorn Andersson interrupt-names = "wdog", "fatal", "ready", 126067779ca2SBjorn Andersson "handover", "stop-ack"; 126167779ca2SBjorn Andersson 126267779ca2SBjorn Andersson clocks = <&xo_board>; 126367779ca2SBjorn Andersson clock-names = "xo"; 126467779ca2SBjorn Andersson 126567779ca2SBjorn Andersson memory-region = <&adsp_fw_mem>; 126667779ca2SBjorn Andersson 126767779ca2SBjorn Andersson qcom,smem-states = <&adsp_smp2p_out 0>; 126867779ca2SBjorn Andersson qcom,smem-state-names = "stop"; 126967779ca2SBjorn Andersson 127067779ca2SBjorn Andersson status = "disabled"; 127167779ca2SBjorn Andersson 127267779ca2SBjorn Andersson glink-edge { 127367779ca2SBjorn Andersson interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 127467779ca2SBjorn Andersson 127567779ca2SBjorn Andersson qcom,remote-pid = <2>; 127667779ca2SBjorn Andersson mboxes = <&apcs_glb 8>; 127767779ca2SBjorn Andersson 127867779ca2SBjorn Andersson label = "adsp"; 127967779ca2SBjorn Andersson }; 128067779ca2SBjorn Andersson }; 1281431f6464SBjorn Andersson 1282431f6464SBjorn Andersson pcie: pci@10000000 { 1283431f6464SBjorn Andersson compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; 1284431f6464SBjorn Andersson reg = <0x10000000 0xf1d>, 1285431f6464SBjorn Andersson <0x10000f20 0xa8>, 1286431f6464SBjorn Andersson <0x07780000 0x2000>, 1287431f6464SBjorn Andersson <0x10001000 0x2000>; 1288431f6464SBjorn Andersson reg-names = "dbi", "elbi", "parf", "config"; 1289431f6464SBjorn Andersson device_type = "pci"; 1290431f6464SBjorn Andersson linux,pci-domain = <0>; 1291431f6464SBjorn Andersson bus-range = <0x00 0xff>; 1292431f6464SBjorn Andersson num-lanes = <1>; 1293431f6464SBjorn Andersson #address-cells = <3>; 1294431f6464SBjorn Andersson #size-cells = <2>; 1295431f6464SBjorn Andersson 1296431f6464SBjorn Andersson ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ 1297431f6464SBjorn Andersson <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ 1298431f6464SBjorn Andersson 1299431f6464SBjorn Andersson interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1300431f6464SBjorn Andersson interrupt-names = "msi"; 1301431f6464SBjorn Andersson #interrupt-cells = <1>; 1302431f6464SBjorn Andersson interrupt-map-mask = <0 0 0 0x7>; 1303431f6464SBjorn Andersson interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1304431f6464SBjorn Andersson <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1305431f6464SBjorn Andersson <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1306431f6464SBjorn Andersson <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1307431f6464SBjorn Andersson clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1308431f6464SBjorn Andersson <&gcc GCC_PCIE_0_AUX_CLK>, 1309431f6464SBjorn Andersson <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1310431f6464SBjorn Andersson <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1311431f6464SBjorn Andersson clock-names = "iface", "aux", "master_bus", "slave_bus"; 1312431f6464SBjorn Andersson 1313431f6464SBjorn Andersson resets = <&gcc 18>, 1314431f6464SBjorn Andersson <&gcc 17>, 1315431f6464SBjorn Andersson <&gcc 15>, 1316431f6464SBjorn Andersson <&gcc 19>, 1317431f6464SBjorn Andersson <&gcc GCC_PCIE_0_BCR>, 1318431f6464SBjorn Andersson <&gcc 16>; 1319431f6464SBjorn Andersson reset-names = "axi_m", 1320431f6464SBjorn Andersson "axi_s", 1321431f6464SBjorn Andersson "axi_m_sticky", 1322431f6464SBjorn Andersson "pipe_sticky", 1323431f6464SBjorn Andersson "pwr", 1324431f6464SBjorn Andersson "ahb"; 1325431f6464SBjorn Andersson 1326431f6464SBjorn Andersson phys = <&pcie_phy>; 1327431f6464SBjorn Andersson phy-names = "pciephy"; 1328431f6464SBjorn Andersson 1329431f6464SBjorn Andersson status = "disabled"; 1330431f6464SBjorn Andersson }; 1331b4d82f4dSVinod Koul }; 1332b4d82f4dSVinod Koul 1333b4d82f4dSVinod Koul timer { 1334b4d82f4dSVinod Koul compatible = "arm,armv8-timer"; 1335b4d82f4dSVinod Koul interrupts = <GIC_PPI 2 0xff08>, 1336b4d82f4dSVinod Koul <GIC_PPI 3 0xff08>, 1337b4d82f4dSVinod Koul <GIC_PPI 4 0xff08>, 1338b4d82f4dSVinod Koul <GIC_PPI 1 0xff08>; 1339b4d82f4dSVinod Koul }; 1340afdfb0b3SVinod Koul 1341afdfb0b3SVinod Koul smp2p-adsp { 1342afdfb0b3SVinod Koul compatible = "qcom,smp2p"; 1343afdfb0b3SVinod Koul qcom,smem = <443>, <429>; 1344afdfb0b3SVinod Koul interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1345afdfb0b3SVinod Koul mboxes = <&apcs_glb 10>; 1346afdfb0b3SVinod Koul qcom,local-pid = <0>; 1347afdfb0b3SVinod Koul qcom,remote-pid = <2>; 1348afdfb0b3SVinod Koul 1349afdfb0b3SVinod Koul adsp_smp2p_out: master-kernel { 1350afdfb0b3SVinod Koul qcom,entry-name = "master-kernel"; 1351afdfb0b3SVinod Koul #qcom,smem-state-cells = <1>; 1352afdfb0b3SVinod Koul }; 1353afdfb0b3SVinod Koul 1354afdfb0b3SVinod Koul adsp_smp2p_in: slave-kernel { 1355afdfb0b3SVinod Koul qcom,entry-name = "slave-kernel"; 1356afdfb0b3SVinod Koul interrupt-controller; 1357afdfb0b3SVinod Koul #interrupt-cells = <2>; 1358afdfb0b3SVinod Koul }; 1359afdfb0b3SVinod Koul }; 1360afdfb0b3SVinod Koul 1361afdfb0b3SVinod Koul smp2p-cdsp { 1362afdfb0b3SVinod Koul compatible = "qcom,smp2p"; 1363afdfb0b3SVinod Koul qcom,smem = <94>, <432>; 1364afdfb0b3SVinod Koul interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1365afdfb0b3SVinod Koul mboxes = <&apcs_glb 14>; 1366afdfb0b3SVinod Koul qcom,local-pid = <0>; 1367afdfb0b3SVinod Koul qcom,remote-pid = <5>; 1368afdfb0b3SVinod Koul 1369afdfb0b3SVinod Koul cdsp_smp2p_out: master-kernel { 1370afdfb0b3SVinod Koul qcom,entry-name = "master-kernel"; 1371afdfb0b3SVinod Koul #qcom,smem-state-cells = <1>; 1372afdfb0b3SVinod Koul }; 1373afdfb0b3SVinod Koul 1374afdfb0b3SVinod Koul cdsp_smp2p_in: slave-kernel { 1375afdfb0b3SVinod Koul qcom,entry-name = "slave-kernel"; 1376afdfb0b3SVinod Koul interrupt-controller; 1377afdfb0b3SVinod Koul #interrupt-cells = <2>; 1378afdfb0b3SVinod Koul }; 1379afdfb0b3SVinod Koul }; 1380afdfb0b3SVinod Koul 1381afdfb0b3SVinod Koul smp2p-wcss { 1382afdfb0b3SVinod Koul compatible = "qcom,smp2p"; 1383afdfb0b3SVinod Koul qcom,smem = <435>, <428>; 1384afdfb0b3SVinod Koul interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1385afdfb0b3SVinod Koul mboxes = <&apcs_glb 18>; 1386afdfb0b3SVinod Koul qcom,local-pid = <0>; 1387afdfb0b3SVinod Koul qcom,remote-pid = <1>; 1388afdfb0b3SVinod Koul 1389afdfb0b3SVinod Koul wcss_smp2p_out: master-kernel { 1390afdfb0b3SVinod Koul qcom,entry-name = "master-kernel"; 1391afdfb0b3SVinod Koul #qcom,smem-state-cells = <1>; 1392afdfb0b3SVinod Koul }; 1393afdfb0b3SVinod Koul 1394afdfb0b3SVinod Koul wcss_smp2p_in: slave-kernel { 1395afdfb0b3SVinod Koul qcom,entry-name = "slave-kernel"; 1396afdfb0b3SVinod Koul interrupt-controller; 1397afdfb0b3SVinod Koul #interrupt-cells = <2>; 1398afdfb0b3SVinod Koul }; 1399afdfb0b3SVinod Koul }; 1400f48cee32SAmit Kucheria 1401f48cee32SAmit Kucheria thermal-zones { 1402f48cee32SAmit Kucheria aoss-thermal { 1403f48cee32SAmit Kucheria polling-delay-passive = <250>; 1404f48cee32SAmit Kucheria polling-delay = <1000>; 1405f48cee32SAmit Kucheria 1406f48cee32SAmit Kucheria thermal-sensors = <&tsens 0>; 1407f48cee32SAmit Kucheria 1408f48cee32SAmit Kucheria trips { 1409e8c48eb0SVinod Koul aoss_alert0: trip-point0 { 1410f48cee32SAmit Kucheria temperature = <105000>; 1411f48cee32SAmit Kucheria hysteresis = <2000>; 1412f48cee32SAmit Kucheria type = "hot"; 1413f48cee32SAmit Kucheria }; 1414f48cee32SAmit Kucheria }; 1415f48cee32SAmit Kucheria }; 1416f48cee32SAmit Kucheria 1417f48cee32SAmit Kucheria q6-hvx-thermal { 1418f48cee32SAmit Kucheria polling-delay-passive = <250>; 1419f48cee32SAmit Kucheria polling-delay = <1000>; 1420f48cee32SAmit Kucheria 1421f48cee32SAmit Kucheria thermal-sensors = <&tsens 1>; 1422f48cee32SAmit Kucheria 1423f48cee32SAmit Kucheria trips { 1424e8c48eb0SVinod Koul q6_hvx_alert0: trip-point0 { 1425f48cee32SAmit Kucheria temperature = <105000>; 1426f48cee32SAmit Kucheria hysteresis = <2000>; 1427f48cee32SAmit Kucheria type = "hot"; 1428f48cee32SAmit Kucheria }; 1429f48cee32SAmit Kucheria }; 1430f48cee32SAmit Kucheria }; 1431f48cee32SAmit Kucheria 1432f48cee32SAmit Kucheria lpass-thermal { 1433f48cee32SAmit Kucheria polling-delay-passive = <250>; 1434f48cee32SAmit Kucheria polling-delay = <1000>; 1435f48cee32SAmit Kucheria 1436f48cee32SAmit Kucheria thermal-sensors = <&tsens 2>; 1437f48cee32SAmit Kucheria 1438f48cee32SAmit Kucheria trips { 1439e8c48eb0SVinod Koul lpass_alert0: trip-point0 { 1440f48cee32SAmit Kucheria temperature = <105000>; 1441f48cee32SAmit Kucheria hysteresis = <2000>; 1442f48cee32SAmit Kucheria type = "hot"; 1443f48cee32SAmit Kucheria }; 1444f48cee32SAmit Kucheria }; 1445f48cee32SAmit Kucheria }; 1446f48cee32SAmit Kucheria 1447f48cee32SAmit Kucheria wlan-thermal { 1448f48cee32SAmit Kucheria polling-delay-passive = <250>; 1449f48cee32SAmit Kucheria polling-delay = <1000>; 1450f48cee32SAmit Kucheria 1451f48cee32SAmit Kucheria thermal-sensors = <&tsens 3>; 1452f48cee32SAmit Kucheria 1453f48cee32SAmit Kucheria trips { 1454e8c48eb0SVinod Koul wlan_alert0: trip-point0 { 1455f48cee32SAmit Kucheria temperature = <105000>; 1456f48cee32SAmit Kucheria hysteresis = <2000>; 1457f48cee32SAmit Kucheria type = "hot"; 1458f48cee32SAmit Kucheria }; 1459f48cee32SAmit Kucheria }; 1460f48cee32SAmit Kucheria }; 1461f48cee32SAmit Kucheria 1462f48cee32SAmit Kucheria cluster-thermal { 1463f48cee32SAmit Kucheria polling-delay-passive = <250>; 1464f48cee32SAmit Kucheria polling-delay = <1000>; 1465f48cee32SAmit Kucheria 1466f48cee32SAmit Kucheria thermal-sensors = <&tsens 4>; 1467f48cee32SAmit Kucheria 1468f48cee32SAmit Kucheria trips { 1469e8c48eb0SVinod Koul cluster_alert0: trip-point0 { 1470f48cee32SAmit Kucheria temperature = <95000>; 1471f48cee32SAmit Kucheria hysteresis = <2000>; 1472f48cee32SAmit Kucheria type = "hot"; 1473f48cee32SAmit Kucheria }; 1474e8c48eb0SVinod Koul cluster_alert1: trip-point1 { 1475f48cee32SAmit Kucheria temperature = <105000>; 1476f48cee32SAmit Kucheria hysteresis = <2000>; 1477f48cee32SAmit Kucheria type = "passive"; 1478f48cee32SAmit Kucheria }; 1479f48cee32SAmit Kucheria cluster_crit: cluster_crit { 1480f48cee32SAmit Kucheria temperature = <120000>; 1481f48cee32SAmit Kucheria hysteresis = <2000>; 1482f48cee32SAmit Kucheria type = "critical"; 1483f48cee32SAmit Kucheria }; 1484f48cee32SAmit Kucheria }; 1485f48cee32SAmit Kucheria cooling-maps { 1486f48cee32SAmit Kucheria map0 { 1487f48cee32SAmit Kucheria trip = <&cluster_alert1>; 1488f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1489f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1490f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1491f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1492f48cee32SAmit Kucheria }; 1493f48cee32SAmit Kucheria }; 1494f48cee32SAmit Kucheria }; 1495f48cee32SAmit Kucheria 1496f48cee32SAmit Kucheria cpu0-thermal { 1497f48cee32SAmit Kucheria polling-delay-passive = <250>; 1498f48cee32SAmit Kucheria polling-delay = <1000>; 1499f48cee32SAmit Kucheria 1500f48cee32SAmit Kucheria thermal-sensors = <&tsens 5>; 1501f48cee32SAmit Kucheria 1502f48cee32SAmit Kucheria trips { 1503e8c48eb0SVinod Koul cpu0_alert0: trip-point0 { 1504f48cee32SAmit Kucheria temperature = <95000>; 1505f48cee32SAmit Kucheria hysteresis = <2000>; 1506f48cee32SAmit Kucheria type = "hot"; 1507f48cee32SAmit Kucheria }; 1508e8c48eb0SVinod Koul cpu0_alert1: trip-point1 { 1509f48cee32SAmit Kucheria temperature = <105000>; 1510f48cee32SAmit Kucheria hysteresis = <2000>; 1511f48cee32SAmit Kucheria type = "passive"; 1512f48cee32SAmit Kucheria }; 1513f48cee32SAmit Kucheria cpu0_crit: cpu_crit { 1514f48cee32SAmit Kucheria temperature = <120000>; 1515f48cee32SAmit Kucheria hysteresis = <2000>; 1516f48cee32SAmit Kucheria type = "critical"; 1517f48cee32SAmit Kucheria }; 1518f48cee32SAmit Kucheria }; 1519f48cee32SAmit Kucheria cooling-maps { 1520f48cee32SAmit Kucheria map0 { 1521f48cee32SAmit Kucheria trip = <&cpu0_alert1>; 1522f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1523f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1524f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1525f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1526f48cee32SAmit Kucheria }; 1527f48cee32SAmit Kucheria }; 1528f48cee32SAmit Kucheria }; 1529f48cee32SAmit Kucheria 1530f48cee32SAmit Kucheria cpu1-thermal { 1531f48cee32SAmit Kucheria polling-delay-passive = <250>; 1532f48cee32SAmit Kucheria polling-delay = <1000>; 1533f48cee32SAmit Kucheria 1534f48cee32SAmit Kucheria thermal-sensors = <&tsens 6>; 1535f48cee32SAmit Kucheria 1536f48cee32SAmit Kucheria trips { 1537e8c48eb0SVinod Koul cpu1_alert0: trip-point0 { 1538f48cee32SAmit Kucheria temperature = <95000>; 1539f48cee32SAmit Kucheria hysteresis = <2000>; 1540f48cee32SAmit Kucheria type = "hot"; 1541f48cee32SAmit Kucheria }; 1542e8c48eb0SVinod Koul cpu1_alert1: trip-point1 { 1543f48cee32SAmit Kucheria temperature = <105000>; 1544f48cee32SAmit Kucheria hysteresis = <2000>; 1545f48cee32SAmit Kucheria type = "passive"; 1546f48cee32SAmit Kucheria }; 1547f48cee32SAmit Kucheria cpu1_crit: cpu_crit { 1548f48cee32SAmit Kucheria temperature = <120000>; 1549f48cee32SAmit Kucheria hysteresis = <2000>; 1550f48cee32SAmit Kucheria type = "critical"; 1551f48cee32SAmit Kucheria }; 1552f48cee32SAmit Kucheria }; 1553f48cee32SAmit Kucheria cooling-maps { 1554f48cee32SAmit Kucheria map0 { 1555f48cee32SAmit Kucheria trip = <&cpu1_alert1>; 1556f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1557f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1558f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1559f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1560f48cee32SAmit Kucheria }; 1561f48cee32SAmit Kucheria }; 1562f48cee32SAmit Kucheria }; 1563f48cee32SAmit Kucheria 1564f48cee32SAmit Kucheria cpu2-thermal { 1565f48cee32SAmit Kucheria polling-delay-passive = <250>; 1566f48cee32SAmit Kucheria polling-delay = <1000>; 1567f48cee32SAmit Kucheria 1568f48cee32SAmit Kucheria thermal-sensors = <&tsens 7>; 1569f48cee32SAmit Kucheria 1570f48cee32SAmit Kucheria trips { 1571e8c48eb0SVinod Koul cpu2_alert0: trip-point0 { 1572f48cee32SAmit Kucheria temperature = <95000>; 1573f48cee32SAmit Kucheria hysteresis = <2000>; 1574f48cee32SAmit Kucheria type = "hot"; 1575f48cee32SAmit Kucheria }; 1576e8c48eb0SVinod Koul cpu2_alert1: trip-point1 { 1577f48cee32SAmit Kucheria temperature = <105000>; 1578f48cee32SAmit Kucheria hysteresis = <2000>; 1579f48cee32SAmit Kucheria type = "passive"; 1580f48cee32SAmit Kucheria }; 1581f48cee32SAmit Kucheria cpu2_crit: cpu_crit { 1582f48cee32SAmit Kucheria temperature = <120000>; 1583f48cee32SAmit Kucheria hysteresis = <2000>; 1584f48cee32SAmit Kucheria type = "critical"; 1585f48cee32SAmit Kucheria }; 1586f48cee32SAmit Kucheria }; 1587f48cee32SAmit Kucheria cooling-maps { 1588f48cee32SAmit Kucheria map0 { 1589f48cee32SAmit Kucheria trip = <&cpu2_alert1>; 1590f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1591f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1592f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1593f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1594f48cee32SAmit Kucheria }; 1595f48cee32SAmit Kucheria }; 1596f48cee32SAmit Kucheria }; 1597f48cee32SAmit Kucheria 1598f48cee32SAmit Kucheria cpu3-thermal { 1599f48cee32SAmit Kucheria polling-delay-passive = <250>; 1600f48cee32SAmit Kucheria polling-delay = <1000>; 1601f48cee32SAmit Kucheria 1602f48cee32SAmit Kucheria thermal-sensors = <&tsens 8>; 1603f48cee32SAmit Kucheria 1604f48cee32SAmit Kucheria trips { 1605e8c48eb0SVinod Koul cpu3_alert0: trip-point0 { 1606f48cee32SAmit Kucheria temperature = <95000>; 1607f48cee32SAmit Kucheria hysteresis = <2000>; 1608f48cee32SAmit Kucheria type = "hot"; 1609f48cee32SAmit Kucheria }; 1610e8c48eb0SVinod Koul cpu3_alert1: trip-point1 { 1611f48cee32SAmit Kucheria temperature = <105000>; 1612f48cee32SAmit Kucheria hysteresis = <2000>; 1613f48cee32SAmit Kucheria type = "passive"; 1614f48cee32SAmit Kucheria }; 1615f48cee32SAmit Kucheria cpu3_crit: cpu_crit { 1616f48cee32SAmit Kucheria temperature = <120000>; 1617f48cee32SAmit Kucheria hysteresis = <2000>; 1618f48cee32SAmit Kucheria type = "critical"; 1619f48cee32SAmit Kucheria }; 1620f48cee32SAmit Kucheria }; 1621f48cee32SAmit Kucheria cooling-maps { 1622f48cee32SAmit Kucheria map0 { 1623f48cee32SAmit Kucheria trip = <&cpu3_alert1>; 1624f48cee32SAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1625f48cee32SAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1626f48cee32SAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1627f48cee32SAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1628f48cee32SAmit Kucheria }; 1629f48cee32SAmit Kucheria }; 1630f48cee32SAmit Kucheria }; 1631f48cee32SAmit Kucheria 1632f48cee32SAmit Kucheria gpu-thermal { 1633f48cee32SAmit Kucheria polling-delay-passive = <250>; 1634f48cee32SAmit Kucheria polling-delay = <1000>; 1635f48cee32SAmit Kucheria 1636f48cee32SAmit Kucheria thermal-sensors = <&tsens 9>; 1637f48cee32SAmit Kucheria 1638f48cee32SAmit Kucheria trips { 1639e8c48eb0SVinod Koul gpu_alert0: trip-point0 { 1640f48cee32SAmit Kucheria temperature = <95000>; 1641f48cee32SAmit Kucheria hysteresis = <2000>; 1642f48cee32SAmit Kucheria type = "hot"; 1643f48cee32SAmit Kucheria }; 1644f48cee32SAmit Kucheria }; 1645f48cee32SAmit Kucheria }; 1646f48cee32SAmit Kucheria }; 1647b4d82f4dSVinod Koul}; 1648