1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32764>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 46 capacity-dmips-mhz = <1024>; 47 dynamic-power-coefficient = <100>; 48 enable-method = "psci"; 49 next-level-cache = <&L2_0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 51 power-domains = <&CPU_PD0>; 52 power-domain-names = "psci"; 53 L2_0: l2-cache { 54 compatible = "cache"; 55 cache-level = <2>; 56 }; 57 }; 58 59 CPU1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0 0x1>; 63 clocks = <&cpufreq_hw 0>; 64 capacity-dmips-mhz = <1024>; 65 dynamic-power-coefficient = <100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 power-domains = <&CPU_PD1>; 70 power-domain-names = "psci"; 71 }; 72 73 CPU2: cpu@2 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x0 0x2>; 77 clocks = <&cpufreq_hw 0>; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_0>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 power-domains = <&CPU_PD2>; 84 power-domain-names = "psci"; 85 }; 86 87 CPU3: cpu@3 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x3>; 91 clocks = <&cpufreq_hw 0>; 92 capacity-dmips-mhz = <1024>; 93 dynamic-power-coefficient = <100>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_0>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 power-domains = <&CPU_PD3>; 98 power-domain-names = "psci"; 99 }; 100 101 cpu-map { 102 cluster0 { 103 core0 { 104 cpu = <&CPU0>; 105 }; 106 107 core1 { 108 cpu = <&CPU1>; 109 }; 110 111 core2 { 112 cpu = <&CPU2>; 113 }; 114 115 core3 { 116 cpu = <&CPU3>; 117 }; 118 }; 119 }; 120 121 domain-idle-states { 122 CLUSTER_SLEEP: cluster-sleep-0 { 123 compatible = "domain-idle-state"; 124 arm,psci-suspend-param = <0x41000043>; 125 entry-latency-us = <800>; 126 exit-latency-us = <2118>; 127 min-residency-us = <7376>; 128 }; 129 }; 130 131 idle-states { 132 entry-method = "psci"; 133 134 CPU_SLEEP: cpu-sleep-0 { 135 compatible = "arm,idle-state"; 136 idle-state-name = "power-collapse"; 137 arm,psci-suspend-param = <0x40000003>; 138 entry-latency-us = <290>; 139 exit-latency-us = <376>; 140 min-residency-us = <1182>; 141 local-timer-stop; 142 }; 143 }; 144 }; 145 146 firmware { 147 scm: scm { 148 compatible = "qcom,scm-qcm2290", "qcom,scm"; 149 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 150 clock-names = "core"; 151 #reset-cells = <1>; 152 }; 153 }; 154 155 memory@40000000 { 156 device_type = "memory"; 157 /* We expect the bootloader to fill in the size */ 158 reg = <0 0x40000000 0 0>; 159 }; 160 161 pmu { 162 compatible = "arm,armv8-pmuv3"; 163 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 psci { 167 compatible = "arm,psci-1.0"; 168 method = "smc"; 169 170 CPU_PD0: power-domain-cpu0 { 171 #power-domain-cells = <0>; 172 power-domains = <&CLUSTER_PD>; 173 domain-idle-states = <&CPU_SLEEP>; 174 }; 175 176 CPU_PD1: power-domain-cpu1 { 177 #power-domain-cells = <0>; 178 power-domains = <&CLUSTER_PD>; 179 domain-idle-states = <&CPU_SLEEP>; 180 }; 181 182 CPU_PD2: power-domain-cpu2 { 183 #power-domain-cells = <0>; 184 power-domains = <&CLUSTER_PD>; 185 domain-idle-states = <&CPU_SLEEP>; 186 }; 187 188 CPU_PD3: power-domain-cpu3 { 189 #power-domain-cells = <0>; 190 power-domains = <&CLUSTER_PD>; 191 domain-idle-states = <&CPU_SLEEP>; 192 }; 193 194 CLUSTER_PD: power-domain-cpu-cluster { 195 #power-domain-cells = <0>; 196 domain-idle-states = <&CLUSTER_SLEEP>; 197 }; 198 }; 199 200 reserved_memory: reserved-memory { 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges; 204 205 hyp_mem: hyp@45700000 { 206 reg = <0x0 0x45700000 0x0 0x600000>; 207 no-map; 208 }; 209 210 xbl_aop_mem: xbl-aop@45e00000 { 211 reg = <0x0 0x45e00000 0x0 0x140000>; 212 no-map; 213 }; 214 215 sec_apps_mem: sec-apps@45fff000 { 216 reg = <0x0 0x45fff000 0x0 0x1000>; 217 no-map; 218 }; 219 220 smem_mem: smem@46000000 { 221 compatible = "qcom,smem"; 222 reg = <0x0 0x46000000 0x0 0x200000>; 223 no-map; 224 225 hwlocks = <&tcsr_mutex 3>; 226 qcom,rpm-msg-ram = <&rpm_msg_ram>; 227 }; 228 229 pil_modem_mem: modem@4ab00000 { 230 reg = <0x0 0x4ab00000 0x0 0x6900000>; 231 no-map; 232 }; 233 234 pil_video_mem: video@51400000 { 235 reg = <0x0 0x51400000 0x0 0x500000>; 236 no-map; 237 }; 238 239 wlan_msa_mem: wlan-msa@51900000 { 240 reg = <0x0 0x51900000 0x0 0x100000>; 241 no-map; 242 }; 243 244 pil_adsp_mem: adsp@51a00000 { 245 reg = <0x0 0x51a00000 0x0 0x1c00000>; 246 no-map; 247 }; 248 249 pil_ipa_fw_mem: ipa-fw@53600000 { 250 reg = <0x0 0x53600000 0x0 0x10000>; 251 no-map; 252 }; 253 254 pil_ipa_gsi_mem: ipa-gsi@53610000 { 255 reg = <0x0 0x53610000 0x0 0x5000>; 256 no-map; 257 }; 258 259 pil_gpu_mem: zap@53615000 { 260 compatible = "shared-dma-pool"; 261 reg = <0x0 0x53615000 0x0 0x2000>; 262 no-map; 263 }; 264 265 cont_splash_memory: framebuffer@5c000000 { 266 reg = <0x0 0x5c000000 0x0 0x00f00000>; 267 no-map; 268 }; 269 270 dfps_data_memory: dpfs-data@5cf00000 { 271 reg = <0x0 0x5cf00000 0x0 0x0100000>; 272 no-map; 273 }; 274 275 removed_mem: reserved@60000000 { 276 reg = <0x0 0x60000000 0x0 0x3900000>; 277 no-map; 278 }; 279 280 rmtfs_mem: memory@89b01000 { 281 compatible = "qcom,rmtfs-mem"; 282 reg = <0x0 0x89b01000 0x0 0x200000>; 283 no-map; 284 285 qcom,client-id = <1>; 286 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 287 }; 288 }; 289 290 rpm-glink { 291 compatible = "qcom,glink-rpm"; 292 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 293 qcom,rpm-msg-ram = <&rpm_msg_ram>; 294 mboxes = <&apcs_glb 0>; 295 296 rpm_requests: rpm-requests { 297 compatible = "qcom,rpm-qcm2290"; 298 qcom,glink-channels = "rpm_requests"; 299 300 rpmcc: clock-controller { 301 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 302 clocks = <&xo_board>; 303 clock-names = "xo"; 304 #clock-cells = <1>; 305 }; 306 307 rpmpd: power-controller { 308 compatible = "qcom,qcm2290-rpmpd"; 309 #power-domain-cells = <1>; 310 operating-points-v2 = <&rpmpd_opp_table>; 311 312 rpmpd_opp_table: opp-table { 313 compatible = "operating-points-v2"; 314 315 rpmpd_opp_min_svs: opp1 { 316 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 317 }; 318 319 rpmpd_opp_low_svs: opp2 { 320 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 321 }; 322 323 rpmpd_opp_svs: opp3 { 324 opp-level = <RPM_SMD_LEVEL_SVS>; 325 }; 326 327 rpmpd_opp_svs_plus: opp4 { 328 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 329 }; 330 331 rpmpd_opp_nom: opp5 { 332 opp-level = <RPM_SMD_LEVEL_NOM>; 333 }; 334 335 rpmpd_opp_nom_plus: opp6 { 336 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 337 }; 338 339 rpmpd_opp_turbo: opp7 { 340 opp-level = <RPM_SMD_LEVEL_TURBO>; 341 }; 342 343 rpmpd_opp_turbo_plus: opp8 { 344 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 345 }; 346 }; 347 }; 348 }; 349 }; 350 351 smp2p-adsp { 352 compatible = "qcom,smp2p"; 353 qcom,smem = <443>, <429>; 354 355 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 356 357 mboxes = <&apcs_glb 10>; 358 359 qcom,local-pid = <0>; 360 qcom,remote-pid = <2>; 361 362 adsp_smp2p_out: master-kernel { 363 qcom,entry-name = "master-kernel"; 364 #qcom,smem-state-cells = <1>; 365 }; 366 367 adsp_smp2p_in: slave-kernel { 368 qcom,entry-name = "slave-kernel"; 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 }; 372 }; 373 374 smp2p-mpss { 375 compatible = "qcom,smp2p"; 376 qcom,smem = <435>, <428>; 377 378 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 379 380 mboxes = <&apcs_glb 14>; 381 382 qcom,local-pid = <0>; 383 qcom,remote-pid = <1>; 384 385 modem_smp2p_out: master-kernel { 386 qcom,entry-name = "master-kernel"; 387 #qcom,smem-state-cells = <1>; 388 }; 389 390 modem_smp2p_in: slave-kernel { 391 qcom,entry-name = "slave-kernel"; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 }; 395 396 wlan_smp2p_in: wlan-wpss-to-ap { 397 qcom,entry-name = "wlan"; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 }; 401 }; 402 403 soc: soc@0 { 404 compatible = "simple-bus"; 405 #address-cells = <2>; 406 #size-cells = <2>; 407 ranges = <0 0 0 0 0x10 0>; 408 dma-ranges = <0 0 0 0 0x10 0>; 409 410 tcsr_mutex: hwlock@340000 { 411 compatible = "qcom,tcsr-mutex"; 412 reg = <0x0 0x00340000 0x0 0x20000>; 413 #hwlock-cells = <1>; 414 }; 415 416 tlmm: pinctrl@500000 { 417 compatible = "qcom,qcm2290-tlmm"; 418 reg = <0x0 0x00500000 0x0 0x300000>; 419 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 420 gpio-controller; 421 gpio-ranges = <&tlmm 0 0 127>; 422 #gpio-cells = <2>; 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 426 qup_i2c0_default: qup-i2c0-default-state { 427 pins = "gpio0", "gpio1"; 428 function = "qup0"; 429 drive-strength = <2>; 430 bias-pull-up; 431 }; 432 433 qup_i2c1_default: qup-i2c1-default-state { 434 pins = "gpio4", "gpio5"; 435 function = "qup1"; 436 drive-strength = <2>; 437 bias-pull-up; 438 }; 439 440 qup_i2c2_default: qup-i2c2-default-state { 441 pins = "gpio6", "gpio7"; 442 function = "qup2"; 443 drive-strength = <2>; 444 bias-pull-up; 445 }; 446 447 qup_i2c3_default: qup-i2c3-default-state { 448 pins = "gpio8", "gpio9"; 449 function = "qup3"; 450 drive-strength = <2>; 451 bias-pull-up; 452 }; 453 454 qup_i2c4_default: qup-i2c4-default-state { 455 pins = "gpio12", "gpio13"; 456 function = "qup4"; 457 drive-strength = <2>; 458 bias-pull-up; 459 }; 460 461 qup_i2c5_default: qup-i2c5-default-state { 462 pins = "gpio14", "gpio15"; 463 function = "qup5"; 464 drive-strength = <2>; 465 bias-pull-up; 466 }; 467 468 qup_spi0_default: qup-spi0-default-state { 469 pins = "gpio0", "gpio1","gpio2", "gpio3"; 470 function = "qup0"; 471 drive-strength = <2>; 472 bias-pull-up; 473 }; 474 475 qup_spi1_default: qup-spi1-default-state { 476 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 477 function = "qup1"; 478 drive-strength = <2>; 479 bias-pull-up; 480 }; 481 482 qup_spi2_default: qup-spi2-default-state { 483 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 484 function = "qup2"; 485 drive-strength = <2>; 486 bias-pull-up; 487 }; 488 489 qup_spi3_default: qup-spi3-default-state { 490 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 491 function = "qup3"; 492 drive-strength = <2>; 493 bias-pull-up; 494 }; 495 496 qup_spi4_default: qup-spi4-default-state { 497 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 498 function = "qup4"; 499 drive-strength = <2>; 500 bias-pull-up; 501 }; 502 503 qup_spi5_default: qup-spi5-default-state { 504 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 505 function = "qup5"; 506 drive-strength = <2>; 507 bias-pull-up; 508 }; 509 510 qup_uart0_default: qup-uart0-default-state { 511 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 512 function = "qup0"; 513 drive-strength = <2>; 514 bias-disable; 515 }; 516 517 qup_uart4_default: qup-uart4-default-state { 518 pins = "gpio12", "gpio13"; 519 function = "qup4"; 520 drive-strength = <2>; 521 bias-disable; 522 }; 523 524 sdc1_state_on: sdc1-on-state { 525 clk-pins { 526 pins = "sdc1_clk"; 527 drive-strength = <16>; 528 bias-disable; 529 }; 530 531 cmd-pins { 532 pins = "sdc1_cmd"; 533 drive-strength = <10>; 534 bias-pull-up; 535 }; 536 537 data-pins { 538 pins = "sdc1_data"; 539 drive-strength = <10>; 540 bias-pull-up; 541 }; 542 543 rclk-pins { 544 pins = "sdc1_rclk"; 545 bias-pull-down; 546 }; 547 }; 548 549 sdc1_state_off: sdc1-off-state { 550 clk-pins { 551 pins = "sdc1_clk"; 552 drive-strength = <2>; 553 bias-disable; 554 }; 555 556 cmd-pins { 557 pins = "sdc1_cmd"; 558 drive-strength = <2>; 559 bias-pull-up; 560 }; 561 562 data-pins { 563 pins = "sdc1_data"; 564 drive-strength = <2>; 565 bias-pull-up; 566 }; 567 568 rclk-pins { 569 pins = "sdc1_rclk"; 570 bias-pull-down; 571 }; 572 }; 573 574 sdc2_state_on: sdc2-on-state { 575 clk-pins { 576 pins = "sdc2_clk"; 577 drive-strength = <16>; 578 bias-disable; 579 }; 580 581 cmd-pins { 582 pins = "sdc2_cmd"; 583 drive-strength = <10>; 584 bias-pull-up; 585 }; 586 587 data-pins { 588 pins = "sdc2_data"; 589 drive-strength = <10>; 590 bias-pull-up; 591 }; 592 }; 593 594 sdc2_state_off: sdc2-off-state { 595 clk-pins { 596 pins = "sdc2_clk"; 597 drive-strength = <2>; 598 bias-disable; 599 }; 600 601 cmd-pins { 602 pins = "sdc2_cmd"; 603 drive-strength = <2>; 604 bias-pull-up; 605 }; 606 607 data-pins { 608 pins = "sdc2_data"; 609 drive-strength = <2>; 610 bias-pull-up; 611 }; 612 }; 613 }; 614 615 gcc: clock-controller@1400000 { 616 compatible = "qcom,gcc-qcm2290"; 617 reg = <0x0 0x01400000 0x0 0x1f0000>; 618 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 619 clock-names = "bi_tcxo", "sleep_clk"; 620 #clock-cells = <1>; 621 #reset-cells = <1>; 622 #power-domain-cells = <1>; 623 }; 624 625 usb_hsphy: phy@1613000 { 626 compatible = "qcom,qcm2290-qusb2-phy"; 627 reg = <0x0 0x01613000 0x0 0x180>; 628 629 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 630 <&rpmcc RPM_SMD_XO_CLK_SRC>; 631 clock-names = "cfg_ahb", "ref"; 632 633 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 634 nvmem-cells = <&qusb2_hstx_trim>; 635 #phy-cells = <0>; 636 637 status = "disabled"; 638 }; 639 640 qfprom@1b44000 { 641 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 642 reg = <0x0 0x01b44000 0x0 0x3000>; 643 #address-cells = <1>; 644 #size-cells = <1>; 645 646 qusb2_hstx_trim: hstx-trim@25b { 647 reg = <0x25b 0x1>; 648 bits = <1 4>; 649 }; 650 }; 651 652 spmi_bus: spmi@1c40000 { 653 compatible = "qcom,spmi-pmic-arb"; 654 reg = <0x0 0x01c40000 0x0 0x1100>, 655 <0x0 0x01e00000 0x0 0x2000000>, 656 <0x0 0x03e00000 0x0 0x100000>, 657 <0x0 0x03f00000 0x0 0xa0000>, 658 <0x0 0x01c0a000 0x0 0x26000>; 659 reg-names = "core", 660 "chnls", 661 "obsrvr", 662 "intr", 663 "cnfg"; 664 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 665 interrupt-names = "periph_irq"; 666 qcom,ee = <0>; 667 qcom,channel = <0>; 668 #address-cells = <2>; 669 #size-cells = <0>; 670 interrupt-controller; 671 #interrupt-cells = <4>; 672 }; 673 674 tsens0: thermal-sensor@4411000 { 675 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 676 reg = <0x0 0x04411000 0x0 0x1ff>, 677 <0x0 0x04410000 0x0 0x8>; 678 #qcom,sensors = <10>; 679 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 681 interrupt-names = "uplow", "critical"; 682 #thermal-sensor-cells = <1>; 683 }; 684 685 rng: rng@4453000 { 686 compatible = "qcom,prng-ee"; 687 reg = <0x0 0x04453000 0x0 0x1000>; 688 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 689 clock-names = "core"; 690 }; 691 692 rpm_msg_ram: sram@45f0000 { 693 compatible = "qcom,rpm-msg-ram"; 694 reg = <0x0 0x045f0000 0x0 0x7000>; 695 }; 696 697 sram@4690000 { 698 compatible = "qcom,rpm-stats"; 699 reg = <0x0 0x04690000 0x0 0x10000>; 700 }; 701 702 sdhc_1: mmc@4744000 { 703 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 704 reg = <0x0 0x04744000 0x0 0x1000>, 705 <0x0 0x04745000 0x0 0x1000>, 706 <0x0 0x04748000 0x0 0x8000>; 707 reg-names = "hc", 708 "cqhci", 709 "ice"; 710 711 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 713 interrupt-names = "hc_irq", "pwr_irq"; 714 715 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 716 <&gcc GCC_SDCC1_APPS_CLK>, 717 <&rpmcc RPM_SMD_XO_CLK_SRC>, 718 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 719 clock-names = "iface", 720 "core", 721 "xo", 722 "ice"; 723 724 resets = <&gcc GCC_SDCC1_BCR>; 725 726 power-domains = <&rpmpd QCM2290_VDDCX>; 727 iommus = <&apps_smmu 0xc0 0x0>; 728 729 qcom,dll-config = <0x000f642c>; 730 qcom,ddr-config = <0x80040868>; 731 bus-width = <8>; 732 733 status = "disabled"; 734 }; 735 736 sdhc_2: mmc@4784000 { 737 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 738 reg = <0x0 0x04784000 0x0 0x1000>; 739 reg-names = "hc"; 740 741 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 743 interrupt-names = "hc_irq", "pwr_irq"; 744 745 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 746 <&gcc GCC_SDCC2_APPS_CLK>, 747 <&rpmcc RPM_SMD_XO_CLK_SRC>; 748 clock-names = "iface", 749 "core", 750 "xo"; 751 752 resets = <&gcc GCC_SDCC2_BCR>; 753 754 power-domains = <&rpmpd QCM2290_VDDCX>; 755 operating-points-v2 = <&sdhc2_opp_table>; 756 iommus = <&apps_smmu 0xa0 0x0>; 757 758 qcom,dll-config = <0x0007642c>; 759 qcom,ddr-config = <0x80040868>; 760 bus-width = <4>; 761 762 status = "disabled"; 763 764 sdhc2_opp_table: opp-table { 765 compatible = "operating-points-v2"; 766 767 opp-100000000 { 768 opp-hz = /bits/ 64 <100000000>; 769 required-opps = <&rpmpd_opp_low_svs>; 770 }; 771 772 opp-202000000 { 773 opp-hz = /bits/ 64 <202000000>; 774 required-opps = <&rpmpd_opp_svs_plus>; 775 }; 776 }; 777 }; 778 779 gpi_dma0: dma-controller@4a00000 { 780 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 781 reg = <0x0 0x04a00000 0x0 0x60000>; 782 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 792 dma-channels = <10>; 793 dma-channel-mask = <0x1f>; 794 iommus = <&apps_smmu 0xf6 0x0>; 795 #dma-cells = <3>; 796 status = "disabled"; 797 }; 798 799 qupv3_id_0: geniqup@4ac0000 { 800 compatible = "qcom,geni-se-qup"; 801 reg = <0x0 0x04ac0000 0x0 0x2000>; 802 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 803 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 804 clock-names = "m-ahb", "s-ahb"; 805 iommus = <&apps_smmu 0xe3 0x0>; 806 #address-cells = <2>; 807 #size-cells = <2>; 808 ranges; 809 status = "disabled"; 810 811 i2c0: i2c@4a80000 { 812 compatible = "qcom,geni-i2c"; 813 reg = <0x0 0x04a80000 0x0 0x4000>; 814 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 816 clock-names = "se"; 817 pinctrl-0 = <&qup_i2c0_default>; 818 pinctrl-names = "default"; 819 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 820 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 821 dma-names = "tx", "rx"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 status = "disabled"; 825 }; 826 827 spi0: spi@4a80000 { 828 compatible = "qcom,geni-spi"; 829 reg = <0x0 0x04a80000 0x0 0x4000>; 830 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 832 clock-names = "se"; 833 pinctrl-0 = <&qup_spi0_default>; 834 pinctrl-names = "default"; 835 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 836 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 837 dma-names = "tx", "rx"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 }; 842 843 uart0: serial@4a80000 { 844 compatible = "qcom,geni-uart"; 845 reg = <0x0 0x04a80000 0x0 0x4000>; 846 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 848 clock-names = "se"; 849 pinctrl-0 = <&qup_uart0_default>; 850 pinctrl-names = "default"; 851 status = "disabled"; 852 }; 853 854 i2c1: i2c@4a84000 { 855 compatible = "qcom,geni-i2c"; 856 reg = <0x0 0x04a84000 0x0 0x4000>; 857 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 859 clock-names = "se"; 860 pinctrl-0 = <&qup_i2c1_default>; 861 pinctrl-names = "default"; 862 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 863 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 864 dma-names = "tx", "rx"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 status = "disabled"; 868 }; 869 870 spi1: spi@4a84000 { 871 compatible = "qcom,geni-spi"; 872 reg = <0x0 0x04a84000 0x0 0x4000>; 873 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 875 clock-names = "se"; 876 pinctrl-0 = <&qup_spi1_default>; 877 pinctrl-names = "default"; 878 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 879 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 880 dma-names = "tx", "rx"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 status = "disabled"; 884 }; 885 886 i2c2: i2c@4a88000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0x0 0x04a88000 0x0 0x4000>; 889 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 891 clock-names = "se"; 892 pinctrl-0 = <&qup_i2c2_default>; 893 pinctrl-names = "default"; 894 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 895 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 896 dma-names = "tx", "rx"; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 status = "disabled"; 900 }; 901 902 spi2: spi@4a88000 { 903 compatible = "qcom,geni-spi"; 904 reg = <0x0 0x04a88000 0x0 0x4000>; 905 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 907 clock-names = "se"; 908 pinctrl-0 = <&qup_spi2_default>; 909 pinctrl-names = "default"; 910 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 911 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 912 dma-names = "tx", "rx"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 i2c3: i2c@4a8c000 { 919 compatible = "qcom,geni-i2c"; 920 reg = <0x0 0x04a8c000 0x0 0x4000>; 921 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 923 clock-names = "se"; 924 pinctrl-0 = <&qup_i2c3_default>; 925 pinctrl-names = "default"; 926 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 927 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 928 dma-names = "tx", "rx"; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 status = "disabled"; 932 }; 933 934 spi3: spi@4a8c000 { 935 compatible = "qcom,geni-spi"; 936 reg = <0x0 0x04a8c000 0x0 0x4000>; 937 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 939 clock-names = "se"; 940 pinctrl-0 = <&qup_spi3_default>; 941 pinctrl-names = "default"; 942 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 943 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 944 dma-names = "tx", "rx"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 i2c4: i2c@4a90000 { 951 compatible = "qcom,geni-i2c"; 952 reg = <0x0 0x04a90000 0x0 0x4000>; 953 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 955 clock-names = "se"; 956 pinctrl-0 = <&qup_i2c4_default>; 957 pinctrl-names = "default"; 958 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 959 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 960 dma-names = "tx", "rx"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 status = "disabled"; 964 }; 965 966 spi4: spi@4a90000 { 967 compatible = "qcom,geni-spi"; 968 reg = <0x0 0x04a90000 0x0 0x4000>; 969 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_spi4_default>; 974 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 975 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 976 dma-names = "tx", "rx"; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 status = "disabled"; 980 }; 981 982 uart4: serial@4a90000 { 983 compatible = "qcom,geni-uart"; 984 reg = <0x0 0x04a90000 0x0 0x4000>; 985 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 987 clock-names = "se"; 988 pinctrl-0 = <&qup_uart4_default>; 989 pinctrl-names = "default"; 990 status = "disabled"; 991 }; 992 993 i2c5: i2c@4a94000 { 994 compatible = "qcom,geni-i2c"; 995 reg = <0x0 0x04a94000 0x0 0x4000>; 996 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 998 clock-names = "se"; 999 pinctrl-0 = <&qup_i2c5_default>; 1000 pinctrl-names = "default"; 1001 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1002 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1003 dma-names = "tx", "rx"; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 status = "disabled"; 1007 }; 1008 1009 spi5: spi@4a94000 { 1010 compatible = "qcom,geni-spi"; 1011 reg = <0x0 0x04a94000 0x0 0x4000>; 1012 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1014 clock-names = "se"; 1015 pinctrl-0 = <&qup_spi5_default>; 1016 pinctrl-names = "default"; 1017 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1018 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1019 dma-names = "tx", "rx"; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 }; 1025 1026 usb: usb@4ef8800 { 1027 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1028 reg = <0x0 0x04ef8800 0x0 0x400>; 1029 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1031 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1032 1033 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1034 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1035 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1036 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1037 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1038 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1039 clock-names = "cfg_noc", 1040 "core", 1041 "iface", 1042 "sleep", 1043 "mock_utmi", 1044 "xo"; 1045 1046 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1047 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1048 assigned-clock-rates = <19200000>, <133333333>; 1049 1050 resets = <&gcc GCC_USB30_PRIM_BCR>; 1051 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1052 wakeup-source; 1053 1054 #address-cells = <2>; 1055 #size-cells = <2>; 1056 ranges; 1057 1058 status = "disabled"; 1059 1060 usb_dwc3: usb@4e00000 { 1061 compatible = "snps,dwc3"; 1062 reg = <0x0 0x04e00000 0x0 0xcd00>; 1063 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1064 phys = <&usb_hsphy>; 1065 phy-names = "usb2-phy"; 1066 iommus = <&apps_smmu 0x120 0x0>; 1067 snps,dis_u2_susphy_quirk; 1068 snps,dis_enblslpm_quirk; 1069 snps,has-lpm-erratum; 1070 snps,hird-threshold = /bits/ 8 <0x10>; 1071 snps,usb3_lpm_capable; 1072 maximum-speed = "super-speed"; 1073 dr_mode = "otg"; 1074 }; 1075 }; 1076 1077 remoteproc_mpss: remoteproc@6080000 { 1078 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 1079 reg = <0x0 0x06080000 0x0 0x100>; 1080 1081 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1082 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1083 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1084 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1085 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1086 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1087 interrupt-names = "wdog", 1088 "fatal", 1089 "ready", 1090 "handover", 1091 "stop-ack", 1092 "shutdown-ack"; 1093 1094 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1095 clock-names = "xo"; 1096 1097 power-domains = <&rpmpd QCM2290_VDDCX>; 1098 1099 memory-region = <&pil_modem_mem>; 1100 1101 qcom,smem-states = <&modem_smp2p_out 0>; 1102 qcom,smem-state-names = "stop"; 1103 1104 status = "disabled"; 1105 1106 glink-edge { 1107 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1108 label = "mpss"; 1109 qcom,remote-pid = <1>; 1110 mboxes = <&apcs_glb 12>; 1111 }; 1112 }; 1113 1114 remoteproc_adsp: remoteproc@ab00000 { 1115 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 1116 reg = <0x0 0x0ab00000 0x0 0x100>; 1117 1118 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1119 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1120 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1121 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1122 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1123 interrupt-names = "wdog", 1124 "fatal", 1125 "ready", 1126 "handover", 1127 "stop-ack"; 1128 1129 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1130 clock-names = "xo"; 1131 1132 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 1133 <&rpmpd QCM2290_VDD_LPI_MX>; 1134 1135 memory-region = <&pil_adsp_mem>; 1136 1137 qcom,smem-states = <&adsp_smp2p_out 0>; 1138 qcom,smem-state-names = "stop"; 1139 1140 status = "disabled"; 1141 1142 glink-edge { 1143 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 1144 label = "lpass"; 1145 qcom,remote-pid = <2>; 1146 mboxes = <&apcs_glb 8>; 1147 }; 1148 }; 1149 1150 apps_smmu: iommu@c600000 { 1151 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1152 reg = <0x0 0x0c600000 0x0 0x80000>; 1153 #iommu-cells = <2>; 1154 #global-interrupts = <1>; 1155 1156 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1221 }; 1222 1223 wifi: wifi@c800000 { 1224 compatible = "qcom,wcn3990-wifi"; 1225 reg = <0x0 0x0c800000 0x0 0x800000>; 1226 reg-names = "membase"; 1227 memory-region = <&wlan_msa_mem>; 1228 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1240 iommus = <&apps_smmu 0x1a0 0x1>; 1241 qcom,msa-fixed-perm; 1242 status = "disabled"; 1243 }; 1244 1245 watchdog@f017000 { 1246 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 1247 reg = <0x0 0x0f017000 0x0 0x1000>; 1248 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1249 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&sleep_clk>; 1251 }; 1252 1253 apcs_glb: mailbox@f111000 { 1254 compatible = "qcom,qcm2290-apcs-hmss-global"; 1255 reg = <0x0 0x0f111000 0x0 0x1000>; 1256 #mbox-cells = <1>; 1257 }; 1258 1259 timer@f120000 { 1260 compatible = "arm,armv7-timer-mem"; 1261 reg = <0x0 0x0f120000 0x0 0x1000>; 1262 #address-cells = <1>; 1263 #size-cells = <1>; 1264 ranges = <0 0x0 0x0f121000 0x8000>; 1265 1266 frame@0 { 1267 reg = <0x0 0x1000>, 1268 <0x1000 0x1000>; 1269 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1271 frame-number = <0>; 1272 }; 1273 1274 frame@2000 { 1275 reg = <0x2000 0x1000>; 1276 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1277 frame-number = <1>; 1278 status = "disabled"; 1279 }; 1280 1281 frame@3000 { 1282 reg = <0x3000 0x1000>; 1283 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1284 frame-number = <2>; 1285 status = "disabled"; 1286 }; 1287 1288 frame@4000 { 1289 reg = <0x4000 0x1000>; 1290 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1291 frame-number = <3>; 1292 status = "disabled"; 1293 }; 1294 1295 frame@5000 { 1296 reg = <0x5000 0x1000>; 1297 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1298 frame-number = <4>; 1299 status = "disabled"; 1300 }; 1301 1302 frame@6000 { 1303 reg = <0x6000 0x1000>; 1304 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1305 frame-number = <5>; 1306 status = "disabled"; 1307 }; 1308 1309 frame@7000 { 1310 reg = <0x7000 0x1000>; 1311 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1312 frame-number = <6>; 1313 status = "disabled"; 1314 }; 1315 }; 1316 1317 intc: interrupt-controller@f200000 { 1318 compatible = "arm,gic-v3"; 1319 reg = <0x0 0x0f200000 0x0 0x10000>, 1320 <0x0 0x0f300000 0x0 0x100000>; 1321 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1322 #interrupt-cells = <3>; 1323 interrupt-controller; 1324 interrupt-parent = <&intc>; 1325 #redistributor-regions = <1>; 1326 redistributor-stride = <0x0 0x20000>; 1327 }; 1328 1329 cpufreq_hw: cpufreq@f521000 { 1330 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 1331 reg = <0x0 0x0f521000 0x0 0x1000>; 1332 reg-names = "freq-domain0"; 1333 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1334 interrupt-names = "dcvsh-irq-0"; 1335 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1336 clock-names = "xo", "alternate"; 1337 1338 #freq-domain-cells = <1>; 1339 #clock-cells = <1>; 1340 }; 1341 }; 1342 1343 thermal-zones { 1344 mapss-thermal { 1345 polling-delay-passive = <0>; 1346 polling-delay = <0>; 1347 1348 thermal-sensors = <&tsens0 0>; 1349 1350 trips { 1351 mapss_alert0: trip-point0 { 1352 temperature = <90000>; 1353 hysteresis = <2000>; 1354 type = "passive"; 1355 }; 1356 1357 mapss_alert1: trip-point1 { 1358 temperature = <95000>; 1359 hysteresis = <2000>; 1360 type = "passive"; 1361 }; 1362 1363 mapss_crit: mapss-crit { 1364 temperature = <110000>; 1365 hysteresis = <1000>; 1366 type = "critical"; 1367 }; 1368 }; 1369 }; 1370 1371 video-thermal { 1372 polling-delay-passive = <0>; 1373 polling-delay = <0>; 1374 1375 thermal-sensors = <&tsens0 1>; 1376 1377 trips { 1378 video_alert0: trip-point0 { 1379 temperature = <90000>; 1380 hysteresis = <2000>; 1381 type = "passive"; 1382 }; 1383 1384 video_alert1: trip-point1 { 1385 temperature = <95000>; 1386 hysteresis = <2000>; 1387 type = "passive"; 1388 }; 1389 1390 video_crit: video-crit { 1391 temperature = <110000>; 1392 hysteresis = <1000>; 1393 type = "critical"; 1394 }; 1395 }; 1396 }; 1397 1398 wlan-thermal { 1399 polling-delay-passive = <0>; 1400 polling-delay = <0>; 1401 1402 thermal-sensors = <&tsens0 2>; 1403 1404 trips { 1405 wlan_alert0: trip-point0 { 1406 temperature = <90000>; 1407 hysteresis = <2000>; 1408 type = "passive"; 1409 }; 1410 1411 wlan_alert1: trip-point1 { 1412 temperature = <95000>; 1413 hysteresis = <2000>; 1414 type = "passive"; 1415 }; 1416 1417 wlan_crit: wlan-crit { 1418 temperature = <110000>; 1419 hysteresis = <1000>; 1420 type = "critical"; 1421 }; 1422 }; 1423 }; 1424 1425 cpuss0-thermal { 1426 polling-delay-passive = <0>; 1427 polling-delay = <0>; 1428 1429 thermal-sensors = <&tsens0 3>; 1430 1431 trips { 1432 cpuss0_alert0: trip-point0 { 1433 temperature = <90000>; 1434 hysteresis = <2000>; 1435 type = "passive"; 1436 }; 1437 1438 cpuss0_alert1: trip-point1 { 1439 temperature = <95000>; 1440 hysteresis = <2000>; 1441 type = "passive"; 1442 }; 1443 1444 cpuss0_crit: cpuss0-crit { 1445 temperature = <110000>; 1446 hysteresis = <1000>; 1447 type = "critical"; 1448 }; 1449 }; 1450 }; 1451 1452 cpuss1-thermal { 1453 polling-delay-passive = <0>; 1454 polling-delay = <0>; 1455 1456 thermal-sensors = <&tsens0 4>; 1457 1458 trips { 1459 cpuss1_alert0: trip-point0 { 1460 temperature = <90000>; 1461 hysteresis = <2000>; 1462 type = "passive"; 1463 }; 1464 1465 cpuss1_alert1: trip-point1 { 1466 temperature = <95000>; 1467 hysteresis = <2000>; 1468 type = "passive"; 1469 }; 1470 1471 cpuss1_crit: cpuss1-crit { 1472 temperature = <110000>; 1473 hysteresis = <1000>; 1474 type = "critical"; 1475 }; 1476 }; 1477 }; 1478 1479 mdm0-thermal { 1480 polling-delay-passive = <0>; 1481 polling-delay = <0>; 1482 1483 thermal-sensors = <&tsens0 5>; 1484 1485 trips { 1486 mdm0_alert0: trip-point0 { 1487 temperature = <90000>; 1488 hysteresis = <2000>; 1489 type = "passive"; 1490 }; 1491 1492 mdm0_alert1: trip-point1 { 1493 temperature = <95000>; 1494 hysteresis = <2000>; 1495 type = "passive"; 1496 }; 1497 1498 mdm0_crit: mdm0-crit { 1499 temperature = <110000>; 1500 hysteresis = <1000>; 1501 type = "critical"; 1502 }; 1503 }; 1504 }; 1505 1506 mdm1-thermal { 1507 polling-delay-passive = <0>; 1508 polling-delay = <0>; 1509 1510 thermal-sensors = <&tsens0 6>; 1511 1512 trips { 1513 mdm1_alert0: trip-point0 { 1514 temperature = <90000>; 1515 hysteresis = <2000>; 1516 type = "passive"; 1517 }; 1518 1519 mdm1_alert1: trip-point1 { 1520 temperature = <95000>; 1521 hysteresis = <2000>; 1522 type = "passive"; 1523 }; 1524 1525 mdm1_crit: mdm1-crit { 1526 temperature = <110000>; 1527 hysteresis = <1000>; 1528 type = "critical"; 1529 }; 1530 }; 1531 }; 1532 1533 gpu-thermal { 1534 polling-delay-passive = <0>; 1535 polling-delay = <0>; 1536 1537 thermal-sensors = <&tsens0 7>; 1538 1539 trips { 1540 gpu_alert0: trip-point0 { 1541 temperature = <90000>; 1542 hysteresis = <2000>; 1543 type = "passive"; 1544 }; 1545 1546 gpu_alert1: trip-point1 { 1547 temperature = <95000>; 1548 hysteresis = <2000>; 1549 type = "passive"; 1550 }; 1551 1552 gpu_crit: gpu-crit { 1553 temperature = <110000>; 1554 hysteresis = <1000>; 1555 type = "critical"; 1556 }; 1557 }; 1558 }; 1559 1560 hm-center-thermal { 1561 polling-delay-passive = <0>; 1562 polling-delay = <0>; 1563 1564 thermal-sensors = <&tsens0 8>; 1565 1566 trips { 1567 hm_center_alert0: trip-point0 { 1568 temperature = <90000>; 1569 hysteresis = <2000>; 1570 type = "passive"; 1571 }; 1572 1573 hm_center_alert1: trip-point1 { 1574 temperature = <95000>; 1575 hysteresis = <2000>; 1576 type = "passive"; 1577 }; 1578 1579 hm_center_crit: hm-center-crit { 1580 temperature = <110000>; 1581 hysteresis = <1000>; 1582 type = "critical"; 1583 }; 1584 }; 1585 }; 1586 1587 camera-thermal { 1588 polling-delay-passive = <0>; 1589 polling-delay = <0>; 1590 1591 thermal-sensors = <&tsens0 9>; 1592 1593 trips { 1594 camera_alert0: trip-point0 { 1595 temperature = <90000>; 1596 hysteresis = <2000>; 1597 type = "passive"; 1598 }; 1599 1600 camera_alert1: trip-point1 { 1601 temperature = <95000>; 1602 hysteresis = <2000>; 1603 type = "passive"; 1604 }; 1605 1606 camera_crit: camera-crit { 1607 temperature = <110000>; 1608 hysteresis = <1000>; 1609 type = "critical"; 1610 }; 1611 }; 1612 }; 1613 }; 1614 1615 timer { 1616 compatible = "arm,armv8-timer"; 1617 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1618 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1619 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1620 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1621 }; 1622}; 1623