1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32764>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 46 capacity-dmips-mhz = <1024>; 47 dynamic-power-coefficient = <100>; 48 enable-method = "psci"; 49 next-level-cache = <&L2_0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 51 L2_0: l2-cache { 52 compatible = "cache"; 53 cache-level = <2>; 54 cache-unified; 55 }; 56 }; 57 58 CPU1: cpu@1 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0 0x1>; 62 clocks = <&cpufreq_hw 0>; 63 capacity-dmips-mhz = <1024>; 64 dynamic-power-coefficient = <100>; 65 enable-method = "psci"; 66 next-level-cache = <&L2_0>; 67 qcom,freq-domain = <&cpufreq_hw 0>; 68 }; 69 70 CPU2: cpu@2 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x0 0x2>; 74 clocks = <&cpufreq_hw 0>; 75 capacity-dmips-mhz = <1024>; 76 dynamic-power-coefficient = <100>; 77 enable-method = "psci"; 78 next-level-cache = <&L2_0>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 }; 81 82 CPU3: cpu@3 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x3>; 86 clocks = <&cpufreq_hw 0>; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 enable-method = "psci"; 90 next-level-cache = <&L2_0>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 }; 93 94 cpu-map { 95 cluster0 { 96 core0 { 97 cpu = <&CPU0>; 98 }; 99 100 core1 { 101 cpu = <&CPU1>; 102 }; 103 104 core2 { 105 cpu = <&CPU2>; 106 }; 107 108 core3 { 109 cpu = <&CPU3>; 110 }; 111 }; 112 }; 113 }; 114 115 firmware { 116 scm: scm { 117 compatible = "qcom,scm-qcm2290", "qcom,scm"; 118 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 119 clock-names = "core"; 120 #reset-cells = <1>; 121 }; 122 }; 123 124 memory@40000000 { 125 device_type = "memory"; 126 /* We expect the bootloader to fill in the size */ 127 reg = <0 0x40000000 0 0>; 128 }; 129 130 pmu { 131 compatible = "arm,armv8-pmuv3"; 132 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 133 }; 134 135 psci { 136 compatible = "arm,psci-1.0"; 137 method = "smc"; 138 }; 139 140 reserved_memory: reserved-memory { 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 hyp_mem: hyp@45700000 { 146 reg = <0x0 0x45700000 0x0 0x600000>; 147 no-map; 148 }; 149 150 xbl_aop_mem: xbl-aop@45e00000 { 151 reg = <0x0 0x45e00000 0x0 0x140000>; 152 no-map; 153 }; 154 155 sec_apps_mem: sec-apps@45fff000 { 156 reg = <0x0 0x45fff000 0x0 0x1000>; 157 no-map; 158 }; 159 160 smem_mem: smem@46000000 { 161 compatible = "qcom,smem"; 162 reg = <0x0 0x46000000 0x0 0x200000>; 163 no-map; 164 165 hwlocks = <&tcsr_mutex 3>; 166 qcom,rpm-msg-ram = <&rpm_msg_ram>; 167 }; 168 169 pil_modem_mem: modem@4ab00000 { 170 reg = <0x0 0x4ab00000 0x0 0x6900000>; 171 no-map; 172 }; 173 174 pil_video_mem: video@51400000 { 175 reg = <0x0 0x51400000 0x0 0x500000>; 176 no-map; 177 }; 178 179 wlan_msa_mem: wlan-msa@51900000 { 180 reg = <0x0 0x51900000 0x0 0x100000>; 181 no-map; 182 }; 183 184 pil_adsp_mem: adsp@51a00000 { 185 reg = <0x0 0x51a00000 0x0 0x1c00000>; 186 no-map; 187 }; 188 189 pil_ipa_fw_mem: ipa-fw@53600000 { 190 reg = <0x0 0x53600000 0x0 0x10000>; 191 no-map; 192 }; 193 194 pil_ipa_gsi_mem: ipa-gsi@53610000 { 195 reg = <0x0 0x53610000 0x0 0x5000>; 196 no-map; 197 }; 198 199 pil_gpu_mem: zap@53615000 { 200 compatible = "shared-dma-pool"; 201 reg = <0x0 0x53615000 0x0 0x2000>; 202 no-map; 203 }; 204 205 cont_splash_memory: framebuffer@5c000000 { 206 reg = <0x0 0x5c000000 0x0 0x00f00000>; 207 no-map; 208 }; 209 210 dfps_data_memory: dpfs-data@5cf00000 { 211 reg = <0x0 0x5cf00000 0x0 0x0100000>; 212 no-map; 213 }; 214 215 removed_mem: reserved@60000000 { 216 reg = <0x0 0x60000000 0x0 0x3900000>; 217 no-map; 218 }; 219 220 rmtfs_mem: memory@89b01000 { 221 compatible = "qcom,rmtfs-mem"; 222 reg = <0x0 0x89b01000 0x0 0x200000>; 223 no-map; 224 225 qcom,client-id = <1>; 226 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 227 }; 228 }; 229 230 rpm-glink { 231 compatible = "qcom,glink-rpm"; 232 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 233 qcom,rpm-msg-ram = <&rpm_msg_ram>; 234 mboxes = <&apcs_glb 0>; 235 236 rpm_requests: rpm-requests { 237 compatible = "qcom,rpm-qcm2290"; 238 qcom,glink-channels = "rpm_requests"; 239 240 rpmcc: clock-controller { 241 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 242 clocks = <&xo_board>; 243 clock-names = "xo"; 244 #clock-cells = <1>; 245 }; 246 247 rpmpd: power-controller { 248 compatible = "qcom,qcm2290-rpmpd"; 249 #power-domain-cells = <1>; 250 operating-points-v2 = <&rpmpd_opp_table>; 251 252 rpmpd_opp_table: opp-table { 253 compatible = "operating-points-v2"; 254 255 rpmpd_opp_min_svs: opp1 { 256 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 257 }; 258 259 rpmpd_opp_low_svs: opp2 { 260 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 261 }; 262 263 rpmpd_opp_svs: opp3 { 264 opp-level = <RPM_SMD_LEVEL_SVS>; 265 }; 266 267 rpmpd_opp_svs_plus: opp4 { 268 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 269 }; 270 271 rpmpd_opp_nom: opp5 { 272 opp-level = <RPM_SMD_LEVEL_NOM>; 273 }; 274 275 rpmpd_opp_nom_plus: opp6 { 276 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 277 }; 278 279 rpmpd_opp_turbo: opp7 { 280 opp-level = <RPM_SMD_LEVEL_TURBO>; 281 }; 282 283 rpmpd_opp_turbo_plus: opp8 { 284 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 285 }; 286 }; 287 }; 288 }; 289 }; 290 291 smp2p-adsp { 292 compatible = "qcom,smp2p"; 293 qcom,smem = <443>, <429>; 294 295 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 296 297 mboxes = <&apcs_glb 10>; 298 299 qcom,local-pid = <0>; 300 qcom,remote-pid = <2>; 301 302 adsp_smp2p_out: master-kernel { 303 qcom,entry-name = "master-kernel"; 304 #qcom,smem-state-cells = <1>; 305 }; 306 307 adsp_smp2p_in: slave-kernel { 308 qcom,entry-name = "slave-kernel"; 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 }; 312 }; 313 314 smp2p-mpss { 315 compatible = "qcom,smp2p"; 316 qcom,smem = <435>, <428>; 317 318 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 319 320 mboxes = <&apcs_glb 14>; 321 322 qcom,local-pid = <0>; 323 qcom,remote-pid = <1>; 324 325 modem_smp2p_out: master-kernel { 326 qcom,entry-name = "master-kernel"; 327 #qcom,smem-state-cells = <1>; 328 }; 329 330 modem_smp2p_in: slave-kernel { 331 qcom,entry-name = "slave-kernel"; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 336 wlan_smp2p_in: wlan-wpss-to-ap { 337 qcom,entry-name = "wlan"; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 }; 342 343 soc: soc@0 { 344 compatible = "simple-bus"; 345 #address-cells = <2>; 346 #size-cells = <2>; 347 ranges = <0 0 0 0 0x10 0>; 348 dma-ranges = <0 0 0 0 0x10 0>; 349 350 tcsr_mutex: hwlock@340000 { 351 compatible = "qcom,tcsr-mutex"; 352 reg = <0x0 0x00340000 0x0 0x20000>; 353 #hwlock-cells = <1>; 354 }; 355 356 tlmm: pinctrl@500000 { 357 compatible = "qcom,qcm2290-tlmm"; 358 reg = <0x0 0x00500000 0x0 0x300000>; 359 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 360 gpio-controller; 361 gpio-ranges = <&tlmm 0 0 127>; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 366 qup_i2c0_default: qup-i2c0-default-state { 367 pins = "gpio0", "gpio1"; 368 function = "qup0"; 369 drive-strength = <2>; 370 bias-pull-up; 371 }; 372 373 qup_i2c1_default: qup-i2c1-default-state { 374 pins = "gpio4", "gpio5"; 375 function = "qup1"; 376 drive-strength = <2>; 377 bias-pull-up; 378 }; 379 380 qup_i2c2_default: qup-i2c2-default-state { 381 pins = "gpio6", "gpio7"; 382 function = "qup2"; 383 drive-strength = <2>; 384 bias-pull-up; 385 }; 386 387 qup_i2c3_default: qup-i2c3-default-state { 388 pins = "gpio8", "gpio9"; 389 function = "qup3"; 390 drive-strength = <2>; 391 bias-pull-up; 392 }; 393 394 qup_i2c4_default: qup-i2c4-default-state { 395 pins = "gpio12", "gpio13"; 396 function = "qup4"; 397 drive-strength = <2>; 398 bias-pull-up; 399 }; 400 401 qup_i2c5_default: qup-i2c5-default-state { 402 pins = "gpio14", "gpio15"; 403 function = "qup5"; 404 drive-strength = <2>; 405 bias-pull-up; 406 }; 407 408 qup_spi0_default: qup-spi0-default-state { 409 pins = "gpio0", "gpio1","gpio2", "gpio3"; 410 function = "qup0"; 411 drive-strength = <2>; 412 bias-pull-up; 413 }; 414 415 qup_spi1_default: qup-spi1-default-state { 416 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 417 function = "qup1"; 418 drive-strength = <2>; 419 bias-pull-up; 420 }; 421 422 qup_spi2_default: qup-spi2-default-state { 423 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 424 function = "qup2"; 425 drive-strength = <2>; 426 bias-pull-up; 427 }; 428 429 qup_spi3_default: qup-spi3-default-state { 430 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 431 function = "qup3"; 432 drive-strength = <2>; 433 bias-pull-up; 434 }; 435 436 qup_spi4_default: qup-spi4-default-state { 437 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 438 function = "qup4"; 439 drive-strength = <2>; 440 bias-pull-up; 441 }; 442 443 qup_spi5_default: qup-spi5-default-state { 444 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 445 function = "qup5"; 446 drive-strength = <2>; 447 bias-pull-up; 448 }; 449 450 qup_uart0_default: qup-uart0-default-state { 451 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 452 function = "qup0"; 453 drive-strength = <2>; 454 bias-disable; 455 }; 456 457 qup_uart4_default: qup-uart4-default-state { 458 pins = "gpio12", "gpio13"; 459 function = "qup4"; 460 drive-strength = <2>; 461 bias-disable; 462 }; 463 464 sdc1_state_on: sdc1-on-state { 465 clk-pins { 466 pins = "sdc1_clk"; 467 drive-strength = <16>; 468 bias-disable; 469 }; 470 471 cmd-pins { 472 pins = "sdc1_cmd"; 473 drive-strength = <10>; 474 bias-pull-up; 475 }; 476 477 data-pins { 478 pins = "sdc1_data"; 479 drive-strength = <10>; 480 bias-pull-up; 481 }; 482 483 rclk-pins { 484 pins = "sdc1_rclk"; 485 bias-pull-down; 486 }; 487 }; 488 489 sdc1_state_off: sdc1-off-state { 490 clk-pins { 491 pins = "sdc1_clk"; 492 drive-strength = <2>; 493 bias-disable; 494 }; 495 496 cmd-pins { 497 pins = "sdc1_cmd"; 498 drive-strength = <2>; 499 bias-pull-up; 500 }; 501 502 data-pins { 503 pins = "sdc1_data"; 504 drive-strength = <2>; 505 bias-pull-up; 506 }; 507 508 rclk-pins { 509 pins = "sdc1_rclk"; 510 bias-pull-down; 511 }; 512 }; 513 514 sdc2_state_on: sdc2-on-state { 515 clk-pins { 516 pins = "sdc2_clk"; 517 drive-strength = <16>; 518 bias-disable; 519 }; 520 521 cmd-pins { 522 pins = "sdc2_cmd"; 523 drive-strength = <10>; 524 bias-pull-up; 525 }; 526 527 data-pins { 528 pins = "sdc2_data"; 529 drive-strength = <10>; 530 bias-pull-up; 531 }; 532 }; 533 534 sdc2_state_off: sdc2-off-state { 535 clk-pins { 536 pins = "sdc2_clk"; 537 drive-strength = <2>; 538 bias-disable; 539 }; 540 541 cmd-pins { 542 pins = "sdc2_cmd"; 543 drive-strength = <2>; 544 bias-pull-up; 545 }; 546 547 data-pins { 548 pins = "sdc2_data"; 549 drive-strength = <2>; 550 bias-pull-up; 551 }; 552 }; 553 }; 554 555 gcc: clock-controller@1400000 { 556 compatible = "qcom,gcc-qcm2290"; 557 reg = <0x0 0x01400000 0x0 0x1f0000>; 558 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 559 clock-names = "bi_tcxo", "sleep_clk"; 560 #clock-cells = <1>; 561 #reset-cells = <1>; 562 #power-domain-cells = <1>; 563 }; 564 565 usb_hsphy: phy@1613000 { 566 compatible = "qcom,qcm2290-qusb2-phy"; 567 reg = <0x0 0x01613000 0x0 0x180>; 568 569 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 570 <&rpmcc RPM_SMD_XO_CLK_SRC>; 571 clock-names = "cfg_ahb", "ref"; 572 573 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 574 nvmem-cells = <&qusb2_hstx_trim>; 575 #phy-cells = <0>; 576 577 status = "disabled"; 578 }; 579 580 qfprom@1b44000 { 581 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 582 reg = <0x0 0x01b44000 0x0 0x3000>; 583 #address-cells = <1>; 584 #size-cells = <1>; 585 586 qusb2_hstx_trim: hstx-trim@25b { 587 reg = <0x25b 0x1>; 588 bits = <1 4>; 589 }; 590 }; 591 592 spmi_bus: spmi@1c40000 { 593 compatible = "qcom,spmi-pmic-arb"; 594 reg = <0x0 0x01c40000 0x0 0x1100>, 595 <0x0 0x01e00000 0x0 0x2000000>, 596 <0x0 0x03e00000 0x0 0x100000>, 597 <0x0 0x03f00000 0x0 0xa0000>, 598 <0x0 0x01c0a000 0x0 0x26000>; 599 reg-names = "core", 600 "chnls", 601 "obsrvr", 602 "intr", 603 "cnfg"; 604 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 605 interrupt-names = "periph_irq"; 606 qcom,ee = <0>; 607 qcom,channel = <0>; 608 #address-cells = <2>; 609 #size-cells = <0>; 610 interrupt-controller; 611 #interrupt-cells = <4>; 612 }; 613 614 tsens0: thermal-sensor@4411000 { 615 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 616 reg = <0x0 0x04411000 0x0 0x1ff>, 617 <0x0 0x04410000 0x0 0x8>; 618 #qcom,sensors = <10>; 619 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "uplow", "critical"; 622 #thermal-sensor-cells = <1>; 623 }; 624 625 rng: rng@4453000 { 626 compatible = "qcom,prng-ee"; 627 reg = <0x0 0x04453000 0x0 0x1000>; 628 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 629 clock-names = "core"; 630 }; 631 632 rpm_msg_ram: sram@45f0000 { 633 compatible = "qcom,rpm-msg-ram"; 634 reg = <0x0 0x045f0000 0x0 0x7000>; 635 }; 636 637 sram@4690000 { 638 compatible = "qcom,rpm-stats"; 639 reg = <0x0 0x04690000 0x0 0x10000>; 640 }; 641 642 sdhc_1: mmc@4744000 { 643 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 644 reg = <0x0 0x04744000 0x0 0x1000>, 645 <0x0 0x04745000 0x0 0x1000>, 646 <0x0 0x04748000 0x0 0x8000>; 647 reg-names = "hc", 648 "cqhci", 649 "ice"; 650 651 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 653 interrupt-names = "hc_irq", "pwr_irq"; 654 655 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 656 <&gcc GCC_SDCC1_APPS_CLK>, 657 <&rpmcc RPM_SMD_XO_CLK_SRC>, 658 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 659 clock-names = "iface", 660 "core", 661 "xo", 662 "ice"; 663 664 resets = <&gcc GCC_SDCC1_BCR>; 665 666 power-domains = <&rpmpd QCM2290_VDDCX>; 667 iommus = <&apps_smmu 0xc0 0x0>; 668 669 qcom,dll-config = <0x000f642c>; 670 qcom,ddr-config = <0x80040868>; 671 bus-width = <8>; 672 673 status = "disabled"; 674 }; 675 676 sdhc_2: mmc@4784000 { 677 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 678 reg = <0x0 0x04784000 0x0 0x1000>; 679 reg-names = "hc"; 680 681 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 683 interrupt-names = "hc_irq", "pwr_irq"; 684 685 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 686 <&gcc GCC_SDCC2_APPS_CLK>, 687 <&rpmcc RPM_SMD_XO_CLK_SRC>; 688 clock-names = "iface", 689 "core", 690 "xo"; 691 692 resets = <&gcc GCC_SDCC2_BCR>; 693 694 power-domains = <&rpmpd QCM2290_VDDCX>; 695 operating-points-v2 = <&sdhc2_opp_table>; 696 iommus = <&apps_smmu 0xa0 0x0>; 697 698 qcom,dll-config = <0x0007642c>; 699 qcom,ddr-config = <0x80040868>; 700 bus-width = <4>; 701 702 status = "disabled"; 703 704 sdhc2_opp_table: opp-table { 705 compatible = "operating-points-v2"; 706 707 opp-100000000 { 708 opp-hz = /bits/ 64 <100000000>; 709 required-opps = <&rpmpd_opp_low_svs>; 710 }; 711 712 opp-202000000 { 713 opp-hz = /bits/ 64 <202000000>; 714 required-opps = <&rpmpd_opp_svs_plus>; 715 }; 716 }; 717 }; 718 719 gpi_dma0: dma-controller@4a00000 { 720 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 721 reg = <0x0 0x04a00000 0x0 0x60000>; 722 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 732 dma-channels = <10>; 733 dma-channel-mask = <0x1f>; 734 iommus = <&apps_smmu 0xf6 0x0>; 735 #dma-cells = <3>; 736 status = "disabled"; 737 }; 738 739 qupv3_id_0: geniqup@4ac0000 { 740 compatible = "qcom,geni-se-qup"; 741 reg = <0x0 0x04ac0000 0x0 0x2000>; 742 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 743 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 744 clock-names = "m-ahb", "s-ahb"; 745 iommus = <&apps_smmu 0xe3 0x0>; 746 #address-cells = <2>; 747 #size-cells = <2>; 748 ranges; 749 status = "disabled"; 750 751 i2c0: i2c@4a80000 { 752 compatible = "qcom,geni-i2c"; 753 reg = <0x0 0x04a80000 0x0 0x4000>; 754 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 756 clock-names = "se"; 757 pinctrl-0 = <&qup_i2c0_default>; 758 pinctrl-names = "default"; 759 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 760 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 761 dma-names = "tx", "rx"; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 status = "disabled"; 765 }; 766 767 spi0: spi@4a80000 { 768 compatible = "qcom,geni-spi"; 769 reg = <0x0 0x04a80000 0x0 0x4000>; 770 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 772 clock-names = "se"; 773 pinctrl-0 = <&qup_spi0_default>; 774 pinctrl-names = "default"; 775 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 776 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 777 dma-names = "tx", "rx"; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 status = "disabled"; 781 }; 782 783 uart0: serial@4a80000 { 784 compatible = "qcom,geni-uart"; 785 reg = <0x0 0x04a80000 0x0 0x4000>; 786 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 788 clock-names = "se"; 789 pinctrl-0 = <&qup_uart0_default>; 790 pinctrl-names = "default"; 791 status = "disabled"; 792 }; 793 794 i2c1: i2c@4a84000 { 795 compatible = "qcom,geni-i2c"; 796 reg = <0x0 0x04a84000 0x0 0x4000>; 797 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 799 clock-names = "se"; 800 pinctrl-0 = <&qup_i2c1_default>; 801 pinctrl-names = "default"; 802 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 803 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 804 dma-names = "tx", "rx"; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 spi1: spi@4a84000 { 811 compatible = "qcom,geni-spi"; 812 reg = <0x0 0x04a84000 0x0 0x4000>; 813 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 815 clock-names = "se"; 816 pinctrl-0 = <&qup_spi1_default>; 817 pinctrl-names = "default"; 818 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 819 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 820 dma-names = "tx", "rx"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 i2c2: i2c@4a88000 { 827 compatible = "qcom,geni-i2c"; 828 reg = <0x0 0x04a88000 0x0 0x4000>; 829 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 831 clock-names = "se"; 832 pinctrl-0 = <&qup_i2c2_default>; 833 pinctrl-names = "default"; 834 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 835 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 836 dma-names = "tx", "rx"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 spi2: spi@4a88000 { 843 compatible = "qcom,geni-spi"; 844 reg = <0x0 0x04a88000 0x0 0x4000>; 845 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 847 clock-names = "se"; 848 pinctrl-0 = <&qup_spi2_default>; 849 pinctrl-names = "default"; 850 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 851 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 852 dma-names = "tx", "rx"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 status = "disabled"; 856 }; 857 858 i2c3: i2c@4a8c000 { 859 compatible = "qcom,geni-i2c"; 860 reg = <0x0 0x04a8c000 0x0 0x4000>; 861 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 863 clock-names = "se"; 864 pinctrl-0 = <&qup_i2c3_default>; 865 pinctrl-names = "default"; 866 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 867 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 868 dma-names = "tx", "rx"; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 status = "disabled"; 872 }; 873 874 spi3: spi@4a8c000 { 875 compatible = "qcom,geni-spi"; 876 reg = <0x0 0x04a8c000 0x0 0x4000>; 877 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 879 clock-names = "se"; 880 pinctrl-0 = <&qup_spi3_default>; 881 pinctrl-names = "default"; 882 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 883 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 884 dma-names = "tx", "rx"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 status = "disabled"; 888 }; 889 890 i2c4: i2c@4a90000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0x0 0x04a90000 0x0 0x4000>; 893 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 895 clock-names = "se"; 896 pinctrl-0 = <&qup_i2c4_default>; 897 pinctrl-names = "default"; 898 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 899 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 900 dma-names = "tx", "rx"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 spi4: spi@4a90000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0x0 0x04a90000 0x0 0x4000>; 909 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi4_default>; 914 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 915 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 922 uart4: serial@4a90000 { 923 compatible = "qcom,geni-uart"; 924 reg = <0x0 0x04a90000 0x0 0x4000>; 925 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 927 clock-names = "se"; 928 pinctrl-0 = <&qup_uart4_default>; 929 pinctrl-names = "default"; 930 status = "disabled"; 931 }; 932 933 i2c5: i2c@4a94000 { 934 compatible = "qcom,geni-i2c"; 935 reg = <0x0 0x04a94000 0x0 0x4000>; 936 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 938 clock-names = "se"; 939 pinctrl-0 = <&qup_i2c5_default>; 940 pinctrl-names = "default"; 941 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 942 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 943 dma-names = "tx", "rx"; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 status = "disabled"; 947 }; 948 949 spi5: spi@4a94000 { 950 compatible = "qcom,geni-spi"; 951 reg = <0x0 0x04a94000 0x0 0x4000>; 952 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 954 clock-names = "se"; 955 pinctrl-0 = <&qup_spi5_default>; 956 pinctrl-names = "default"; 957 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 958 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 959 dma-names = "tx", "rx"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 status = "disabled"; 963 }; 964 }; 965 966 usb: usb@4ef8800 { 967 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 968 reg = <0x0 0x04ef8800 0x0 0x400>; 969 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 972 973 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 974 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 975 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 976 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 977 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 978 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 979 clock-names = "cfg_noc", 980 "core", 981 "iface", 982 "sleep", 983 "mock_utmi", 984 "xo"; 985 986 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 987 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 988 assigned-clock-rates = <19200000>, <133333333>; 989 990 resets = <&gcc GCC_USB30_PRIM_BCR>; 991 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 992 wakeup-source; 993 994 #address-cells = <2>; 995 #size-cells = <2>; 996 ranges; 997 998 status = "disabled"; 999 1000 usb_dwc3: usb@4e00000 { 1001 compatible = "snps,dwc3"; 1002 reg = <0x0 0x04e00000 0x0 0xcd00>; 1003 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1004 phys = <&usb_hsphy>; 1005 phy-names = "usb2-phy"; 1006 iommus = <&apps_smmu 0x120 0x0>; 1007 snps,dis_u2_susphy_quirk; 1008 snps,dis_enblslpm_quirk; 1009 snps,has-lpm-erratum; 1010 snps,hird-threshold = /bits/ 8 <0x10>; 1011 snps,usb3_lpm_capable; 1012 maximum-speed = "super-speed"; 1013 dr_mode = "otg"; 1014 }; 1015 }; 1016 1017 remoteproc_mpss: remoteproc@6080000 { 1018 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 1019 reg = <0x0 0x06080000 0x0 0x100>; 1020 1021 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1022 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1023 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1024 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1025 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1026 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1027 interrupt-names = "wdog", 1028 "fatal", 1029 "ready", 1030 "handover", 1031 "stop-ack", 1032 "shutdown-ack"; 1033 1034 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1035 clock-names = "xo"; 1036 1037 power-domains = <&rpmpd QCM2290_VDDCX>; 1038 1039 memory-region = <&pil_modem_mem>; 1040 1041 qcom,smem-states = <&modem_smp2p_out 0>; 1042 qcom,smem-state-names = "stop"; 1043 1044 status = "disabled"; 1045 1046 glink-edge { 1047 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1048 label = "mpss"; 1049 qcom,remote-pid = <1>; 1050 mboxes = <&apcs_glb 12>; 1051 }; 1052 }; 1053 1054 remoteproc_adsp: remoteproc@ab00000 { 1055 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 1056 reg = <0x0 0x0ab00000 0x0 0x100>; 1057 1058 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1059 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1060 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1061 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1062 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1063 interrupt-names = "wdog", 1064 "fatal", 1065 "ready", 1066 "handover", 1067 "stop-ack"; 1068 1069 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1070 clock-names = "xo"; 1071 1072 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 1073 <&rpmpd QCM2290_VDD_LPI_MX>; 1074 1075 memory-region = <&pil_adsp_mem>; 1076 1077 qcom,smem-states = <&adsp_smp2p_out 0>; 1078 qcom,smem-state-names = "stop"; 1079 1080 status = "disabled"; 1081 1082 glink-edge { 1083 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 1084 label = "lpass"; 1085 qcom,remote-pid = <2>; 1086 mboxes = <&apcs_glb 8>; 1087 }; 1088 }; 1089 1090 apps_smmu: iommu@c600000 { 1091 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1092 reg = <0x0 0x0c600000 0x0 0x80000>; 1093 #iommu-cells = <2>; 1094 #global-interrupts = <1>; 1095 1096 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1161 }; 1162 1163 wifi: wifi@c800000 { 1164 compatible = "qcom,wcn3990-wifi"; 1165 reg = <0x0 0x0c800000 0x0 0x800000>; 1166 reg-names = "membase"; 1167 memory-region = <&wlan_msa_mem>; 1168 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1180 iommus = <&apps_smmu 0x1a0 0x1>; 1181 qcom,msa-fixed-perm; 1182 status = "disabled"; 1183 }; 1184 1185 watchdog@f017000 { 1186 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 1187 reg = <0x0 0x0f017000 0x0 0x1000>; 1188 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1189 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&sleep_clk>; 1191 }; 1192 1193 apcs_glb: mailbox@f111000 { 1194 compatible = "qcom,qcm2290-apcs-hmss-global"; 1195 reg = <0x0 0x0f111000 0x0 0x1000>; 1196 #mbox-cells = <1>; 1197 }; 1198 1199 timer@f120000 { 1200 compatible = "arm,armv7-timer-mem"; 1201 reg = <0x0 0x0f120000 0x0 0x1000>; 1202 #address-cells = <1>; 1203 #size-cells = <1>; 1204 ranges = <0 0x0 0x0f121000 0x8000>; 1205 1206 frame@0 { 1207 reg = <0x0 0x1000>, 1208 <0x1000 0x1000>; 1209 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1211 frame-number = <0>; 1212 }; 1213 1214 frame@2000 { 1215 reg = <0x2000 0x1000>; 1216 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1217 frame-number = <1>; 1218 status = "disabled"; 1219 }; 1220 1221 frame@3000 { 1222 reg = <0x3000 0x1000>; 1223 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1224 frame-number = <2>; 1225 status = "disabled"; 1226 }; 1227 1228 frame@4000 { 1229 reg = <0x4000 0x1000>; 1230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1231 frame-number = <3>; 1232 status = "disabled"; 1233 }; 1234 1235 frame@5000 { 1236 reg = <0x5000 0x1000>; 1237 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1238 frame-number = <4>; 1239 status = "disabled"; 1240 }; 1241 1242 frame@6000 { 1243 reg = <0x6000 0x1000>; 1244 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1245 frame-number = <5>; 1246 status = "disabled"; 1247 }; 1248 1249 frame@7000 { 1250 reg = <0x7000 0x1000>; 1251 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1252 frame-number = <6>; 1253 status = "disabled"; 1254 }; 1255 }; 1256 1257 intc: interrupt-controller@f200000 { 1258 compatible = "arm,gic-v3"; 1259 reg = <0x0 0x0f200000 0x0 0x10000>, 1260 <0x0 0x0f300000 0x0 0x100000>; 1261 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1262 #interrupt-cells = <3>; 1263 interrupt-controller; 1264 interrupt-parent = <&intc>; 1265 #redistributor-regions = <1>; 1266 redistributor-stride = <0x0 0x20000>; 1267 }; 1268 1269 cpufreq_hw: cpufreq@f521000 { 1270 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 1271 reg = <0x0 0x0f521000 0x0 0x1000>; 1272 reg-names = "freq-domain0"; 1273 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1274 interrupt-names = "dcvsh-irq-0"; 1275 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1276 clock-names = "xo", "alternate"; 1277 1278 #freq-domain-cells = <1>; 1279 #clock-cells = <1>; 1280 }; 1281 }; 1282 1283 thermal-zones { 1284 mapss-thermal { 1285 polling-delay-passive = <0>; 1286 polling-delay = <0>; 1287 1288 thermal-sensors = <&tsens0 0>; 1289 1290 trips { 1291 mapss_alert0: trip-point0 { 1292 temperature = <90000>; 1293 hysteresis = <2000>; 1294 type = "passive"; 1295 }; 1296 1297 mapss_alert1: trip-point1 { 1298 temperature = <95000>; 1299 hysteresis = <2000>; 1300 type = "passive"; 1301 }; 1302 1303 mapss_crit: mapss-crit { 1304 temperature = <110000>; 1305 hysteresis = <1000>; 1306 type = "critical"; 1307 }; 1308 }; 1309 }; 1310 1311 video-thermal { 1312 polling-delay-passive = <0>; 1313 polling-delay = <0>; 1314 1315 thermal-sensors = <&tsens0 1>; 1316 1317 trips { 1318 video_alert0: trip-point0 { 1319 temperature = <90000>; 1320 hysteresis = <2000>; 1321 type = "passive"; 1322 }; 1323 1324 video_alert1: trip-point1 { 1325 temperature = <95000>; 1326 hysteresis = <2000>; 1327 type = "passive"; 1328 }; 1329 1330 video_crit: video-crit { 1331 temperature = <110000>; 1332 hysteresis = <1000>; 1333 type = "critical"; 1334 }; 1335 }; 1336 }; 1337 1338 wlan-thermal { 1339 polling-delay-passive = <0>; 1340 polling-delay = <0>; 1341 1342 thermal-sensors = <&tsens0 2>; 1343 1344 trips { 1345 wlan_alert0: trip-point0 { 1346 temperature = <90000>; 1347 hysteresis = <2000>; 1348 type = "passive"; 1349 }; 1350 1351 wlan_alert1: trip-point1 { 1352 temperature = <95000>; 1353 hysteresis = <2000>; 1354 type = "passive"; 1355 }; 1356 1357 wlan_crit: wlan-crit { 1358 temperature = <110000>; 1359 hysteresis = <1000>; 1360 type = "critical"; 1361 }; 1362 }; 1363 }; 1364 1365 cpuss0-thermal { 1366 polling-delay-passive = <0>; 1367 polling-delay = <0>; 1368 1369 thermal-sensors = <&tsens0 3>; 1370 1371 trips { 1372 cpuss0_alert0: trip-point0 { 1373 temperature = <90000>; 1374 hysteresis = <2000>; 1375 type = "passive"; 1376 }; 1377 1378 cpuss0_alert1: trip-point1 { 1379 temperature = <95000>; 1380 hysteresis = <2000>; 1381 type = "passive"; 1382 }; 1383 1384 cpuss0_crit: cpuss0-crit { 1385 temperature = <110000>; 1386 hysteresis = <1000>; 1387 type = "critical"; 1388 }; 1389 }; 1390 }; 1391 1392 cpuss1-thermal { 1393 polling-delay-passive = <0>; 1394 polling-delay = <0>; 1395 1396 thermal-sensors = <&tsens0 4>; 1397 1398 trips { 1399 cpuss1_alert0: trip-point0 { 1400 temperature = <90000>; 1401 hysteresis = <2000>; 1402 type = "passive"; 1403 }; 1404 1405 cpuss1_alert1: trip-point1 { 1406 temperature = <95000>; 1407 hysteresis = <2000>; 1408 type = "passive"; 1409 }; 1410 1411 cpuss1_crit: cpuss1-crit { 1412 temperature = <110000>; 1413 hysteresis = <1000>; 1414 type = "critical"; 1415 }; 1416 }; 1417 }; 1418 1419 mdm0-thermal { 1420 polling-delay-passive = <0>; 1421 polling-delay = <0>; 1422 1423 thermal-sensors = <&tsens0 5>; 1424 1425 trips { 1426 mdm0_alert0: trip-point0 { 1427 temperature = <90000>; 1428 hysteresis = <2000>; 1429 type = "passive"; 1430 }; 1431 1432 mdm0_alert1: trip-point1 { 1433 temperature = <95000>; 1434 hysteresis = <2000>; 1435 type = "passive"; 1436 }; 1437 1438 mdm0_crit: mdm0-crit { 1439 temperature = <110000>; 1440 hysteresis = <1000>; 1441 type = "critical"; 1442 }; 1443 }; 1444 }; 1445 1446 mdm1-thermal { 1447 polling-delay-passive = <0>; 1448 polling-delay = <0>; 1449 1450 thermal-sensors = <&tsens0 6>; 1451 1452 trips { 1453 mdm1_alert0: trip-point0 { 1454 temperature = <90000>; 1455 hysteresis = <2000>; 1456 type = "passive"; 1457 }; 1458 1459 mdm1_alert1: trip-point1 { 1460 temperature = <95000>; 1461 hysteresis = <2000>; 1462 type = "passive"; 1463 }; 1464 1465 mdm1_crit: mdm1-crit { 1466 temperature = <110000>; 1467 hysteresis = <1000>; 1468 type = "critical"; 1469 }; 1470 }; 1471 }; 1472 1473 gpu-thermal { 1474 polling-delay-passive = <0>; 1475 polling-delay = <0>; 1476 1477 thermal-sensors = <&tsens0 7>; 1478 1479 trips { 1480 gpu_alert0: trip-point0 { 1481 temperature = <90000>; 1482 hysteresis = <2000>; 1483 type = "passive"; 1484 }; 1485 1486 gpu_alert1: trip-point1 { 1487 temperature = <95000>; 1488 hysteresis = <2000>; 1489 type = "passive"; 1490 }; 1491 1492 gpu_crit: gpu-crit { 1493 temperature = <110000>; 1494 hysteresis = <1000>; 1495 type = "critical"; 1496 }; 1497 }; 1498 }; 1499 1500 hm-center-thermal { 1501 polling-delay-passive = <0>; 1502 polling-delay = <0>; 1503 1504 thermal-sensors = <&tsens0 8>; 1505 1506 trips { 1507 hm_center_alert0: trip-point0 { 1508 temperature = <90000>; 1509 hysteresis = <2000>; 1510 type = "passive"; 1511 }; 1512 1513 hm_center_alert1: trip-point1 { 1514 temperature = <95000>; 1515 hysteresis = <2000>; 1516 type = "passive"; 1517 }; 1518 1519 hm_center_crit: hm-center-crit { 1520 temperature = <110000>; 1521 hysteresis = <1000>; 1522 type = "critical"; 1523 }; 1524 }; 1525 }; 1526 1527 camera-thermal { 1528 polling-delay-passive = <0>; 1529 polling-delay = <0>; 1530 1531 thermal-sensors = <&tsens0 9>; 1532 1533 trips { 1534 camera_alert0: trip-point0 { 1535 temperature = <90000>; 1536 hysteresis = <2000>; 1537 type = "passive"; 1538 }; 1539 1540 camera_alert1: trip-point1 { 1541 temperature = <95000>; 1542 hysteresis = <2000>; 1543 type = "passive"; 1544 }; 1545 1546 camera_crit: camera-crit { 1547 temperature = <110000>; 1548 hysteresis = <1000>; 1549 type = "critical"; 1550 }; 1551 }; 1552 }; 1553 }; 1554 1555 timer { 1556 compatible = "arm,armv8-timer"; 1557 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1558 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1559 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1560 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1561 }; 1562}; 1563