1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32764>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 46 capacity-dmips-mhz = <1024>; 47 dynamic-power-coefficient = <100>; 48 enable-method = "psci"; 49 next-level-cache = <&L2_0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 51 power-domains = <&CPU_PD0>; 52 power-domain-names = "psci"; 53 L2_0: l2-cache { 54 compatible = "cache"; 55 cache-level = <2>; 56 cache-unified; 57 }; 58 }; 59 60 CPU1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x1>; 64 clocks = <&cpufreq_hw 0>; 65 capacity-dmips-mhz = <1024>; 66 dynamic-power-coefficient = <100>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_0>; 69 qcom,freq-domain = <&cpufreq_hw 0>; 70 power-domains = <&CPU_PD1>; 71 power-domain-names = "psci"; 72 }; 73 74 CPU2: cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x2>; 78 clocks = <&cpufreq_hw 0>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 power-domains = <&CPU_PD2>; 85 power-domain-names = "psci"; 86 }; 87 88 CPU3: cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x0 0x3>; 92 clocks = <&cpufreq_hw 0>; 93 capacity-dmips-mhz = <1024>; 94 dynamic-power-coefficient = <100>; 95 enable-method = "psci"; 96 next-level-cache = <&L2_0>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 power-domains = <&CPU_PD3>; 99 power-domain-names = "psci"; 100 }; 101 102 cpu-map { 103 cluster0 { 104 core0 { 105 cpu = <&CPU0>; 106 }; 107 108 core1 { 109 cpu = <&CPU1>; 110 }; 111 112 core2 { 113 cpu = <&CPU2>; 114 }; 115 116 core3 { 117 cpu = <&CPU3>; 118 }; 119 }; 120 }; 121 122 domain-idle-states { 123 CLUSTER_SLEEP: cluster-sleep-0 { 124 compatible = "domain-idle-state"; 125 arm,psci-suspend-param = <0x41000043>; 126 entry-latency-us = <800>; 127 exit-latency-us = <2118>; 128 min-residency-us = <7376>; 129 }; 130 }; 131 132 idle-states { 133 entry-method = "psci"; 134 135 CPU_SLEEP: cpu-sleep-0 { 136 compatible = "arm,idle-state"; 137 idle-state-name = "power-collapse"; 138 arm,psci-suspend-param = <0x40000003>; 139 entry-latency-us = <290>; 140 exit-latency-us = <376>; 141 min-residency-us = <1182>; 142 local-timer-stop; 143 }; 144 }; 145 }; 146 147 firmware { 148 scm: scm { 149 compatible = "qcom,scm-qcm2290", "qcom,scm"; 150 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 151 clock-names = "core"; 152 #reset-cells = <1>; 153 }; 154 }; 155 156 memory@40000000 { 157 device_type = "memory"; 158 /* We expect the bootloader to fill in the size */ 159 reg = <0 0x40000000 0 0>; 160 }; 161 162 pmu { 163 compatible = "arm,armv8-pmuv3"; 164 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 171 CPU_PD0: power-domain-cpu0 { 172 #power-domain-cells = <0>; 173 power-domains = <&CLUSTER_PD>; 174 domain-idle-states = <&CPU_SLEEP>; 175 }; 176 177 CPU_PD1: power-domain-cpu1 { 178 #power-domain-cells = <0>; 179 power-domains = <&CLUSTER_PD>; 180 domain-idle-states = <&CPU_SLEEP>; 181 }; 182 183 CPU_PD2: power-domain-cpu2 { 184 #power-domain-cells = <0>; 185 power-domains = <&CLUSTER_PD>; 186 domain-idle-states = <&CPU_SLEEP>; 187 }; 188 189 CPU_PD3: power-domain-cpu3 { 190 #power-domain-cells = <0>; 191 power-domains = <&CLUSTER_PD>; 192 domain-idle-states = <&CPU_SLEEP>; 193 }; 194 195 CLUSTER_PD: power-domain-cpu-cluster { 196 #power-domain-cells = <0>; 197 domain-idle-states = <&CLUSTER_SLEEP>; 198 }; 199 }; 200 201 rpm: remoteproc { 202 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 203 204 glink-edge { 205 compatible = "qcom,glink-rpm"; 206 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 207 qcom,rpm-msg-ram = <&rpm_msg_ram>; 208 mboxes = <&apcs_glb 0>; 209 210 rpm_requests: rpm-requests { 211 compatible = "qcom,rpm-qcm2290"; 212 qcom,glink-channels = "rpm_requests"; 213 214 rpmcc: clock-controller { 215 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 216 clocks = <&xo_board>; 217 clock-names = "xo"; 218 #clock-cells = <1>; 219 }; 220 221 rpmpd: power-controller { 222 compatible = "qcom,qcm2290-rpmpd"; 223 #power-domain-cells = <1>; 224 operating-points-v2 = <&rpmpd_opp_table>; 225 226 rpmpd_opp_table: opp-table { 227 compatible = "operating-points-v2"; 228 229 rpmpd_opp_min_svs: opp1 { 230 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 231 }; 232 233 rpmpd_opp_low_svs: opp2 { 234 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 235 }; 236 237 rpmpd_opp_svs: opp3 { 238 opp-level = <RPM_SMD_LEVEL_SVS>; 239 }; 240 241 rpmpd_opp_svs_plus: opp4 { 242 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 243 }; 244 245 rpmpd_opp_nom: opp5 { 246 opp-level = <RPM_SMD_LEVEL_NOM>; 247 }; 248 249 rpmpd_opp_nom_plus: opp6 { 250 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 251 }; 252 253 rpmpd_opp_turbo: opp7 { 254 opp-level = <RPM_SMD_LEVEL_TURBO>; 255 }; 256 257 rpmpd_opp_turbo_plus: opp8 { 258 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 259 }; 260 }; 261 }; 262 }; 263 }; 264 }; 265 266 reserved_memory: reserved-memory { 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges; 270 271 hyp_mem: hyp@45700000 { 272 reg = <0x0 0x45700000 0x0 0x600000>; 273 no-map; 274 }; 275 276 xbl_aop_mem: xbl-aop@45e00000 { 277 reg = <0x0 0x45e00000 0x0 0x140000>; 278 no-map; 279 }; 280 281 sec_apps_mem: sec-apps@45fff000 { 282 reg = <0x0 0x45fff000 0x0 0x1000>; 283 no-map; 284 }; 285 286 smem_mem: smem@46000000 { 287 compatible = "qcom,smem"; 288 reg = <0x0 0x46000000 0x0 0x200000>; 289 no-map; 290 291 hwlocks = <&tcsr_mutex 3>; 292 qcom,rpm-msg-ram = <&rpm_msg_ram>; 293 }; 294 295 pil_modem_mem: modem@4ab00000 { 296 reg = <0x0 0x4ab00000 0x0 0x6900000>; 297 no-map; 298 }; 299 300 pil_video_mem: video@51400000 { 301 reg = <0x0 0x51400000 0x0 0x500000>; 302 no-map; 303 }; 304 305 wlan_msa_mem: wlan-msa@51900000 { 306 reg = <0x0 0x51900000 0x0 0x100000>; 307 no-map; 308 }; 309 310 pil_adsp_mem: adsp@51a00000 { 311 reg = <0x0 0x51a00000 0x0 0x1c00000>; 312 no-map; 313 }; 314 315 pil_ipa_fw_mem: ipa-fw@53600000 { 316 reg = <0x0 0x53600000 0x0 0x10000>; 317 no-map; 318 }; 319 320 pil_ipa_gsi_mem: ipa-gsi@53610000 { 321 reg = <0x0 0x53610000 0x0 0x5000>; 322 no-map; 323 }; 324 325 pil_gpu_mem: zap@53615000 { 326 compatible = "shared-dma-pool"; 327 reg = <0x0 0x53615000 0x0 0x2000>; 328 no-map; 329 }; 330 331 cont_splash_memory: framebuffer@5c000000 { 332 reg = <0x0 0x5c000000 0x0 0x00f00000>; 333 no-map; 334 }; 335 336 dfps_data_memory: dpfs-data@5cf00000 { 337 reg = <0x0 0x5cf00000 0x0 0x0100000>; 338 no-map; 339 }; 340 341 removed_mem: reserved@60000000 { 342 reg = <0x0 0x60000000 0x0 0x3900000>; 343 no-map; 344 }; 345 346 rmtfs_mem: memory@89b01000 { 347 compatible = "qcom,rmtfs-mem"; 348 reg = <0x0 0x89b01000 0x0 0x200000>; 349 no-map; 350 351 qcom,client-id = <1>; 352 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 353 }; 354 }; 355 356 smp2p-adsp { 357 compatible = "qcom,smp2p"; 358 qcom,smem = <443>, <429>; 359 360 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 361 362 mboxes = <&apcs_glb 10>; 363 364 qcom,local-pid = <0>; 365 qcom,remote-pid = <2>; 366 367 adsp_smp2p_out: master-kernel { 368 qcom,entry-name = "master-kernel"; 369 #qcom,smem-state-cells = <1>; 370 }; 371 372 adsp_smp2p_in: slave-kernel { 373 qcom,entry-name = "slave-kernel"; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 }; 377 }; 378 379 smp2p-mpss { 380 compatible = "qcom,smp2p"; 381 qcom,smem = <435>, <428>; 382 383 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 384 385 mboxes = <&apcs_glb 14>; 386 387 qcom,local-pid = <0>; 388 qcom,remote-pid = <1>; 389 390 modem_smp2p_out: master-kernel { 391 qcom,entry-name = "master-kernel"; 392 #qcom,smem-state-cells = <1>; 393 }; 394 395 modem_smp2p_in: slave-kernel { 396 qcom,entry-name = "slave-kernel"; 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 }; 400 401 wlan_smp2p_in: wlan-wpss-to-ap { 402 qcom,entry-name = "wlan"; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 }; 407 408 soc: soc@0 { 409 compatible = "simple-bus"; 410 #address-cells = <2>; 411 #size-cells = <2>; 412 ranges = <0 0 0 0 0x10 0>; 413 dma-ranges = <0 0 0 0 0x10 0>; 414 415 tcsr_mutex: hwlock@340000 { 416 compatible = "qcom,tcsr-mutex"; 417 reg = <0x0 0x00340000 0x0 0x20000>; 418 #hwlock-cells = <1>; 419 }; 420 421 tcsr_regs: syscon@3c0000 { 422 compatible = "qcom,qcm2290-tcsr", "syscon"; 423 reg = <0x0 0x003c0000 0x0 0x40000>; 424 }; 425 426 tlmm: pinctrl@500000 { 427 compatible = "qcom,qcm2290-tlmm"; 428 reg = <0x0 0x00500000 0x0 0x300000>; 429 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 430 gpio-controller; 431 gpio-ranges = <&tlmm 0 0 127>; 432 #gpio-cells = <2>; 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 436 qup_i2c0_default: qup-i2c0-default-state { 437 pins = "gpio0", "gpio1"; 438 function = "qup0"; 439 drive-strength = <2>; 440 bias-pull-up; 441 }; 442 443 qup_i2c1_default: qup-i2c1-default-state { 444 pins = "gpio4", "gpio5"; 445 function = "qup1"; 446 drive-strength = <2>; 447 bias-pull-up; 448 }; 449 450 qup_i2c2_default: qup-i2c2-default-state { 451 pins = "gpio6", "gpio7"; 452 function = "qup2"; 453 drive-strength = <2>; 454 bias-pull-up; 455 }; 456 457 qup_i2c3_default: qup-i2c3-default-state { 458 pins = "gpio8", "gpio9"; 459 function = "qup3"; 460 drive-strength = <2>; 461 bias-pull-up; 462 }; 463 464 qup_i2c4_default: qup-i2c4-default-state { 465 pins = "gpio12", "gpio13"; 466 function = "qup4"; 467 drive-strength = <2>; 468 bias-pull-up; 469 }; 470 471 qup_i2c5_default: qup-i2c5-default-state { 472 pins = "gpio14", "gpio15"; 473 function = "qup5"; 474 drive-strength = <2>; 475 bias-pull-up; 476 }; 477 478 qup_spi0_default: qup-spi0-default-state { 479 pins = "gpio0", "gpio1","gpio2", "gpio3"; 480 function = "qup0"; 481 drive-strength = <2>; 482 bias-pull-up; 483 }; 484 485 qup_spi1_default: qup-spi1-default-state { 486 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 487 function = "qup1"; 488 drive-strength = <2>; 489 bias-pull-up; 490 }; 491 492 qup_spi2_default: qup-spi2-default-state { 493 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 494 function = "qup2"; 495 drive-strength = <2>; 496 bias-pull-up; 497 }; 498 499 qup_spi3_default: qup-spi3-default-state { 500 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 501 function = "qup3"; 502 drive-strength = <2>; 503 bias-pull-up; 504 }; 505 506 qup_spi4_default: qup-spi4-default-state { 507 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 508 function = "qup4"; 509 drive-strength = <2>; 510 bias-pull-up; 511 }; 512 513 qup_spi5_default: qup-spi5-default-state { 514 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 515 function = "qup5"; 516 drive-strength = <2>; 517 bias-pull-up; 518 }; 519 520 qup_uart0_default: qup-uart0-default-state { 521 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 522 function = "qup0"; 523 drive-strength = <2>; 524 bias-disable; 525 }; 526 527 qup_uart4_default: qup-uart4-default-state { 528 pins = "gpio12", "gpio13"; 529 function = "qup4"; 530 drive-strength = <2>; 531 bias-disable; 532 }; 533 534 sdc1_state_on: sdc1-on-state { 535 clk-pins { 536 pins = "sdc1_clk"; 537 drive-strength = <16>; 538 bias-disable; 539 }; 540 541 cmd-pins { 542 pins = "sdc1_cmd"; 543 drive-strength = <10>; 544 bias-pull-up; 545 }; 546 547 data-pins { 548 pins = "sdc1_data"; 549 drive-strength = <10>; 550 bias-pull-up; 551 }; 552 553 rclk-pins { 554 pins = "sdc1_rclk"; 555 bias-pull-down; 556 }; 557 }; 558 559 sdc1_state_off: sdc1-off-state { 560 clk-pins { 561 pins = "sdc1_clk"; 562 drive-strength = <2>; 563 bias-disable; 564 }; 565 566 cmd-pins { 567 pins = "sdc1_cmd"; 568 drive-strength = <2>; 569 bias-pull-up; 570 }; 571 572 data-pins { 573 pins = "sdc1_data"; 574 drive-strength = <2>; 575 bias-pull-up; 576 }; 577 578 rclk-pins { 579 pins = "sdc1_rclk"; 580 bias-pull-down; 581 }; 582 }; 583 584 sdc2_state_on: sdc2-on-state { 585 clk-pins { 586 pins = "sdc2_clk"; 587 drive-strength = <16>; 588 bias-disable; 589 }; 590 591 cmd-pins { 592 pins = "sdc2_cmd"; 593 drive-strength = <10>; 594 bias-pull-up; 595 }; 596 597 data-pins { 598 pins = "sdc2_data"; 599 drive-strength = <10>; 600 bias-pull-up; 601 }; 602 }; 603 604 sdc2_state_off: sdc2-off-state { 605 clk-pins { 606 pins = "sdc2_clk"; 607 drive-strength = <2>; 608 bias-disable; 609 }; 610 611 cmd-pins { 612 pins = "sdc2_cmd"; 613 drive-strength = <2>; 614 bias-pull-up; 615 }; 616 617 data-pins { 618 pins = "sdc2_data"; 619 drive-strength = <2>; 620 bias-pull-up; 621 }; 622 }; 623 }; 624 625 gcc: clock-controller@1400000 { 626 compatible = "qcom,gcc-qcm2290"; 627 reg = <0x0 0x01400000 0x0 0x1f0000>; 628 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 629 clock-names = "bi_tcxo", "sleep_clk"; 630 #clock-cells = <1>; 631 #reset-cells = <1>; 632 #power-domain-cells = <1>; 633 }; 634 635 usb_hsphy: phy@1613000 { 636 compatible = "qcom,qcm2290-qusb2-phy"; 637 reg = <0x0 0x01613000 0x0 0x180>; 638 639 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 640 <&rpmcc RPM_SMD_XO_CLK_SRC>; 641 clock-names = "cfg_ahb", "ref"; 642 643 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 644 nvmem-cells = <&qusb2_hstx_trim>; 645 #phy-cells = <0>; 646 647 status = "disabled"; 648 }; 649 650 usb_qmpphy: phy@1615000 { 651 compatible = "qcom,qcm2290-qmp-usb3-phy"; 652 reg = <0x0 0x01615000 0x0 0x1000>; 653 654 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 655 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 656 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 657 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 658 clock-names = "cfg_ahb", 659 "ref", 660 "com_aux", 661 "pipe"; 662 663 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 664 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 665 reset-names = "phy", 666 "phy_phy"; 667 668 #clock-cells = <0>; 669 clock-output-names = "usb3_phy_pipe_clk_src"; 670 671 #phy-cells = <0>; 672 673 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 674 675 status = "disabled"; 676 }; 677 678 qfprom@1b44000 { 679 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 680 reg = <0x0 0x01b44000 0x0 0x3000>; 681 #address-cells = <1>; 682 #size-cells = <1>; 683 684 qusb2_hstx_trim: hstx-trim@25b { 685 reg = <0x25b 0x1>; 686 bits = <1 4>; 687 }; 688 }; 689 690 spmi_bus: spmi@1c40000 { 691 compatible = "qcom,spmi-pmic-arb"; 692 reg = <0x0 0x01c40000 0x0 0x1100>, 693 <0x0 0x01e00000 0x0 0x2000000>, 694 <0x0 0x03e00000 0x0 0x100000>, 695 <0x0 0x03f00000 0x0 0xa0000>, 696 <0x0 0x01c0a000 0x0 0x26000>; 697 reg-names = "core", 698 "chnls", 699 "obsrvr", 700 "intr", 701 "cnfg"; 702 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "periph_irq"; 704 qcom,ee = <0>; 705 qcom,channel = <0>; 706 #address-cells = <2>; 707 #size-cells = <0>; 708 interrupt-controller; 709 #interrupt-cells = <4>; 710 }; 711 712 tsens0: thermal-sensor@4411000 { 713 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 714 reg = <0x0 0x04411000 0x0 0x1ff>, 715 <0x0 0x04410000 0x0 0x8>; 716 #qcom,sensors = <10>; 717 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "uplow", "critical"; 720 #thermal-sensor-cells = <1>; 721 }; 722 723 rng: rng@4453000 { 724 compatible = "qcom,prng-ee"; 725 reg = <0x0 0x04453000 0x0 0x1000>; 726 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 727 clock-names = "core"; 728 }; 729 730 rpm_msg_ram: sram@45f0000 { 731 compatible = "qcom,rpm-msg-ram"; 732 reg = <0x0 0x045f0000 0x0 0x7000>; 733 }; 734 735 sram@4690000 { 736 compatible = "qcom,rpm-stats"; 737 reg = <0x0 0x04690000 0x0 0x10000>; 738 }; 739 740 sdhc_1: mmc@4744000 { 741 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 742 reg = <0x0 0x04744000 0x0 0x1000>, 743 <0x0 0x04745000 0x0 0x1000>, 744 <0x0 0x04748000 0x0 0x8000>; 745 reg-names = "hc", 746 "cqhci", 747 "ice"; 748 749 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 751 interrupt-names = "hc_irq", "pwr_irq"; 752 753 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 754 <&gcc GCC_SDCC1_APPS_CLK>, 755 <&rpmcc RPM_SMD_XO_CLK_SRC>, 756 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 757 clock-names = "iface", 758 "core", 759 "xo", 760 "ice"; 761 762 resets = <&gcc GCC_SDCC1_BCR>; 763 764 power-domains = <&rpmpd QCM2290_VDDCX>; 765 iommus = <&apps_smmu 0xc0 0x0>; 766 767 qcom,dll-config = <0x000f642c>; 768 qcom,ddr-config = <0x80040868>; 769 bus-width = <8>; 770 771 status = "disabled"; 772 }; 773 774 sdhc_2: mmc@4784000 { 775 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 776 reg = <0x0 0x04784000 0x0 0x1000>; 777 reg-names = "hc"; 778 779 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 781 interrupt-names = "hc_irq", "pwr_irq"; 782 783 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 784 <&gcc GCC_SDCC2_APPS_CLK>, 785 <&rpmcc RPM_SMD_XO_CLK_SRC>; 786 clock-names = "iface", 787 "core", 788 "xo"; 789 790 resets = <&gcc GCC_SDCC2_BCR>; 791 792 power-domains = <&rpmpd QCM2290_VDDCX>; 793 operating-points-v2 = <&sdhc2_opp_table>; 794 iommus = <&apps_smmu 0xa0 0x0>; 795 796 qcom,dll-config = <0x0007642c>; 797 qcom,ddr-config = <0x80040868>; 798 bus-width = <4>; 799 800 status = "disabled"; 801 802 sdhc2_opp_table: opp-table { 803 compatible = "operating-points-v2"; 804 805 opp-100000000 { 806 opp-hz = /bits/ 64 <100000000>; 807 required-opps = <&rpmpd_opp_low_svs>; 808 }; 809 810 opp-202000000 { 811 opp-hz = /bits/ 64 <202000000>; 812 required-opps = <&rpmpd_opp_svs_plus>; 813 }; 814 }; 815 }; 816 817 gpi_dma0: dma-controller@4a00000 { 818 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 819 reg = <0x0 0x04a00000 0x0 0x60000>; 820 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 830 dma-channels = <10>; 831 dma-channel-mask = <0x1f>; 832 iommus = <&apps_smmu 0xf6 0x0>; 833 #dma-cells = <3>; 834 status = "disabled"; 835 }; 836 837 qupv3_id_0: geniqup@4ac0000 { 838 compatible = "qcom,geni-se-qup"; 839 reg = <0x0 0x04ac0000 0x0 0x2000>; 840 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 841 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 842 clock-names = "m-ahb", "s-ahb"; 843 iommus = <&apps_smmu 0xe3 0x0>; 844 #address-cells = <2>; 845 #size-cells = <2>; 846 ranges; 847 status = "disabled"; 848 849 i2c0: i2c@4a80000 { 850 compatible = "qcom,geni-i2c"; 851 reg = <0x0 0x04a80000 0x0 0x4000>; 852 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 854 clock-names = "se"; 855 pinctrl-0 = <&qup_i2c0_default>; 856 pinctrl-names = "default"; 857 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 858 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 859 dma-names = "tx", "rx"; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 status = "disabled"; 863 }; 864 865 spi0: spi@4a80000 { 866 compatible = "qcom,geni-spi"; 867 reg = <0x0 0x04a80000 0x0 0x4000>; 868 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 870 clock-names = "se"; 871 pinctrl-0 = <&qup_spi0_default>; 872 pinctrl-names = "default"; 873 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 874 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 875 dma-names = "tx", "rx"; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 status = "disabled"; 879 }; 880 881 uart0: serial@4a80000 { 882 compatible = "qcom,geni-uart"; 883 reg = <0x0 0x04a80000 0x0 0x4000>; 884 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 886 clock-names = "se"; 887 pinctrl-0 = <&qup_uart0_default>; 888 pinctrl-names = "default"; 889 status = "disabled"; 890 }; 891 892 i2c1: i2c@4a84000 { 893 compatible = "qcom,geni-i2c"; 894 reg = <0x0 0x04a84000 0x0 0x4000>; 895 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 897 clock-names = "se"; 898 pinctrl-0 = <&qup_i2c1_default>; 899 pinctrl-names = "default"; 900 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 901 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 902 dma-names = "tx", "rx"; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 status = "disabled"; 906 }; 907 908 spi1: spi@4a84000 { 909 compatible = "qcom,geni-spi"; 910 reg = <0x0 0x04a84000 0x0 0x4000>; 911 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 913 clock-names = "se"; 914 pinctrl-0 = <&qup_spi1_default>; 915 pinctrl-names = "default"; 916 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 917 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 918 dma-names = "tx", "rx"; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 status = "disabled"; 922 }; 923 924 i2c2: i2c@4a88000 { 925 compatible = "qcom,geni-i2c"; 926 reg = <0x0 0x04a88000 0x0 0x4000>; 927 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 929 clock-names = "se"; 930 pinctrl-0 = <&qup_i2c2_default>; 931 pinctrl-names = "default"; 932 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 933 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 934 dma-names = "tx", "rx"; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 status = "disabled"; 938 }; 939 940 spi2: spi@4a88000 { 941 compatible = "qcom,geni-spi"; 942 reg = <0x0 0x04a88000 0x0 0x4000>; 943 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 945 clock-names = "se"; 946 pinctrl-0 = <&qup_spi2_default>; 947 pinctrl-names = "default"; 948 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 949 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 950 dma-names = "tx", "rx"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 status = "disabled"; 954 }; 955 956 i2c3: i2c@4a8c000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0x0 0x04a8c000 0x0 0x4000>; 959 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 961 clock-names = "se"; 962 pinctrl-0 = <&qup_i2c3_default>; 963 pinctrl-names = "default"; 964 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 965 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 966 dma-names = "tx", "rx"; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "disabled"; 970 }; 971 972 spi3: spi@4a8c000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0x0 0x04a8c000 0x0 0x4000>; 975 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 977 clock-names = "se"; 978 pinctrl-0 = <&qup_spi3_default>; 979 pinctrl-names = "default"; 980 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 981 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 982 dma-names = "tx", "rx"; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 status = "disabled"; 986 }; 987 988 i2c4: i2c@4a90000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0x0 0x04a90000 0x0 0x4000>; 991 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 993 clock-names = "se"; 994 pinctrl-0 = <&qup_i2c4_default>; 995 pinctrl-names = "default"; 996 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 997 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 998 dma-names = "tx", "rx"; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 spi4: spi@4a90000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0x0 0x04a90000 0x0 0x4000>; 1007 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&qup_spi4_default>; 1012 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1013 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1014 dma-names = "tx", "rx"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 uart4: serial@4a90000 { 1021 compatible = "qcom,geni-uart"; 1022 reg = <0x0 0x04a90000 0x0 0x4000>; 1023 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1025 clock-names = "se"; 1026 pinctrl-0 = <&qup_uart4_default>; 1027 pinctrl-names = "default"; 1028 status = "disabled"; 1029 }; 1030 1031 i2c5: i2c@4a94000 { 1032 compatible = "qcom,geni-i2c"; 1033 reg = <0x0 0x04a94000 0x0 0x4000>; 1034 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1036 clock-names = "se"; 1037 pinctrl-0 = <&qup_i2c5_default>; 1038 pinctrl-names = "default"; 1039 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1040 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1041 dma-names = "tx", "rx"; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 spi5: spi@4a94000 { 1048 compatible = "qcom,geni-spi"; 1049 reg = <0x0 0x04a94000 0x0 0x4000>; 1050 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1052 clock-names = "se"; 1053 pinctrl-0 = <&qup_spi5_default>; 1054 pinctrl-names = "default"; 1055 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1056 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1057 dma-names = "tx", "rx"; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 }; 1063 1064 usb: usb@4ef8800 { 1065 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1066 reg = <0x0 0x04ef8800 0x0 0x400>; 1067 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1069 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1070 1071 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1072 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1073 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1074 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1075 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1076 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1077 clock-names = "cfg_noc", 1078 "core", 1079 "iface", 1080 "sleep", 1081 "mock_utmi", 1082 "xo"; 1083 1084 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1085 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1086 assigned-clock-rates = <19200000>, <133333333>; 1087 1088 resets = <&gcc GCC_USB30_PRIM_BCR>; 1089 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1090 wakeup-source; 1091 1092 #address-cells = <2>; 1093 #size-cells = <2>; 1094 ranges; 1095 1096 status = "disabled"; 1097 1098 usb_dwc3: usb@4e00000 { 1099 compatible = "snps,dwc3"; 1100 reg = <0x0 0x04e00000 0x0 0xcd00>; 1101 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1102 phys = <&usb_hsphy>, <&usb_qmpphy>; 1103 phy-names = "usb2-phy", "usb3-phy"; 1104 iommus = <&apps_smmu 0x120 0x0>; 1105 snps,dis_u2_susphy_quirk; 1106 snps,dis_enblslpm_quirk; 1107 snps,has-lpm-erratum; 1108 snps,hird-threshold = /bits/ 8 <0x10>; 1109 snps,usb3_lpm_capable; 1110 maximum-speed = "super-speed"; 1111 dr_mode = "otg"; 1112 }; 1113 }; 1114 1115 remoteproc_mpss: remoteproc@6080000 { 1116 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 1117 reg = <0x0 0x06080000 0x0 0x100>; 1118 1119 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1120 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1121 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1122 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1123 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1124 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1125 interrupt-names = "wdog", 1126 "fatal", 1127 "ready", 1128 "handover", 1129 "stop-ack", 1130 "shutdown-ack"; 1131 1132 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1133 clock-names = "xo"; 1134 1135 power-domains = <&rpmpd QCM2290_VDDCX>; 1136 1137 memory-region = <&pil_modem_mem>; 1138 1139 qcom,smem-states = <&modem_smp2p_out 0>; 1140 qcom,smem-state-names = "stop"; 1141 1142 status = "disabled"; 1143 1144 glink-edge { 1145 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1146 label = "mpss"; 1147 qcom,remote-pid = <1>; 1148 mboxes = <&apcs_glb 12>; 1149 }; 1150 }; 1151 1152 remoteproc_adsp: remoteproc@ab00000 { 1153 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 1154 reg = <0x0 0x0ab00000 0x0 0x100>; 1155 1156 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1157 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1158 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1159 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1160 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1161 interrupt-names = "wdog", 1162 "fatal", 1163 "ready", 1164 "handover", 1165 "stop-ack"; 1166 1167 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1168 clock-names = "xo"; 1169 1170 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 1171 <&rpmpd QCM2290_VDD_LPI_MX>; 1172 1173 memory-region = <&pil_adsp_mem>; 1174 1175 qcom,smem-states = <&adsp_smp2p_out 0>; 1176 qcom,smem-state-names = "stop"; 1177 1178 status = "disabled"; 1179 1180 glink-edge { 1181 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 1182 label = "lpass"; 1183 qcom,remote-pid = <2>; 1184 mboxes = <&apcs_glb 8>; 1185 }; 1186 }; 1187 1188 apps_smmu: iommu@c600000 { 1189 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1190 reg = <0x0 0x0c600000 0x0 0x80000>; 1191 #iommu-cells = <2>; 1192 #global-interrupts = <1>; 1193 1194 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1259 }; 1260 1261 wifi: wifi@c800000 { 1262 compatible = "qcom,wcn3990-wifi"; 1263 reg = <0x0 0x0c800000 0x0 0x800000>; 1264 reg-names = "membase"; 1265 memory-region = <&wlan_msa_mem>; 1266 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1278 iommus = <&apps_smmu 0x1a0 0x1>; 1279 qcom,msa-fixed-perm; 1280 status = "disabled"; 1281 }; 1282 1283 watchdog@f017000 { 1284 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 1285 reg = <0x0 0x0f017000 0x0 0x1000>; 1286 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1287 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&sleep_clk>; 1289 }; 1290 1291 apcs_glb: mailbox@f111000 { 1292 compatible = "qcom,qcm2290-apcs-hmss-global"; 1293 reg = <0x0 0x0f111000 0x0 0x1000>; 1294 #mbox-cells = <1>; 1295 }; 1296 1297 timer@f120000 { 1298 compatible = "arm,armv7-timer-mem"; 1299 reg = <0x0 0x0f120000 0x0 0x1000>; 1300 #address-cells = <1>; 1301 #size-cells = <1>; 1302 ranges = <0 0x0 0x0f121000 0x8000>; 1303 1304 frame@0 { 1305 reg = <0x0 0x1000>, 1306 <0x1000 0x1000>; 1307 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1309 frame-number = <0>; 1310 }; 1311 1312 frame@2000 { 1313 reg = <0x2000 0x1000>; 1314 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1315 frame-number = <1>; 1316 status = "disabled"; 1317 }; 1318 1319 frame@3000 { 1320 reg = <0x3000 0x1000>; 1321 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1322 frame-number = <2>; 1323 status = "disabled"; 1324 }; 1325 1326 frame@4000 { 1327 reg = <0x4000 0x1000>; 1328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1329 frame-number = <3>; 1330 status = "disabled"; 1331 }; 1332 1333 frame@5000 { 1334 reg = <0x5000 0x1000>; 1335 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1336 frame-number = <4>; 1337 status = "disabled"; 1338 }; 1339 1340 frame@6000 { 1341 reg = <0x6000 0x1000>; 1342 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1343 frame-number = <5>; 1344 status = "disabled"; 1345 }; 1346 1347 frame@7000 { 1348 reg = <0x7000 0x1000>; 1349 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1350 frame-number = <6>; 1351 status = "disabled"; 1352 }; 1353 }; 1354 1355 intc: interrupt-controller@f200000 { 1356 compatible = "arm,gic-v3"; 1357 reg = <0x0 0x0f200000 0x0 0x10000>, 1358 <0x0 0x0f300000 0x0 0x100000>; 1359 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1360 #interrupt-cells = <3>; 1361 interrupt-controller; 1362 interrupt-parent = <&intc>; 1363 #redistributor-regions = <1>; 1364 redistributor-stride = <0x0 0x20000>; 1365 }; 1366 1367 cpufreq_hw: cpufreq@f521000 { 1368 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 1369 reg = <0x0 0x0f521000 0x0 0x1000>; 1370 reg-names = "freq-domain0"; 1371 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1372 interrupt-names = "dcvsh-irq-0"; 1373 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1374 clock-names = "xo", "alternate"; 1375 1376 #freq-domain-cells = <1>; 1377 #clock-cells = <1>; 1378 }; 1379 }; 1380 1381 thermal-zones { 1382 mapss-thermal { 1383 polling-delay-passive = <0>; 1384 polling-delay = <0>; 1385 1386 thermal-sensors = <&tsens0 0>; 1387 1388 trips { 1389 mapss_alert0: trip-point0 { 1390 temperature = <90000>; 1391 hysteresis = <2000>; 1392 type = "passive"; 1393 }; 1394 1395 mapss_alert1: trip-point1 { 1396 temperature = <95000>; 1397 hysteresis = <2000>; 1398 type = "passive"; 1399 }; 1400 1401 mapss_crit: mapss-crit { 1402 temperature = <110000>; 1403 hysteresis = <1000>; 1404 type = "critical"; 1405 }; 1406 }; 1407 }; 1408 1409 video-thermal { 1410 polling-delay-passive = <0>; 1411 polling-delay = <0>; 1412 1413 thermal-sensors = <&tsens0 1>; 1414 1415 trips { 1416 video_alert0: trip-point0 { 1417 temperature = <90000>; 1418 hysteresis = <2000>; 1419 type = "passive"; 1420 }; 1421 1422 video_alert1: trip-point1 { 1423 temperature = <95000>; 1424 hysteresis = <2000>; 1425 type = "passive"; 1426 }; 1427 1428 video_crit: video-crit { 1429 temperature = <110000>; 1430 hysteresis = <1000>; 1431 type = "critical"; 1432 }; 1433 }; 1434 }; 1435 1436 wlan-thermal { 1437 polling-delay-passive = <0>; 1438 polling-delay = <0>; 1439 1440 thermal-sensors = <&tsens0 2>; 1441 1442 trips { 1443 wlan_alert0: trip-point0 { 1444 temperature = <90000>; 1445 hysteresis = <2000>; 1446 type = "passive"; 1447 }; 1448 1449 wlan_alert1: trip-point1 { 1450 temperature = <95000>; 1451 hysteresis = <2000>; 1452 type = "passive"; 1453 }; 1454 1455 wlan_crit: wlan-crit { 1456 temperature = <110000>; 1457 hysteresis = <1000>; 1458 type = "critical"; 1459 }; 1460 }; 1461 }; 1462 1463 cpuss0-thermal { 1464 polling-delay-passive = <0>; 1465 polling-delay = <0>; 1466 1467 thermal-sensors = <&tsens0 3>; 1468 1469 trips { 1470 cpuss0_alert0: trip-point0 { 1471 temperature = <90000>; 1472 hysteresis = <2000>; 1473 type = "passive"; 1474 }; 1475 1476 cpuss0_alert1: trip-point1 { 1477 temperature = <95000>; 1478 hysteresis = <2000>; 1479 type = "passive"; 1480 }; 1481 1482 cpuss0_crit: cpuss0-crit { 1483 temperature = <110000>; 1484 hysteresis = <1000>; 1485 type = "critical"; 1486 }; 1487 }; 1488 }; 1489 1490 cpuss1-thermal { 1491 polling-delay-passive = <0>; 1492 polling-delay = <0>; 1493 1494 thermal-sensors = <&tsens0 4>; 1495 1496 trips { 1497 cpuss1_alert0: trip-point0 { 1498 temperature = <90000>; 1499 hysteresis = <2000>; 1500 type = "passive"; 1501 }; 1502 1503 cpuss1_alert1: trip-point1 { 1504 temperature = <95000>; 1505 hysteresis = <2000>; 1506 type = "passive"; 1507 }; 1508 1509 cpuss1_crit: cpuss1-crit { 1510 temperature = <110000>; 1511 hysteresis = <1000>; 1512 type = "critical"; 1513 }; 1514 }; 1515 }; 1516 1517 mdm0-thermal { 1518 polling-delay-passive = <0>; 1519 polling-delay = <0>; 1520 1521 thermal-sensors = <&tsens0 5>; 1522 1523 trips { 1524 mdm0_alert0: trip-point0 { 1525 temperature = <90000>; 1526 hysteresis = <2000>; 1527 type = "passive"; 1528 }; 1529 1530 mdm0_alert1: trip-point1 { 1531 temperature = <95000>; 1532 hysteresis = <2000>; 1533 type = "passive"; 1534 }; 1535 1536 mdm0_crit: mdm0-crit { 1537 temperature = <110000>; 1538 hysteresis = <1000>; 1539 type = "critical"; 1540 }; 1541 }; 1542 }; 1543 1544 mdm1-thermal { 1545 polling-delay-passive = <0>; 1546 polling-delay = <0>; 1547 1548 thermal-sensors = <&tsens0 6>; 1549 1550 trips { 1551 mdm1_alert0: trip-point0 { 1552 temperature = <90000>; 1553 hysteresis = <2000>; 1554 type = "passive"; 1555 }; 1556 1557 mdm1_alert1: trip-point1 { 1558 temperature = <95000>; 1559 hysteresis = <2000>; 1560 type = "passive"; 1561 }; 1562 1563 mdm1_crit: mdm1-crit { 1564 temperature = <110000>; 1565 hysteresis = <1000>; 1566 type = "critical"; 1567 }; 1568 }; 1569 }; 1570 1571 gpu-thermal { 1572 polling-delay-passive = <0>; 1573 polling-delay = <0>; 1574 1575 thermal-sensors = <&tsens0 7>; 1576 1577 trips { 1578 gpu_alert0: trip-point0 { 1579 temperature = <90000>; 1580 hysteresis = <2000>; 1581 type = "passive"; 1582 }; 1583 1584 gpu_alert1: trip-point1 { 1585 temperature = <95000>; 1586 hysteresis = <2000>; 1587 type = "passive"; 1588 }; 1589 1590 gpu_crit: gpu-crit { 1591 temperature = <110000>; 1592 hysteresis = <1000>; 1593 type = "critical"; 1594 }; 1595 }; 1596 }; 1597 1598 hm-center-thermal { 1599 polling-delay-passive = <0>; 1600 polling-delay = <0>; 1601 1602 thermal-sensors = <&tsens0 8>; 1603 1604 trips { 1605 hm_center_alert0: trip-point0 { 1606 temperature = <90000>; 1607 hysteresis = <2000>; 1608 type = "passive"; 1609 }; 1610 1611 hm_center_alert1: trip-point1 { 1612 temperature = <95000>; 1613 hysteresis = <2000>; 1614 type = "passive"; 1615 }; 1616 1617 hm_center_crit: hm-center-crit { 1618 temperature = <110000>; 1619 hysteresis = <1000>; 1620 type = "critical"; 1621 }; 1622 }; 1623 }; 1624 1625 camera-thermal { 1626 polling-delay-passive = <0>; 1627 polling-delay = <0>; 1628 1629 thermal-sensors = <&tsens0 9>; 1630 1631 trips { 1632 camera_alert0: trip-point0 { 1633 temperature = <90000>; 1634 hysteresis = <2000>; 1635 type = "passive"; 1636 }; 1637 1638 camera_alert1: trip-point1 { 1639 temperature = <95000>; 1640 hysteresis = <2000>; 1641 type = "passive"; 1642 }; 1643 1644 camera_crit: camera-crit { 1645 temperature = <110000>; 1646 hysteresis = <1000>; 1647 type = "critical"; 1648 }; 1649 }; 1650 }; 1651 }; 1652 1653 timer { 1654 compatible = "arm,armv8-timer"; 1655 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1656 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1657 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1658 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1659 }; 1660}; 1661