1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32764>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x0>; 45 clocks = <&cpufreq_hw 0>; 46 capacity-dmips-mhz = <1024>; 47 dynamic-power-coefficient = <100>; 48 enable-method = "psci"; 49 next-level-cache = <&L2_0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 51 L2_0: l2-cache { 52 compatible = "cache"; 53 cache-level = <2>; 54 }; 55 }; 56 57 CPU1: cpu@1 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x0 0x1>; 61 clocks = <&cpufreq_hw 0>; 62 capacity-dmips-mhz = <1024>; 63 dynamic-power-coefficient = <100>; 64 enable-method = "psci"; 65 next-level-cache = <&L2_0>; 66 qcom,freq-domain = <&cpufreq_hw 0>; 67 }; 68 69 CPU2: cpu@2 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x2>; 73 clocks = <&cpufreq_hw 0>; 74 capacity-dmips-mhz = <1024>; 75 dynamic-power-coefficient = <100>; 76 enable-method = "psci"; 77 next-level-cache = <&L2_0>; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 }; 80 81 CPU3: cpu@3 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x3>; 85 clocks = <&cpufreq_hw 0>; 86 capacity-dmips-mhz = <1024>; 87 dynamic-power-coefficient = <100>; 88 enable-method = "psci"; 89 next-level-cache = <&L2_0>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 }; 92 93 cpu-map { 94 cluster0 { 95 core0 { 96 cpu = <&CPU0>; 97 }; 98 99 core1 { 100 cpu = <&CPU1>; 101 }; 102 103 core2 { 104 cpu = <&CPU2>; 105 }; 106 107 core3 { 108 cpu = <&CPU3>; 109 }; 110 }; 111 }; 112 }; 113 114 firmware { 115 scm: scm { 116 compatible = "qcom,scm-qcm2290", "qcom,scm"; 117 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 118 clock-names = "core"; 119 #reset-cells = <1>; 120 }; 121 }; 122 123 memory@40000000 { 124 device_type = "memory"; 125 /* We expect the bootloader to fill in the size */ 126 reg = <0 0x40000000 0 0>; 127 }; 128 129 pmu { 130 compatible = "arm,armv8-pmuv3"; 131 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 132 }; 133 134 psci { 135 compatible = "arm,psci-1.0"; 136 method = "smc"; 137 }; 138 139 reserved_memory: reserved-memory { 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges; 143 144 hyp_mem: hyp@45700000 { 145 reg = <0x0 0x45700000 0x0 0x600000>; 146 no-map; 147 }; 148 149 xbl_aop_mem: xbl-aop@45e00000 { 150 reg = <0x0 0x45e00000 0x0 0x140000>; 151 no-map; 152 }; 153 154 sec_apps_mem: sec-apps@45fff000 { 155 reg = <0x0 0x45fff000 0x0 0x1000>; 156 no-map; 157 }; 158 159 smem_mem: smem@46000000 { 160 compatible = "qcom,smem"; 161 reg = <0x0 0x46000000 0x0 0x200000>; 162 no-map; 163 164 hwlocks = <&tcsr_mutex 3>; 165 qcom,rpm-msg-ram = <&rpm_msg_ram>; 166 }; 167 168 pil_modem_mem: modem@4ab00000 { 169 reg = <0x0 0x4ab00000 0x0 0x6900000>; 170 no-map; 171 }; 172 173 pil_video_mem: video@51400000 { 174 reg = <0x0 0x51400000 0x0 0x500000>; 175 no-map; 176 }; 177 178 wlan_msa_mem: wlan-msa@51900000 { 179 reg = <0x0 0x51900000 0x0 0x100000>; 180 no-map; 181 }; 182 183 pil_adsp_mem: adsp@51a00000 { 184 reg = <0x0 0x51a00000 0x0 0x1c00000>; 185 no-map; 186 }; 187 188 pil_ipa_fw_mem: ipa-fw@53600000 { 189 reg = <0x0 0x53600000 0x0 0x10000>; 190 no-map; 191 }; 192 193 pil_ipa_gsi_mem: ipa-gsi@53610000 { 194 reg = <0x0 0x53610000 0x0 0x5000>; 195 no-map; 196 }; 197 198 pil_gpu_mem: zap@53615000 { 199 compatible = "shared-dma-pool"; 200 reg = <0x0 0x53615000 0x0 0x2000>; 201 no-map; 202 }; 203 204 cont_splash_memory: framebuffer@5c000000 { 205 reg = <0x0 0x5c000000 0x0 0x00f00000>; 206 no-map; 207 }; 208 209 dfps_data_memory: dpfs-data@5cf00000 { 210 reg = <0x0 0x5cf00000 0x0 0x0100000>; 211 no-map; 212 }; 213 214 removed_mem: reserved@60000000 { 215 reg = <0x0 0x60000000 0x0 0x3900000>; 216 no-map; 217 }; 218 219 rmtfs_mem: memory@89b01000 { 220 compatible = "qcom,rmtfs-mem"; 221 reg = <0x0 0x89b01000 0x0 0x200000>; 222 no-map; 223 224 qcom,client-id = <1>; 225 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 226 }; 227 }; 228 229 rpm-glink { 230 compatible = "qcom,glink-rpm"; 231 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 232 qcom,rpm-msg-ram = <&rpm_msg_ram>; 233 mboxes = <&apcs_glb 0>; 234 235 rpm_requests: rpm-requests { 236 compatible = "qcom,rpm-qcm2290"; 237 qcom,glink-channels = "rpm_requests"; 238 239 rpmcc: clock-controller { 240 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 241 clocks = <&xo_board>; 242 clock-names = "xo"; 243 #clock-cells = <1>; 244 }; 245 246 rpmpd: power-controller { 247 compatible = "qcom,qcm2290-rpmpd"; 248 #power-domain-cells = <1>; 249 operating-points-v2 = <&rpmpd_opp_table>; 250 251 rpmpd_opp_table: opp-table { 252 compatible = "operating-points-v2"; 253 254 rpmpd_opp_min_svs: opp1 { 255 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 256 }; 257 258 rpmpd_opp_low_svs: opp2 { 259 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 260 }; 261 262 rpmpd_opp_svs: opp3 { 263 opp-level = <RPM_SMD_LEVEL_SVS>; 264 }; 265 266 rpmpd_opp_svs_plus: opp4 { 267 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 268 }; 269 270 rpmpd_opp_nom: opp5 { 271 opp-level = <RPM_SMD_LEVEL_NOM>; 272 }; 273 274 rpmpd_opp_nom_plus: opp6 { 275 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 276 }; 277 278 rpmpd_opp_turbo: opp7 { 279 opp-level = <RPM_SMD_LEVEL_TURBO>; 280 }; 281 282 rpmpd_opp_turbo_plus: opp8 { 283 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 284 }; 285 }; 286 }; 287 }; 288 }; 289 290 smp2p-adsp { 291 compatible = "qcom,smp2p"; 292 qcom,smem = <443>, <429>; 293 294 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 295 296 mboxes = <&apcs_glb 10>; 297 298 qcom,local-pid = <0>; 299 qcom,remote-pid = <2>; 300 301 adsp_smp2p_out: master-kernel { 302 qcom,entry-name = "master-kernel"; 303 #qcom,smem-state-cells = <1>; 304 }; 305 306 adsp_smp2p_in: slave-kernel { 307 qcom,entry-name = "slave-kernel"; 308 interrupt-controller; 309 #interrupt-cells = <2>; 310 }; 311 }; 312 313 smp2p-mpss { 314 compatible = "qcom,smp2p"; 315 qcom,smem = <435>, <428>; 316 317 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 318 319 mboxes = <&apcs_glb 14>; 320 321 qcom,local-pid = <0>; 322 qcom,remote-pid = <1>; 323 324 modem_smp2p_out: master-kernel { 325 qcom,entry-name = "master-kernel"; 326 #qcom,smem-state-cells = <1>; 327 }; 328 329 modem_smp2p_in: slave-kernel { 330 qcom,entry-name = "slave-kernel"; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 }; 334 335 wlan_smp2p_in: wlan-wpss-to-ap { 336 qcom,entry-name = "wlan"; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 }; 341 342 soc: soc@0 { 343 compatible = "simple-bus"; 344 #address-cells = <2>; 345 #size-cells = <2>; 346 ranges = <0 0 0 0 0x10 0>; 347 dma-ranges = <0 0 0 0 0x10 0>; 348 349 tcsr_mutex: hwlock@340000 { 350 compatible = "qcom,tcsr-mutex"; 351 reg = <0x0 0x00340000 0x0 0x20000>; 352 #hwlock-cells = <1>; 353 }; 354 355 tlmm: pinctrl@500000 { 356 compatible = "qcom,qcm2290-tlmm"; 357 reg = <0x0 0x00500000 0x0 0x300000>; 358 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 359 gpio-controller; 360 gpio-ranges = <&tlmm 0 0 127>; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 365 qup_i2c0_default: qup-i2c0-default-state { 366 pins = "gpio0", "gpio1"; 367 function = "qup0"; 368 drive-strength = <2>; 369 bias-pull-up; 370 }; 371 372 qup_i2c1_default: qup-i2c1-default-state { 373 pins = "gpio4", "gpio5"; 374 function = "qup1"; 375 drive-strength = <2>; 376 bias-pull-up; 377 }; 378 379 qup_i2c2_default: qup-i2c2-default-state { 380 pins = "gpio6", "gpio7"; 381 function = "qup2"; 382 drive-strength = <2>; 383 bias-pull-up; 384 }; 385 386 qup_i2c3_default: qup-i2c3-default-state { 387 pins = "gpio8", "gpio9"; 388 function = "qup3"; 389 drive-strength = <2>; 390 bias-pull-up; 391 }; 392 393 qup_i2c4_default: qup-i2c4-default-state { 394 pins = "gpio12", "gpio13"; 395 function = "qup4"; 396 drive-strength = <2>; 397 bias-pull-up; 398 }; 399 400 qup_i2c5_default: qup-i2c5-default-state { 401 pins = "gpio14", "gpio15"; 402 function = "qup5"; 403 drive-strength = <2>; 404 bias-pull-up; 405 }; 406 407 qup_spi0_default: qup-spi0-default-state { 408 pins = "gpio0", "gpio1","gpio2", "gpio3"; 409 function = "qup0"; 410 drive-strength = <2>; 411 bias-pull-up; 412 }; 413 414 qup_spi1_default: qup-spi1-default-state { 415 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 416 function = "qup1"; 417 drive-strength = <2>; 418 bias-pull-up; 419 }; 420 421 qup_spi2_default: qup-spi2-default-state { 422 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 423 function = "qup2"; 424 drive-strength = <2>; 425 bias-pull-up; 426 }; 427 428 qup_spi3_default: qup-spi3-default-state { 429 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 430 function = "qup3"; 431 drive-strength = <2>; 432 bias-pull-up; 433 }; 434 435 qup_spi4_default: qup-spi4-default-state { 436 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 437 function = "qup4"; 438 drive-strength = <2>; 439 bias-pull-up; 440 }; 441 442 qup_spi5_default: qup-spi5-default-state { 443 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 444 function = "qup5"; 445 drive-strength = <2>; 446 bias-pull-up; 447 }; 448 449 qup_uart0_default: qup-uart0-default-state { 450 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 451 function = "qup0"; 452 drive-strength = <2>; 453 bias-disable; 454 }; 455 456 qup_uart4_default: qup-uart4-default-state { 457 pins = "gpio12", "gpio13"; 458 function = "qup4"; 459 drive-strength = <2>; 460 bias-disable; 461 }; 462 463 sdc1_state_on: sdc1-on-state { 464 clk-pins { 465 pins = "sdc1_clk"; 466 drive-strength = <16>; 467 bias-disable; 468 }; 469 470 cmd-pins { 471 pins = "sdc1_cmd"; 472 drive-strength = <10>; 473 bias-pull-up; 474 }; 475 476 data-pins { 477 pins = "sdc1_data"; 478 drive-strength = <10>; 479 bias-pull-up; 480 }; 481 482 rclk-pins { 483 pins = "sdc1_rclk"; 484 bias-pull-down; 485 }; 486 }; 487 488 sdc1_state_off: sdc1-off-state { 489 clk-pins { 490 pins = "sdc1_clk"; 491 drive-strength = <2>; 492 bias-disable; 493 }; 494 495 cmd-pins { 496 pins = "sdc1_cmd"; 497 drive-strength = <2>; 498 bias-pull-up; 499 }; 500 501 data-pins { 502 pins = "sdc1_data"; 503 drive-strength = <2>; 504 bias-pull-up; 505 }; 506 507 rclk-pins { 508 pins = "sdc1_rclk"; 509 bias-pull-down; 510 }; 511 }; 512 513 sdc2_state_on: sdc2-on-state { 514 clk-pins { 515 pins = "sdc2_clk"; 516 drive-strength = <16>; 517 bias-disable; 518 }; 519 520 cmd-pins { 521 pins = "sdc2_cmd"; 522 drive-strength = <10>; 523 bias-pull-up; 524 }; 525 526 data-pins { 527 pins = "sdc2_data"; 528 drive-strength = <10>; 529 bias-pull-up; 530 }; 531 }; 532 533 sdc2_state_off: sdc2-off-state { 534 clk-pins { 535 pins = "sdc2_clk"; 536 drive-strength = <2>; 537 bias-disable; 538 }; 539 540 cmd-pins { 541 pins = "sdc2_cmd"; 542 drive-strength = <2>; 543 bias-pull-up; 544 }; 545 546 data-pins { 547 pins = "sdc2_data"; 548 drive-strength = <2>; 549 bias-pull-up; 550 }; 551 }; 552 }; 553 554 gcc: clock-controller@1400000 { 555 compatible = "qcom,gcc-qcm2290"; 556 reg = <0x0 0x01400000 0x0 0x1f0000>; 557 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 558 clock-names = "bi_tcxo", "sleep_clk"; 559 #clock-cells = <1>; 560 #reset-cells = <1>; 561 #power-domain-cells = <1>; 562 }; 563 564 usb_hsphy: phy@1613000 { 565 compatible = "qcom,qcm2290-qusb2-phy"; 566 reg = <0x0 0x01613000 0x0 0x180>; 567 568 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 569 <&rpmcc RPM_SMD_XO_CLK_SRC>; 570 clock-names = "cfg_ahb", "ref"; 571 572 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 573 nvmem-cells = <&qusb2_hstx_trim>; 574 #phy-cells = <0>; 575 576 status = "disabled"; 577 }; 578 579 qfprom@1b44000 { 580 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 581 reg = <0x0 0x01b44000 0x0 0x3000>; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 585 qusb2_hstx_trim: hstx-trim@25b { 586 reg = <0x25b 0x1>; 587 bits = <1 4>; 588 }; 589 }; 590 591 spmi_bus: spmi@1c40000 { 592 compatible = "qcom,spmi-pmic-arb"; 593 reg = <0x0 0x01c40000 0x0 0x1100>, 594 <0x0 0x01e00000 0x0 0x2000000>, 595 <0x0 0x03e00000 0x0 0x100000>, 596 <0x0 0x03f00000 0x0 0xa0000>, 597 <0x0 0x01c0a000 0x0 0x26000>; 598 reg-names = "core", 599 "chnls", 600 "obsrvr", 601 "intr", 602 "cnfg"; 603 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 604 interrupt-names = "periph_irq"; 605 qcom,ee = <0>; 606 qcom,channel = <0>; 607 #address-cells = <2>; 608 #size-cells = <0>; 609 interrupt-controller; 610 #interrupt-cells = <4>; 611 }; 612 613 tsens0: thermal-sensor@4411000 { 614 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 615 reg = <0x0 0x04411000 0x0 0x1ff>, 616 <0x0 0x04410000 0x0 0x8>; 617 #qcom,sensors = <10>; 618 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 620 interrupt-names = "uplow", "critical"; 621 #thermal-sensor-cells = <1>; 622 }; 623 624 rng: rng@4453000 { 625 compatible = "qcom,prng-ee"; 626 reg = <0x0 0x04453000 0x0 0x1000>; 627 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 628 clock-names = "core"; 629 }; 630 631 rpm_msg_ram: sram@45f0000 { 632 compatible = "qcom,rpm-msg-ram"; 633 reg = <0x0 0x045f0000 0x0 0x7000>; 634 }; 635 636 sram@4690000 { 637 compatible = "qcom,rpm-stats"; 638 reg = <0x0 0x04690000 0x0 0x10000>; 639 }; 640 641 sdhc_1: mmc@4744000 { 642 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 643 reg = <0x0 0x04744000 0x0 0x1000>, 644 <0x0 0x04745000 0x0 0x1000>, 645 <0x0 0x04748000 0x0 0x8000>; 646 reg-names = "hc", 647 "cqhci", 648 "ice"; 649 650 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 652 interrupt-names = "hc_irq", "pwr_irq"; 653 654 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 655 <&gcc GCC_SDCC1_APPS_CLK>, 656 <&rpmcc RPM_SMD_XO_CLK_SRC>, 657 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 658 clock-names = "iface", 659 "core", 660 "xo", 661 "ice"; 662 663 resets = <&gcc GCC_SDCC1_BCR>; 664 665 power-domains = <&rpmpd QCM2290_VDDCX>; 666 iommus = <&apps_smmu 0xc0 0x0>; 667 668 qcom,dll-config = <0x000f642c>; 669 qcom,ddr-config = <0x80040868>; 670 bus-width = <8>; 671 672 status = "disabled"; 673 }; 674 675 sdhc_2: mmc@4784000 { 676 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 677 reg = <0x0 0x04784000 0x0 0x1000>; 678 reg-names = "hc"; 679 680 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 682 interrupt-names = "hc_irq", "pwr_irq"; 683 684 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 685 <&gcc GCC_SDCC2_APPS_CLK>, 686 <&rpmcc RPM_SMD_XO_CLK_SRC>; 687 clock-names = "iface", 688 "core", 689 "xo"; 690 691 resets = <&gcc GCC_SDCC2_BCR>; 692 693 power-domains = <&rpmpd QCM2290_VDDCX>; 694 operating-points-v2 = <&sdhc2_opp_table>; 695 iommus = <&apps_smmu 0xa0 0x0>; 696 697 qcom,dll-config = <0x0007642c>; 698 qcom,ddr-config = <0x80040868>; 699 bus-width = <4>; 700 701 status = "disabled"; 702 703 sdhc2_opp_table: opp-table { 704 compatible = "operating-points-v2"; 705 706 opp-100000000 { 707 opp-hz = /bits/ 64 <100000000>; 708 required-opps = <&rpmpd_opp_low_svs>; 709 }; 710 711 opp-202000000 { 712 opp-hz = /bits/ 64 <202000000>; 713 required-opps = <&rpmpd_opp_svs_plus>; 714 }; 715 }; 716 }; 717 718 gpi_dma0: dma-controller@4a00000 { 719 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 720 reg = <0x0 0x04a00000 0x0 0x60000>; 721 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 731 dma-channels = <10>; 732 dma-channel-mask = <0x1f>; 733 iommus = <&apps_smmu 0xf6 0x0>; 734 #dma-cells = <3>; 735 status = "disabled"; 736 }; 737 738 qupv3_id_0: geniqup@4ac0000 { 739 compatible = "qcom,geni-se-qup"; 740 reg = <0x0 0x04ac0000 0x0 0x2000>; 741 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 742 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 743 clock-names = "m-ahb", "s-ahb"; 744 iommus = <&apps_smmu 0xe3 0x0>; 745 #address-cells = <2>; 746 #size-cells = <2>; 747 ranges; 748 status = "disabled"; 749 750 i2c0: i2c@4a80000 { 751 compatible = "qcom,geni-i2c"; 752 reg = <0x0 0x04a80000 0x0 0x4000>; 753 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 755 clock-names = "se"; 756 pinctrl-0 = <&qup_i2c0_default>; 757 pinctrl-names = "default"; 758 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 759 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 760 dma-names = "tx", "rx"; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 status = "disabled"; 764 }; 765 766 spi0: spi@4a80000 { 767 compatible = "qcom,geni-spi"; 768 reg = <0x0 0x04a80000 0x0 0x4000>; 769 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 771 clock-names = "se"; 772 pinctrl-0 = <&qup_spi0_default>; 773 pinctrl-names = "default"; 774 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 775 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 776 dma-names = "tx", "rx"; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 status = "disabled"; 780 }; 781 782 uart0: serial@4a80000 { 783 compatible = "qcom,geni-uart"; 784 reg = <0x0 0x04a80000 0x0 0x4000>; 785 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 787 clock-names = "se"; 788 pinctrl-0 = <&qup_uart0_default>; 789 pinctrl-names = "default"; 790 status = "disabled"; 791 }; 792 793 i2c1: i2c@4a84000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0x0 0x04a84000 0x0 0x4000>; 796 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 798 clock-names = "se"; 799 pinctrl-0 = <&qup_i2c1_default>; 800 pinctrl-names = "default"; 801 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 802 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 803 dma-names = "tx", "rx"; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 spi1: spi@4a84000 { 810 compatible = "qcom,geni-spi"; 811 reg = <0x0 0x04a84000 0x0 0x4000>; 812 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 814 clock-names = "se"; 815 pinctrl-0 = <&qup_spi1_default>; 816 pinctrl-names = "default"; 817 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 818 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 819 dma-names = "tx", "rx"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 i2c2: i2c@4a88000 { 826 compatible = "qcom,geni-i2c"; 827 reg = <0x0 0x04a88000 0x0 0x4000>; 828 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 830 clock-names = "se"; 831 pinctrl-0 = <&qup_i2c2_default>; 832 pinctrl-names = "default"; 833 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 834 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 835 dma-names = "tx", "rx"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 spi2: spi@4a88000 { 842 compatible = "qcom,geni-spi"; 843 reg = <0x0 0x04a88000 0x0 0x4000>; 844 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 846 clock-names = "se"; 847 pinctrl-0 = <&qup_spi2_default>; 848 pinctrl-names = "default"; 849 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 850 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 851 dma-names = "tx", "rx"; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 status = "disabled"; 855 }; 856 857 i2c3: i2c@4a8c000 { 858 compatible = "qcom,geni-i2c"; 859 reg = <0x0 0x04a8c000 0x0 0x4000>; 860 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 862 clock-names = "se"; 863 pinctrl-0 = <&qup_i2c3_default>; 864 pinctrl-names = "default"; 865 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 866 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 867 dma-names = "tx", "rx"; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 status = "disabled"; 871 }; 872 873 spi3: spi@4a8c000 { 874 compatible = "qcom,geni-spi"; 875 reg = <0x0 0x04a8c000 0x0 0x4000>; 876 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 878 clock-names = "se"; 879 pinctrl-0 = <&qup_spi3_default>; 880 pinctrl-names = "default"; 881 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 882 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 883 dma-names = "tx", "rx"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 status = "disabled"; 887 }; 888 889 i2c4: i2c@4a90000 { 890 compatible = "qcom,geni-i2c"; 891 reg = <0x0 0x04a90000 0x0 0x4000>; 892 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 894 clock-names = "se"; 895 pinctrl-0 = <&qup_i2c4_default>; 896 pinctrl-names = "default"; 897 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 898 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 899 dma-names = "tx", "rx"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 905 spi4: spi@4a90000 { 906 compatible = "qcom,geni-spi"; 907 reg = <0x0 0x04a90000 0x0 0x4000>; 908 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_spi4_default>; 913 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 914 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 915 dma-names = "tx", "rx"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "disabled"; 919 }; 920 921 uart4: serial@4a90000 { 922 compatible = "qcom,geni-uart"; 923 reg = <0x0 0x04a90000 0x0 0x4000>; 924 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 926 clock-names = "se"; 927 pinctrl-0 = <&qup_uart4_default>; 928 pinctrl-names = "default"; 929 status = "disabled"; 930 }; 931 932 i2c5: i2c@4a94000 { 933 compatible = "qcom,geni-i2c"; 934 reg = <0x0 0x04a94000 0x0 0x4000>; 935 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 937 clock-names = "se"; 938 pinctrl-0 = <&qup_i2c5_default>; 939 pinctrl-names = "default"; 940 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 941 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 942 dma-names = "tx", "rx"; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 status = "disabled"; 946 }; 947 948 spi5: spi@4a94000 { 949 compatible = "qcom,geni-spi"; 950 reg = <0x0 0x04a94000 0x0 0x4000>; 951 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 953 clock-names = "se"; 954 pinctrl-0 = <&qup_spi5_default>; 955 pinctrl-names = "default"; 956 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 957 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 958 dma-names = "tx", "rx"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 }; 964 965 usb: usb@4ef8800 { 966 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 967 reg = <0x0 0x04ef8800 0x0 0x400>; 968 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 970 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 971 972 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 973 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 974 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 975 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 976 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 977 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 978 clock-names = "cfg_noc", 979 "core", 980 "iface", 981 "sleep", 982 "mock_utmi", 983 "xo"; 984 985 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 986 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 987 assigned-clock-rates = <19200000>, <133333333>; 988 989 resets = <&gcc GCC_USB30_PRIM_BCR>; 990 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 991 wakeup-source; 992 993 #address-cells = <2>; 994 #size-cells = <2>; 995 ranges; 996 997 status = "disabled"; 998 999 usb_dwc3: usb@4e00000 { 1000 compatible = "snps,dwc3"; 1001 reg = <0x0 0x04e00000 0x0 0xcd00>; 1002 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1003 phys = <&usb_hsphy>; 1004 phy-names = "usb2-phy"; 1005 iommus = <&apps_smmu 0x120 0x0>; 1006 snps,dis_u2_susphy_quirk; 1007 snps,dis_enblslpm_quirk; 1008 snps,has-lpm-erratum; 1009 snps,hird-threshold = /bits/ 8 <0x10>; 1010 snps,usb3_lpm_capable; 1011 maximum-speed = "super-speed"; 1012 dr_mode = "otg"; 1013 }; 1014 }; 1015 1016 remoteproc_mpss: remoteproc@6080000 { 1017 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 1018 reg = <0x0 0x06080000 0x0 0x100>; 1019 1020 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1021 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1022 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1023 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1024 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1025 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1026 interrupt-names = "wdog", 1027 "fatal", 1028 "ready", 1029 "handover", 1030 "stop-ack", 1031 "shutdown-ack"; 1032 1033 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1034 clock-names = "xo"; 1035 1036 power-domains = <&rpmpd QCM2290_VDDCX>; 1037 1038 memory-region = <&pil_modem_mem>; 1039 1040 qcom,smem-states = <&modem_smp2p_out 0>; 1041 qcom,smem-state-names = "stop"; 1042 1043 status = "disabled"; 1044 1045 glink-edge { 1046 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1047 label = "mpss"; 1048 qcom,remote-pid = <1>; 1049 mboxes = <&apcs_glb 12>; 1050 }; 1051 }; 1052 1053 remoteproc_adsp: remoteproc@ab00000 { 1054 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 1055 reg = <0x0 0x0ab00000 0x0 0x100>; 1056 1057 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1058 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1059 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1060 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1061 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1062 interrupt-names = "wdog", 1063 "fatal", 1064 "ready", 1065 "handover", 1066 "stop-ack"; 1067 1068 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1069 clock-names = "xo"; 1070 1071 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 1072 <&rpmpd QCM2290_VDD_LPI_MX>; 1073 1074 memory-region = <&pil_adsp_mem>; 1075 1076 qcom,smem-states = <&adsp_smp2p_out 0>; 1077 qcom,smem-state-names = "stop"; 1078 1079 status = "disabled"; 1080 1081 glink-edge { 1082 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 1083 label = "lpass"; 1084 qcom,remote-pid = <2>; 1085 mboxes = <&apcs_glb 8>; 1086 }; 1087 }; 1088 1089 apps_smmu: iommu@c600000 { 1090 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1091 reg = <0x0 0x0c600000 0x0 0x80000>; 1092 #iommu-cells = <2>; 1093 #global-interrupts = <1>; 1094 1095 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1160 }; 1161 1162 wifi: wifi@c800000 { 1163 compatible = "qcom,wcn3990-wifi"; 1164 reg = <0x0 0x0c800000 0x0 0x800000>; 1165 reg-names = "membase"; 1166 memory-region = <&wlan_msa_mem>; 1167 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1179 iommus = <&apps_smmu 0x1a0 0x1>; 1180 qcom,msa-fixed-perm; 1181 status = "disabled"; 1182 }; 1183 1184 watchdog@f017000 { 1185 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 1186 reg = <0x0 0x0f017000 0x0 0x1000>; 1187 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1188 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&sleep_clk>; 1190 }; 1191 1192 apcs_glb: mailbox@f111000 { 1193 compatible = "qcom,qcm2290-apcs-hmss-global"; 1194 reg = <0x0 0x0f111000 0x0 0x1000>; 1195 #mbox-cells = <1>; 1196 }; 1197 1198 timer@f120000 { 1199 compatible = "arm,armv7-timer-mem"; 1200 reg = <0x0 0x0f120000 0x0 0x1000>; 1201 #address-cells = <1>; 1202 #size-cells = <1>; 1203 ranges = <0 0x0 0x0f121000 0x8000>; 1204 1205 frame@0 { 1206 reg = <0x0 0x1000>, 1207 <0x1000 0x1000>; 1208 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1210 frame-number = <0>; 1211 }; 1212 1213 frame@2000 { 1214 reg = <0x2000 0x1000>; 1215 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1216 frame-number = <1>; 1217 status = "disabled"; 1218 }; 1219 1220 frame@3000 { 1221 reg = <0x3000 0x1000>; 1222 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1223 frame-number = <2>; 1224 status = "disabled"; 1225 }; 1226 1227 frame@4000 { 1228 reg = <0x4000 0x1000>; 1229 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1230 frame-number = <3>; 1231 status = "disabled"; 1232 }; 1233 1234 frame@5000 { 1235 reg = <0x5000 0x1000>; 1236 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1237 frame-number = <4>; 1238 status = "disabled"; 1239 }; 1240 1241 frame@6000 { 1242 reg = <0x6000 0x1000>; 1243 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1244 frame-number = <5>; 1245 status = "disabled"; 1246 }; 1247 1248 frame@7000 { 1249 reg = <0x7000 0x1000>; 1250 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1251 frame-number = <6>; 1252 status = "disabled"; 1253 }; 1254 }; 1255 1256 intc: interrupt-controller@f200000 { 1257 compatible = "arm,gic-v3"; 1258 reg = <0x0 0x0f200000 0x0 0x10000>, 1259 <0x0 0x0f300000 0x0 0x100000>; 1260 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1261 #interrupt-cells = <3>; 1262 interrupt-controller; 1263 interrupt-parent = <&intc>; 1264 #redistributor-regions = <1>; 1265 redistributor-stride = <0x0 0x20000>; 1266 }; 1267 1268 cpufreq_hw: cpufreq@f521000 { 1269 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 1270 reg = <0x0 0x0f521000 0x0 0x1000>; 1271 reg-names = "freq-domain0"; 1272 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1273 interrupt-names = "dcvsh-irq-0"; 1274 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1275 clock-names = "xo", "alternate"; 1276 1277 #freq-domain-cells = <1>; 1278 #clock-cells = <1>; 1279 }; 1280 }; 1281 1282 thermal-zones { 1283 mapss-thermal { 1284 polling-delay-passive = <0>; 1285 polling-delay = <0>; 1286 1287 thermal-sensors = <&tsens0 0>; 1288 1289 trips { 1290 mapss_alert0: trip-point0 { 1291 temperature = <90000>; 1292 hysteresis = <2000>; 1293 type = "passive"; 1294 }; 1295 1296 mapss_alert1: trip-point1 { 1297 temperature = <95000>; 1298 hysteresis = <2000>; 1299 type = "passive"; 1300 }; 1301 1302 mapss_crit: mapss-crit { 1303 temperature = <110000>; 1304 hysteresis = <1000>; 1305 type = "critical"; 1306 }; 1307 }; 1308 }; 1309 1310 video-thermal { 1311 polling-delay-passive = <0>; 1312 polling-delay = <0>; 1313 1314 thermal-sensors = <&tsens0 1>; 1315 1316 trips { 1317 video_alert0: trip-point0 { 1318 temperature = <90000>; 1319 hysteresis = <2000>; 1320 type = "passive"; 1321 }; 1322 1323 video_alert1: trip-point1 { 1324 temperature = <95000>; 1325 hysteresis = <2000>; 1326 type = "passive"; 1327 }; 1328 1329 video_crit: video-crit { 1330 temperature = <110000>; 1331 hysteresis = <1000>; 1332 type = "critical"; 1333 }; 1334 }; 1335 }; 1336 1337 wlan-thermal { 1338 polling-delay-passive = <0>; 1339 polling-delay = <0>; 1340 1341 thermal-sensors = <&tsens0 2>; 1342 1343 trips { 1344 wlan_alert0: trip-point0 { 1345 temperature = <90000>; 1346 hysteresis = <2000>; 1347 type = "passive"; 1348 }; 1349 1350 wlan_alert1: trip-point1 { 1351 temperature = <95000>; 1352 hysteresis = <2000>; 1353 type = "passive"; 1354 }; 1355 1356 wlan_crit: wlan-crit { 1357 temperature = <110000>; 1358 hysteresis = <1000>; 1359 type = "critical"; 1360 }; 1361 }; 1362 }; 1363 1364 cpuss0-thermal { 1365 polling-delay-passive = <0>; 1366 polling-delay = <0>; 1367 1368 thermal-sensors = <&tsens0 3>; 1369 1370 trips { 1371 cpuss0_alert0: trip-point0 { 1372 temperature = <90000>; 1373 hysteresis = <2000>; 1374 type = "passive"; 1375 }; 1376 1377 cpuss0_alert1: trip-point1 { 1378 temperature = <95000>; 1379 hysteresis = <2000>; 1380 type = "passive"; 1381 }; 1382 1383 cpuss0_crit: cpuss0-crit { 1384 temperature = <110000>; 1385 hysteresis = <1000>; 1386 type = "critical"; 1387 }; 1388 }; 1389 }; 1390 1391 cpuss1-thermal { 1392 polling-delay-passive = <0>; 1393 polling-delay = <0>; 1394 1395 thermal-sensors = <&tsens0 4>; 1396 1397 trips { 1398 cpuss1_alert0: trip-point0 { 1399 temperature = <90000>; 1400 hysteresis = <2000>; 1401 type = "passive"; 1402 }; 1403 1404 cpuss1_alert1: trip-point1 { 1405 temperature = <95000>; 1406 hysteresis = <2000>; 1407 type = "passive"; 1408 }; 1409 1410 cpuss1_crit: cpuss1-crit { 1411 temperature = <110000>; 1412 hysteresis = <1000>; 1413 type = "critical"; 1414 }; 1415 }; 1416 }; 1417 1418 mdm0-thermal { 1419 polling-delay-passive = <0>; 1420 polling-delay = <0>; 1421 1422 thermal-sensors = <&tsens0 5>; 1423 1424 trips { 1425 mdm0_alert0: trip-point0 { 1426 temperature = <90000>; 1427 hysteresis = <2000>; 1428 type = "passive"; 1429 }; 1430 1431 mdm0_alert1: trip-point1 { 1432 temperature = <95000>; 1433 hysteresis = <2000>; 1434 type = "passive"; 1435 }; 1436 1437 mdm0_crit: mdm0-crit { 1438 temperature = <110000>; 1439 hysteresis = <1000>; 1440 type = "critical"; 1441 }; 1442 }; 1443 }; 1444 1445 mdm1-thermal { 1446 polling-delay-passive = <0>; 1447 polling-delay = <0>; 1448 1449 thermal-sensors = <&tsens0 6>; 1450 1451 trips { 1452 mdm1_alert0: trip-point0 { 1453 temperature = <90000>; 1454 hysteresis = <2000>; 1455 type = "passive"; 1456 }; 1457 1458 mdm1_alert1: trip-point1 { 1459 temperature = <95000>; 1460 hysteresis = <2000>; 1461 type = "passive"; 1462 }; 1463 1464 mdm1_crit: mdm1-crit { 1465 temperature = <110000>; 1466 hysteresis = <1000>; 1467 type = "critical"; 1468 }; 1469 }; 1470 }; 1471 1472 gpu-thermal { 1473 polling-delay-passive = <0>; 1474 polling-delay = <0>; 1475 1476 thermal-sensors = <&tsens0 7>; 1477 1478 trips { 1479 gpu_alert0: trip-point0 { 1480 temperature = <90000>; 1481 hysteresis = <2000>; 1482 type = "passive"; 1483 }; 1484 1485 gpu_alert1: trip-point1 { 1486 temperature = <95000>; 1487 hysteresis = <2000>; 1488 type = "passive"; 1489 }; 1490 1491 gpu_crit: gpu-crit { 1492 temperature = <110000>; 1493 hysteresis = <1000>; 1494 type = "critical"; 1495 }; 1496 }; 1497 }; 1498 1499 hm-center-thermal { 1500 polling-delay-passive = <0>; 1501 polling-delay = <0>; 1502 1503 thermal-sensors = <&tsens0 8>; 1504 1505 trips { 1506 hm_center_alert0: trip-point0 { 1507 temperature = <90000>; 1508 hysteresis = <2000>; 1509 type = "passive"; 1510 }; 1511 1512 hm_center_alert1: trip-point1 { 1513 temperature = <95000>; 1514 hysteresis = <2000>; 1515 type = "passive"; 1516 }; 1517 1518 hm_center_crit: hm-center-crit { 1519 temperature = <110000>; 1520 hysteresis = <1000>; 1521 type = "critical"; 1522 }; 1523 }; 1524 }; 1525 1526 camera-thermal { 1527 polling-delay-passive = <0>; 1528 polling-delay = <0>; 1529 1530 thermal-sensors = <&tsens0 9>; 1531 1532 trips { 1533 camera_alert0: trip-point0 { 1534 temperature = <90000>; 1535 hysteresis = <2000>; 1536 type = "passive"; 1537 }; 1538 1539 camera_alert1: trip-point1 { 1540 temperature = <95000>; 1541 hysteresis = <2000>; 1542 type = "passive"; 1543 }; 1544 1545 camera_crit: camera-crit { 1546 temperature = <110000>; 1547 hysteresis = <1000>; 1548 type = "critical"; 1549 }; 1550 }; 1551 }; 1552 }; 1553 1554 timer { 1555 compatible = "arm,armv8-timer"; 1556 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1557 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1558 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1559 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1560 }; 1561}; 1562