xref: /openbmc/linux/arch/arm64/boot/dts/qcom/pms405.dtsi (revision 47ebd031)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, Linaro Limited
4 */
5
6#include <dt-bindings/spmi/spmi.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/iio/qcom,spmi-vadc.h>
9#include <dt-bindings/thermal/thermal.h>
10
11/ {
12	thermal-zones {
13		pms405-thermal {
14			polling-delay-passive = <250>;
15			polling-delay = <1000>;
16
17			thermal-sensors = <&pms405_temp>;
18
19			trips {
20				pms405_alert0: pms405-alert0 {
21					temperature = <105000>;
22					hysteresis = <2000>;
23					type = "passive";
24				};
25				pms405_crit: pms405-crit {
26					temperature = <125000>;
27					hysteresis = <2000>;
28					type = "critical";
29				};
30			};
31		};
32	};
33};
34
35&spmi_bus {
36	pms405_0: pms405@0 {
37		compatible = "qcom,pms405", "qcom,spmi-pmic";
38		reg = <0x0 SPMI_USID>;
39		#address-cells = <1>;
40		#size-cells = <0>;
41
42		pms405_gpios: gpio@c000 {
43			compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
44			reg = <0xc000>;
45			gpio-controller;
46			gpio-ranges = <&pms405_gpios 0 0 12>;
47			#gpio-cells = <2>;
48			interrupt-controller;
49			#interrupt-cells = <2>;
50		};
51
52		pon@800 {
53			compatible = "qcom,pms405-pon";
54			reg = <0x0800>;
55			mode-bootloader = <0x2>;
56			mode-recovery = <0x1>;
57
58			pwrkey {
59				compatible = "qcom,pm8941-pwrkey";
60				interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
61				debounce = <15625>;
62				bias-pull-up;
63				linux,code = <KEY_POWER>;
64			};
65		};
66
67		pms405_temp: temp-alarm@2400 {
68			compatible = "qcom,spmi-temp-alarm";
69			reg = <0x2400>;
70			interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
71			io-channels = <&pms405_adc ADC5_DIE_TEMP>;
72			io-channel-names = "thermal";
73			#thermal-sensor-cells = <0>;
74		};
75
76		pms405_adc: adc@3100 {
77			compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
78			reg = <0x3100>;
79			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
80			#address-cells = <1>;
81			#size-cells = <0>;
82			#io-channel-cells = <1>;
83
84			ref_gnd@0 {
85				reg = <ADC5_REF_GND>;
86				qcom,pre-scaling = <1 1>;
87			};
88
89			vref_1p25@1 {
90				reg = <ADC5_1P25VREF>;
91				qcom,pre-scaling = <1 1>;
92			};
93
94			pon_1: vph_pwr@131 {
95				reg = <ADC5_VPH_PWR>;
96				qcom,pre-scaling = <1 3>;
97			};
98
99			die_temp@6 {
100				reg = <ADC5_DIE_TEMP>;
101				qcom,pre-scaling = <1 1>;
102			};
103
104			pa_therm1: thermistor1@77 {
105				reg = <ADC5_AMUX_THM1_100K_PU>;
106				qcom,ratiometric;
107				qcom,hw-settle-time = <200>;
108				qcom,pre-scaling = <1 1>;
109			};
110
111			pa_therm3: thermistor3@79 {
112				reg = <ADC5_AMUX_THM3_100K_PU>;
113				qcom,ratiometric;
114				qcom,hw-settle-time = <200>;
115				qcom,pre-scaling = <1 1>;
116			};
117
118			xo_therm: xo_temp@76 {
119				reg = <ADC5_XO_THERM_100K_PU>;
120				qcom,ratiometric;
121				qcom,hw-settle-time = <200>;
122				qcom,pre-scaling = <1 1>;
123			};
124		};
125
126		rtc@6000 {
127			compatible = "qcom,pm8941-rtc";
128			reg = <0x6000>, <0x6100>;
129			reg-names = "rtc", "alarm";
130			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
131		};
132	};
133
134	pms405_1: pms405@1 {
135		compatible = "qcom,pms405", "qcom,spmi-pmic";
136		reg = <0x1 SPMI_USID>;
137
138		pms405_spmi_regulators: regulators {
139			compatible = "qcom,pms405-regulators";
140		};
141	};
142};
143