1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 qcom,msm-id = <292 0x0>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 memory@80000000 { 23 device_type = "memory"; 24 /* We expect the bootloader to fill in the reg */ 25 reg = <0x0 0x80000000 0x0 0x0>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 hyp_mem: memory@85800000 { 34 reg = <0x0 0x85800000 0x0 0x600000>; 35 no-map; 36 }; 37 38 xbl_mem: memory@85e00000 { 39 reg = <0x0 0x85e00000 0x0 0x100000>; 40 no-map; 41 }; 42 43 smem_mem: smem-mem@86000000 { 44 reg = <0x0 0x86000000 0x0 0x200000>; 45 no-map; 46 }; 47 48 tz_mem: memory@86200000 { 49 reg = <0x0 0x86200000 0x0 0x2d00000>; 50 no-map; 51 }; 52 53 rmtfs_mem: memory@88f00000 { 54 compatible = "qcom,rmtfs-mem"; 55 reg = <0x0 0x88f00000 0x0 0x200000>; 56 no-map; 57 58 qcom,client-id = <1>; 59 qcom,vmid = <15>; 60 }; 61 62 spss_mem: memory@8ab00000 { 63 reg = <0x0 0x8ab00000 0x0 0x700000>; 64 no-map; 65 }; 66 67 adsp_mem: memory@8b200000 { 68 reg = <0x0 0x8b200000 0x0 0x1a00000>; 69 no-map; 70 }; 71 72 mpss_mem: memory@8cc00000 { 73 reg = <0x0 0x8cc00000 0x0 0x7000000>; 74 no-map; 75 }; 76 77 venus_mem: memory@93c00000 { 78 reg = <0x0 0x93c00000 0x0 0x500000>; 79 no-map; 80 }; 81 82 mba_mem: memory@94100000 { 83 reg = <0x0 0x94100000 0x0 0x200000>; 84 no-map; 85 }; 86 87 slpi_mem: memory@94300000 { 88 reg = <0x0 0x94300000 0x0 0xf00000>; 89 no-map; 90 }; 91 92 ipa_fw_mem: memory@95200000 { 93 reg = <0x0 0x95200000 0x0 0x10000>; 94 no-map; 95 }; 96 97 ipa_gsi_mem: memory@95210000 { 98 reg = <0x0 0x95210000 0x0 0x5000>; 99 no-map; 100 }; 101 102 gpu_mem: memory@95600000 { 103 reg = <0x0 0x95600000 0x0 0x100000>; 104 no-map; 105 }; 106 107 wlan_msa_mem: memory@95700000 { 108 reg = <0x0 0x95700000 0x0 0x100000>; 109 no-map; 110 }; 111 112 mdata_mem: mpss-metadata { 113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 114 size = <0x0 0x4000>; 115 no-map; 116 }; 117 }; 118 119 clocks { 120 xo: xo-board { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <19200000>; 124 clock-output-names = "xo_board"; 125 }; 126 127 sleep_clk: sleep-clk { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <32764>; 131 }; 132 }; 133 134 cpus { 135 #address-cells = <2>; 136 #size-cells = <0>; 137 138 CPU0: cpu@0 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo280"; 141 reg = <0x0 0x0>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 145 next-level-cache = <&L2_0>; 146 L2_0: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 }; 150 }; 151 152 CPU1: cpu@1 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo280"; 155 reg = <0x0 0x1>; 156 enable-method = "psci"; 157 capacity-dmips-mhz = <1024>; 158 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 159 next-level-cache = <&L2_0>; 160 }; 161 162 CPU2: cpu@2 { 163 device_type = "cpu"; 164 compatible = "qcom,kryo280"; 165 reg = <0x0 0x2>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <1024>; 168 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 169 next-level-cache = <&L2_0>; 170 }; 171 172 CPU3: cpu@3 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo280"; 175 reg = <0x0 0x3>; 176 enable-method = "psci"; 177 capacity-dmips-mhz = <1024>; 178 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 179 next-level-cache = <&L2_0>; 180 }; 181 182 CPU4: cpu@100 { 183 device_type = "cpu"; 184 compatible = "qcom,kryo280"; 185 reg = <0x0 0x100>; 186 enable-method = "psci"; 187 capacity-dmips-mhz = <1536>; 188 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 189 next-level-cache = <&L2_1>; 190 L2_1: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 }; 194 }; 195 196 CPU5: cpu@101 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo280"; 199 reg = <0x0 0x101>; 200 enable-method = "psci"; 201 capacity-dmips-mhz = <1536>; 202 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 203 next-level-cache = <&L2_1>; 204 }; 205 206 CPU6: cpu@102 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo280"; 209 reg = <0x0 0x102>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1536>; 212 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 213 next-level-cache = <&L2_1>; 214 }; 215 216 CPU7: cpu@103 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo280"; 219 reg = <0x0 0x103>; 220 enable-method = "psci"; 221 capacity-dmips-mhz = <1536>; 222 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 223 next-level-cache = <&L2_1>; 224 }; 225 226 cpu-map { 227 cluster0 { 228 core0 { 229 cpu = <&CPU0>; 230 }; 231 232 core1 { 233 cpu = <&CPU1>; 234 }; 235 236 core2 { 237 cpu = <&CPU2>; 238 }; 239 240 core3 { 241 cpu = <&CPU3>; 242 }; 243 }; 244 245 cluster1 { 246 core0 { 247 cpu = <&CPU4>; 248 }; 249 250 core1 { 251 cpu = <&CPU5>; 252 }; 253 254 core2 { 255 cpu = <&CPU6>; 256 }; 257 258 core3 { 259 cpu = <&CPU7>; 260 }; 261 }; 262 }; 263 264 idle-states { 265 entry-method = "psci"; 266 267 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "little-retention"; 270 /* CPU Retention (C2D), L2 Active */ 271 arm,psci-suspend-param = <0x00000002>; 272 entry-latency-us = <81>; 273 exit-latency-us = <86>; 274 min-residency-us = <504>; 275 }; 276 277 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "little-power-collapse"; 280 /* CPU + L2 Power Collapse (C3, D4) */ 281 arm,psci-suspend-param = <0x40000003>; 282 entry-latency-us = <814>; 283 exit-latency-us = <4562>; 284 min-residency-us = <9183>; 285 local-timer-stop; 286 }; 287 288 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 289 compatible = "arm,idle-state"; 290 idle-state-name = "big-retention"; 291 /* CPU Retention (C2D), L2 Active */ 292 arm,psci-suspend-param = <0x00000002>; 293 entry-latency-us = <79>; 294 exit-latency-us = <82>; 295 min-residency-us = <1302>; 296 }; 297 298 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 299 compatible = "arm,idle-state"; 300 idle-state-name = "big-power-collapse"; 301 /* CPU + L2 Power Collapse (C3, D4) */ 302 arm,psci-suspend-param = <0x40000003>; 303 entry-latency-us = <724>; 304 exit-latency-us = <2027>; 305 min-residency-us = <9419>; 306 local-timer-stop; 307 }; 308 }; 309 }; 310 311 firmware { 312 scm { 313 compatible = "qcom,scm-msm8998", "qcom,scm"; 314 }; 315 }; 316 317 psci { 318 compatible = "arm,psci-1.0"; 319 method = "smc"; 320 }; 321 322 rpm-glink { 323 compatible = "qcom,glink-rpm"; 324 325 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 326 qcom,rpm-msg-ram = <&rpm_msg_ram>; 327 mboxes = <&apcs_glb 0>; 328 329 rpm_requests: rpm-requests { 330 compatible = "qcom,rpm-msm8998"; 331 qcom,glink-channels = "rpm_requests"; 332 333 rpmcc: clock-controller { 334 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 335 #clock-cells = <1>; 336 }; 337 338 rpmpd: power-controller { 339 compatible = "qcom,msm8998-rpmpd"; 340 #power-domain-cells = <1>; 341 operating-points-v2 = <&rpmpd_opp_table>; 342 343 rpmpd_opp_table: opp-table { 344 compatible = "operating-points-v2"; 345 346 rpmpd_opp_ret: opp1 { 347 opp-level = <RPM_SMD_LEVEL_RETENTION>; 348 }; 349 350 rpmpd_opp_ret_plus: opp2 { 351 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 352 }; 353 354 rpmpd_opp_min_svs: opp3 { 355 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 356 }; 357 358 rpmpd_opp_low_svs: opp4 { 359 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 360 }; 361 362 rpmpd_opp_svs: opp5 { 363 opp-level = <RPM_SMD_LEVEL_SVS>; 364 }; 365 366 rpmpd_opp_svs_plus: opp6 { 367 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 368 }; 369 370 rpmpd_opp_nom: opp7 { 371 opp-level = <RPM_SMD_LEVEL_NOM>; 372 }; 373 374 rpmpd_opp_nom_plus: opp8 { 375 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 376 }; 377 378 rpmpd_opp_turbo: opp9 { 379 opp-level = <RPM_SMD_LEVEL_TURBO>; 380 }; 381 382 rpmpd_opp_turbo_plus: opp10 { 383 opp-level = <RPM_SMD_LEVEL_BINNING>; 384 }; 385 }; 386 }; 387 }; 388 }; 389 390 smem { 391 compatible = "qcom,smem"; 392 memory-region = <&smem_mem>; 393 hwlocks = <&tcsr_mutex 3>; 394 }; 395 396 smp2p-lpass { 397 compatible = "qcom,smp2p"; 398 qcom,smem = <443>, <429>; 399 400 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 401 402 mboxes = <&apcs_glb 10>; 403 404 qcom,local-pid = <0>; 405 qcom,remote-pid = <2>; 406 407 adsp_smp2p_out: master-kernel { 408 qcom,entry-name = "master-kernel"; 409 #qcom,smem-state-cells = <1>; 410 }; 411 412 adsp_smp2p_in: slave-kernel { 413 qcom,entry-name = "slave-kernel"; 414 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 smp2p-mpss { 421 compatible = "qcom,smp2p"; 422 qcom,smem = <435>, <428>; 423 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 424 mboxes = <&apcs_glb 14>; 425 qcom,local-pid = <0>; 426 qcom,remote-pid = <1>; 427 428 modem_smp2p_out: master-kernel { 429 qcom,entry-name = "master-kernel"; 430 #qcom,smem-state-cells = <1>; 431 }; 432 433 modem_smp2p_in: slave-kernel { 434 qcom,entry-name = "slave-kernel"; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 }; 438 }; 439 440 smp2p-slpi { 441 compatible = "qcom,smp2p"; 442 qcom,smem = <481>, <430>; 443 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 444 mboxes = <&apcs_glb 26>; 445 qcom,local-pid = <0>; 446 qcom,remote-pid = <3>; 447 448 slpi_smp2p_out: master-kernel { 449 qcom,entry-name = "master-kernel"; 450 #qcom,smem-state-cells = <1>; 451 }; 452 453 slpi_smp2p_in: slave-kernel { 454 qcom,entry-name = "slave-kernel"; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 }; 458 }; 459 460 thermal-zones { 461 cpu0-thermal { 462 polling-delay-passive = <250>; 463 polling-delay = <1000>; 464 465 thermal-sensors = <&tsens0 1>; 466 467 trips { 468 cpu0_alert0: trip-point0 { 469 temperature = <75000>; 470 hysteresis = <2000>; 471 type = "passive"; 472 }; 473 474 cpu0_crit: cpu-crit { 475 temperature = <110000>; 476 hysteresis = <2000>; 477 type = "critical"; 478 }; 479 }; 480 }; 481 482 cpu1-thermal { 483 polling-delay-passive = <250>; 484 polling-delay = <1000>; 485 486 thermal-sensors = <&tsens0 2>; 487 488 trips { 489 cpu1_alert0: trip-point0 { 490 temperature = <75000>; 491 hysteresis = <2000>; 492 type = "passive"; 493 }; 494 495 cpu1_crit: cpu-crit { 496 temperature = <110000>; 497 hysteresis = <2000>; 498 type = "critical"; 499 }; 500 }; 501 }; 502 503 cpu2-thermal { 504 polling-delay-passive = <250>; 505 polling-delay = <1000>; 506 507 thermal-sensors = <&tsens0 3>; 508 509 trips { 510 cpu2_alert0: trip-point0 { 511 temperature = <75000>; 512 hysteresis = <2000>; 513 type = "passive"; 514 }; 515 516 cpu2_crit: cpu-crit { 517 temperature = <110000>; 518 hysteresis = <2000>; 519 type = "critical"; 520 }; 521 }; 522 }; 523 524 cpu3-thermal { 525 polling-delay-passive = <250>; 526 polling-delay = <1000>; 527 528 thermal-sensors = <&tsens0 4>; 529 530 trips { 531 cpu3_alert0: trip-point0 { 532 temperature = <75000>; 533 hysteresis = <2000>; 534 type = "passive"; 535 }; 536 537 cpu3_crit: cpu-crit { 538 temperature = <110000>; 539 hysteresis = <2000>; 540 type = "critical"; 541 }; 542 }; 543 }; 544 545 cpu4-thermal { 546 polling-delay-passive = <250>; 547 polling-delay = <1000>; 548 549 thermal-sensors = <&tsens0 7>; 550 551 trips { 552 cpu4_alert0: trip-point0 { 553 temperature = <75000>; 554 hysteresis = <2000>; 555 type = "passive"; 556 }; 557 558 cpu4_crit: cpu-crit { 559 temperature = <110000>; 560 hysteresis = <2000>; 561 type = "critical"; 562 }; 563 }; 564 }; 565 566 cpu5-thermal { 567 polling-delay-passive = <250>; 568 polling-delay = <1000>; 569 570 thermal-sensors = <&tsens0 8>; 571 572 trips { 573 cpu5_alert0: trip-point0 { 574 temperature = <75000>; 575 hysteresis = <2000>; 576 type = "passive"; 577 }; 578 579 cpu5_crit: cpu-crit { 580 temperature = <110000>; 581 hysteresis = <2000>; 582 type = "critical"; 583 }; 584 }; 585 }; 586 587 cpu6-thermal { 588 polling-delay-passive = <250>; 589 polling-delay = <1000>; 590 591 thermal-sensors = <&tsens0 9>; 592 593 trips { 594 cpu6_alert0: trip-point0 { 595 temperature = <75000>; 596 hysteresis = <2000>; 597 type = "passive"; 598 }; 599 600 cpu6_crit: cpu-crit { 601 temperature = <110000>; 602 hysteresis = <2000>; 603 type = "critical"; 604 }; 605 }; 606 }; 607 608 cpu7-thermal { 609 polling-delay-passive = <250>; 610 polling-delay = <1000>; 611 612 thermal-sensors = <&tsens0 10>; 613 614 trips { 615 cpu7_alert0: trip-point0 { 616 temperature = <75000>; 617 hysteresis = <2000>; 618 type = "passive"; 619 }; 620 621 cpu7_crit: cpu-crit { 622 temperature = <110000>; 623 hysteresis = <2000>; 624 type = "critical"; 625 }; 626 }; 627 }; 628 629 gpu-bottom-thermal { 630 polling-delay-passive = <250>; 631 polling-delay = <1000>; 632 633 thermal-sensors = <&tsens0 12>; 634 635 trips { 636 gpu1_alert0: trip-point0 { 637 temperature = <90000>; 638 hysteresis = <2000>; 639 type = "hot"; 640 }; 641 }; 642 }; 643 644 gpu-top-thermal { 645 polling-delay-passive = <250>; 646 polling-delay = <1000>; 647 648 thermal-sensors = <&tsens0 13>; 649 650 trips { 651 gpu2_alert0: trip-point0 { 652 temperature = <90000>; 653 hysteresis = <2000>; 654 type = "hot"; 655 }; 656 }; 657 }; 658 659 clust0-mhm-thermal { 660 polling-delay-passive = <250>; 661 polling-delay = <1000>; 662 663 thermal-sensors = <&tsens0 5>; 664 665 trips { 666 cluster0_mhm_alert0: trip-point0 { 667 temperature = <90000>; 668 hysteresis = <2000>; 669 type = "hot"; 670 }; 671 }; 672 }; 673 674 clust1-mhm-thermal { 675 polling-delay-passive = <250>; 676 polling-delay = <1000>; 677 678 thermal-sensors = <&tsens0 6>; 679 680 trips { 681 cluster1_mhm_alert0: trip-point0 { 682 temperature = <90000>; 683 hysteresis = <2000>; 684 type = "hot"; 685 }; 686 }; 687 }; 688 689 cluster1-l2-thermal { 690 polling-delay-passive = <250>; 691 polling-delay = <1000>; 692 693 thermal-sensors = <&tsens0 11>; 694 695 trips { 696 cluster1_l2_alert0: trip-point0 { 697 temperature = <90000>; 698 hysteresis = <2000>; 699 type = "hot"; 700 }; 701 }; 702 }; 703 704 modem-thermal { 705 polling-delay-passive = <250>; 706 polling-delay = <1000>; 707 708 thermal-sensors = <&tsens1 1>; 709 710 trips { 711 modem_alert0: trip-point0 { 712 temperature = <90000>; 713 hysteresis = <2000>; 714 type = "hot"; 715 }; 716 }; 717 }; 718 719 mem-thermal { 720 polling-delay-passive = <250>; 721 polling-delay = <1000>; 722 723 thermal-sensors = <&tsens1 2>; 724 725 trips { 726 mem_alert0: trip-point0 { 727 temperature = <90000>; 728 hysteresis = <2000>; 729 type = "hot"; 730 }; 731 }; 732 }; 733 734 wlan-thermal { 735 polling-delay-passive = <250>; 736 polling-delay = <1000>; 737 738 thermal-sensors = <&tsens1 3>; 739 740 trips { 741 wlan_alert0: trip-point0 { 742 temperature = <90000>; 743 hysteresis = <2000>; 744 type = "hot"; 745 }; 746 }; 747 }; 748 749 q6-dsp-thermal { 750 polling-delay-passive = <250>; 751 polling-delay = <1000>; 752 753 thermal-sensors = <&tsens1 4>; 754 755 trips { 756 q6_dsp_alert0: trip-point0 { 757 temperature = <90000>; 758 hysteresis = <2000>; 759 type = "hot"; 760 }; 761 }; 762 }; 763 764 camera-thermal { 765 polling-delay-passive = <250>; 766 polling-delay = <1000>; 767 768 thermal-sensors = <&tsens1 5>; 769 770 trips { 771 camera_alert0: trip-point0 { 772 temperature = <90000>; 773 hysteresis = <2000>; 774 type = "hot"; 775 }; 776 }; 777 }; 778 779 multimedia-thermal { 780 polling-delay-passive = <250>; 781 polling-delay = <1000>; 782 783 thermal-sensors = <&tsens1 6>; 784 785 trips { 786 multimedia_alert0: trip-point0 { 787 temperature = <90000>; 788 hysteresis = <2000>; 789 type = "hot"; 790 }; 791 }; 792 }; 793 }; 794 795 timer { 796 compatible = "arm,armv8-timer"; 797 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 798 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 799 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 800 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 801 }; 802 803 soc: soc { 804 #address-cells = <1>; 805 #size-cells = <1>; 806 ranges = <0 0 0 0xffffffff>; 807 compatible = "simple-bus"; 808 809 gcc: clock-controller@100000 { 810 compatible = "qcom,gcc-msm8998"; 811 #clock-cells = <1>; 812 #reset-cells = <1>; 813 #power-domain-cells = <1>; 814 reg = <0x00100000 0xb0000>; 815 816 clock-names = "xo", "sleep_clk"; 817 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 818 819 /* 820 * The hypervisor typically configures the memory region where these clocks 821 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 822 * these clocks on a device with such configuration (e.g. because they are 823 * enabled but unused during boot-up), the device will most likely decide 824 * to reboot. 825 * In light of that, we are conservative here and we list all such clocks 826 * as protected. The board dts (or a user-supplied dts) can override the 827 * list of protected clocks if it differs from the norm, and it is in fact 828 * desired for the HLOS to manage these clocks 829 */ 830 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 831 <SSC_XO>, 832 <SSC_CNOC_AHBS_CLK>; 833 }; 834 835 rpm_msg_ram: sram@778000 { 836 compatible = "qcom,rpm-msg-ram"; 837 reg = <0x00778000 0x7000>; 838 }; 839 840 qfprom: qfprom@784000 { 841 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 842 reg = <0x00784000 0x621c>; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 846 qusb2_hstx_trim: hstx-trim@23a { 847 reg = <0x23a 0x1>; 848 bits = <0 4>; 849 }; 850 }; 851 852 tsens0: thermal@10ab000 { 853 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 854 reg = <0x010ab000 0x1000>, /* TM */ 855 <0x010aa000 0x1000>; /* SROT */ 856 #qcom,sensors = <14>; 857 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-names = "uplow", "critical"; 860 #thermal-sensor-cells = <1>; 861 }; 862 863 tsens1: thermal@10ae000 { 864 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 865 reg = <0x010ae000 0x1000>, /* TM */ 866 <0x010ad000 0x1000>; /* SROT */ 867 #qcom,sensors = <8>; 868 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "uplow", "critical"; 871 #thermal-sensor-cells = <1>; 872 }; 873 874 anoc1_smmu: iommu@1680000 { 875 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 876 reg = <0x01680000 0x10000>; 877 #iommu-cells = <1>; 878 879 #global-interrupts = <0>; 880 interrupts = 881 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 882 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 883 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 884 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 885 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 886 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 887 }; 888 889 anoc2_smmu: iommu@16c0000 { 890 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 891 reg = <0x016c0000 0x40000>; 892 #iommu-cells = <1>; 893 894 #global-interrupts = <0>; 895 interrupts = 896 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 897 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 898 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 899 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 900 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 902 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 903 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 904 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 905 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 906 }; 907 908 pcie0: pci@1c00000 { 909 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 910 reg = <0x01c00000 0x2000>, 911 <0x1b000000 0xf1d>, 912 <0x1b000f20 0xa8>, 913 <0x1b100000 0x100000>; 914 reg-names = "parf", "dbi", "elbi", "config"; 915 device_type = "pci"; 916 linux,pci-domain = <0>; 917 bus-range = <0x00 0xff>; 918 #address-cells = <3>; 919 #size-cells = <2>; 920 num-lanes = <1>; 921 phys = <&pciephy>; 922 phy-names = "pciephy"; 923 status = "disabled"; 924 925 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 926 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 927 928 #interrupt-cells = <1>; 929 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "msi"; 931 interrupt-map-mask = <0 0 0 0x7>; 932 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 933 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 934 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 935 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 936 937 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 938 <&gcc GCC_PCIE_0_AUX_CLK>, 939 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 940 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 941 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 942 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 943 944 power-domains = <&gcc PCIE_0_GDSC>; 945 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 946 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 947 }; 948 949 pcie_phy: phy@1c06000 { 950 compatible = "qcom,msm8998-qmp-pcie-phy"; 951 reg = <0x01c06000 0x18c>; 952 #address-cells = <1>; 953 #size-cells = <1>; 954 status = "disabled"; 955 ranges; 956 957 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 958 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 959 <&gcc GCC_PCIE_CLKREF_CLK>; 960 clock-names = "aux", "cfg_ahb", "ref"; 961 962 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 963 reset-names = "phy", "common"; 964 965 vdda-phy-supply = <&vreg_l1a_0p875>; 966 vdda-pll-supply = <&vreg_l2a_1p2>; 967 968 pciephy: phy@1c06800 { 969 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 970 #phy-cells = <0>; 971 972 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 973 clock-names = "pipe0"; 974 clock-output-names = "pcie_0_pipe_clk_src"; 975 #clock-cells = <0>; 976 }; 977 }; 978 979 ufshc: ufshc@1da4000 { 980 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 981 reg = <0x01da4000 0x2500>; 982 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 983 phys = <&ufsphy_lanes>; 984 phy-names = "ufsphy"; 985 lanes-per-direction = <2>; 986 power-domains = <&gcc UFS_GDSC>; 987 status = "disabled"; 988 #reset-cells = <1>; 989 990 clock-names = 991 "core_clk", 992 "bus_aggr_clk", 993 "iface_clk", 994 "core_clk_unipro", 995 "ref_clk", 996 "tx_lane0_sync_clk", 997 "rx_lane0_sync_clk", 998 "rx_lane1_sync_clk"; 999 clocks = 1000 <&gcc GCC_UFS_AXI_CLK>, 1001 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1002 <&gcc GCC_UFS_AHB_CLK>, 1003 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1004 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1005 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1006 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1007 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1008 freq-table-hz = 1009 <50000000 200000000>, 1010 <0 0>, 1011 <0 0>, 1012 <37500000 150000000>, 1013 <0 0>, 1014 <0 0>, 1015 <0 0>, 1016 <0 0>; 1017 1018 resets = <&gcc GCC_UFS_BCR>; 1019 reset-names = "rst"; 1020 }; 1021 1022 ufsphy: phy@1da7000 { 1023 compatible = "qcom,msm8998-qmp-ufs-phy"; 1024 reg = <0x01da7000 0x18c>; 1025 #address-cells = <1>; 1026 #size-cells = <1>; 1027 status = "disabled"; 1028 ranges; 1029 1030 clock-names = 1031 "ref", 1032 "ref_aux"; 1033 clocks = 1034 <&gcc GCC_UFS_CLKREF_CLK>, 1035 <&gcc GCC_UFS_PHY_AUX_CLK>; 1036 1037 reset-names = "ufsphy"; 1038 resets = <&ufshc 0>; 1039 1040 ufsphy_lanes: phy@1da7400 { 1041 reg = <0x01da7400 0x128>, 1042 <0x01da7600 0x1fc>, 1043 <0x01da7c00 0x1dc>, 1044 <0x01da7800 0x128>, 1045 <0x01da7a00 0x1fc>; 1046 #phy-cells = <0>; 1047 }; 1048 }; 1049 1050 tcsr_mutex: hwlock@1f40000 { 1051 compatible = "qcom,tcsr-mutex"; 1052 reg = <0x01f40000 0x20000>; 1053 #hwlock-cells = <1>; 1054 }; 1055 1056 tcsr_regs_1: syscon@1f60000 { 1057 compatible = "qcom,msm8998-tcsr", "syscon"; 1058 reg = <0x01f60000 0x20000>; 1059 }; 1060 1061 tlmm: pinctrl@3400000 { 1062 compatible = "qcom,msm8998-pinctrl"; 1063 reg = <0x03400000 0xc00000>; 1064 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1065 gpio-ranges = <&tlmm 0 0 150>; 1066 gpio-controller; 1067 #gpio-cells = <2>; 1068 interrupt-controller; 1069 #interrupt-cells = <2>; 1070 1071 sdc2_on: sdc2-on-state { 1072 clk-pins { 1073 pins = "sdc2_clk"; 1074 drive-strength = <16>; 1075 bias-disable; 1076 }; 1077 1078 cmd-pins { 1079 pins = "sdc2_cmd"; 1080 drive-strength = <10>; 1081 bias-pull-up; 1082 }; 1083 1084 data-pins { 1085 pins = "sdc2_data"; 1086 drive-strength = <10>; 1087 bias-pull-up; 1088 }; 1089 }; 1090 1091 sdc2_off: sdc2-off-state { 1092 clk-pins { 1093 pins = "sdc2_clk"; 1094 drive-strength = <2>; 1095 bias-disable; 1096 }; 1097 1098 cmd-pins { 1099 pins = "sdc2_cmd"; 1100 drive-strength = <2>; 1101 bias-pull-up; 1102 }; 1103 1104 data-pins { 1105 pins = "sdc2_data"; 1106 drive-strength = <2>; 1107 bias-pull-up; 1108 }; 1109 }; 1110 1111 sdc2_cd: sdc2-cd-state { 1112 pins = "gpio95"; 1113 function = "gpio"; 1114 bias-pull-up; 1115 drive-strength = <2>; 1116 }; 1117 1118 blsp1_uart3_on: blsp1-uart3-on-state { 1119 tx-pins { 1120 pins = "gpio45"; 1121 function = "blsp_uart3_a"; 1122 drive-strength = <2>; 1123 bias-disable; 1124 }; 1125 1126 rx-pins { 1127 pins = "gpio46"; 1128 function = "blsp_uart3_a"; 1129 drive-strength = <2>; 1130 bias-disable; 1131 }; 1132 1133 cts-pins { 1134 pins = "gpio47"; 1135 function = "blsp_uart3_a"; 1136 drive-strength = <2>; 1137 bias-disable; 1138 }; 1139 1140 rfr-pins { 1141 pins = "gpio48"; 1142 function = "blsp_uart3_a"; 1143 drive-strength = <2>; 1144 bias-disable; 1145 }; 1146 }; 1147 1148 blsp1_i2c1_default: blsp1-i2c1-default-state { 1149 pins = "gpio2", "gpio3"; 1150 function = "blsp_i2c1"; 1151 drive-strength = <2>; 1152 bias-disable; 1153 }; 1154 1155 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1156 pins = "gpio2", "gpio3"; 1157 function = "blsp_i2c1"; 1158 drive-strength = <2>; 1159 bias-pull-up; 1160 }; 1161 1162 blsp1_i2c2_default: blsp1-i2c2-default-state { 1163 pins = "gpio32", "gpio33"; 1164 function = "blsp_i2c2"; 1165 drive-strength = <2>; 1166 bias-disable; 1167 }; 1168 1169 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1170 pins = "gpio32", "gpio33"; 1171 function = "blsp_i2c2"; 1172 drive-strength = <2>; 1173 bias-pull-up; 1174 }; 1175 1176 blsp1_i2c3_default: blsp1-i2c3-default-state { 1177 pins = "gpio47", "gpio48"; 1178 function = "blsp_i2c3"; 1179 drive-strength = <2>; 1180 bias-disable; 1181 }; 1182 1183 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1184 pins = "gpio47", "gpio48"; 1185 function = "blsp_i2c3"; 1186 drive-strength = <2>; 1187 bias-pull-up; 1188 }; 1189 1190 blsp1_i2c4_default: blsp1-i2c4-default-state { 1191 pins = "gpio10", "gpio11"; 1192 function = "blsp_i2c4"; 1193 drive-strength = <2>; 1194 bias-disable; 1195 }; 1196 1197 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1198 pins = "gpio10", "gpio11"; 1199 function = "blsp_i2c4"; 1200 drive-strength = <2>; 1201 bias-pull-up; 1202 }; 1203 1204 blsp1_i2c5_default: blsp1-i2c5-default-state { 1205 pins = "gpio87", "gpio88"; 1206 function = "blsp_i2c5"; 1207 drive-strength = <2>; 1208 bias-disable; 1209 }; 1210 1211 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1212 pins = "gpio87", "gpio88"; 1213 function = "blsp_i2c5"; 1214 drive-strength = <2>; 1215 bias-pull-up; 1216 }; 1217 1218 blsp1_i2c6_default: blsp1-i2c6-default-state { 1219 pins = "gpio43", "gpio44"; 1220 function = "blsp_i2c6"; 1221 drive-strength = <2>; 1222 bias-disable; 1223 }; 1224 1225 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1226 pins = "gpio43", "gpio44"; 1227 function = "blsp_i2c6"; 1228 drive-strength = <2>; 1229 bias-pull-up; 1230 }; 1231 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1232 blsp2_i2c1_default: blsp2-i2c1-default-state { 1233 pins = "gpio55", "gpio56"; 1234 function = "blsp_i2c7"; 1235 drive-strength = <2>; 1236 bias-disable; 1237 }; 1238 1239 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1240 pins = "gpio55", "gpio56"; 1241 function = "blsp_i2c7"; 1242 drive-strength = <2>; 1243 bias-pull-up; 1244 }; 1245 1246 blsp2_i2c2_default: blsp2-i2c2-default-state { 1247 pins = "gpio6", "gpio7"; 1248 function = "blsp_i2c8"; 1249 drive-strength = <2>; 1250 bias-disable; 1251 }; 1252 1253 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1254 pins = "gpio6", "gpio7"; 1255 function = "blsp_i2c8"; 1256 drive-strength = <2>; 1257 bias-pull-up; 1258 }; 1259 1260 blsp2_i2c3_default: blsp2-i2c3-default-state { 1261 pins = "gpio51", "gpio52"; 1262 function = "blsp_i2c9"; 1263 drive-strength = <2>; 1264 bias-disable; 1265 }; 1266 1267 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1268 pins = "gpio51", "gpio52"; 1269 function = "blsp_i2c9"; 1270 drive-strength = <2>; 1271 bias-pull-up; 1272 }; 1273 1274 blsp2_i2c4_default: blsp2-i2c4-default-state { 1275 pins = "gpio67", "gpio68"; 1276 function = "blsp_i2c10"; 1277 drive-strength = <2>; 1278 bias-disable; 1279 }; 1280 1281 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1282 pins = "gpio67", "gpio68"; 1283 function = "blsp_i2c10"; 1284 drive-strength = <2>; 1285 bias-pull-up; 1286 }; 1287 1288 blsp2_i2c5_default: blsp2-i2c5-default-state { 1289 pins = "gpio60", "gpio61"; 1290 function = "blsp_i2c11"; 1291 drive-strength = <2>; 1292 bias-disable; 1293 }; 1294 1295 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1296 pins = "gpio60", "gpio61"; 1297 function = "blsp_i2c11"; 1298 drive-strength = <2>; 1299 bias-pull-up; 1300 }; 1301 1302 blsp2_i2c6_default: blsp2-i2c6-default-state { 1303 pins = "gpio83", "gpio84"; 1304 function = "blsp_i2c12"; 1305 drive-strength = <2>; 1306 bias-disable; 1307 }; 1308 1309 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1310 pins = "gpio83", "gpio84"; 1311 function = "blsp_i2c12"; 1312 drive-strength = <2>; 1313 bias-pull-up; 1314 }; 1315 }; 1316 1317 remoteproc_mss: remoteproc@4080000 { 1318 compatible = "qcom,msm8998-mss-pil"; 1319 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1320 reg-names = "qdsp6", "rmb"; 1321 1322 interrupts-extended = 1323 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1324 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1325 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1326 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1327 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1328 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1329 interrupt-names = "wdog", "fatal", "ready", 1330 "handover", "stop-ack", 1331 "shutdown-ack"; 1332 1333 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1334 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1335 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1336 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1337 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1338 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1339 <&rpmcc RPM_SMD_QDSS_CLK>, 1340 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1341 clock-names = "iface", "bus", "mem", "gpll0_mss", 1342 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1343 1344 qcom,smem-states = <&modem_smp2p_out 0>; 1345 qcom,smem-state-names = "stop"; 1346 1347 resets = <&gcc GCC_MSS_RESTART>; 1348 reset-names = "mss_restart"; 1349 1350 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1351 1352 power-domains = <&rpmpd MSM8998_VDDCX>, 1353 <&rpmpd MSM8998_VDDMX>; 1354 power-domain-names = "cx", "mx"; 1355 1356 status = "disabled"; 1357 1358 mba { 1359 memory-region = <&mba_mem>; 1360 }; 1361 1362 mpss { 1363 memory-region = <&mpss_mem>; 1364 }; 1365 1366 metadata { 1367 memory-region = <&mdata_mem>; 1368 }; 1369 1370 glink-edge { 1371 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1372 label = "modem"; 1373 qcom,remote-pid = <1>; 1374 mboxes = <&apcs_glb 15>; 1375 }; 1376 }; 1377 1378 adreno_gpu: gpu@5000000 { 1379 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1380 reg = <0x05000000 0x40000>; 1381 reg-names = "kgsl_3d0_reg_memory"; 1382 1383 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1384 <&gpucc RBBMTIMER_CLK>, 1385 <&gcc GCC_BIMC_GFX_CLK>, 1386 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1387 <&gpucc RBCPR_CLK>, 1388 <&gpucc GFX3D_CLK>; 1389 clock-names = "iface", 1390 "rbbmtimer", 1391 "mem", 1392 "mem_iface", 1393 "rbcpr", 1394 "core"; 1395 1396 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1397 iommus = <&adreno_smmu 0>; 1398 operating-points-v2 = <&gpu_opp_table>; 1399 power-domains = <&rpmpd MSM8998_VDDMX>; 1400 status = "disabled"; 1401 1402 gpu_opp_table: opp-table { 1403 compatible = "operating-points-v2"; 1404 opp-710000097 { 1405 opp-hz = /bits/ 64 <710000097>; 1406 opp-level = <RPM_SMD_LEVEL_TURBO>; 1407 opp-supported-hw = <0xff>; 1408 }; 1409 1410 opp-670000048 { 1411 opp-hz = /bits/ 64 <670000048>; 1412 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1413 opp-supported-hw = <0xff>; 1414 }; 1415 1416 opp-596000097 { 1417 opp-hz = /bits/ 64 <596000097>; 1418 opp-level = <RPM_SMD_LEVEL_NOM>; 1419 opp-supported-hw = <0xff>; 1420 }; 1421 1422 opp-515000097 { 1423 opp-hz = /bits/ 64 <515000097>; 1424 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1425 opp-supported-hw = <0xff>; 1426 }; 1427 1428 opp-414000000 { 1429 opp-hz = /bits/ 64 <414000000>; 1430 opp-level = <RPM_SMD_LEVEL_SVS>; 1431 opp-supported-hw = <0xff>; 1432 }; 1433 1434 opp-342000000 { 1435 opp-hz = /bits/ 64 <342000000>; 1436 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1437 opp-supported-hw = <0xff>; 1438 }; 1439 1440 opp-257000000 { 1441 opp-hz = /bits/ 64 <257000000>; 1442 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1443 opp-supported-hw = <0xff>; 1444 }; 1445 }; 1446 }; 1447 1448 adreno_smmu: iommu@5040000 { 1449 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1450 reg = <0x05040000 0x10000>; 1451 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1452 <&gcc GCC_BIMC_GFX_CLK>, 1453 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1454 clock-names = "iface", "mem", "mem_iface"; 1455 1456 #global-interrupts = <0>; 1457 #iommu-cells = <1>; 1458 interrupts = 1459 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1462 /* 1463 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1464 * GPU-CX for SMMU but we need both of them up for Adreno. 1465 * Contemporarily, we also need to manage the VDDMX rpmpd 1466 * domain in the Adreno driver. 1467 * Enable GPU CX/GX GDSCs here so that we can manage the 1468 * SoC VDDMX RPM Power Domain in the Adreno driver. 1469 */ 1470 power-domains = <&gpucc GPU_GX_GDSC>; 1471 status = "disabled"; 1472 }; 1473 1474 gpucc: clock-controller@5065000 { 1475 compatible = "qcom,msm8998-gpucc"; 1476 #clock-cells = <1>; 1477 #reset-cells = <1>; 1478 #power-domain-cells = <1>; 1479 reg = <0x05065000 0x9000>; 1480 1481 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1482 <&gcc GPLL0_OUT_MAIN>; 1483 clock-names = "xo", 1484 "gpll0"; 1485 }; 1486 1487 remoteproc_slpi: remoteproc@5800000 { 1488 compatible = "qcom,msm8998-slpi-pas"; 1489 reg = <0x05800000 0x4040>; 1490 1491 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1492 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1493 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1494 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1495 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1496 interrupt-names = "wdog", "fatal", "ready", 1497 "handover", "stop-ack"; 1498 1499 px-supply = <&vreg_lvs2a_1p8>; 1500 1501 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1502 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1503 clock-names = "xo", "aggre2"; 1504 1505 memory-region = <&slpi_mem>; 1506 1507 qcom,smem-states = <&slpi_smp2p_out 0>; 1508 qcom,smem-state-names = "stop"; 1509 1510 power-domains = <&rpmpd MSM8998_SSCCX>; 1511 power-domain-names = "ssc_cx"; 1512 1513 status = "disabled"; 1514 1515 glink-edge { 1516 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1517 label = "dsps"; 1518 qcom,remote-pid = <3>; 1519 mboxes = <&apcs_glb 27>; 1520 }; 1521 }; 1522 1523 stm: stm@6002000 { 1524 compatible = "arm,coresight-stm", "arm,primecell"; 1525 reg = <0x06002000 0x1000>, 1526 <0x16280000 0x180000>; 1527 reg-names = "stm-base", "stm-stimulus-base"; 1528 status = "disabled"; 1529 1530 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1531 clock-names = "apb_pclk", "atclk"; 1532 1533 out-ports { 1534 port { 1535 stm_out: endpoint { 1536 remote-endpoint = <&funnel0_in7>; 1537 }; 1538 }; 1539 }; 1540 }; 1541 1542 funnel1: funnel@6041000 { 1543 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1544 reg = <0x06041000 0x1000>; 1545 status = "disabled"; 1546 1547 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1548 clock-names = "apb_pclk", "atclk"; 1549 1550 out-ports { 1551 port { 1552 funnel0_out: endpoint { 1553 remote-endpoint = 1554 <&merge_funnel_in0>; 1555 }; 1556 }; 1557 }; 1558 1559 in-ports { 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 1563 port@7 { 1564 reg = <7>; 1565 funnel0_in7: endpoint { 1566 remote-endpoint = <&stm_out>; 1567 }; 1568 }; 1569 }; 1570 }; 1571 1572 funnel2: funnel@6042000 { 1573 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1574 reg = <0x06042000 0x1000>; 1575 status = "disabled"; 1576 1577 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1578 clock-names = "apb_pclk", "atclk"; 1579 1580 out-ports { 1581 port { 1582 funnel1_out: endpoint { 1583 remote-endpoint = 1584 <&merge_funnel_in1>; 1585 }; 1586 }; 1587 }; 1588 1589 in-ports { 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 1593 port@6 { 1594 reg = <6>; 1595 funnel1_in6: endpoint { 1596 remote-endpoint = 1597 <&apss_merge_funnel_out>; 1598 }; 1599 }; 1600 }; 1601 }; 1602 1603 funnel3: funnel@6045000 { 1604 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1605 reg = <0x06045000 0x1000>; 1606 status = "disabled"; 1607 1608 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1609 clock-names = "apb_pclk", "atclk"; 1610 1611 out-ports { 1612 port { 1613 merge_funnel_out: endpoint { 1614 remote-endpoint = 1615 <&etf_in>; 1616 }; 1617 }; 1618 }; 1619 1620 in-ports { 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 1624 port@0 { 1625 reg = <0>; 1626 merge_funnel_in0: endpoint { 1627 remote-endpoint = 1628 <&funnel0_out>; 1629 }; 1630 }; 1631 1632 port@1 { 1633 reg = <1>; 1634 merge_funnel_in1: endpoint { 1635 remote-endpoint = 1636 <&funnel1_out>; 1637 }; 1638 }; 1639 }; 1640 }; 1641 1642 replicator1: replicator@6046000 { 1643 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1644 reg = <0x06046000 0x1000>; 1645 status = "disabled"; 1646 1647 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1648 clock-names = "apb_pclk", "atclk"; 1649 1650 out-ports { 1651 port { 1652 replicator_out: endpoint { 1653 remote-endpoint = <&etr_in>; 1654 }; 1655 }; 1656 }; 1657 1658 in-ports { 1659 port { 1660 replicator_in: endpoint { 1661 remote-endpoint = <&etf_out>; 1662 }; 1663 }; 1664 }; 1665 }; 1666 1667 etf: etf@6047000 { 1668 compatible = "arm,coresight-tmc", "arm,primecell"; 1669 reg = <0x06047000 0x1000>; 1670 status = "disabled"; 1671 1672 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1673 clock-names = "apb_pclk", "atclk"; 1674 1675 out-ports { 1676 port { 1677 etf_out: endpoint { 1678 remote-endpoint = 1679 <&replicator_in>; 1680 }; 1681 }; 1682 }; 1683 1684 in-ports { 1685 port { 1686 etf_in: endpoint { 1687 remote-endpoint = 1688 <&merge_funnel_out>; 1689 }; 1690 }; 1691 }; 1692 }; 1693 1694 etr: etr@6048000 { 1695 compatible = "arm,coresight-tmc", "arm,primecell"; 1696 reg = <0x06048000 0x1000>; 1697 status = "disabled"; 1698 1699 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1700 clock-names = "apb_pclk", "atclk"; 1701 arm,scatter-gather; 1702 1703 in-ports { 1704 port { 1705 etr_in: endpoint { 1706 remote-endpoint = 1707 <&replicator_out>; 1708 }; 1709 }; 1710 }; 1711 }; 1712 1713 etm1: etm@7840000 { 1714 compatible = "arm,coresight-etm4x", "arm,primecell"; 1715 reg = <0x07840000 0x1000>; 1716 status = "disabled"; 1717 1718 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1719 clock-names = "apb_pclk", "atclk"; 1720 1721 cpu = <&CPU0>; 1722 1723 out-ports { 1724 port { 1725 etm0_out: endpoint { 1726 remote-endpoint = 1727 <&apss_funnel_in0>; 1728 }; 1729 }; 1730 }; 1731 }; 1732 1733 etm2: etm@7940000 { 1734 compatible = "arm,coresight-etm4x", "arm,primecell"; 1735 reg = <0x07940000 0x1000>; 1736 status = "disabled"; 1737 1738 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1739 clock-names = "apb_pclk", "atclk"; 1740 1741 cpu = <&CPU1>; 1742 1743 out-ports { 1744 port { 1745 etm1_out: endpoint { 1746 remote-endpoint = 1747 <&apss_funnel_in1>; 1748 }; 1749 }; 1750 }; 1751 }; 1752 1753 etm3: etm@7a40000 { 1754 compatible = "arm,coresight-etm4x", "arm,primecell"; 1755 reg = <0x07a40000 0x1000>; 1756 status = "disabled"; 1757 1758 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1759 clock-names = "apb_pclk", "atclk"; 1760 1761 cpu = <&CPU2>; 1762 1763 out-ports { 1764 port { 1765 etm2_out: endpoint { 1766 remote-endpoint = 1767 <&apss_funnel_in2>; 1768 }; 1769 }; 1770 }; 1771 }; 1772 1773 etm4: etm@7b40000 { 1774 compatible = "arm,coresight-etm4x", "arm,primecell"; 1775 reg = <0x07b40000 0x1000>; 1776 status = "disabled"; 1777 1778 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1779 clock-names = "apb_pclk", "atclk"; 1780 1781 cpu = <&CPU3>; 1782 1783 out-ports { 1784 port { 1785 etm3_out: endpoint { 1786 remote-endpoint = 1787 <&apss_funnel_in3>; 1788 }; 1789 }; 1790 }; 1791 }; 1792 1793 funnel4: funnel@7b60000 { /* APSS Funnel */ 1794 compatible = "arm,coresight-etm4x", "arm,primecell"; 1795 reg = <0x07b60000 0x1000>; 1796 status = "disabled"; 1797 1798 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1799 clock-names = "apb_pclk", "atclk"; 1800 1801 out-ports { 1802 port { 1803 apss_funnel_out: endpoint { 1804 remote-endpoint = 1805 <&apss_merge_funnel_in>; 1806 }; 1807 }; 1808 }; 1809 1810 in-ports { 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 1814 port@0 { 1815 reg = <0>; 1816 apss_funnel_in0: endpoint { 1817 remote-endpoint = 1818 <&etm0_out>; 1819 }; 1820 }; 1821 1822 port@1 { 1823 reg = <1>; 1824 apss_funnel_in1: endpoint { 1825 remote-endpoint = 1826 <&etm1_out>; 1827 }; 1828 }; 1829 1830 port@2 { 1831 reg = <2>; 1832 apss_funnel_in2: endpoint { 1833 remote-endpoint = 1834 <&etm2_out>; 1835 }; 1836 }; 1837 1838 port@3 { 1839 reg = <3>; 1840 apss_funnel_in3: endpoint { 1841 remote-endpoint = 1842 <&etm3_out>; 1843 }; 1844 }; 1845 1846 port@4 { 1847 reg = <4>; 1848 apss_funnel_in4: endpoint { 1849 remote-endpoint = 1850 <&etm4_out>; 1851 }; 1852 }; 1853 1854 port@5 { 1855 reg = <5>; 1856 apss_funnel_in5: endpoint { 1857 remote-endpoint = 1858 <&etm5_out>; 1859 }; 1860 }; 1861 1862 port@6 { 1863 reg = <6>; 1864 apss_funnel_in6: endpoint { 1865 remote-endpoint = 1866 <&etm6_out>; 1867 }; 1868 }; 1869 1870 port@7 { 1871 reg = <7>; 1872 apss_funnel_in7: endpoint { 1873 remote-endpoint = 1874 <&etm7_out>; 1875 }; 1876 }; 1877 }; 1878 }; 1879 1880 funnel5: funnel@7b70000 { 1881 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1882 reg = <0x07b70000 0x1000>; 1883 status = "disabled"; 1884 1885 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1886 clock-names = "apb_pclk", "atclk"; 1887 1888 out-ports { 1889 port { 1890 apss_merge_funnel_out: endpoint { 1891 remote-endpoint = 1892 <&funnel1_in6>; 1893 }; 1894 }; 1895 }; 1896 1897 in-ports { 1898 port { 1899 apss_merge_funnel_in: endpoint { 1900 remote-endpoint = 1901 <&apss_funnel_out>; 1902 }; 1903 }; 1904 }; 1905 }; 1906 1907 etm5: etm@7c40000 { 1908 compatible = "arm,coresight-etm4x", "arm,primecell"; 1909 reg = <0x07c40000 0x1000>; 1910 status = "disabled"; 1911 1912 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1913 clock-names = "apb_pclk", "atclk"; 1914 1915 cpu = <&CPU4>; 1916 1917 port { 1918 etm4_out: endpoint { 1919 remote-endpoint = <&apss_funnel_in4>; 1920 }; 1921 }; 1922 }; 1923 1924 etm6: etm@7d40000 { 1925 compatible = "arm,coresight-etm4x", "arm,primecell"; 1926 reg = <0x07d40000 0x1000>; 1927 status = "disabled"; 1928 1929 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1930 clock-names = "apb_pclk", "atclk"; 1931 1932 cpu = <&CPU5>; 1933 1934 port { 1935 etm5_out: endpoint { 1936 remote-endpoint = <&apss_funnel_in5>; 1937 }; 1938 }; 1939 }; 1940 1941 etm7: etm@7e40000 { 1942 compatible = "arm,coresight-etm4x", "arm,primecell"; 1943 reg = <0x07e40000 0x1000>; 1944 status = "disabled"; 1945 1946 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1947 clock-names = "apb_pclk", "atclk"; 1948 1949 cpu = <&CPU6>; 1950 1951 port { 1952 etm6_out: endpoint { 1953 remote-endpoint = <&apss_funnel_in6>; 1954 }; 1955 }; 1956 }; 1957 1958 etm8: etm@7f40000 { 1959 compatible = "arm,coresight-etm4x", "arm,primecell"; 1960 reg = <0x07f40000 0x1000>; 1961 status = "disabled"; 1962 1963 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1964 clock-names = "apb_pclk", "atclk"; 1965 1966 cpu = <&CPU7>; 1967 1968 port { 1969 etm7_out: endpoint { 1970 remote-endpoint = <&apss_funnel_in7>; 1971 }; 1972 }; 1973 }; 1974 1975 sram@290000 { 1976 compatible = "qcom,rpm-stats"; 1977 reg = <0x00290000 0x10000>; 1978 }; 1979 1980 spmi_bus: spmi@800f000 { 1981 compatible = "qcom,spmi-pmic-arb"; 1982 reg = <0x0800f000 0x1000>, 1983 <0x08400000 0x1000000>, 1984 <0x09400000 0x1000000>, 1985 <0x0a400000 0x220000>, 1986 <0x0800a000 0x3000>; 1987 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1988 interrupt-names = "periph_irq"; 1989 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1990 qcom,ee = <0>; 1991 qcom,channel = <0>; 1992 #address-cells = <2>; 1993 #size-cells = <0>; 1994 interrupt-controller; 1995 #interrupt-cells = <4>; 1996 }; 1997 1998 usb3: usb@a8f8800 { 1999 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2000 reg = <0x0a8f8800 0x400>; 2001 status = "disabled"; 2002 #address-cells = <1>; 2003 #size-cells = <1>; 2004 ranges; 2005 2006 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2007 <&gcc GCC_USB30_MASTER_CLK>, 2008 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2009 <&gcc GCC_USB30_SLEEP_CLK>, 2010 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2011 clock-names = "cfg_noc", 2012 "core", 2013 "iface", 2014 "sleep", 2015 "mock_utmi"; 2016 2017 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2018 <&gcc GCC_USB30_MASTER_CLK>; 2019 assigned-clock-rates = <19200000>, <120000000>; 2020 2021 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2023 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2024 2025 power-domains = <&gcc USB_30_GDSC>; 2026 2027 resets = <&gcc GCC_USB_30_BCR>; 2028 2029 usb3_dwc3: usb@a800000 { 2030 compatible = "snps,dwc3"; 2031 reg = <0x0a800000 0xcd00>; 2032 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2033 snps,dis_u2_susphy_quirk; 2034 snps,dis_enblslpm_quirk; 2035 phys = <&qusb2phy>, <&usb1_ssphy>; 2036 phy-names = "usb2-phy", "usb3-phy"; 2037 snps,has-lpm-erratum; 2038 snps,hird-threshold = /bits/ 8 <0x10>; 2039 }; 2040 }; 2041 2042 usb3phy: phy@c010000 { 2043 compatible = "qcom,msm8998-qmp-usb3-phy"; 2044 reg = <0x0c010000 0x18c>; 2045 status = "disabled"; 2046 #address-cells = <1>; 2047 #size-cells = <1>; 2048 ranges; 2049 2050 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2051 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2052 <&gcc GCC_USB3_CLKREF_CLK>; 2053 clock-names = "aux", "cfg_ahb", "ref"; 2054 2055 resets = <&gcc GCC_USB3_PHY_BCR>, 2056 <&gcc GCC_USB3PHY_PHY_BCR>; 2057 reset-names = "phy", "common"; 2058 2059 usb1_ssphy: phy@c010200 { 2060 reg = <0xc010200 0x128>, 2061 <0xc010400 0x200>, 2062 <0xc010c00 0x20c>, 2063 <0xc010600 0x128>, 2064 <0xc010800 0x200>; 2065 #phy-cells = <0>; 2066 #clock-cells = <0>; 2067 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2068 clock-names = "pipe0"; 2069 clock-output-names = "usb3_phy_pipe_clk_src"; 2070 }; 2071 }; 2072 2073 qusb2phy: phy@c012000 { 2074 compatible = "qcom,msm8998-qusb2-phy"; 2075 reg = <0x0c012000 0x2a8>; 2076 status = "disabled"; 2077 #phy-cells = <0>; 2078 2079 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2080 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2081 clock-names = "cfg_ahb", "ref"; 2082 2083 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2084 2085 nvmem-cells = <&qusb2_hstx_trim>; 2086 }; 2087 2088 sdhc2: mmc@c0a4900 { 2089 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2090 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2091 reg-names = "hc", "core"; 2092 2093 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2095 interrupt-names = "hc_irq", "pwr_irq"; 2096 2097 clock-names = "iface", "core", "xo"; 2098 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2099 <&gcc GCC_SDCC2_APPS_CLK>, 2100 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2101 bus-width = <4>; 2102 status = "disabled"; 2103 }; 2104 2105 blsp1_dma: dma-controller@c144000 { 2106 compatible = "qcom,bam-v1.7.0"; 2107 reg = <0x0c144000 0x25000>; 2108 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2109 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2110 clock-names = "bam_clk"; 2111 #dma-cells = <1>; 2112 qcom,ee = <0>; 2113 qcom,controlled-remotely; 2114 num-channels = <18>; 2115 qcom,num-ees = <4>; 2116 }; 2117 2118 blsp1_uart3: serial@c171000 { 2119 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2120 reg = <0x0c171000 0x1000>; 2121 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2122 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2123 <&gcc GCC_BLSP1_AHB_CLK>; 2124 clock-names = "core", "iface"; 2125 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2126 dma-names = "tx", "rx"; 2127 pinctrl-names = "default"; 2128 pinctrl-0 = <&blsp1_uart3_on>; 2129 status = "disabled"; 2130 }; 2131 2132 blsp1_i2c1: i2c@c175000 { 2133 compatible = "qcom,i2c-qup-v2.2.1"; 2134 reg = <0x0c175000 0x600>; 2135 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2136 2137 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2138 <&gcc GCC_BLSP1_AHB_CLK>; 2139 clock-names = "core", "iface"; 2140 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2141 dma-names = "tx", "rx"; 2142 pinctrl-names = "default", "sleep"; 2143 pinctrl-0 = <&blsp1_i2c1_default>; 2144 pinctrl-1 = <&blsp1_i2c1_sleep>; 2145 clock-frequency = <400000>; 2146 2147 status = "disabled"; 2148 #address-cells = <1>; 2149 #size-cells = <0>; 2150 }; 2151 2152 blsp1_i2c2: i2c@c176000 { 2153 compatible = "qcom,i2c-qup-v2.2.1"; 2154 reg = <0x0c176000 0x600>; 2155 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2156 2157 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2158 <&gcc GCC_BLSP1_AHB_CLK>; 2159 clock-names = "core", "iface"; 2160 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2161 dma-names = "tx", "rx"; 2162 pinctrl-names = "default", "sleep"; 2163 pinctrl-0 = <&blsp1_i2c2_default>; 2164 pinctrl-1 = <&blsp1_i2c2_sleep>; 2165 clock-frequency = <400000>; 2166 2167 status = "disabled"; 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 }; 2171 2172 blsp1_i2c3: i2c@c177000 { 2173 compatible = "qcom,i2c-qup-v2.2.1"; 2174 reg = <0x0c177000 0x600>; 2175 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2176 2177 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2178 <&gcc GCC_BLSP1_AHB_CLK>; 2179 clock-names = "core", "iface"; 2180 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2181 dma-names = "tx", "rx"; 2182 pinctrl-names = "default", "sleep"; 2183 pinctrl-0 = <&blsp1_i2c3_default>; 2184 pinctrl-1 = <&blsp1_i2c3_sleep>; 2185 clock-frequency = <400000>; 2186 2187 status = "disabled"; 2188 #address-cells = <1>; 2189 #size-cells = <0>; 2190 }; 2191 2192 blsp1_i2c4: i2c@c178000 { 2193 compatible = "qcom,i2c-qup-v2.2.1"; 2194 reg = <0x0c178000 0x600>; 2195 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2196 2197 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2198 <&gcc GCC_BLSP1_AHB_CLK>; 2199 clock-names = "core", "iface"; 2200 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2201 dma-names = "tx", "rx"; 2202 pinctrl-names = "default", "sleep"; 2203 pinctrl-0 = <&blsp1_i2c4_default>; 2204 pinctrl-1 = <&blsp1_i2c4_sleep>; 2205 clock-frequency = <400000>; 2206 2207 status = "disabled"; 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 }; 2211 2212 blsp1_i2c5: i2c@c179000 { 2213 compatible = "qcom,i2c-qup-v2.2.1"; 2214 reg = <0x0c179000 0x600>; 2215 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2216 2217 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2218 <&gcc GCC_BLSP1_AHB_CLK>; 2219 clock-names = "core", "iface"; 2220 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2221 dma-names = "tx", "rx"; 2222 pinctrl-names = "default", "sleep"; 2223 pinctrl-0 = <&blsp1_i2c5_default>; 2224 pinctrl-1 = <&blsp1_i2c5_sleep>; 2225 clock-frequency = <400000>; 2226 2227 status = "disabled"; 2228 #address-cells = <1>; 2229 #size-cells = <0>; 2230 }; 2231 2232 blsp1_i2c6: i2c@c17a000 { 2233 compatible = "qcom,i2c-qup-v2.2.1"; 2234 reg = <0x0c17a000 0x600>; 2235 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2236 2237 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2238 <&gcc GCC_BLSP1_AHB_CLK>; 2239 clock-names = "core", "iface"; 2240 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2241 dma-names = "tx", "rx"; 2242 pinctrl-names = "default", "sleep"; 2243 pinctrl-0 = <&blsp1_i2c6_default>; 2244 pinctrl-1 = <&blsp1_i2c6_sleep>; 2245 clock-frequency = <400000>; 2246 2247 status = "disabled"; 2248 #address-cells = <1>; 2249 #size-cells = <0>; 2250 }; 2251 2252 blsp2_dma: dma-controller@c184000 { 2253 compatible = "qcom,bam-v1.7.0"; 2254 reg = <0x0c184000 0x25000>; 2255 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2256 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2257 clock-names = "bam_clk"; 2258 #dma-cells = <1>; 2259 qcom,ee = <0>; 2260 qcom,controlled-remotely; 2261 num-channels = <18>; 2262 qcom,num-ees = <4>; 2263 }; 2264 2265 blsp2_uart1: serial@c1b0000 { 2266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2267 reg = <0x0c1b0000 0x1000>; 2268 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2269 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2270 <&gcc GCC_BLSP2_AHB_CLK>; 2271 clock-names = "core", "iface"; 2272 status = "disabled"; 2273 }; 2274 2275 blsp2_i2c1: i2c@c1b5000 { 2276 compatible = "qcom,i2c-qup-v2.2.1"; 2277 reg = <0x0c1b5000 0x600>; 2278 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2279 2280 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2281 <&gcc GCC_BLSP2_AHB_CLK>; 2282 clock-names = "core", "iface"; 2283 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2284 dma-names = "tx", "rx"; 2285 pinctrl-names = "default", "sleep"; 2286 pinctrl-0 = <&blsp2_i2c1_default>; 2287 pinctrl-1 = <&blsp2_i2c1_sleep>; 2288 clock-frequency = <400000>; 2289 2290 status = "disabled"; 2291 #address-cells = <1>; 2292 #size-cells = <0>; 2293 }; 2294 2295 blsp2_i2c2: i2c@c1b6000 { 2296 compatible = "qcom,i2c-qup-v2.2.1"; 2297 reg = <0x0c1b6000 0x600>; 2298 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2299 2300 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2301 <&gcc GCC_BLSP2_AHB_CLK>; 2302 clock-names = "core", "iface"; 2303 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2304 dma-names = "tx", "rx"; 2305 pinctrl-names = "default", "sleep"; 2306 pinctrl-0 = <&blsp2_i2c2_default>; 2307 pinctrl-1 = <&blsp2_i2c2_sleep>; 2308 clock-frequency = <400000>; 2309 2310 status = "disabled"; 2311 #address-cells = <1>; 2312 #size-cells = <0>; 2313 }; 2314 2315 blsp2_i2c3: i2c@c1b7000 { 2316 compatible = "qcom,i2c-qup-v2.2.1"; 2317 reg = <0x0c1b7000 0x600>; 2318 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2319 2320 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2321 <&gcc GCC_BLSP2_AHB_CLK>; 2322 clock-names = "core", "iface"; 2323 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2324 dma-names = "tx", "rx"; 2325 pinctrl-names = "default", "sleep"; 2326 pinctrl-0 = <&blsp2_i2c3_default>; 2327 pinctrl-1 = <&blsp2_i2c3_sleep>; 2328 clock-frequency = <400000>; 2329 2330 status = "disabled"; 2331 #address-cells = <1>; 2332 #size-cells = <0>; 2333 }; 2334 2335 blsp2_i2c4: i2c@c1b8000 { 2336 compatible = "qcom,i2c-qup-v2.2.1"; 2337 reg = <0x0c1b8000 0x600>; 2338 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2339 2340 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2341 <&gcc GCC_BLSP2_AHB_CLK>; 2342 clock-names = "core", "iface"; 2343 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2344 dma-names = "tx", "rx"; 2345 pinctrl-names = "default", "sleep"; 2346 pinctrl-0 = <&blsp2_i2c4_default>; 2347 pinctrl-1 = <&blsp2_i2c4_sleep>; 2348 clock-frequency = <400000>; 2349 2350 status = "disabled"; 2351 #address-cells = <1>; 2352 #size-cells = <0>; 2353 }; 2354 2355 blsp2_i2c5: i2c@c1b9000 { 2356 compatible = "qcom,i2c-qup-v2.2.1"; 2357 reg = <0x0c1b9000 0x600>; 2358 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2359 2360 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2361 <&gcc GCC_BLSP2_AHB_CLK>; 2362 clock-names = "core", "iface"; 2363 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2364 dma-names = "tx", "rx"; 2365 pinctrl-names = "default", "sleep"; 2366 pinctrl-0 = <&blsp2_i2c5_default>; 2367 pinctrl-1 = <&blsp2_i2c5_sleep>; 2368 clock-frequency = <400000>; 2369 2370 status = "disabled"; 2371 #address-cells = <1>; 2372 #size-cells = <0>; 2373 }; 2374 2375 blsp2_i2c6: i2c@c1ba000 { 2376 compatible = "qcom,i2c-qup-v2.2.1"; 2377 reg = <0x0c1ba000 0x600>; 2378 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2379 2380 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2381 <&gcc GCC_BLSP2_AHB_CLK>; 2382 clock-names = "core", "iface"; 2383 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2384 dma-names = "tx", "rx"; 2385 pinctrl-names = "default", "sleep"; 2386 pinctrl-0 = <&blsp2_i2c6_default>; 2387 pinctrl-1 = <&blsp2_i2c6_sleep>; 2388 clock-frequency = <400000>; 2389 2390 status = "disabled"; 2391 #address-cells = <1>; 2392 #size-cells = <0>; 2393 }; 2394 2395 mmcc: clock-controller@c8c0000 { 2396 compatible = "qcom,mmcc-msm8998"; 2397 #clock-cells = <1>; 2398 #reset-cells = <1>; 2399 #power-domain-cells = <1>; 2400 reg = <0xc8c0000 0x40000>; 2401 2402 clock-names = "xo", 2403 "gpll0", 2404 "dsi0dsi", 2405 "dsi0byte", 2406 "dsi1dsi", 2407 "dsi1byte", 2408 "hdmipll", 2409 "dplink", 2410 "dpvco"; 2411 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2412 <&gcc GCC_MMSS_GPLL0_CLK>, 2413 <0>, 2414 <0>, 2415 <0>, 2416 <0>, 2417 <0>, 2418 <0>, 2419 <0>; 2420 }; 2421 2422 mmss_smmu: iommu@cd00000 { 2423 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 2424 reg = <0x0cd00000 0x40000>; 2425 #iommu-cells = <1>; 2426 2427 clocks = <&mmcc MNOC_AHB_CLK>, 2428 <&mmcc BIMC_SMMU_AHB_CLK>, 2429 <&rpmcc RPM_SMD_MMAXI_CLK>, 2430 <&mmcc BIMC_SMMU_AXI_CLK>; 2431 clock-names = "iface-mm", "iface-smmu", 2432 "bus-mm", "bus-smmu"; 2433 2434 #global-interrupts = <0>; 2435 interrupts = 2436 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2455 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2456 }; 2457 2458 remoteproc_adsp: remoteproc@17300000 { 2459 compatible = "qcom,msm8998-adsp-pas"; 2460 reg = <0x17300000 0x4040>; 2461 2462 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2463 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2464 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2465 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2466 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2467 interrupt-names = "wdog", "fatal", "ready", 2468 "handover", "stop-ack"; 2469 2470 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2471 clock-names = "xo"; 2472 2473 memory-region = <&adsp_mem>; 2474 2475 qcom,smem-states = <&adsp_smp2p_out 0>; 2476 qcom,smem-state-names = "stop"; 2477 2478 power-domains = <&rpmpd MSM8998_VDDCX>; 2479 power-domain-names = "cx"; 2480 2481 status = "disabled"; 2482 2483 glink-edge { 2484 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2485 label = "lpass"; 2486 qcom,remote-pid = <2>; 2487 mboxes = <&apcs_glb 9>; 2488 }; 2489 }; 2490 2491 apcs_glb: mailbox@17911000 { 2492 compatible = "qcom,msm8998-apcs-hmss-global", 2493 "qcom,msm8994-apcs-kpss-global"; 2494 reg = <0x17911000 0x1000>; 2495 2496 #mbox-cells = <1>; 2497 }; 2498 2499 timer@17920000 { 2500 #address-cells = <1>; 2501 #size-cells = <1>; 2502 ranges; 2503 compatible = "arm,armv7-timer-mem"; 2504 reg = <0x17920000 0x1000>; 2505 2506 frame@17921000 { 2507 frame-number = <0>; 2508 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2510 reg = <0x17921000 0x1000>, 2511 <0x17922000 0x1000>; 2512 }; 2513 2514 frame@17923000 { 2515 frame-number = <1>; 2516 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2517 reg = <0x17923000 0x1000>; 2518 status = "disabled"; 2519 }; 2520 2521 frame@17924000 { 2522 frame-number = <2>; 2523 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2524 reg = <0x17924000 0x1000>; 2525 status = "disabled"; 2526 }; 2527 2528 frame@17925000 { 2529 frame-number = <3>; 2530 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2531 reg = <0x17925000 0x1000>; 2532 status = "disabled"; 2533 }; 2534 2535 frame@17926000 { 2536 frame-number = <4>; 2537 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2538 reg = <0x17926000 0x1000>; 2539 status = "disabled"; 2540 }; 2541 2542 frame@17927000 { 2543 frame-number = <5>; 2544 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2545 reg = <0x17927000 0x1000>; 2546 status = "disabled"; 2547 }; 2548 2549 frame@17928000 { 2550 frame-number = <6>; 2551 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2552 reg = <0x17928000 0x1000>; 2553 status = "disabled"; 2554 }; 2555 }; 2556 2557 intc: interrupt-controller@17a00000 { 2558 compatible = "arm,gic-v3"; 2559 reg = <0x17a00000 0x10000>, /* GICD */ 2560 <0x17b00000 0x100000>; /* GICR * 8 */ 2561 #interrupt-cells = <3>; 2562 #address-cells = <1>; 2563 #size-cells = <1>; 2564 ranges; 2565 interrupt-controller; 2566 #redistributor-regions = <1>; 2567 redistributor-stride = <0x0 0x20000>; 2568 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2569 }; 2570 2571 wifi: wifi@18800000 { 2572 compatible = "qcom,wcn3990-wifi"; 2573 status = "disabled"; 2574 reg = <0x18800000 0x800000>; 2575 reg-names = "membase"; 2576 memory-region = <&wlan_msa_mem>; 2577 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2578 clock-names = "cxo_ref_clk_pin"; 2579 interrupts = 2580 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2592 iommus = <&anoc2_smmu 0x1900>, 2593 <&anoc2_smmu 0x1901>; 2594 qcom,snoc-host-cap-8bit-quirk; 2595 }; 2596 }; 2597}; 2598