1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/gpio/gpio.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 qcom,msm-id = <292 0x0>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 memory { 22 device_type = "memory"; 23 /* We expect the bootloader to fill in the reg */ 24 reg = <0 0 0 0>; 25 }; 26 27 reserved-memory { 28 #address-cells = <2>; 29 #size-cells = <2>; 30 ranges; 31 32 hyp_mem: memory@85800000 { 33 reg = <0x0 0x85800000 0x0 0x600000>; 34 no-map; 35 }; 36 37 xbl_mem: memory@85e00000 { 38 reg = <0x0 0x85e00000 0x0 0x100000>; 39 no-map; 40 }; 41 42 smem_mem: smem-mem@86000000 { 43 reg = <0x0 0x86000000 0x0 0x200000>; 44 no-map; 45 }; 46 47 tz_mem: memory@86200000 { 48 reg = <0x0 0x86200000 0x0 0x2d00000>; 49 no-map; 50 }; 51 52 rmtfs_mem: memory@88f00000 { 53 compatible = "qcom,rmtfs-mem"; 54 reg = <0x0 0x88f00000 0x0 0x200000>; 55 no-map; 56 57 qcom,client-id = <1>; 58 qcom,vmid = <15>; 59 }; 60 61 spss_mem: memory@8ab00000 { 62 reg = <0x0 0x8ab00000 0x0 0x700000>; 63 no-map; 64 }; 65 66 adsp_mem: memory@8b200000 { 67 reg = <0x0 0x8b200000 0x0 0x1a00000>; 68 no-map; 69 }; 70 71 mpss_mem: memory@8cc00000 { 72 reg = <0x0 0x8cc00000 0x0 0x7000000>; 73 no-map; 74 }; 75 76 venus_mem: memory@93c00000 { 77 reg = <0x0 0x93c00000 0x0 0x500000>; 78 no-map; 79 }; 80 81 mba_mem: memory@94100000 { 82 reg = <0x0 0x94100000 0x0 0x200000>; 83 no-map; 84 }; 85 86 slpi_mem: memory@94300000 { 87 reg = <0x0 0x94300000 0x0 0xf00000>; 88 no-map; 89 }; 90 91 ipa_fw_mem: memory@95200000 { 92 reg = <0x0 0x95200000 0x0 0x10000>; 93 no-map; 94 }; 95 96 ipa_gsi_mem: memory@95210000 { 97 reg = <0x0 0x95210000 0x0 0x5000>; 98 no-map; 99 }; 100 101 gpu_mem: memory@95600000 { 102 reg = <0x0 0x95600000 0x0 0x100000>; 103 no-map; 104 }; 105 106 wlan_msa_mem: memory@95700000 { 107 reg = <0x0 0x95700000 0x0 0x100000>; 108 no-map; 109 }; 110 }; 111 112 clocks { 113 xo: xo-board { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <19200000>; 117 clock-output-names = "xo_board"; 118 }; 119 120 sleep_clk { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <32764>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <2>; 129 #size-cells = <0>; 130 131 CPU0: cpu@0 { 132 device_type = "cpu"; 133 compatible = "arm,armv8"; 134 reg = <0x0 0x0>; 135 enable-method = "psci"; 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 137 next-level-cache = <&L2_0>; 138 L2_0: l2-cache { 139 compatible = "arm,arch-cache"; 140 cache-level = <2>; 141 }; 142 L1_I_0: l1-icache { 143 compatible = "arm,arch-cache"; 144 }; 145 L1_D_0: l1-dcache { 146 compatible = "arm,arch-cache"; 147 }; 148 }; 149 150 CPU1: cpu@1 { 151 device_type = "cpu"; 152 compatible = "arm,armv8"; 153 reg = <0x0 0x1>; 154 enable-method = "psci"; 155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 156 next-level-cache = <&L2_0>; 157 L1_I_1: l1-icache { 158 compatible = "arm,arch-cache"; 159 }; 160 L1_D_1: l1-dcache { 161 compatible = "arm,arch-cache"; 162 }; 163 }; 164 165 CPU2: cpu@2 { 166 device_type = "cpu"; 167 compatible = "arm,armv8"; 168 reg = <0x0 0x2>; 169 enable-method = "psci"; 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 171 next-level-cache = <&L2_0>; 172 L1_I_2: l1-icache { 173 compatible = "arm,arch-cache"; 174 }; 175 L1_D_2: l1-dcache { 176 compatible = "arm,arch-cache"; 177 }; 178 }; 179 180 CPU3: cpu@3 { 181 device_type = "cpu"; 182 compatible = "arm,armv8"; 183 reg = <0x0 0x3>; 184 enable-method = "psci"; 185 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 186 next-level-cache = <&L2_0>; 187 L1_I_3: l1-icache { 188 compatible = "arm,arch-cache"; 189 }; 190 L1_D_3: l1-dcache { 191 compatible = "arm,arch-cache"; 192 }; 193 }; 194 195 CPU4: cpu@100 { 196 device_type = "cpu"; 197 compatible = "arm,armv8"; 198 reg = <0x0 0x100>; 199 enable-method = "psci"; 200 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 201 next-level-cache = <&L2_1>; 202 L2_1: l2-cache { 203 compatible = "arm,arch-cache"; 204 cache-level = <2>; 205 }; 206 L1_I_100: l1-icache { 207 compatible = "arm,arch-cache"; 208 }; 209 L1_D_100: l1-dcache { 210 compatible = "arm,arch-cache"; 211 }; 212 }; 213 214 CPU5: cpu@101 { 215 device_type = "cpu"; 216 compatible = "arm,armv8"; 217 reg = <0x0 0x101>; 218 enable-method = "psci"; 219 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 220 next-level-cache = <&L2_1>; 221 L1_I_101: l1-icache { 222 compatible = "arm,arch-cache"; 223 }; 224 L1_D_101: l1-dcache { 225 compatible = "arm,arch-cache"; 226 }; 227 }; 228 229 CPU6: cpu@102 { 230 device_type = "cpu"; 231 compatible = "arm,armv8"; 232 reg = <0x0 0x102>; 233 enable-method = "psci"; 234 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 235 next-level-cache = <&L2_1>; 236 L1_I_102: l1-icache { 237 compatible = "arm,arch-cache"; 238 }; 239 L1_D_102: l1-dcache { 240 compatible = "arm,arch-cache"; 241 }; 242 }; 243 244 CPU7: cpu@103 { 245 device_type = "cpu"; 246 compatible = "arm,armv8"; 247 reg = <0x0 0x103>; 248 enable-method = "psci"; 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 250 next-level-cache = <&L2_1>; 251 L1_I_103: l1-icache { 252 compatible = "arm,arch-cache"; 253 }; 254 L1_D_103: l1-dcache { 255 compatible = "arm,arch-cache"; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&CPU0>; 263 }; 264 265 core1 { 266 cpu = <&CPU1>; 267 }; 268 269 core2 { 270 cpu = <&CPU2>; 271 }; 272 273 core3 { 274 cpu = <&CPU3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&CPU4>; 281 }; 282 283 core1 { 284 cpu = <&CPU5>; 285 }; 286 287 core2 { 288 cpu = <&CPU6>; 289 }; 290 291 core3 { 292 cpu = <&CPU7>; 293 }; 294 }; 295 }; 296 297 idle-states { 298 entry-method = "psci"; 299 300 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "little-retention"; 303 arm,psci-suspend-param = <0x00000002>; 304 entry-latency-us = <81>; 305 exit-latency-us = <86>; 306 min-residency-us = <200>; 307 }; 308 309 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 310 compatible = "arm,idle-state"; 311 idle-state-name = "little-power-collapse"; 312 arm,psci-suspend-param = <0x40000003>; 313 entry-latency-us = <273>; 314 exit-latency-us = <612>; 315 min-residency-us = <1000>; 316 local-timer-stop; 317 }; 318 319 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 320 compatible = "arm,idle-state"; 321 idle-state-name = "big-retention"; 322 arm,psci-suspend-param = <0x00000002>; 323 entry-latency-us = <79>; 324 exit-latency-us = <82>; 325 min-residency-us = <200>; 326 }; 327 328 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 329 compatible = "arm,idle-state"; 330 idle-state-name = "big-power-collapse"; 331 arm,psci-suspend-param = <0x40000003>; 332 entry-latency-us = <336>; 333 exit-latency-us = <525>; 334 min-residency-us = <1000>; 335 local-timer-stop; 336 }; 337 }; 338 }; 339 340 firmware { 341 scm { 342 compatible = "qcom,scm-msm8998", "qcom,scm"; 343 }; 344 }; 345 346 tcsr_mutex: hwlock { 347 compatible = "qcom,tcsr-mutex"; 348 syscon = <&tcsr_mutex_regs 0 0x1000>; 349 #hwlock-cells = <1>; 350 }; 351 352 psci { 353 compatible = "arm,psci-1.0"; 354 method = "smc"; 355 }; 356 357 rpm-glink { 358 compatible = "qcom,glink-rpm"; 359 360 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 361 qcom,rpm-msg-ram = <&rpm_msg_ram>; 362 mboxes = <&apcs_glb 0>; 363 364 rpm_requests: rpm-requests { 365 compatible = "qcom,rpm-msm8998"; 366 qcom,glink-channels = "rpm_requests"; 367 368 rpmcc: clock-controller { 369 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 370 #clock-cells = <1>; 371 }; 372 373 rpmpd: power-controller { 374 compatible = "qcom,msm8998-rpmpd"; 375 #power-domain-cells = <1>; 376 operating-points-v2 = <&rpmpd_opp_table>; 377 378 rpmpd_opp_table: opp-table { 379 compatible = "operating-points-v2"; 380 381 rpmpd_opp_ret: opp1 { 382 opp-level = <16>; 383 }; 384 385 rpmpd_opp_ret_plus: opp2 { 386 opp-level = <32>; 387 }; 388 389 rpmpd_opp_min_svs: opp3 { 390 opp-level = <48>; 391 }; 392 393 rpmpd_opp_low_svs: opp4 { 394 opp-level = <64>; 395 }; 396 397 rpmpd_opp_svs: opp5 { 398 opp-level = <128>; 399 }; 400 401 rpmpd_opp_svs_plus: opp6 { 402 opp-level = <192>; 403 }; 404 405 rpmpd_opp_nom: opp7 { 406 opp-level = <256>; 407 }; 408 409 rpmpd_opp_nom_plus: opp8 { 410 opp-level = <320>; 411 }; 412 413 rpmpd_opp_turbo: opp9 { 414 opp-level = <384>; 415 }; 416 417 rpmpd_opp_turbo_plus: opp10 { 418 opp-level = <512>; 419 }; 420 }; 421 }; 422 }; 423 }; 424 425 smem { 426 compatible = "qcom,smem"; 427 memory-region = <&smem_mem>; 428 hwlocks = <&tcsr_mutex 3>; 429 }; 430 431 smp2p-lpass { 432 compatible = "qcom,smp2p"; 433 qcom,smem = <443>, <429>; 434 435 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 436 437 mboxes = <&apcs_glb 10>; 438 439 qcom,local-pid = <0>; 440 qcom,remote-pid = <2>; 441 442 adsp_smp2p_out: master-kernel { 443 qcom,entry-name = "master-kernel"; 444 #qcom,smem-state-cells = <1>; 445 }; 446 447 adsp_smp2p_in: slave-kernel { 448 qcom,entry-name = "slave-kernel"; 449 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 }; 453 }; 454 455 smp2p-mpss { 456 compatible = "qcom,smp2p"; 457 qcom,smem = <435>, <428>; 458 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 459 mboxes = <&apcs_glb 14>; 460 qcom,local-pid = <0>; 461 qcom,remote-pid = <1>; 462 463 modem_smp2p_out: master-kernel { 464 qcom,entry-name = "master-kernel"; 465 #qcom,smem-state-cells = <1>; 466 }; 467 468 modem_smp2p_in: slave-kernel { 469 qcom,entry-name = "slave-kernel"; 470 interrupt-controller; 471 #interrupt-cells = <2>; 472 }; 473 }; 474 475 smp2p-slpi { 476 compatible = "qcom,smp2p"; 477 qcom,smem = <481>, <430>; 478 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 479 mboxes = <&apcs_glb 26>; 480 qcom,local-pid = <0>; 481 qcom,remote-pid = <3>; 482 483 slpi_smp2p_out: master-kernel { 484 qcom,entry-name = "master-kernel"; 485 #qcom,smem-state-cells = <1>; 486 }; 487 488 slpi_smp2p_in: slave-kernel { 489 qcom,entry-name = "slave-kernel"; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 }; 493 }; 494 495 thermal-zones { 496 cpu0-thermal { 497 polling-delay-passive = <250>; 498 polling-delay = <1000>; 499 500 thermal-sensors = <&tsens0 1>; 501 502 trips { 503 cpu0_alert0: trip-point@0 { 504 temperature = <75000>; 505 hysteresis = <2000>; 506 type = "passive"; 507 }; 508 509 cpu0_crit: cpu_crit { 510 temperature = <110000>; 511 hysteresis = <2000>; 512 type = "critical"; 513 }; 514 }; 515 }; 516 517 cpu1-thermal { 518 polling-delay-passive = <250>; 519 polling-delay = <1000>; 520 521 thermal-sensors = <&tsens0 2>; 522 523 trips { 524 cpu1_alert0: trip-point@0 { 525 temperature = <75000>; 526 hysteresis = <2000>; 527 type = "passive"; 528 }; 529 530 cpu1_crit: cpu_crit { 531 temperature = <110000>; 532 hysteresis = <2000>; 533 type = "critical"; 534 }; 535 }; 536 }; 537 538 cpu2-thermal { 539 polling-delay-passive = <250>; 540 polling-delay = <1000>; 541 542 thermal-sensors = <&tsens0 3>; 543 544 trips { 545 cpu2_alert0: trip-point@0 { 546 temperature = <75000>; 547 hysteresis = <2000>; 548 type = "passive"; 549 }; 550 551 cpu2_crit: cpu_crit { 552 temperature = <110000>; 553 hysteresis = <2000>; 554 type = "critical"; 555 }; 556 }; 557 }; 558 559 cpu3-thermal { 560 polling-delay-passive = <250>; 561 polling-delay = <1000>; 562 563 thermal-sensors = <&tsens0 4>; 564 565 trips { 566 cpu3_alert0: trip-point@0 { 567 temperature = <75000>; 568 hysteresis = <2000>; 569 type = "passive"; 570 }; 571 572 cpu3_crit: cpu_crit { 573 temperature = <110000>; 574 hysteresis = <2000>; 575 type = "critical"; 576 }; 577 }; 578 }; 579 580 cpu4-thermal { 581 polling-delay-passive = <250>; 582 polling-delay = <1000>; 583 584 thermal-sensors = <&tsens0 7>; 585 586 trips { 587 cpu4_alert0: trip-point@0 { 588 temperature = <75000>; 589 hysteresis = <2000>; 590 type = "passive"; 591 }; 592 593 cpu4_crit: cpu_crit { 594 temperature = <110000>; 595 hysteresis = <2000>; 596 type = "critical"; 597 }; 598 }; 599 }; 600 601 cpu5-thermal { 602 polling-delay-passive = <250>; 603 polling-delay = <1000>; 604 605 thermal-sensors = <&tsens0 8>; 606 607 trips { 608 cpu5_alert0: trip-point@0 { 609 temperature = <75000>; 610 hysteresis = <2000>; 611 type = "passive"; 612 }; 613 614 cpu5_crit: cpu_crit { 615 temperature = <110000>; 616 hysteresis = <2000>; 617 type = "critical"; 618 }; 619 }; 620 }; 621 622 cpu6-thermal { 623 polling-delay-passive = <250>; 624 polling-delay = <1000>; 625 626 thermal-sensors = <&tsens0 9>; 627 628 trips { 629 cpu6_alert0: trip-point@0 { 630 temperature = <75000>; 631 hysteresis = <2000>; 632 type = "passive"; 633 }; 634 635 cpu6_crit: cpu_crit { 636 temperature = <110000>; 637 hysteresis = <2000>; 638 type = "critical"; 639 }; 640 }; 641 }; 642 643 cpu7-thermal { 644 polling-delay-passive = <250>; 645 polling-delay = <1000>; 646 647 thermal-sensors = <&tsens0 10>; 648 649 trips { 650 cpu7_alert0: trip-point@0 { 651 temperature = <75000>; 652 hysteresis = <2000>; 653 type = "passive"; 654 }; 655 656 cpu7_crit: cpu_crit { 657 temperature = <110000>; 658 hysteresis = <2000>; 659 type = "critical"; 660 }; 661 }; 662 }; 663 664 gpu-thermal-bottom { 665 polling-delay-passive = <250>; 666 polling-delay = <1000>; 667 668 thermal-sensors = <&tsens0 12>; 669 670 trips { 671 gpu1_alert0: trip-point@0 { 672 temperature = <90000>; 673 hysteresis = <2000>; 674 type = "hot"; 675 }; 676 }; 677 }; 678 679 gpu-thermal-top { 680 polling-delay-passive = <250>; 681 polling-delay = <1000>; 682 683 thermal-sensors = <&tsens0 13>; 684 685 trips { 686 gpu2_alert0: trip-point@0 { 687 temperature = <90000>; 688 hysteresis = <2000>; 689 type = "hot"; 690 }; 691 }; 692 }; 693 694 clust0-mhm-thermal { 695 polling-delay-passive = <250>; 696 polling-delay = <1000>; 697 698 thermal-sensors = <&tsens0 5>; 699 700 trips { 701 cluster0_mhm_alert0: trip-point@0 { 702 temperature = <90000>; 703 hysteresis = <2000>; 704 type = "hot"; 705 }; 706 }; 707 }; 708 709 clust1-mhm-thermal { 710 polling-delay-passive = <250>; 711 polling-delay = <1000>; 712 713 thermal-sensors = <&tsens0 6>; 714 715 trips { 716 cluster1_mhm_alert0: trip-point@0 { 717 temperature = <90000>; 718 hysteresis = <2000>; 719 type = "hot"; 720 }; 721 }; 722 }; 723 724 cluster1-l2-thermal { 725 polling-delay-passive = <250>; 726 polling-delay = <1000>; 727 728 thermal-sensors = <&tsens0 11>; 729 730 trips { 731 cluster1_l2_alert0: trip-point@0 { 732 temperature = <90000>; 733 hysteresis = <2000>; 734 type = "hot"; 735 }; 736 }; 737 }; 738 739 modem-thermal { 740 polling-delay-passive = <250>; 741 polling-delay = <1000>; 742 743 thermal-sensors = <&tsens1 1>; 744 745 trips { 746 modem_alert0: trip-point@0 { 747 temperature = <90000>; 748 hysteresis = <2000>; 749 type = "hot"; 750 }; 751 }; 752 }; 753 754 mem-thermal { 755 polling-delay-passive = <250>; 756 polling-delay = <1000>; 757 758 thermal-sensors = <&tsens1 2>; 759 760 trips { 761 mem_alert0: trip-point@0 { 762 temperature = <90000>; 763 hysteresis = <2000>; 764 type = "hot"; 765 }; 766 }; 767 }; 768 769 wlan-thermal { 770 polling-delay-passive = <250>; 771 polling-delay = <1000>; 772 773 thermal-sensors = <&tsens1 3>; 774 775 trips { 776 wlan_alert0: trip-point@0 { 777 temperature = <90000>; 778 hysteresis = <2000>; 779 type = "hot"; 780 }; 781 }; 782 }; 783 784 q6-dsp-thermal { 785 polling-delay-passive = <250>; 786 polling-delay = <1000>; 787 788 thermal-sensors = <&tsens1 4>; 789 790 trips { 791 q6_dsp_alert0: trip-point@0 { 792 temperature = <90000>; 793 hysteresis = <2000>; 794 type = "hot"; 795 }; 796 }; 797 }; 798 799 camera-thermal { 800 polling-delay-passive = <250>; 801 polling-delay = <1000>; 802 803 thermal-sensors = <&tsens1 5>; 804 805 trips { 806 camera_alert0: trip-point@0 { 807 temperature = <90000>; 808 hysteresis = <2000>; 809 type = "hot"; 810 }; 811 }; 812 }; 813 814 multimedia-thermal { 815 polling-delay-passive = <250>; 816 polling-delay = <1000>; 817 818 thermal-sensors = <&tsens1 6>; 819 820 trips { 821 multimedia_alert0: trip-point@0 { 822 temperature = <90000>; 823 hysteresis = <2000>; 824 type = "hot"; 825 }; 826 }; 827 }; 828 }; 829 830 timer { 831 compatible = "arm,armv8-timer"; 832 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 833 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 834 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 835 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 836 }; 837 838 soc: soc { 839 #address-cells = <1>; 840 #size-cells = <1>; 841 ranges = <0 0 0 0xffffffff>; 842 compatible = "simple-bus"; 843 844 gcc: clock-controller@100000 { 845 compatible = "qcom,gcc-msm8998"; 846 #clock-cells = <1>; 847 #reset-cells = <1>; 848 #power-domain-cells = <1>; 849 reg = <0x00100000 0xb0000>; 850 }; 851 852 rpm_msg_ram: memory@778000 { 853 compatible = "qcom,rpm-msg-ram"; 854 reg = <0x00778000 0x7000>; 855 }; 856 857 qfprom: qfprom@780000 { 858 compatible = "qcom,qfprom"; 859 reg = <0x00780000 0x621c>; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 863 qusb2_hstx_trim: hstx-trim@423a { 864 reg = <0x423a 0x1>; 865 bits = <0 4>; 866 }; 867 }; 868 869 tsens0: thermal@10ab000 { 870 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 871 reg = <0x010ab000 0x1000>, /* TM */ 872 <0x010aa000 0x1000>; /* SROT */ 873 #qcom,sensors = <14>; 874 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "uplow"; 876 #thermal-sensor-cells = <1>; 877 }; 878 879 tsens1: thermal@10ae000 { 880 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 881 reg = <0x010ae000 0x1000>, /* TM */ 882 <0x010ad000 0x1000>; /* SROT */ 883 #qcom,sensors = <8>; 884 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 885 interrupt-names = "uplow"; 886 #thermal-sensor-cells = <1>; 887 }; 888 889 anoc1_smmu: iommu@1680000 { 890 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 891 reg = <0x01680000 0x10000>; 892 #iommu-cells = <1>; 893 894 #global-interrupts = <0>; 895 interrupts = 896 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 897 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 898 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 899 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 900 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 902 }; 903 904 anoc2_smmu: iommu@16c0000 { 905 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 906 reg = <0x016c0000 0x40000>; 907 #iommu-cells = <1>; 908 909 #global-interrupts = <0>; 910 interrupts = 911 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 912 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 913 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 914 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 915 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 916 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 917 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 918 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 919 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 920 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 921 }; 922 923 pcie0: pci@1c00000 { 924 compatible = "qcom,pcie-msm8996"; 925 reg = <0x01c00000 0x2000>, 926 <0x1b000000 0xf1d>, 927 <0x1b000f20 0xa8>, 928 <0x1b100000 0x100000>; 929 reg-names = "parf", "dbi", "elbi", "config"; 930 device_type = "pci"; 931 linux,pci-domain = <0>; 932 bus-range = <0x00 0xff>; 933 #address-cells = <3>; 934 #size-cells = <2>; 935 num-lanes = <1>; 936 phys = <&pciephy>; 937 phy-names = "pciephy"; 938 939 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, 940 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 941 942 #interrupt-cells = <1>; 943 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 944 interrupt-names = "msi"; 945 interrupt-map-mask = <0 0 0 0x7>; 946 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, 947 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, 948 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, 949 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; 950 951 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 952 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 953 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 954 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 955 <&gcc GCC_PCIE_0_AUX_CLK>; 956 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 957 958 power-domains = <&gcc PCIE_0_GDSC>; 959 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 960 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 961 }; 962 963 phy@1c06000 { 964 compatible = "qcom,msm8998-qmp-pcie-phy"; 965 reg = <0x01c06000 0x18c>; 966 #address-cells = <1>; 967 #size-cells = <1>; 968 ranges; 969 970 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 971 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 972 <&gcc GCC_PCIE_CLKREF_CLK>; 973 clock-names = "aux", "cfg_ahb", "ref"; 974 975 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 976 reset-names = "phy", "common"; 977 978 vdda-phy-supply = <&vreg_l1a_0p875>; 979 vdda-pll-supply = <&vreg_l2a_1p2>; 980 981 pciephy: lane@1c06800 { 982 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 983 #phy-cells = <0>; 984 985 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 986 clock-names = "pipe0"; 987 clock-output-names = "pcie_0_pipe_clk_src"; 988 #clock-cells = <0>; 989 }; 990 }; 991 992 ufshc: ufshc@1da4000 { 993 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 994 reg = <0x01da4000 0x2500>; 995 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 996 phys = <&ufsphy_lanes>; 997 phy-names = "ufsphy"; 998 lanes-per-direction = <2>; 999 power-domains = <&gcc UFS_GDSC>; 1000 #reset-cells = <1>; 1001 1002 clock-names = 1003 "core_clk", 1004 "bus_aggr_clk", 1005 "iface_clk", 1006 "core_clk_unipro", 1007 "ref_clk", 1008 "tx_lane0_sync_clk", 1009 "rx_lane0_sync_clk", 1010 "rx_lane1_sync_clk"; 1011 clocks = 1012 <&gcc GCC_UFS_AXI_CLK>, 1013 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1014 <&gcc GCC_UFS_AHB_CLK>, 1015 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1016 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1017 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1018 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1019 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1020 freq-table-hz = 1021 <50000000 200000000>, 1022 <0 0>, 1023 <0 0>, 1024 <37500000 150000000>, 1025 <0 0>, 1026 <0 0>, 1027 <0 0>, 1028 <0 0>; 1029 1030 resets = <&gcc GCC_UFS_BCR>; 1031 reset-names = "rst"; 1032 }; 1033 1034 ufsphy: phy@1da7000 { 1035 compatible = "qcom,msm8998-qmp-ufs-phy"; 1036 reg = <0x01da7000 0x18c>; 1037 #address-cells = <1>; 1038 #size-cells = <1>; 1039 ranges; 1040 1041 clock-names = 1042 "ref", 1043 "ref_aux"; 1044 clocks = 1045 <&gcc GCC_UFS_CLKREF_CLK>, 1046 <&gcc GCC_UFS_PHY_AUX_CLK>; 1047 1048 reset-names = "ufsphy"; 1049 resets = <&ufshc 0>; 1050 1051 ufsphy_lanes: lanes@1da7400 { 1052 reg = <0x01da7400 0x128>, 1053 <0x01da7600 0x1fc>, 1054 <0x01da7c00 0x1dc>, 1055 <0x01da7800 0x128>, 1056 <0x01da7a00 0x1fc>; 1057 #phy-cells = <0>; 1058 }; 1059 }; 1060 1061 tcsr_mutex_regs: syscon@1f40000 { 1062 compatible = "syscon"; 1063 reg = <0x01f40000 0x40000>; 1064 }; 1065 1066 tlmm: pinctrl@3400000 { 1067 compatible = "qcom,msm8998-pinctrl"; 1068 reg = <0x03400000 0xc00000>; 1069 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1070 gpio-controller; 1071 #gpio-cells = <0x2>; 1072 interrupt-controller; 1073 #interrupt-cells = <0x2>; 1074 }; 1075 1076 gpucc: clock-controller@5065000 { 1077 compatible = "qcom,msm8998-gpucc"; 1078 #clock-cells = <1>; 1079 #reset-cells = <1>; 1080 #power-domain-cells = <1>; 1081 reg = <0x05065000 0x9000>; 1082 1083 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1084 <&gcc GPLL0_OUT_MAIN>; 1085 clock-names = "xo", 1086 "gpll0"; 1087 }; 1088 1089 stm: stm@6002000 { 1090 compatible = "arm,coresight-stm", "arm,primecell"; 1091 reg = <0x06002000 0x1000>, 1092 <0x16280000 0x180000>; 1093 reg-names = "stm-base", "stm-data-base"; 1094 status = "disabled"; 1095 1096 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1097 clock-names = "apb_pclk", "atclk"; 1098 1099 out-ports { 1100 port { 1101 stm_out: endpoint { 1102 remote-endpoint = <&funnel0_in7>; 1103 }; 1104 }; 1105 }; 1106 }; 1107 1108 funnel1: funnel@6041000 { 1109 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1110 reg = <0x06041000 0x1000>; 1111 status = "disabled"; 1112 1113 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1114 clock-names = "apb_pclk", "atclk"; 1115 1116 out-ports { 1117 port { 1118 funnel0_out: endpoint { 1119 remote-endpoint = 1120 <&merge_funnel_in0>; 1121 }; 1122 }; 1123 }; 1124 1125 in-ports { 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 1129 port@7 { 1130 reg = <7>; 1131 funnel0_in7: endpoint { 1132 remote-endpoint = <&stm_out>; 1133 }; 1134 }; 1135 }; 1136 }; 1137 1138 funnel2: funnel@6042000 { 1139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1140 reg = <0x06042000 0x1000>; 1141 status = "disabled"; 1142 1143 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1144 clock-names = "apb_pclk", "atclk"; 1145 1146 out-ports { 1147 port { 1148 funnel1_out: endpoint { 1149 remote-endpoint = 1150 <&merge_funnel_in1>; 1151 }; 1152 }; 1153 }; 1154 1155 in-ports { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 1159 port@6 { 1160 reg = <6>; 1161 funnel1_in6: endpoint { 1162 remote-endpoint = 1163 <&apss_merge_funnel_out>; 1164 }; 1165 }; 1166 }; 1167 }; 1168 1169 funnel3: funnel@6045000 { 1170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1171 reg = <0x06045000 0x1000>; 1172 status = "disabled"; 1173 1174 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1175 clock-names = "apb_pclk", "atclk"; 1176 1177 out-ports { 1178 port { 1179 merge_funnel_out: endpoint { 1180 remote-endpoint = 1181 <&etf_in>; 1182 }; 1183 }; 1184 }; 1185 1186 in-ports { 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 1190 port@0 { 1191 reg = <0>; 1192 merge_funnel_in0: endpoint { 1193 remote-endpoint = 1194 <&funnel0_out>; 1195 }; 1196 }; 1197 1198 port@1 { 1199 reg = <1>; 1200 merge_funnel_in1: endpoint { 1201 remote-endpoint = 1202 <&funnel1_out>; 1203 }; 1204 }; 1205 }; 1206 }; 1207 1208 replicator1: replicator@6046000 { 1209 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1210 reg = <0x06046000 0x1000>; 1211 status = "disabled"; 1212 1213 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1214 clock-names = "apb_pclk", "atclk"; 1215 1216 out-ports { 1217 port { 1218 replicator_out: endpoint { 1219 remote-endpoint = <&etr_in>; 1220 }; 1221 }; 1222 }; 1223 1224 in-ports { 1225 port { 1226 replicator_in: endpoint { 1227 remote-endpoint = <&etf_out>; 1228 }; 1229 }; 1230 }; 1231 }; 1232 1233 etf: etf@6047000 { 1234 compatible = "arm,coresight-tmc", "arm,primecell"; 1235 reg = <0x06047000 0x1000>; 1236 status = "disabled"; 1237 1238 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1239 clock-names = "apb_pclk", "atclk"; 1240 1241 out-ports { 1242 port { 1243 etf_out: endpoint { 1244 remote-endpoint = 1245 <&replicator_in>; 1246 }; 1247 }; 1248 }; 1249 1250 in-ports { 1251 port { 1252 etf_in: endpoint { 1253 remote-endpoint = 1254 <&merge_funnel_out>; 1255 }; 1256 }; 1257 }; 1258 }; 1259 1260 etr: etr@6048000 { 1261 compatible = "arm,coresight-tmc", "arm,primecell"; 1262 reg = <0x06048000 0x1000>; 1263 status = "disabled"; 1264 1265 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1266 clock-names = "apb_pclk", "atclk"; 1267 arm,scatter-gather; 1268 1269 in-ports { 1270 port { 1271 etr_in: endpoint { 1272 remote-endpoint = 1273 <&replicator_out>; 1274 }; 1275 }; 1276 }; 1277 }; 1278 1279 etm1: etm@7840000 { 1280 compatible = "arm,coresight-etm4x", "arm,primecell"; 1281 reg = <0x07840000 0x1000>; 1282 status = "disabled"; 1283 1284 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1285 clock-names = "apb_pclk", "atclk"; 1286 1287 cpu = <&CPU0>; 1288 1289 out-ports { 1290 port { 1291 etm0_out: endpoint { 1292 remote-endpoint = 1293 <&apss_funnel_in0>; 1294 }; 1295 }; 1296 }; 1297 }; 1298 1299 etm2: etm@7940000 { 1300 compatible = "arm,coresight-etm4x", "arm,primecell"; 1301 reg = <0x07940000 0x1000>; 1302 status = "disabled"; 1303 1304 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1305 clock-names = "apb_pclk", "atclk"; 1306 1307 cpu = <&CPU1>; 1308 1309 out-ports { 1310 port { 1311 etm1_out: endpoint { 1312 remote-endpoint = 1313 <&apss_funnel_in1>; 1314 }; 1315 }; 1316 }; 1317 }; 1318 1319 etm3: etm@7a40000 { 1320 compatible = "arm,coresight-etm4x", "arm,primecell"; 1321 reg = <0x07a40000 0x1000>; 1322 status = "disabled"; 1323 1324 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1325 clock-names = "apb_pclk", "atclk"; 1326 1327 cpu = <&CPU2>; 1328 1329 out-ports { 1330 port { 1331 etm2_out: endpoint { 1332 remote-endpoint = 1333 <&apss_funnel_in2>; 1334 }; 1335 }; 1336 }; 1337 }; 1338 1339 etm4: etm@7b40000 { 1340 compatible = "arm,coresight-etm4x", "arm,primecell"; 1341 reg = <0x07b40000 0x1000>; 1342 status = "disabled"; 1343 1344 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1345 clock-names = "apb_pclk", "atclk"; 1346 1347 cpu = <&CPU3>; 1348 1349 out-ports { 1350 port { 1351 etm3_out: endpoint { 1352 remote-endpoint = 1353 <&apss_funnel_in3>; 1354 }; 1355 }; 1356 }; 1357 }; 1358 1359 funnel4: funnel@7b60000 { /* APSS Funnel */ 1360 compatible = "arm,coresight-etm4x", "arm,primecell"; 1361 reg = <0x07b60000 0x1000>; 1362 status = "disabled"; 1363 1364 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1365 clock-names = "apb_pclk", "atclk"; 1366 1367 out-ports { 1368 port { 1369 apss_funnel_out: endpoint { 1370 remote-endpoint = 1371 <&apss_merge_funnel_in>; 1372 }; 1373 }; 1374 }; 1375 1376 in-ports { 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 1380 port@0 { 1381 reg = <0>; 1382 apss_funnel_in0: endpoint { 1383 remote-endpoint = 1384 <&etm0_out>; 1385 }; 1386 }; 1387 1388 port@1 { 1389 reg = <1>; 1390 apss_funnel_in1: endpoint { 1391 remote-endpoint = 1392 <&etm1_out>; 1393 }; 1394 }; 1395 1396 port@2 { 1397 reg = <2>; 1398 apss_funnel_in2: endpoint { 1399 remote-endpoint = 1400 <&etm2_out>; 1401 }; 1402 }; 1403 1404 port@3 { 1405 reg = <3>; 1406 apss_funnel_in3: endpoint { 1407 remote-endpoint = 1408 <&etm3_out>; 1409 }; 1410 }; 1411 1412 port@4 { 1413 reg = <4>; 1414 apss_funnel_in4: endpoint { 1415 remote-endpoint = 1416 <&etm4_out>; 1417 }; 1418 }; 1419 1420 port@5 { 1421 reg = <5>; 1422 apss_funnel_in5: endpoint { 1423 remote-endpoint = 1424 <&etm5_out>; 1425 }; 1426 }; 1427 1428 port@6 { 1429 reg = <6>; 1430 apss_funnel_in6: endpoint { 1431 remote-endpoint = 1432 <&etm6_out>; 1433 }; 1434 }; 1435 1436 port@7 { 1437 reg = <7>; 1438 apss_funnel_in7: endpoint { 1439 remote-endpoint = 1440 <&etm7_out>; 1441 }; 1442 }; 1443 }; 1444 }; 1445 1446 funnel5: funnel@7b70000 { 1447 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1448 reg = <0x07b70000 0x1000>; 1449 status = "disabled"; 1450 1451 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1452 clock-names = "apb_pclk", "atclk"; 1453 1454 out-ports { 1455 port { 1456 apss_merge_funnel_out: endpoint { 1457 remote-endpoint = 1458 <&funnel1_in6>; 1459 }; 1460 }; 1461 }; 1462 1463 in-ports { 1464 port { 1465 apss_merge_funnel_in: endpoint { 1466 remote-endpoint = 1467 <&apss_funnel_out>; 1468 }; 1469 }; 1470 }; 1471 }; 1472 1473 etm5: etm@7c40000 { 1474 compatible = "arm,coresight-etm4x", "arm,primecell"; 1475 reg = <0x07c40000 0x1000>; 1476 status = "disabled"; 1477 1478 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1479 clock-names = "apb_pclk", "atclk"; 1480 1481 cpu = <&CPU4>; 1482 1483 port{ 1484 etm4_out: endpoint { 1485 remote-endpoint = <&apss_funnel_in4>; 1486 }; 1487 }; 1488 }; 1489 1490 etm6: etm@7d40000 { 1491 compatible = "arm,coresight-etm4x", "arm,primecell"; 1492 reg = <0x07d40000 0x1000>; 1493 status = "disabled"; 1494 1495 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1496 clock-names = "apb_pclk", "atclk"; 1497 1498 cpu = <&CPU5>; 1499 1500 port{ 1501 etm5_out: endpoint { 1502 remote-endpoint = <&apss_funnel_in5>; 1503 }; 1504 }; 1505 }; 1506 1507 etm7: etm@7e40000 { 1508 compatible = "arm,coresight-etm4x", "arm,primecell"; 1509 reg = <0x07e40000 0x1000>; 1510 status = "disabled"; 1511 1512 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1513 clock-names = "apb_pclk", "atclk"; 1514 1515 cpu = <&CPU6>; 1516 1517 port{ 1518 etm6_out: endpoint { 1519 remote-endpoint = <&apss_funnel_in6>; 1520 }; 1521 }; 1522 }; 1523 1524 etm8: etm@7f40000 { 1525 compatible = "arm,coresight-etm4x", "arm,primecell"; 1526 reg = <0x07f40000 0x1000>; 1527 status = "disabled"; 1528 1529 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1530 clock-names = "apb_pclk", "atclk"; 1531 1532 cpu = <&CPU7>; 1533 1534 port{ 1535 etm7_out: endpoint { 1536 remote-endpoint = <&apss_funnel_in7>; 1537 }; 1538 }; 1539 }; 1540 1541 spmi_bus: spmi@800f000 { 1542 compatible = "qcom,spmi-pmic-arb"; 1543 reg = <0x0800f000 0x1000>, 1544 <0x08400000 0x1000000>, 1545 <0x09400000 0x1000000>, 1546 <0x0a400000 0x220000>, 1547 <0x0800a000 0x3000>; 1548 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1549 interrupt-names = "periph_irq"; 1550 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1551 qcom,ee = <0>; 1552 qcom,channel = <0>; 1553 #address-cells = <2>; 1554 #size-cells = <0>; 1555 interrupt-controller; 1556 #interrupt-cells = <4>; 1557 cell-index = <0>; 1558 }; 1559 1560 usb3: usb@a8f8800 { 1561 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 1562 reg = <0x0a8f8800 0x400>; 1563 status = "disabled"; 1564 #address-cells = <1>; 1565 #size-cells = <1>; 1566 ranges; 1567 1568 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1569 <&gcc GCC_USB30_MASTER_CLK>, 1570 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 1571 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1572 <&gcc GCC_USB30_SLEEP_CLK>; 1573 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1574 "sleep"; 1575 1576 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1577 <&gcc GCC_USB30_MASTER_CLK>; 1578 assigned-clock-rates = <19200000>, <120000000>; 1579 1580 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1582 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1583 1584 power-domains = <&gcc USB_30_GDSC>; 1585 1586 resets = <&gcc GCC_USB_30_BCR>; 1587 1588 usb3_dwc3: dwc3@a800000 { 1589 compatible = "snps,dwc3"; 1590 reg = <0x0a800000 0xcd00>; 1591 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1592 snps,dis_u2_susphy_quirk; 1593 snps,dis_enblslpm_quirk; 1594 phys = <&qusb2phy>, <&usb1_ssphy>; 1595 phy-names = "usb2-phy", "usb3-phy"; 1596 snps,has-lpm-erratum; 1597 snps,hird-threshold = /bits/ 8 <0x10>; 1598 }; 1599 }; 1600 1601 usb3phy: phy@c010000 { 1602 compatible = "qcom,msm8998-qmp-usb3-phy"; 1603 reg = <0x0c010000 0x18c>; 1604 status = "disabled"; 1605 #clock-cells = <1>; 1606 #address-cells = <1>; 1607 #size-cells = <1>; 1608 ranges; 1609 1610 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1611 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1612 <&gcc GCC_USB3_CLKREF_CLK>; 1613 clock-names = "aux", "cfg_ahb", "ref"; 1614 1615 resets = <&gcc GCC_USB3_PHY_BCR>, 1616 <&gcc GCC_USB3PHY_PHY_BCR>; 1617 reset-names = "phy", "common"; 1618 1619 usb1_ssphy: lane@c010200 { 1620 reg = <0xc010200 0x128>, 1621 <0xc010400 0x200>, 1622 <0xc010c00 0x20c>, 1623 <0xc010600 0x128>, 1624 <0xc010800 0x200>; 1625 #phy-cells = <0>; 1626 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1627 clock-names = "pipe0"; 1628 clock-output-names = "usb3_phy_pipe_clk_src"; 1629 }; 1630 }; 1631 1632 qusb2phy: phy@c012000 { 1633 compatible = "qcom,msm8998-qusb2-phy"; 1634 reg = <0x0c012000 0x2a8>; 1635 status = "disabled"; 1636 #phy-cells = <0>; 1637 1638 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1639 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1640 clock-names = "cfg_ahb", "ref"; 1641 1642 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1643 1644 nvmem-cells = <&qusb2_hstx_trim>; 1645 }; 1646 1647 sdhc2: sdhci@c0a4900 { 1648 compatible = "qcom,sdhci-msm-v4"; 1649 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 1650 reg-names = "hc_mem", "core_mem"; 1651 1652 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1654 interrupt-names = "hc_irq", "pwr_irq"; 1655 1656 clock-names = "iface", "core", "xo"; 1657 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1658 <&gcc GCC_SDCC2_APPS_CLK>, 1659 <&xo>; 1660 bus-width = <4>; 1661 status = "disabled"; 1662 }; 1663 1664 blsp1_dma: dma@c144000 { 1665 compatible = "qcom,bam-v1.7.0"; 1666 reg = <0x0c144000 0x25000>; 1667 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1668 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1669 clock-names = "bam_clk"; 1670 #dma-cells = <1>; 1671 qcom,ee = <0>; 1672 qcom,controlled-remotely; 1673 num-channels = <18>; 1674 qcom,num-ees = <4>; 1675 }; 1676 1677 blsp1_uart3: serial@c171000 { 1678 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1679 reg = <0x0c171000 0x1000>; 1680 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1681 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 1682 <&gcc GCC_BLSP1_AHB_CLK>; 1683 clock-names = "core", "iface"; 1684 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1685 dma-names = "tx", "rx"; 1686 pinctrl-names = "default"; 1687 pinctrl-0 = <&blsp1_uart3_on>; 1688 status = "disabled"; 1689 }; 1690 1691 blsp1_i2c1: i2c@c175000 { 1692 compatible = "qcom,i2c-qup-v2.2.1"; 1693 reg = <0x0c175000 0x600>; 1694 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1695 1696 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1697 <&gcc GCC_BLSP1_AHB_CLK>; 1698 clock-names = "core", "iface"; 1699 clock-frequency = <400000>; 1700 1701 status = "disabled"; 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 }; 1705 1706 blsp1_i2c2: i2c@c176000 { 1707 compatible = "qcom,i2c-qup-v2.2.1"; 1708 reg = <0x0c176000 0x600>; 1709 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1710 1711 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1712 <&gcc GCC_BLSP1_AHB_CLK>; 1713 clock-names = "core", "iface"; 1714 clock-frequency = <400000>; 1715 1716 status = "disabled"; 1717 #address-cells = <1>; 1718 #size-cells = <0>; 1719 }; 1720 1721 blsp1_i2c3: i2c@c177000 { 1722 compatible = "qcom,i2c-qup-v2.2.1"; 1723 reg = <0x0c177000 0x600>; 1724 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1725 1726 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1727 <&gcc GCC_BLSP1_AHB_CLK>; 1728 clock-names = "core", "iface"; 1729 clock-frequency = <400000>; 1730 1731 status = "disabled"; 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 }; 1735 1736 blsp1_i2c4: i2c@c178000 { 1737 compatible = "qcom,i2c-qup-v2.2.1"; 1738 reg = <0x0c178000 0x600>; 1739 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1740 1741 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1742 <&gcc GCC_BLSP1_AHB_CLK>; 1743 clock-names = "core", "iface"; 1744 clock-frequency = <400000>; 1745 1746 status = "disabled"; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 }; 1750 1751 blsp1_i2c5: i2c@c179000 { 1752 compatible = "qcom,i2c-qup-v2.2.1"; 1753 reg = <0x0c179000 0x600>; 1754 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1755 1756 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1757 <&gcc GCC_BLSP1_AHB_CLK>; 1758 clock-names = "core", "iface"; 1759 clock-frequency = <400000>; 1760 1761 status = "disabled"; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 }; 1765 1766 blsp1_i2c6: i2c@c17a000 { 1767 compatible = "qcom,i2c-qup-v2.2.1"; 1768 reg = <0x0c17a000 0x600>; 1769 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1770 1771 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1772 <&gcc GCC_BLSP1_AHB_CLK>; 1773 clock-names = "core", "iface"; 1774 clock-frequency = <400000>; 1775 1776 status = "disabled"; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 }; 1780 1781 blsp2_uart1: serial@c1b0000 { 1782 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1783 reg = <0x0c1b0000 0x1000>; 1784 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1785 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1786 <&gcc GCC_BLSP2_AHB_CLK>; 1787 clock-names = "core", "iface"; 1788 status = "disabled"; 1789 }; 1790 1791 blsp2_i2c0: i2c@c1b5000 { 1792 compatible = "qcom,i2c-qup-v2.2.1"; 1793 reg = <0x0c1b5000 0x600>; 1794 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1795 1796 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1797 <&gcc GCC_BLSP2_AHB_CLK>; 1798 clock-names = "core", "iface"; 1799 clock-frequency = <400000>; 1800 1801 status = "disabled"; 1802 #address-cells = <1>; 1803 #size-cells = <0>; 1804 }; 1805 1806 blsp2_i2c1: i2c@c1b6000 { 1807 compatible = "qcom,i2c-qup-v2.2.1"; 1808 reg = <0x0c1b6000 0x600>; 1809 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1810 1811 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1812 <&gcc GCC_BLSP2_AHB_CLK>; 1813 clock-names = "core", "iface"; 1814 clock-frequency = <400000>; 1815 1816 status = "disabled"; 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 }; 1820 1821 blsp2_i2c2: i2c@c1b7000 { 1822 compatible = "qcom,i2c-qup-v2.2.1"; 1823 reg = <0x0c1b7000 0x600>; 1824 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1825 1826 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1827 <&gcc GCC_BLSP2_AHB_CLK>; 1828 clock-names = "core", "iface"; 1829 clock-frequency = <400000>; 1830 1831 status = "disabled"; 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 }; 1835 1836 blsp2_i2c3: i2c@c1b8000 { 1837 compatible = "qcom,i2c-qup-v2.2.1"; 1838 reg = <0x0c1b8000 0x600>; 1839 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1840 1841 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1842 <&gcc GCC_BLSP2_AHB_CLK>; 1843 clock-names = "core", "iface"; 1844 clock-frequency = <400000>; 1845 1846 status = "disabled"; 1847 #address-cells = <1>; 1848 #size-cells = <0>; 1849 }; 1850 1851 blsp2_i2c4: i2c@c1b9000 { 1852 compatible = "qcom,i2c-qup-v2.2.1"; 1853 reg = <0x0c1b9000 0x600>; 1854 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1855 1856 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 1857 <&gcc GCC_BLSP2_AHB_CLK>; 1858 clock-names = "core", "iface"; 1859 clock-frequency = <400000>; 1860 1861 status = "disabled"; 1862 #address-cells = <1>; 1863 #size-cells = <0>; 1864 }; 1865 1866 blsp2_i2c5: i2c@c1ba000 { 1867 compatible = "qcom,i2c-qup-v2.2.1"; 1868 reg = <0x0c1ba000 0x600>; 1869 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1870 1871 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 1872 <&gcc GCC_BLSP2_AHB_CLK>; 1873 clock-names = "core", "iface"; 1874 clock-frequency = <400000>; 1875 1876 status = "disabled"; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 }; 1880 1881 apcs_glb: mailbox@17911000 { 1882 compatible = "qcom,msm8998-apcs-hmss-global"; 1883 reg = <0x17911000 0x1000>; 1884 1885 #mbox-cells = <1>; 1886 }; 1887 1888 timer@17920000 { 1889 #address-cells = <1>; 1890 #size-cells = <1>; 1891 ranges; 1892 compatible = "arm,armv7-timer-mem"; 1893 reg = <0x17920000 0x1000>; 1894 1895 frame@17921000 { 1896 frame-number = <0>; 1897 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1899 reg = <0x17921000 0x1000>, 1900 <0x17922000 0x1000>; 1901 }; 1902 1903 frame@17923000 { 1904 frame-number = <1>; 1905 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1906 reg = <0x17923000 0x1000>; 1907 status = "disabled"; 1908 }; 1909 1910 frame@17924000 { 1911 frame-number = <2>; 1912 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1913 reg = <0x17924000 0x1000>; 1914 status = "disabled"; 1915 }; 1916 1917 frame@17925000 { 1918 frame-number = <3>; 1919 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1920 reg = <0x17925000 0x1000>; 1921 status = "disabled"; 1922 }; 1923 1924 frame@17926000 { 1925 frame-number = <4>; 1926 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1927 reg = <0x17926000 0x1000>; 1928 status = "disabled"; 1929 }; 1930 1931 frame@17927000 { 1932 frame-number = <5>; 1933 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1934 reg = <0x17927000 0x1000>; 1935 status = "disabled"; 1936 }; 1937 1938 frame@17928000 { 1939 frame-number = <6>; 1940 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1941 reg = <0x17928000 0x1000>; 1942 status = "disabled"; 1943 }; 1944 }; 1945 1946 intc: interrupt-controller@17a00000 { 1947 compatible = "arm,gic-v3"; 1948 reg = <0x17a00000 0x10000>, /* GICD */ 1949 <0x17b00000 0x100000>; /* GICR * 8 */ 1950 #interrupt-cells = <3>; 1951 #address-cells = <1>; 1952 #size-cells = <1>; 1953 ranges; 1954 interrupt-controller; 1955 #redistributor-regions = <1>; 1956 redistributor-stride = <0x0 0x20000>; 1957 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1958 }; 1959 1960 wifi: wifi@18800000 { 1961 compatible = "qcom,wcn3990-wifi"; 1962 status = "disabled"; 1963 reg = <0x18800000 0x800000>; 1964 reg-names = "membase"; 1965 memory-region = <&wlan_msa_mem>; 1966 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 1967 clock-names = "cxo_ref_clk_pin"; 1968 interrupts = 1969 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1981 iommus = <&anoc2_smmu 0x1900>, 1982 <&anoc2_smmu 0x1901>; 1983 qcom,snoc-host-cap-8bit-quirk; 1984 }; 1985 }; 1986}; 1987 1988#include "msm8998-pins.dtsi" 1989