1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 qcom,msm-id = <292 0x0>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 memory@80000000 { 23 device_type = "memory"; 24 /* We expect the bootloader to fill in the reg */ 25 reg = <0x0 0x80000000 0x0 0x0>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 hyp_mem: memory@85800000 { 34 reg = <0x0 0x85800000 0x0 0x600000>; 35 no-map; 36 }; 37 38 xbl_mem: memory@85e00000 { 39 reg = <0x0 0x85e00000 0x0 0x100000>; 40 no-map; 41 }; 42 43 smem_mem: smem-mem@86000000 { 44 reg = <0x0 0x86000000 0x0 0x200000>; 45 no-map; 46 }; 47 48 tz_mem: memory@86200000 { 49 reg = <0x0 0x86200000 0x0 0x2d00000>; 50 no-map; 51 }; 52 53 rmtfs_mem: memory@88f00000 { 54 compatible = "qcom,rmtfs-mem"; 55 reg = <0x0 0x88f00000 0x0 0x200000>; 56 no-map; 57 58 qcom,client-id = <1>; 59 qcom,vmid = <15>; 60 }; 61 62 spss_mem: memory@8ab00000 { 63 reg = <0x0 0x8ab00000 0x0 0x700000>; 64 no-map; 65 }; 66 67 adsp_mem: memory@8b200000 { 68 reg = <0x0 0x8b200000 0x0 0x1a00000>; 69 no-map; 70 }; 71 72 mpss_mem: memory@8cc00000 { 73 reg = <0x0 0x8cc00000 0x0 0x7000000>; 74 no-map; 75 }; 76 77 venus_mem: memory@93c00000 { 78 reg = <0x0 0x93c00000 0x0 0x500000>; 79 no-map; 80 }; 81 82 mba_mem: memory@94100000 { 83 reg = <0x0 0x94100000 0x0 0x200000>; 84 no-map; 85 }; 86 87 slpi_mem: memory@94300000 { 88 reg = <0x0 0x94300000 0x0 0xf00000>; 89 no-map; 90 }; 91 92 ipa_fw_mem: memory@95200000 { 93 reg = <0x0 0x95200000 0x0 0x10000>; 94 no-map; 95 }; 96 97 ipa_gsi_mem: memory@95210000 { 98 reg = <0x0 0x95210000 0x0 0x5000>; 99 no-map; 100 }; 101 102 gpu_mem: memory@95600000 { 103 reg = <0x0 0x95600000 0x0 0x100000>; 104 no-map; 105 }; 106 107 wlan_msa_mem: memory@95700000 { 108 reg = <0x0 0x95700000 0x0 0x100000>; 109 no-map; 110 }; 111 112 mdata_mem: mpss-metadata { 113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 114 size = <0x0 0x4000>; 115 no-map; 116 }; 117 }; 118 119 clocks { 120 xo: xo-board { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <19200000>; 124 clock-output-names = "xo_board"; 125 }; 126 127 sleep_clk: sleep-clk { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <32764>; 131 }; 132 }; 133 134 cpus { 135 #address-cells = <2>; 136 #size-cells = <0>; 137 138 CPU0: cpu@0 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo280"; 141 reg = <0x0 0x0>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 145 next-level-cache = <&L2_0>; 146 L2_0: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 }; 151 }; 152 153 CPU1: cpu@1 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo280"; 156 reg = <0x0 0x1>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <1024>; 159 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 160 next-level-cache = <&L2_0>; 161 }; 162 163 CPU2: cpu@2 { 164 device_type = "cpu"; 165 compatible = "qcom,kryo280"; 166 reg = <0x0 0x2>; 167 enable-method = "psci"; 168 capacity-dmips-mhz = <1024>; 169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 170 next-level-cache = <&L2_0>; 171 }; 172 173 CPU3: cpu@3 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo280"; 176 reg = <0x0 0x3>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <1024>; 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 180 next-level-cache = <&L2_0>; 181 }; 182 183 CPU4: cpu@100 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo280"; 186 reg = <0x0 0x100>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1536>; 189 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 190 next-level-cache = <&L2_1>; 191 L2_1: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 }; 196 }; 197 198 CPU5: cpu@101 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo280"; 201 reg = <0x0 0x101>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1536>; 204 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 205 next-level-cache = <&L2_1>; 206 }; 207 208 CPU6: cpu@102 { 209 device_type = "cpu"; 210 compatible = "qcom,kryo280"; 211 reg = <0x0 0x102>; 212 enable-method = "psci"; 213 capacity-dmips-mhz = <1536>; 214 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 215 next-level-cache = <&L2_1>; 216 }; 217 218 CPU7: cpu@103 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo280"; 221 reg = <0x0 0x103>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1536>; 224 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 225 next-level-cache = <&L2_1>; 226 }; 227 228 cpu-map { 229 cluster0 { 230 core0 { 231 cpu = <&CPU0>; 232 }; 233 234 core1 { 235 cpu = <&CPU1>; 236 }; 237 238 core2 { 239 cpu = <&CPU2>; 240 }; 241 242 core3 { 243 cpu = <&CPU3>; 244 }; 245 }; 246 247 cluster1 { 248 core0 { 249 cpu = <&CPU4>; 250 }; 251 252 core1 { 253 cpu = <&CPU5>; 254 }; 255 256 core2 { 257 cpu = <&CPU6>; 258 }; 259 260 core3 { 261 cpu = <&CPU7>; 262 }; 263 }; 264 }; 265 266 idle-states { 267 entry-method = "psci"; 268 269 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 270 compatible = "arm,idle-state"; 271 idle-state-name = "little-retention"; 272 /* CPU Retention (C2D), L2 Active */ 273 arm,psci-suspend-param = <0x00000002>; 274 entry-latency-us = <81>; 275 exit-latency-us = <86>; 276 min-residency-us = <504>; 277 }; 278 279 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "little-power-collapse"; 282 /* CPU + L2 Power Collapse (C3, D4) */ 283 arm,psci-suspend-param = <0x40000003>; 284 entry-latency-us = <814>; 285 exit-latency-us = <4562>; 286 min-residency-us = <9183>; 287 local-timer-stop; 288 }; 289 290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 idle-state-name = "big-retention"; 293 /* CPU Retention (C2D), L2 Active */ 294 arm,psci-suspend-param = <0x00000002>; 295 entry-latency-us = <79>; 296 exit-latency-us = <82>; 297 min-residency-us = <1302>; 298 }; 299 300 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "big-power-collapse"; 303 /* CPU + L2 Power Collapse (C3, D4) */ 304 arm,psci-suspend-param = <0x40000003>; 305 entry-latency-us = <724>; 306 exit-latency-us = <2027>; 307 min-residency-us = <9419>; 308 local-timer-stop; 309 }; 310 }; 311 }; 312 313 firmware { 314 scm { 315 compatible = "qcom,scm-msm8998", "qcom,scm"; 316 }; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 }; 323 324 rpm-glink { 325 compatible = "qcom,glink-rpm"; 326 327 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 328 qcom,rpm-msg-ram = <&rpm_msg_ram>; 329 mboxes = <&apcs_glb 0>; 330 331 rpm_requests: rpm-requests { 332 compatible = "qcom,rpm-msm8998"; 333 qcom,glink-channels = "rpm_requests"; 334 335 rpmcc: clock-controller { 336 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 337 clocks = <&xo>; 338 clock-names = "xo"; 339 #clock-cells = <1>; 340 }; 341 342 rpmpd: power-controller { 343 compatible = "qcom,msm8998-rpmpd"; 344 #power-domain-cells = <1>; 345 operating-points-v2 = <&rpmpd_opp_table>; 346 347 rpmpd_opp_table: opp-table { 348 compatible = "operating-points-v2"; 349 350 rpmpd_opp_ret: opp1 { 351 opp-level = <RPM_SMD_LEVEL_RETENTION>; 352 }; 353 354 rpmpd_opp_ret_plus: opp2 { 355 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 356 }; 357 358 rpmpd_opp_min_svs: opp3 { 359 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 360 }; 361 362 rpmpd_opp_low_svs: opp4 { 363 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 364 }; 365 366 rpmpd_opp_svs: opp5 { 367 opp-level = <RPM_SMD_LEVEL_SVS>; 368 }; 369 370 rpmpd_opp_svs_plus: opp6 { 371 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 372 }; 373 374 rpmpd_opp_nom: opp7 { 375 opp-level = <RPM_SMD_LEVEL_NOM>; 376 }; 377 378 rpmpd_opp_nom_plus: opp8 { 379 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 380 }; 381 382 rpmpd_opp_turbo: opp9 { 383 opp-level = <RPM_SMD_LEVEL_TURBO>; 384 }; 385 386 rpmpd_opp_turbo_plus: opp10 { 387 opp-level = <RPM_SMD_LEVEL_BINNING>; 388 }; 389 }; 390 }; 391 }; 392 }; 393 394 smem { 395 compatible = "qcom,smem"; 396 memory-region = <&smem_mem>; 397 hwlocks = <&tcsr_mutex 3>; 398 }; 399 400 smp2p-lpass { 401 compatible = "qcom,smp2p"; 402 qcom,smem = <443>, <429>; 403 404 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 405 406 mboxes = <&apcs_glb 10>; 407 408 qcom,local-pid = <0>; 409 qcom,remote-pid = <2>; 410 411 adsp_smp2p_out: master-kernel { 412 qcom,entry-name = "master-kernel"; 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 adsp_smp2p_in: slave-kernel { 417 qcom,entry-name = "slave-kernel"; 418 419 interrupt-controller; 420 #interrupt-cells = <2>; 421 }; 422 }; 423 424 smp2p-mpss { 425 compatible = "qcom,smp2p"; 426 qcom,smem = <435>, <428>; 427 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 428 mboxes = <&apcs_glb 14>; 429 qcom,local-pid = <0>; 430 qcom,remote-pid = <1>; 431 432 modem_smp2p_out: master-kernel { 433 qcom,entry-name = "master-kernel"; 434 #qcom,smem-state-cells = <1>; 435 }; 436 437 modem_smp2p_in: slave-kernel { 438 qcom,entry-name = "slave-kernel"; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 }; 442 }; 443 444 smp2p-slpi { 445 compatible = "qcom,smp2p"; 446 qcom,smem = <481>, <430>; 447 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 448 mboxes = <&apcs_glb 26>; 449 qcom,local-pid = <0>; 450 qcom,remote-pid = <3>; 451 452 slpi_smp2p_out: master-kernel { 453 qcom,entry-name = "master-kernel"; 454 #qcom,smem-state-cells = <1>; 455 }; 456 457 slpi_smp2p_in: slave-kernel { 458 qcom,entry-name = "slave-kernel"; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 }; 462 }; 463 464 thermal-zones { 465 cpu0-thermal { 466 polling-delay-passive = <250>; 467 polling-delay = <1000>; 468 469 thermal-sensors = <&tsens0 1>; 470 471 trips { 472 cpu0_alert0: trip-point0 { 473 temperature = <75000>; 474 hysteresis = <2000>; 475 type = "passive"; 476 }; 477 478 cpu0_crit: cpu-crit { 479 temperature = <110000>; 480 hysteresis = <2000>; 481 type = "critical"; 482 }; 483 }; 484 }; 485 486 cpu1-thermal { 487 polling-delay-passive = <250>; 488 polling-delay = <1000>; 489 490 thermal-sensors = <&tsens0 2>; 491 492 trips { 493 cpu1_alert0: trip-point0 { 494 temperature = <75000>; 495 hysteresis = <2000>; 496 type = "passive"; 497 }; 498 499 cpu1_crit: cpu-crit { 500 temperature = <110000>; 501 hysteresis = <2000>; 502 type = "critical"; 503 }; 504 }; 505 }; 506 507 cpu2-thermal { 508 polling-delay-passive = <250>; 509 polling-delay = <1000>; 510 511 thermal-sensors = <&tsens0 3>; 512 513 trips { 514 cpu2_alert0: trip-point0 { 515 temperature = <75000>; 516 hysteresis = <2000>; 517 type = "passive"; 518 }; 519 520 cpu2_crit: cpu-crit { 521 temperature = <110000>; 522 hysteresis = <2000>; 523 type = "critical"; 524 }; 525 }; 526 }; 527 528 cpu3-thermal { 529 polling-delay-passive = <250>; 530 polling-delay = <1000>; 531 532 thermal-sensors = <&tsens0 4>; 533 534 trips { 535 cpu3_alert0: trip-point0 { 536 temperature = <75000>; 537 hysteresis = <2000>; 538 type = "passive"; 539 }; 540 541 cpu3_crit: cpu-crit { 542 temperature = <110000>; 543 hysteresis = <2000>; 544 type = "critical"; 545 }; 546 }; 547 }; 548 549 cpu4-thermal { 550 polling-delay-passive = <250>; 551 polling-delay = <1000>; 552 553 thermal-sensors = <&tsens0 7>; 554 555 trips { 556 cpu4_alert0: trip-point0 { 557 temperature = <75000>; 558 hysteresis = <2000>; 559 type = "passive"; 560 }; 561 562 cpu4_crit: cpu-crit { 563 temperature = <110000>; 564 hysteresis = <2000>; 565 type = "critical"; 566 }; 567 }; 568 }; 569 570 cpu5-thermal { 571 polling-delay-passive = <250>; 572 polling-delay = <1000>; 573 574 thermal-sensors = <&tsens0 8>; 575 576 trips { 577 cpu5_alert0: trip-point0 { 578 temperature = <75000>; 579 hysteresis = <2000>; 580 type = "passive"; 581 }; 582 583 cpu5_crit: cpu-crit { 584 temperature = <110000>; 585 hysteresis = <2000>; 586 type = "critical"; 587 }; 588 }; 589 }; 590 591 cpu6-thermal { 592 polling-delay-passive = <250>; 593 polling-delay = <1000>; 594 595 thermal-sensors = <&tsens0 9>; 596 597 trips { 598 cpu6_alert0: trip-point0 { 599 temperature = <75000>; 600 hysteresis = <2000>; 601 type = "passive"; 602 }; 603 604 cpu6_crit: cpu-crit { 605 temperature = <110000>; 606 hysteresis = <2000>; 607 type = "critical"; 608 }; 609 }; 610 }; 611 612 cpu7-thermal { 613 polling-delay-passive = <250>; 614 polling-delay = <1000>; 615 616 thermal-sensors = <&tsens0 10>; 617 618 trips { 619 cpu7_alert0: trip-point0 { 620 temperature = <75000>; 621 hysteresis = <2000>; 622 type = "passive"; 623 }; 624 625 cpu7_crit: cpu-crit { 626 temperature = <110000>; 627 hysteresis = <2000>; 628 type = "critical"; 629 }; 630 }; 631 }; 632 633 gpu-bottom-thermal { 634 polling-delay-passive = <250>; 635 polling-delay = <1000>; 636 637 thermal-sensors = <&tsens0 12>; 638 639 trips { 640 gpu1_alert0: trip-point0 { 641 temperature = <90000>; 642 hysteresis = <2000>; 643 type = "hot"; 644 }; 645 }; 646 }; 647 648 gpu-top-thermal { 649 polling-delay-passive = <250>; 650 polling-delay = <1000>; 651 652 thermal-sensors = <&tsens0 13>; 653 654 trips { 655 gpu2_alert0: trip-point0 { 656 temperature = <90000>; 657 hysteresis = <2000>; 658 type = "hot"; 659 }; 660 }; 661 }; 662 663 clust0-mhm-thermal { 664 polling-delay-passive = <250>; 665 polling-delay = <1000>; 666 667 thermal-sensors = <&tsens0 5>; 668 669 trips { 670 cluster0_mhm_alert0: trip-point0 { 671 temperature = <90000>; 672 hysteresis = <2000>; 673 type = "hot"; 674 }; 675 }; 676 }; 677 678 clust1-mhm-thermal { 679 polling-delay-passive = <250>; 680 polling-delay = <1000>; 681 682 thermal-sensors = <&tsens0 6>; 683 684 trips { 685 cluster1_mhm_alert0: trip-point0 { 686 temperature = <90000>; 687 hysteresis = <2000>; 688 type = "hot"; 689 }; 690 }; 691 }; 692 693 cluster1-l2-thermal { 694 polling-delay-passive = <250>; 695 polling-delay = <1000>; 696 697 thermal-sensors = <&tsens0 11>; 698 699 trips { 700 cluster1_l2_alert0: trip-point0 { 701 temperature = <90000>; 702 hysteresis = <2000>; 703 type = "hot"; 704 }; 705 }; 706 }; 707 708 modem-thermal { 709 polling-delay-passive = <250>; 710 polling-delay = <1000>; 711 712 thermal-sensors = <&tsens1 1>; 713 714 trips { 715 modem_alert0: trip-point0 { 716 temperature = <90000>; 717 hysteresis = <2000>; 718 type = "hot"; 719 }; 720 }; 721 }; 722 723 mem-thermal { 724 polling-delay-passive = <250>; 725 polling-delay = <1000>; 726 727 thermal-sensors = <&tsens1 2>; 728 729 trips { 730 mem_alert0: trip-point0 { 731 temperature = <90000>; 732 hysteresis = <2000>; 733 type = "hot"; 734 }; 735 }; 736 }; 737 738 wlan-thermal { 739 polling-delay-passive = <250>; 740 polling-delay = <1000>; 741 742 thermal-sensors = <&tsens1 3>; 743 744 trips { 745 wlan_alert0: trip-point0 { 746 temperature = <90000>; 747 hysteresis = <2000>; 748 type = "hot"; 749 }; 750 }; 751 }; 752 753 q6-dsp-thermal { 754 polling-delay-passive = <250>; 755 polling-delay = <1000>; 756 757 thermal-sensors = <&tsens1 4>; 758 759 trips { 760 q6_dsp_alert0: trip-point0 { 761 temperature = <90000>; 762 hysteresis = <2000>; 763 type = "hot"; 764 }; 765 }; 766 }; 767 768 camera-thermal { 769 polling-delay-passive = <250>; 770 polling-delay = <1000>; 771 772 thermal-sensors = <&tsens1 5>; 773 774 trips { 775 camera_alert0: trip-point0 { 776 temperature = <90000>; 777 hysteresis = <2000>; 778 type = "hot"; 779 }; 780 }; 781 }; 782 783 multimedia-thermal { 784 polling-delay-passive = <250>; 785 polling-delay = <1000>; 786 787 thermal-sensors = <&tsens1 6>; 788 789 trips { 790 multimedia_alert0: trip-point0 { 791 temperature = <90000>; 792 hysteresis = <2000>; 793 type = "hot"; 794 }; 795 }; 796 }; 797 }; 798 799 timer { 800 compatible = "arm,armv8-timer"; 801 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 802 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 803 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 804 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 805 }; 806 807 soc: soc@0 { 808 #address-cells = <1>; 809 #size-cells = <1>; 810 ranges = <0 0 0 0xffffffff>; 811 compatible = "simple-bus"; 812 813 gcc: clock-controller@100000 { 814 compatible = "qcom,gcc-msm8998"; 815 #clock-cells = <1>; 816 #reset-cells = <1>; 817 #power-domain-cells = <1>; 818 reg = <0x00100000 0xb0000>; 819 820 clock-names = "xo", "sleep_clk"; 821 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 822 823 /* 824 * The hypervisor typically configures the memory region where these clocks 825 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 826 * these clocks on a device with such configuration (e.g. because they are 827 * enabled but unused during boot-up), the device will most likely decide 828 * to reboot. 829 * In light of that, we are conservative here and we list all such clocks 830 * as protected. The board dts (or a user-supplied dts) can override the 831 * list of protected clocks if it differs from the norm, and it is in fact 832 * desired for the HLOS to manage these clocks 833 */ 834 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 835 <SSC_XO>, 836 <SSC_CNOC_AHBS_CLK>; 837 }; 838 839 rpm_msg_ram: sram@778000 { 840 compatible = "qcom,rpm-msg-ram"; 841 reg = <0x00778000 0x7000>; 842 }; 843 844 qfprom: qfprom@784000 { 845 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 846 reg = <0x00784000 0x621c>; 847 #address-cells = <1>; 848 #size-cells = <1>; 849 850 qusb2_hstx_trim: hstx-trim@23a { 851 reg = <0x23a 0x1>; 852 bits = <0 4>; 853 }; 854 }; 855 856 tsens0: thermal@10ab000 { 857 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 858 reg = <0x010ab000 0x1000>, /* TM */ 859 <0x010aa000 0x1000>; /* SROT */ 860 #qcom,sensors = <14>; 861 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "uplow", "critical"; 864 #thermal-sensor-cells = <1>; 865 }; 866 867 tsens1: thermal@10ae000 { 868 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 869 reg = <0x010ae000 0x1000>, /* TM */ 870 <0x010ad000 0x1000>; /* SROT */ 871 #qcom,sensors = <8>; 872 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 874 interrupt-names = "uplow", "critical"; 875 #thermal-sensor-cells = <1>; 876 }; 877 878 anoc1_smmu: iommu@1680000 { 879 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 880 reg = <0x01680000 0x10000>; 881 #iommu-cells = <1>; 882 883 #global-interrupts = <0>; 884 interrupts = 885 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 886 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 887 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 888 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 889 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 890 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 891 }; 892 893 anoc2_smmu: iommu@16c0000 { 894 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 895 reg = <0x016c0000 0x40000>; 896 #iommu-cells = <1>; 897 898 #global-interrupts = <0>; 899 interrupts = 900 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 902 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 903 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 904 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 905 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 906 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 907 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 908 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 909 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 910 }; 911 912 pcie0: pci@1c00000 { 913 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 914 reg = <0x01c00000 0x2000>, 915 <0x1b000000 0xf1d>, 916 <0x1b000f20 0xa8>, 917 <0x1b100000 0x100000>; 918 reg-names = "parf", "dbi", "elbi", "config"; 919 device_type = "pci"; 920 linux,pci-domain = <0>; 921 bus-range = <0x00 0xff>; 922 #address-cells = <3>; 923 #size-cells = <2>; 924 num-lanes = <1>; 925 phys = <&pciephy>; 926 phy-names = "pciephy"; 927 status = "disabled"; 928 929 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 930 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 931 932 #interrupt-cells = <1>; 933 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-names = "msi"; 935 interrupt-map-mask = <0 0 0 0x7>; 936 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 937 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 938 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 939 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 940 941 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 942 <&gcc GCC_PCIE_0_AUX_CLK>, 943 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 944 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 945 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 946 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 947 948 power-domains = <&gcc PCIE_0_GDSC>; 949 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 950 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 951 }; 952 953 pcie_phy: phy@1c06000 { 954 compatible = "qcom,msm8998-qmp-pcie-phy"; 955 reg = <0x01c06000 0x18c>; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 status = "disabled"; 959 ranges; 960 961 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 962 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 963 <&gcc GCC_PCIE_CLKREF_CLK>; 964 clock-names = "aux", "cfg_ahb", "ref"; 965 966 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 967 reset-names = "phy", "common"; 968 969 vdda-phy-supply = <&vreg_l1a_0p875>; 970 vdda-pll-supply = <&vreg_l2a_1p2>; 971 972 pciephy: phy@1c06800 { 973 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 974 #phy-cells = <0>; 975 976 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 977 clock-names = "pipe0"; 978 clock-output-names = "pcie_0_pipe_clk_src"; 979 #clock-cells = <0>; 980 }; 981 }; 982 983 ufshc: ufshc@1da4000 { 984 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 985 reg = <0x01da4000 0x2500>; 986 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 987 phys = <&ufsphy_lanes>; 988 phy-names = "ufsphy"; 989 lanes-per-direction = <2>; 990 power-domains = <&gcc UFS_GDSC>; 991 status = "disabled"; 992 #reset-cells = <1>; 993 994 clock-names = 995 "core_clk", 996 "bus_aggr_clk", 997 "iface_clk", 998 "core_clk_unipro", 999 "ref_clk", 1000 "tx_lane0_sync_clk", 1001 "rx_lane0_sync_clk", 1002 "rx_lane1_sync_clk"; 1003 clocks = 1004 <&gcc GCC_UFS_AXI_CLK>, 1005 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1006 <&gcc GCC_UFS_AHB_CLK>, 1007 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1008 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1009 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1010 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1011 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1012 freq-table-hz = 1013 <50000000 200000000>, 1014 <0 0>, 1015 <0 0>, 1016 <37500000 150000000>, 1017 <0 0>, 1018 <0 0>, 1019 <0 0>, 1020 <0 0>; 1021 1022 resets = <&gcc GCC_UFS_BCR>; 1023 reset-names = "rst"; 1024 }; 1025 1026 ufsphy: phy@1da7000 { 1027 compatible = "qcom,msm8998-qmp-ufs-phy"; 1028 reg = <0x01da7000 0x18c>; 1029 #address-cells = <1>; 1030 #size-cells = <1>; 1031 status = "disabled"; 1032 ranges; 1033 1034 clock-names = 1035 "ref", 1036 "ref_aux"; 1037 clocks = 1038 <&gcc GCC_UFS_CLKREF_CLK>, 1039 <&gcc GCC_UFS_PHY_AUX_CLK>; 1040 1041 reset-names = "ufsphy"; 1042 resets = <&ufshc 0>; 1043 1044 ufsphy_lanes: phy@1da7400 { 1045 reg = <0x01da7400 0x128>, 1046 <0x01da7600 0x1fc>, 1047 <0x01da7c00 0x1dc>, 1048 <0x01da7800 0x128>, 1049 <0x01da7a00 0x1fc>; 1050 #phy-cells = <0>; 1051 }; 1052 }; 1053 1054 tcsr_mutex: hwlock@1f40000 { 1055 compatible = "qcom,tcsr-mutex"; 1056 reg = <0x01f40000 0x20000>; 1057 #hwlock-cells = <1>; 1058 }; 1059 1060 tcsr_regs_1: syscon@1f60000 { 1061 compatible = "qcom,msm8998-tcsr", "syscon"; 1062 reg = <0x01f60000 0x20000>; 1063 }; 1064 1065 tlmm: pinctrl@3400000 { 1066 compatible = "qcom,msm8998-pinctrl"; 1067 reg = <0x03400000 0xc00000>; 1068 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1069 gpio-ranges = <&tlmm 0 0 150>; 1070 gpio-controller; 1071 #gpio-cells = <2>; 1072 interrupt-controller; 1073 #interrupt-cells = <2>; 1074 1075 sdc2_on: sdc2-on-state { 1076 clk-pins { 1077 pins = "sdc2_clk"; 1078 drive-strength = <16>; 1079 bias-disable; 1080 }; 1081 1082 cmd-pins { 1083 pins = "sdc2_cmd"; 1084 drive-strength = <10>; 1085 bias-pull-up; 1086 }; 1087 1088 data-pins { 1089 pins = "sdc2_data"; 1090 drive-strength = <10>; 1091 bias-pull-up; 1092 }; 1093 }; 1094 1095 sdc2_off: sdc2-off-state { 1096 clk-pins { 1097 pins = "sdc2_clk"; 1098 drive-strength = <2>; 1099 bias-disable; 1100 }; 1101 1102 cmd-pins { 1103 pins = "sdc2_cmd"; 1104 drive-strength = <2>; 1105 bias-pull-up; 1106 }; 1107 1108 data-pins { 1109 pins = "sdc2_data"; 1110 drive-strength = <2>; 1111 bias-pull-up; 1112 }; 1113 }; 1114 1115 sdc2_cd: sdc2-cd-state { 1116 pins = "gpio95"; 1117 function = "gpio"; 1118 bias-pull-up; 1119 drive-strength = <2>; 1120 }; 1121 1122 blsp1_uart3_on: blsp1-uart3-on-state { 1123 tx-pins { 1124 pins = "gpio45"; 1125 function = "blsp_uart3_a"; 1126 drive-strength = <2>; 1127 bias-disable; 1128 }; 1129 1130 rx-pins { 1131 pins = "gpio46"; 1132 function = "blsp_uart3_a"; 1133 drive-strength = <2>; 1134 bias-disable; 1135 }; 1136 1137 cts-pins { 1138 pins = "gpio47"; 1139 function = "blsp_uart3_a"; 1140 drive-strength = <2>; 1141 bias-disable; 1142 }; 1143 1144 rfr-pins { 1145 pins = "gpio48"; 1146 function = "blsp_uart3_a"; 1147 drive-strength = <2>; 1148 bias-disable; 1149 }; 1150 }; 1151 1152 blsp1_i2c1_default: blsp1-i2c1-default-state { 1153 pins = "gpio2", "gpio3"; 1154 function = "blsp_i2c1"; 1155 drive-strength = <2>; 1156 bias-disable; 1157 }; 1158 1159 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1160 pins = "gpio2", "gpio3"; 1161 function = "blsp_i2c1"; 1162 drive-strength = <2>; 1163 bias-pull-up; 1164 }; 1165 1166 blsp1_i2c2_default: blsp1-i2c2-default-state { 1167 pins = "gpio32", "gpio33"; 1168 function = "blsp_i2c2"; 1169 drive-strength = <2>; 1170 bias-disable; 1171 }; 1172 1173 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1174 pins = "gpio32", "gpio33"; 1175 function = "blsp_i2c2"; 1176 drive-strength = <2>; 1177 bias-pull-up; 1178 }; 1179 1180 blsp1_i2c3_default: blsp1-i2c3-default-state { 1181 pins = "gpio47", "gpio48"; 1182 function = "blsp_i2c3"; 1183 drive-strength = <2>; 1184 bias-disable; 1185 }; 1186 1187 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1188 pins = "gpio47", "gpio48"; 1189 function = "blsp_i2c3"; 1190 drive-strength = <2>; 1191 bias-pull-up; 1192 }; 1193 1194 blsp1_i2c4_default: blsp1-i2c4-default-state { 1195 pins = "gpio10", "gpio11"; 1196 function = "blsp_i2c4"; 1197 drive-strength = <2>; 1198 bias-disable; 1199 }; 1200 1201 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1202 pins = "gpio10", "gpio11"; 1203 function = "blsp_i2c4"; 1204 drive-strength = <2>; 1205 bias-pull-up; 1206 }; 1207 1208 blsp1_i2c5_default: blsp1-i2c5-default-state { 1209 pins = "gpio87", "gpio88"; 1210 function = "blsp_i2c5"; 1211 drive-strength = <2>; 1212 bias-disable; 1213 }; 1214 1215 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1216 pins = "gpio87", "gpio88"; 1217 function = "blsp_i2c5"; 1218 drive-strength = <2>; 1219 bias-pull-up; 1220 }; 1221 1222 blsp1_i2c6_default: blsp1-i2c6-default-state { 1223 pins = "gpio43", "gpio44"; 1224 function = "blsp_i2c6"; 1225 drive-strength = <2>; 1226 bias-disable; 1227 }; 1228 1229 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1230 pins = "gpio43", "gpio44"; 1231 function = "blsp_i2c6"; 1232 drive-strength = <2>; 1233 bias-pull-up; 1234 }; 1235 1236 blsp1_spi_b_default: blsp1-spi-b-default-state { 1237 pins = "gpio23", "gpio28"; 1238 function = "blsp1_spi_b"; 1239 drive-strength = <6>; 1240 bias-disable; 1241 }; 1242 1243 blsp1_spi1_default: blsp1-spi1-default-state { 1244 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1245 function = "blsp_spi1"; 1246 drive-strength = <6>; 1247 bias-disable; 1248 }; 1249 1250 blsp1_spi2_default: blsp1-spi2-default-state { 1251 pins = "gpio31", "gpio34", "gpio32", "gpio33"; 1252 function = "blsp_spi2"; 1253 drive-strength = <6>; 1254 bias-disable; 1255 }; 1256 1257 blsp1_spi3_default: blsp1-spi3-default-state { 1258 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 1259 function = "blsp_spi2"; 1260 drive-strength = <6>; 1261 bias-disable; 1262 }; 1263 1264 blsp1_spi4_default: blsp1-spi4-default-state { 1265 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1266 function = "blsp_spi4"; 1267 drive-strength = <6>; 1268 bias-disable; 1269 }; 1270 1271 blsp1_spi5_default: blsp1-spi5-default-state { 1272 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1273 function = "blsp_spi5"; 1274 drive-strength = <6>; 1275 bias-disable; 1276 }; 1277 1278 blsp1_spi6_default: blsp1-spi6-default-state { 1279 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1280 function = "blsp_spi6"; 1281 drive-strength = <6>; 1282 bias-disable; 1283 }; 1284 1285 1286 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1287 blsp2_i2c1_default: blsp2-i2c1-default-state { 1288 pins = "gpio55", "gpio56"; 1289 function = "blsp_i2c7"; 1290 drive-strength = <2>; 1291 bias-disable; 1292 }; 1293 1294 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1295 pins = "gpio55", "gpio56"; 1296 function = "blsp_i2c7"; 1297 drive-strength = <2>; 1298 bias-pull-up; 1299 }; 1300 1301 blsp2_i2c2_default: blsp2-i2c2-default-state { 1302 pins = "gpio6", "gpio7"; 1303 function = "blsp_i2c8"; 1304 drive-strength = <2>; 1305 bias-disable; 1306 }; 1307 1308 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1309 pins = "gpio6", "gpio7"; 1310 function = "blsp_i2c8"; 1311 drive-strength = <2>; 1312 bias-pull-up; 1313 }; 1314 1315 blsp2_i2c3_default: blsp2-i2c3-default-state { 1316 pins = "gpio51", "gpio52"; 1317 function = "blsp_i2c9"; 1318 drive-strength = <2>; 1319 bias-disable; 1320 }; 1321 1322 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1323 pins = "gpio51", "gpio52"; 1324 function = "blsp_i2c9"; 1325 drive-strength = <2>; 1326 bias-pull-up; 1327 }; 1328 1329 blsp2_i2c4_default: blsp2-i2c4-default-state { 1330 pins = "gpio67", "gpio68"; 1331 function = "blsp_i2c10"; 1332 drive-strength = <2>; 1333 bias-disable; 1334 }; 1335 1336 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1337 pins = "gpio67", "gpio68"; 1338 function = "blsp_i2c10"; 1339 drive-strength = <2>; 1340 bias-pull-up; 1341 }; 1342 1343 blsp2_i2c5_default: blsp2-i2c5-default-state { 1344 pins = "gpio60", "gpio61"; 1345 function = "blsp_i2c11"; 1346 drive-strength = <2>; 1347 bias-disable; 1348 }; 1349 1350 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1351 pins = "gpio60", "gpio61"; 1352 function = "blsp_i2c11"; 1353 drive-strength = <2>; 1354 bias-pull-up; 1355 }; 1356 1357 blsp2_i2c6_default: blsp2-i2c6-default-state { 1358 pins = "gpio83", "gpio84"; 1359 function = "blsp_i2c12"; 1360 drive-strength = <2>; 1361 bias-disable; 1362 }; 1363 1364 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1365 pins = "gpio83", "gpio84"; 1366 function = "blsp_i2c12"; 1367 drive-strength = <2>; 1368 bias-pull-up; 1369 }; 1370 1371 blsp2_spi1_default: blsp2-spi1-default-state { 1372 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1373 function = "blsp_spi7"; 1374 drive-strength = <6>; 1375 bias-disable; 1376 }; 1377 1378 blsp2_spi2_default: blsp2-spi2-default-state { 1379 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1380 function = "blsp_spi8"; 1381 drive-strength = <6>; 1382 bias-disable; 1383 }; 1384 1385 blsp2_spi3_default: blsp2-spi3-default-state { 1386 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1387 function = "blsp_spi9"; 1388 drive-strength = <6>; 1389 bias-disable; 1390 }; 1391 1392 blsp2_spi4_default: blsp2-spi4-default-state { 1393 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 1394 function = "blsp_spi10"; 1395 drive-strength = <6>; 1396 bias-disable; 1397 }; 1398 1399 blsp2_spi5_default: blsp2-spi5-default-state { 1400 pins = "gpio58", "gpio59", "gpio60", "gpio61"; 1401 function = "blsp_spi11"; 1402 drive-strength = <6>; 1403 bias-disable; 1404 }; 1405 1406 blsp2_spi6_default: blsp2-spi6-default-state { 1407 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 1408 function = "blsp_spi12"; 1409 drive-strength = <6>; 1410 bias-disable; 1411 }; 1412 }; 1413 1414 remoteproc_mss: remoteproc@4080000 { 1415 compatible = "qcom,msm8998-mss-pil"; 1416 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1417 reg-names = "qdsp6", "rmb"; 1418 1419 interrupts-extended = 1420 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1421 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1422 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1423 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1424 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1425 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1426 interrupt-names = "wdog", "fatal", "ready", 1427 "handover", "stop-ack", 1428 "shutdown-ack"; 1429 1430 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1431 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1432 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1433 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1434 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1435 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1436 <&rpmcc RPM_SMD_QDSS_CLK>, 1437 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1438 clock-names = "iface", "bus", "mem", "gpll0_mss", 1439 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1440 1441 qcom,smem-states = <&modem_smp2p_out 0>; 1442 qcom,smem-state-names = "stop"; 1443 1444 resets = <&gcc GCC_MSS_RESTART>; 1445 reset-names = "mss_restart"; 1446 1447 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1448 1449 power-domains = <&rpmpd MSM8998_VDDCX>, 1450 <&rpmpd MSM8998_VDDMX>; 1451 power-domain-names = "cx", "mx"; 1452 1453 status = "disabled"; 1454 1455 mba { 1456 memory-region = <&mba_mem>; 1457 }; 1458 1459 mpss { 1460 memory-region = <&mpss_mem>; 1461 }; 1462 1463 metadata { 1464 memory-region = <&mdata_mem>; 1465 }; 1466 1467 glink-edge { 1468 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1469 label = "modem"; 1470 qcom,remote-pid = <1>; 1471 mboxes = <&apcs_glb 15>; 1472 }; 1473 }; 1474 1475 adreno_gpu: gpu@5000000 { 1476 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1477 reg = <0x05000000 0x40000>; 1478 reg-names = "kgsl_3d0_reg_memory"; 1479 1480 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1481 <&gpucc RBBMTIMER_CLK>, 1482 <&gcc GCC_BIMC_GFX_CLK>, 1483 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1484 <&gpucc RBCPR_CLK>, 1485 <&gpucc GFX3D_CLK>; 1486 clock-names = "iface", 1487 "rbbmtimer", 1488 "mem", 1489 "mem_iface", 1490 "rbcpr", 1491 "core"; 1492 1493 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1494 iommus = <&adreno_smmu 0>; 1495 operating-points-v2 = <&gpu_opp_table>; 1496 power-domains = <&rpmpd MSM8998_VDDMX>; 1497 status = "disabled"; 1498 1499 gpu_opp_table: opp-table { 1500 compatible = "operating-points-v2"; 1501 opp-710000097 { 1502 opp-hz = /bits/ 64 <710000097>; 1503 opp-level = <RPM_SMD_LEVEL_TURBO>; 1504 opp-supported-hw = <0xff>; 1505 }; 1506 1507 opp-670000048 { 1508 opp-hz = /bits/ 64 <670000048>; 1509 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1510 opp-supported-hw = <0xff>; 1511 }; 1512 1513 opp-596000097 { 1514 opp-hz = /bits/ 64 <596000097>; 1515 opp-level = <RPM_SMD_LEVEL_NOM>; 1516 opp-supported-hw = <0xff>; 1517 }; 1518 1519 opp-515000097 { 1520 opp-hz = /bits/ 64 <515000097>; 1521 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1522 opp-supported-hw = <0xff>; 1523 }; 1524 1525 opp-414000000 { 1526 opp-hz = /bits/ 64 <414000000>; 1527 opp-level = <RPM_SMD_LEVEL_SVS>; 1528 opp-supported-hw = <0xff>; 1529 }; 1530 1531 opp-342000000 { 1532 opp-hz = /bits/ 64 <342000000>; 1533 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1534 opp-supported-hw = <0xff>; 1535 }; 1536 1537 opp-257000000 { 1538 opp-hz = /bits/ 64 <257000000>; 1539 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1540 opp-supported-hw = <0xff>; 1541 }; 1542 }; 1543 }; 1544 1545 adreno_smmu: iommu@5040000 { 1546 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1547 reg = <0x05040000 0x10000>; 1548 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1549 <&gcc GCC_BIMC_GFX_CLK>, 1550 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1551 clock-names = "iface", "mem", "mem_iface"; 1552 1553 #global-interrupts = <0>; 1554 #iommu-cells = <1>; 1555 interrupts = 1556 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1559 /* 1560 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1561 * GPU-CX for SMMU but we need both of them up for Adreno. 1562 * Contemporarily, we also need to manage the VDDMX rpmpd 1563 * domain in the Adreno driver. 1564 * Enable GPU CX/GX GDSCs here so that we can manage the 1565 * SoC VDDMX RPM Power Domain in the Adreno driver. 1566 */ 1567 power-domains = <&gpucc GPU_GX_GDSC>; 1568 status = "disabled"; 1569 }; 1570 1571 gpucc: clock-controller@5065000 { 1572 compatible = "qcom,msm8998-gpucc"; 1573 #clock-cells = <1>; 1574 #reset-cells = <1>; 1575 #power-domain-cells = <1>; 1576 reg = <0x05065000 0x9000>; 1577 1578 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1579 <&gcc GPLL0_OUT_MAIN>; 1580 clock-names = "xo", 1581 "gpll0"; 1582 }; 1583 1584 remoteproc_slpi: remoteproc@5800000 { 1585 compatible = "qcom,msm8998-slpi-pas"; 1586 reg = <0x05800000 0x4040>; 1587 1588 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1589 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1590 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1591 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1592 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1593 interrupt-names = "wdog", "fatal", "ready", 1594 "handover", "stop-ack"; 1595 1596 px-supply = <&vreg_lvs2a_1p8>; 1597 1598 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1599 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1600 clock-names = "xo", "aggre2"; 1601 1602 memory-region = <&slpi_mem>; 1603 1604 qcom,smem-states = <&slpi_smp2p_out 0>; 1605 qcom,smem-state-names = "stop"; 1606 1607 power-domains = <&rpmpd MSM8998_SSCCX>; 1608 power-domain-names = "ssc_cx"; 1609 1610 status = "disabled"; 1611 1612 glink-edge { 1613 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1614 label = "dsps"; 1615 qcom,remote-pid = <3>; 1616 mboxes = <&apcs_glb 27>; 1617 }; 1618 }; 1619 1620 stm: stm@6002000 { 1621 compatible = "arm,coresight-stm", "arm,primecell"; 1622 reg = <0x06002000 0x1000>, 1623 <0x16280000 0x180000>; 1624 reg-names = "stm-base", "stm-stimulus-base"; 1625 status = "disabled"; 1626 1627 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1628 clock-names = "apb_pclk", "atclk"; 1629 1630 out-ports { 1631 port { 1632 stm_out: endpoint { 1633 remote-endpoint = <&funnel0_in7>; 1634 }; 1635 }; 1636 }; 1637 }; 1638 1639 funnel1: funnel@6041000 { 1640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1641 reg = <0x06041000 0x1000>; 1642 status = "disabled"; 1643 1644 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1645 clock-names = "apb_pclk", "atclk"; 1646 1647 out-ports { 1648 port { 1649 funnel0_out: endpoint { 1650 remote-endpoint = 1651 <&merge_funnel_in0>; 1652 }; 1653 }; 1654 }; 1655 1656 in-ports { 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 1660 port@7 { 1661 reg = <7>; 1662 funnel0_in7: endpoint { 1663 remote-endpoint = <&stm_out>; 1664 }; 1665 }; 1666 }; 1667 }; 1668 1669 funnel2: funnel@6042000 { 1670 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1671 reg = <0x06042000 0x1000>; 1672 status = "disabled"; 1673 1674 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1675 clock-names = "apb_pclk", "atclk"; 1676 1677 out-ports { 1678 port { 1679 funnel1_out: endpoint { 1680 remote-endpoint = 1681 <&merge_funnel_in1>; 1682 }; 1683 }; 1684 }; 1685 1686 in-ports { 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 1690 port@6 { 1691 reg = <6>; 1692 funnel1_in6: endpoint { 1693 remote-endpoint = 1694 <&apss_merge_funnel_out>; 1695 }; 1696 }; 1697 }; 1698 }; 1699 1700 funnel3: funnel@6045000 { 1701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1702 reg = <0x06045000 0x1000>; 1703 status = "disabled"; 1704 1705 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1706 clock-names = "apb_pclk", "atclk"; 1707 1708 out-ports { 1709 port { 1710 merge_funnel_out: endpoint { 1711 remote-endpoint = 1712 <&etf_in>; 1713 }; 1714 }; 1715 }; 1716 1717 in-ports { 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 1721 port@0 { 1722 reg = <0>; 1723 merge_funnel_in0: endpoint { 1724 remote-endpoint = 1725 <&funnel0_out>; 1726 }; 1727 }; 1728 1729 port@1 { 1730 reg = <1>; 1731 merge_funnel_in1: endpoint { 1732 remote-endpoint = 1733 <&funnel1_out>; 1734 }; 1735 }; 1736 }; 1737 }; 1738 1739 replicator1: replicator@6046000 { 1740 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1741 reg = <0x06046000 0x1000>; 1742 status = "disabled"; 1743 1744 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1745 clock-names = "apb_pclk", "atclk"; 1746 1747 out-ports { 1748 port { 1749 replicator_out: endpoint { 1750 remote-endpoint = <&etr_in>; 1751 }; 1752 }; 1753 }; 1754 1755 in-ports { 1756 port { 1757 replicator_in: endpoint { 1758 remote-endpoint = <&etf_out>; 1759 }; 1760 }; 1761 }; 1762 }; 1763 1764 etf: etf@6047000 { 1765 compatible = "arm,coresight-tmc", "arm,primecell"; 1766 reg = <0x06047000 0x1000>; 1767 status = "disabled"; 1768 1769 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1770 clock-names = "apb_pclk", "atclk"; 1771 1772 out-ports { 1773 port { 1774 etf_out: endpoint { 1775 remote-endpoint = 1776 <&replicator_in>; 1777 }; 1778 }; 1779 }; 1780 1781 in-ports { 1782 port { 1783 etf_in: endpoint { 1784 remote-endpoint = 1785 <&merge_funnel_out>; 1786 }; 1787 }; 1788 }; 1789 }; 1790 1791 etr: etr@6048000 { 1792 compatible = "arm,coresight-tmc", "arm,primecell"; 1793 reg = <0x06048000 0x1000>; 1794 status = "disabled"; 1795 1796 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1797 clock-names = "apb_pclk", "atclk"; 1798 arm,scatter-gather; 1799 1800 in-ports { 1801 port { 1802 etr_in: endpoint { 1803 remote-endpoint = 1804 <&replicator_out>; 1805 }; 1806 }; 1807 }; 1808 }; 1809 1810 etm1: etm@7840000 { 1811 compatible = "arm,coresight-etm4x", "arm,primecell"; 1812 reg = <0x07840000 0x1000>; 1813 status = "disabled"; 1814 1815 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1816 clock-names = "apb_pclk", "atclk"; 1817 1818 cpu = <&CPU0>; 1819 1820 out-ports { 1821 port { 1822 etm0_out: endpoint { 1823 remote-endpoint = 1824 <&apss_funnel_in0>; 1825 }; 1826 }; 1827 }; 1828 }; 1829 1830 etm2: etm@7940000 { 1831 compatible = "arm,coresight-etm4x", "arm,primecell"; 1832 reg = <0x07940000 0x1000>; 1833 status = "disabled"; 1834 1835 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1836 clock-names = "apb_pclk", "atclk"; 1837 1838 cpu = <&CPU1>; 1839 1840 out-ports { 1841 port { 1842 etm1_out: endpoint { 1843 remote-endpoint = 1844 <&apss_funnel_in1>; 1845 }; 1846 }; 1847 }; 1848 }; 1849 1850 etm3: etm@7a40000 { 1851 compatible = "arm,coresight-etm4x", "arm,primecell"; 1852 reg = <0x07a40000 0x1000>; 1853 status = "disabled"; 1854 1855 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1856 clock-names = "apb_pclk", "atclk"; 1857 1858 cpu = <&CPU2>; 1859 1860 out-ports { 1861 port { 1862 etm2_out: endpoint { 1863 remote-endpoint = 1864 <&apss_funnel_in2>; 1865 }; 1866 }; 1867 }; 1868 }; 1869 1870 etm4: etm@7b40000 { 1871 compatible = "arm,coresight-etm4x", "arm,primecell"; 1872 reg = <0x07b40000 0x1000>; 1873 status = "disabled"; 1874 1875 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1876 clock-names = "apb_pclk", "atclk"; 1877 1878 cpu = <&CPU3>; 1879 1880 out-ports { 1881 port { 1882 etm3_out: endpoint { 1883 remote-endpoint = 1884 <&apss_funnel_in3>; 1885 }; 1886 }; 1887 }; 1888 }; 1889 1890 funnel4: funnel@7b60000 { /* APSS Funnel */ 1891 compatible = "arm,coresight-etm4x", "arm,primecell"; 1892 reg = <0x07b60000 0x1000>; 1893 status = "disabled"; 1894 1895 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1896 clock-names = "apb_pclk", "atclk"; 1897 1898 out-ports { 1899 port { 1900 apss_funnel_out: endpoint { 1901 remote-endpoint = 1902 <&apss_merge_funnel_in>; 1903 }; 1904 }; 1905 }; 1906 1907 in-ports { 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 1911 port@0 { 1912 reg = <0>; 1913 apss_funnel_in0: endpoint { 1914 remote-endpoint = 1915 <&etm0_out>; 1916 }; 1917 }; 1918 1919 port@1 { 1920 reg = <1>; 1921 apss_funnel_in1: endpoint { 1922 remote-endpoint = 1923 <&etm1_out>; 1924 }; 1925 }; 1926 1927 port@2 { 1928 reg = <2>; 1929 apss_funnel_in2: endpoint { 1930 remote-endpoint = 1931 <&etm2_out>; 1932 }; 1933 }; 1934 1935 port@3 { 1936 reg = <3>; 1937 apss_funnel_in3: endpoint { 1938 remote-endpoint = 1939 <&etm3_out>; 1940 }; 1941 }; 1942 1943 port@4 { 1944 reg = <4>; 1945 apss_funnel_in4: endpoint { 1946 remote-endpoint = 1947 <&etm4_out>; 1948 }; 1949 }; 1950 1951 port@5 { 1952 reg = <5>; 1953 apss_funnel_in5: endpoint { 1954 remote-endpoint = 1955 <&etm5_out>; 1956 }; 1957 }; 1958 1959 port@6 { 1960 reg = <6>; 1961 apss_funnel_in6: endpoint { 1962 remote-endpoint = 1963 <&etm6_out>; 1964 }; 1965 }; 1966 1967 port@7 { 1968 reg = <7>; 1969 apss_funnel_in7: endpoint { 1970 remote-endpoint = 1971 <&etm7_out>; 1972 }; 1973 }; 1974 }; 1975 }; 1976 1977 funnel5: funnel@7b70000 { 1978 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1979 reg = <0x07b70000 0x1000>; 1980 status = "disabled"; 1981 1982 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1983 clock-names = "apb_pclk", "atclk"; 1984 1985 out-ports { 1986 port { 1987 apss_merge_funnel_out: endpoint { 1988 remote-endpoint = 1989 <&funnel1_in6>; 1990 }; 1991 }; 1992 }; 1993 1994 in-ports { 1995 port { 1996 apss_merge_funnel_in: endpoint { 1997 remote-endpoint = 1998 <&apss_funnel_out>; 1999 }; 2000 }; 2001 }; 2002 }; 2003 2004 etm5: etm@7c40000 { 2005 compatible = "arm,coresight-etm4x", "arm,primecell"; 2006 reg = <0x07c40000 0x1000>; 2007 status = "disabled"; 2008 2009 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2010 clock-names = "apb_pclk", "atclk"; 2011 2012 cpu = <&CPU4>; 2013 2014 port { 2015 etm4_out: endpoint { 2016 remote-endpoint = <&apss_funnel_in4>; 2017 }; 2018 }; 2019 }; 2020 2021 etm6: etm@7d40000 { 2022 compatible = "arm,coresight-etm4x", "arm,primecell"; 2023 reg = <0x07d40000 0x1000>; 2024 status = "disabled"; 2025 2026 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2027 clock-names = "apb_pclk", "atclk"; 2028 2029 cpu = <&CPU5>; 2030 2031 port { 2032 etm5_out: endpoint { 2033 remote-endpoint = <&apss_funnel_in5>; 2034 }; 2035 }; 2036 }; 2037 2038 etm7: etm@7e40000 { 2039 compatible = "arm,coresight-etm4x", "arm,primecell"; 2040 reg = <0x07e40000 0x1000>; 2041 status = "disabled"; 2042 2043 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2044 clock-names = "apb_pclk", "atclk"; 2045 2046 cpu = <&CPU6>; 2047 2048 port { 2049 etm6_out: endpoint { 2050 remote-endpoint = <&apss_funnel_in6>; 2051 }; 2052 }; 2053 }; 2054 2055 etm8: etm@7f40000 { 2056 compatible = "arm,coresight-etm4x", "arm,primecell"; 2057 reg = <0x07f40000 0x1000>; 2058 status = "disabled"; 2059 2060 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2061 clock-names = "apb_pclk", "atclk"; 2062 2063 cpu = <&CPU7>; 2064 2065 port { 2066 etm7_out: endpoint { 2067 remote-endpoint = <&apss_funnel_in7>; 2068 }; 2069 }; 2070 }; 2071 2072 sram@290000 { 2073 compatible = "qcom,rpm-stats"; 2074 reg = <0x00290000 0x10000>; 2075 }; 2076 2077 spmi_bus: spmi@800f000 { 2078 compatible = "qcom,spmi-pmic-arb"; 2079 reg = <0x0800f000 0x1000>, 2080 <0x08400000 0x1000000>, 2081 <0x09400000 0x1000000>, 2082 <0x0a400000 0x220000>, 2083 <0x0800a000 0x3000>; 2084 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2085 interrupt-names = "periph_irq"; 2086 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2087 qcom,ee = <0>; 2088 qcom,channel = <0>; 2089 #address-cells = <2>; 2090 #size-cells = <0>; 2091 interrupt-controller; 2092 #interrupt-cells = <4>; 2093 }; 2094 2095 usb3: usb@a8f8800 { 2096 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2097 reg = <0x0a8f8800 0x400>; 2098 status = "disabled"; 2099 #address-cells = <1>; 2100 #size-cells = <1>; 2101 ranges; 2102 2103 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2104 <&gcc GCC_USB30_MASTER_CLK>, 2105 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2106 <&gcc GCC_USB30_SLEEP_CLK>, 2107 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2108 clock-names = "cfg_noc", 2109 "core", 2110 "iface", 2111 "sleep", 2112 "mock_utmi"; 2113 2114 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2115 <&gcc GCC_USB30_MASTER_CLK>; 2116 assigned-clock-rates = <19200000>, <120000000>; 2117 2118 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2120 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2121 2122 power-domains = <&gcc USB_30_GDSC>; 2123 2124 resets = <&gcc GCC_USB_30_BCR>; 2125 2126 usb3_dwc3: usb@a800000 { 2127 compatible = "snps,dwc3"; 2128 reg = <0x0a800000 0xcd00>; 2129 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2130 snps,dis_u2_susphy_quirk; 2131 snps,dis_enblslpm_quirk; 2132 phys = <&qusb2phy>, <&usb1_ssphy>; 2133 phy-names = "usb2-phy", "usb3-phy"; 2134 snps,has-lpm-erratum; 2135 snps,hird-threshold = /bits/ 8 <0x10>; 2136 }; 2137 }; 2138 2139 usb3phy: phy@c010000 { 2140 compatible = "qcom,msm8998-qmp-usb3-phy"; 2141 reg = <0x0c010000 0x18c>; 2142 status = "disabled"; 2143 #address-cells = <1>; 2144 #size-cells = <1>; 2145 ranges; 2146 2147 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2148 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2149 <&gcc GCC_USB3_CLKREF_CLK>; 2150 clock-names = "aux", "cfg_ahb", "ref"; 2151 2152 resets = <&gcc GCC_USB3_PHY_BCR>, 2153 <&gcc GCC_USB3PHY_PHY_BCR>; 2154 reset-names = "phy", "common"; 2155 2156 usb1_ssphy: phy@c010200 { 2157 reg = <0xc010200 0x128>, 2158 <0xc010400 0x200>, 2159 <0xc010c00 0x20c>, 2160 <0xc010600 0x128>, 2161 <0xc010800 0x200>; 2162 #phy-cells = <0>; 2163 #clock-cells = <0>; 2164 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2165 clock-names = "pipe0"; 2166 clock-output-names = "usb3_phy_pipe_clk_src"; 2167 }; 2168 }; 2169 2170 qusb2phy: phy@c012000 { 2171 compatible = "qcom,msm8998-qusb2-phy"; 2172 reg = <0x0c012000 0x2a8>; 2173 status = "disabled"; 2174 #phy-cells = <0>; 2175 2176 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2177 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2178 clock-names = "cfg_ahb", "ref"; 2179 2180 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2181 2182 nvmem-cells = <&qusb2_hstx_trim>; 2183 }; 2184 2185 sdhc2: mmc@c0a4900 { 2186 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2187 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2188 reg-names = "hc", "core"; 2189 2190 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2192 interrupt-names = "hc_irq", "pwr_irq"; 2193 2194 clock-names = "iface", "core", "xo"; 2195 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2196 <&gcc GCC_SDCC2_APPS_CLK>, 2197 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2198 bus-width = <4>; 2199 status = "disabled"; 2200 }; 2201 2202 blsp1_dma: dma-controller@c144000 { 2203 compatible = "qcom,bam-v1.7.0"; 2204 reg = <0x0c144000 0x25000>; 2205 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2206 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2207 clock-names = "bam_clk"; 2208 #dma-cells = <1>; 2209 qcom,ee = <0>; 2210 qcom,controlled-remotely; 2211 num-channels = <18>; 2212 qcom,num-ees = <4>; 2213 }; 2214 2215 blsp1_uart3: serial@c171000 { 2216 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2217 reg = <0x0c171000 0x1000>; 2218 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2219 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2220 <&gcc GCC_BLSP1_AHB_CLK>; 2221 clock-names = "core", "iface"; 2222 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2223 dma-names = "tx", "rx"; 2224 pinctrl-names = "default"; 2225 pinctrl-0 = <&blsp1_uart3_on>; 2226 status = "disabled"; 2227 }; 2228 2229 blsp1_i2c1: i2c@c175000 { 2230 compatible = "qcom,i2c-qup-v2.2.1"; 2231 reg = <0x0c175000 0x600>; 2232 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2233 2234 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2235 <&gcc GCC_BLSP1_AHB_CLK>; 2236 clock-names = "core", "iface"; 2237 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2238 dma-names = "tx", "rx"; 2239 pinctrl-names = "default", "sleep"; 2240 pinctrl-0 = <&blsp1_i2c1_default>; 2241 pinctrl-1 = <&blsp1_i2c1_sleep>; 2242 clock-frequency = <400000>; 2243 2244 status = "disabled"; 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 }; 2248 2249 blsp1_i2c2: i2c@c176000 { 2250 compatible = "qcom,i2c-qup-v2.2.1"; 2251 reg = <0x0c176000 0x600>; 2252 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2253 2254 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2255 <&gcc GCC_BLSP1_AHB_CLK>; 2256 clock-names = "core", "iface"; 2257 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2258 dma-names = "tx", "rx"; 2259 pinctrl-names = "default", "sleep"; 2260 pinctrl-0 = <&blsp1_i2c2_default>; 2261 pinctrl-1 = <&blsp1_i2c2_sleep>; 2262 clock-frequency = <400000>; 2263 2264 status = "disabled"; 2265 #address-cells = <1>; 2266 #size-cells = <0>; 2267 }; 2268 2269 blsp1_i2c3: i2c@c177000 { 2270 compatible = "qcom,i2c-qup-v2.2.1"; 2271 reg = <0x0c177000 0x600>; 2272 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2273 2274 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2275 <&gcc GCC_BLSP1_AHB_CLK>; 2276 clock-names = "core", "iface"; 2277 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2278 dma-names = "tx", "rx"; 2279 pinctrl-names = "default", "sleep"; 2280 pinctrl-0 = <&blsp1_i2c3_default>; 2281 pinctrl-1 = <&blsp1_i2c3_sleep>; 2282 clock-frequency = <400000>; 2283 2284 status = "disabled"; 2285 #address-cells = <1>; 2286 #size-cells = <0>; 2287 }; 2288 2289 blsp1_i2c4: i2c@c178000 { 2290 compatible = "qcom,i2c-qup-v2.2.1"; 2291 reg = <0x0c178000 0x600>; 2292 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2293 2294 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2295 <&gcc GCC_BLSP1_AHB_CLK>; 2296 clock-names = "core", "iface"; 2297 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2298 dma-names = "tx", "rx"; 2299 pinctrl-names = "default", "sleep"; 2300 pinctrl-0 = <&blsp1_i2c4_default>; 2301 pinctrl-1 = <&blsp1_i2c4_sleep>; 2302 clock-frequency = <400000>; 2303 2304 status = "disabled"; 2305 #address-cells = <1>; 2306 #size-cells = <0>; 2307 }; 2308 2309 blsp1_i2c5: i2c@c179000 { 2310 compatible = "qcom,i2c-qup-v2.2.1"; 2311 reg = <0x0c179000 0x600>; 2312 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2313 2314 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2315 <&gcc GCC_BLSP1_AHB_CLK>; 2316 clock-names = "core", "iface"; 2317 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2318 dma-names = "tx", "rx"; 2319 pinctrl-names = "default", "sleep"; 2320 pinctrl-0 = <&blsp1_i2c5_default>; 2321 pinctrl-1 = <&blsp1_i2c5_sleep>; 2322 clock-frequency = <400000>; 2323 2324 status = "disabled"; 2325 #address-cells = <1>; 2326 #size-cells = <0>; 2327 }; 2328 2329 blsp1_i2c6: i2c@c17a000 { 2330 compatible = "qcom,i2c-qup-v2.2.1"; 2331 reg = <0x0c17a000 0x600>; 2332 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2333 2334 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2335 <&gcc GCC_BLSP1_AHB_CLK>; 2336 clock-names = "core", "iface"; 2337 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2338 dma-names = "tx", "rx"; 2339 pinctrl-names = "default", "sleep"; 2340 pinctrl-0 = <&blsp1_i2c6_default>; 2341 pinctrl-1 = <&blsp1_i2c6_sleep>; 2342 clock-frequency = <400000>; 2343 2344 status = "disabled"; 2345 #address-cells = <1>; 2346 #size-cells = <0>; 2347 }; 2348 2349 blsp1_spi1: spi@c175000 { 2350 compatible = "qcom,spi-qup-v2.2.1"; 2351 reg = <0x0c175000 0x600>; 2352 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2353 2354 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2355 <&gcc GCC_BLSP1_AHB_CLK>; 2356 clock-names = "core", "iface"; 2357 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2358 dma-names = "tx", "rx"; 2359 pinctrl-names = "default"; 2360 pinctrl-0 = <&blsp1_spi1_default>; 2361 2362 status = "disabled"; 2363 #address-cells = <1>; 2364 #size-cells = <0>; 2365 }; 2366 2367 blsp1_spi2: spi@c176000 { 2368 compatible = "qcom,spi-qup-v2.2.1"; 2369 reg = <0x0c176000 0x600>; 2370 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2371 2372 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2373 <&gcc GCC_BLSP1_AHB_CLK>; 2374 clock-names = "core", "iface"; 2375 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2376 dma-names = "tx", "rx"; 2377 pinctrl-names = "default"; 2378 pinctrl-0 = <&blsp1_spi2_default>; 2379 2380 status = "disabled"; 2381 #address-cells = <1>; 2382 #size-cells = <0>; 2383 }; 2384 2385 blsp1_spi3: spi@c177000 { 2386 compatible = "qcom,spi-qup-v2.2.1"; 2387 reg = <0x0c177000 0x600>; 2388 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2389 2390 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2391 <&gcc GCC_BLSP1_AHB_CLK>; 2392 clock-names = "core", "iface"; 2393 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2394 dma-names = "tx", "rx"; 2395 pinctrl-names = "default"; 2396 pinctrl-0 = <&blsp1_spi3_default>; 2397 2398 status = "disabled"; 2399 #address-cells = <1>; 2400 #size-cells = <0>; 2401 }; 2402 2403 blsp1_spi4: spi@c178000 { 2404 compatible = "qcom,spi-qup-v2.2.1"; 2405 reg = <0x0c178000 0x600>; 2406 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2407 2408 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2409 <&gcc GCC_BLSP1_AHB_CLK>; 2410 clock-names = "core", "iface"; 2411 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2412 dma-names = "tx", "rx"; 2413 pinctrl-names = "default"; 2414 pinctrl-0 = <&blsp1_spi4_default>; 2415 2416 status = "disabled"; 2417 #address-cells = <1>; 2418 #size-cells = <0>; 2419 }; 2420 2421 blsp1_spi5: spi@c179000 { 2422 compatible = "qcom,spi-qup-v2.2.1"; 2423 reg = <0x0c179000 0x600>; 2424 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2425 2426 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2427 <&gcc GCC_BLSP1_AHB_CLK>; 2428 clock-names = "core", "iface"; 2429 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2430 dma-names = "tx", "rx"; 2431 pinctrl-names = "default"; 2432 pinctrl-0 = <&blsp1_spi5_default>; 2433 2434 status = "disabled"; 2435 #address-cells = <1>; 2436 #size-cells = <0>; 2437 }; 2438 2439 blsp1_spi6: spi@c17a000 { 2440 compatible = "qcom,spi-qup-v2.2.1"; 2441 reg = <0x0c17a000 0x600>; 2442 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2443 2444 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2445 <&gcc GCC_BLSP1_AHB_CLK>; 2446 clock-names = "core", "iface"; 2447 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2448 dma-names = "tx", "rx"; 2449 pinctrl-names = "default"; 2450 pinctrl-0 = <&blsp1_spi6_default>; 2451 2452 status = "disabled"; 2453 #address-cells = <1>; 2454 #size-cells = <0>; 2455 }; 2456 2457 blsp2_dma: dma-controller@c184000 { 2458 compatible = "qcom,bam-v1.7.0"; 2459 reg = <0x0c184000 0x25000>; 2460 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2461 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2462 clock-names = "bam_clk"; 2463 #dma-cells = <1>; 2464 qcom,ee = <0>; 2465 qcom,controlled-remotely; 2466 num-channels = <18>; 2467 qcom,num-ees = <4>; 2468 }; 2469 2470 blsp2_uart1: serial@c1b0000 { 2471 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2472 reg = <0x0c1b0000 0x1000>; 2473 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2474 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2475 <&gcc GCC_BLSP2_AHB_CLK>; 2476 clock-names = "core", "iface"; 2477 status = "disabled"; 2478 }; 2479 2480 blsp2_i2c1: i2c@c1b5000 { 2481 compatible = "qcom,i2c-qup-v2.2.1"; 2482 reg = <0x0c1b5000 0x600>; 2483 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2484 2485 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2486 <&gcc GCC_BLSP2_AHB_CLK>; 2487 clock-names = "core", "iface"; 2488 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2489 dma-names = "tx", "rx"; 2490 pinctrl-names = "default", "sleep"; 2491 pinctrl-0 = <&blsp2_i2c1_default>; 2492 pinctrl-1 = <&blsp2_i2c1_sleep>; 2493 clock-frequency = <400000>; 2494 2495 status = "disabled"; 2496 #address-cells = <1>; 2497 #size-cells = <0>; 2498 }; 2499 2500 blsp2_i2c2: i2c@c1b6000 { 2501 compatible = "qcom,i2c-qup-v2.2.1"; 2502 reg = <0x0c1b6000 0x600>; 2503 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2504 2505 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2506 <&gcc GCC_BLSP2_AHB_CLK>; 2507 clock-names = "core", "iface"; 2508 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2509 dma-names = "tx", "rx"; 2510 pinctrl-names = "default", "sleep"; 2511 pinctrl-0 = <&blsp2_i2c2_default>; 2512 pinctrl-1 = <&blsp2_i2c2_sleep>; 2513 clock-frequency = <400000>; 2514 2515 status = "disabled"; 2516 #address-cells = <1>; 2517 #size-cells = <0>; 2518 }; 2519 2520 blsp2_i2c3: i2c@c1b7000 { 2521 compatible = "qcom,i2c-qup-v2.2.1"; 2522 reg = <0x0c1b7000 0x600>; 2523 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2524 2525 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2526 <&gcc GCC_BLSP2_AHB_CLK>; 2527 clock-names = "core", "iface"; 2528 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2529 dma-names = "tx", "rx"; 2530 pinctrl-names = "default", "sleep"; 2531 pinctrl-0 = <&blsp2_i2c3_default>; 2532 pinctrl-1 = <&blsp2_i2c3_sleep>; 2533 clock-frequency = <400000>; 2534 2535 status = "disabled"; 2536 #address-cells = <1>; 2537 #size-cells = <0>; 2538 }; 2539 2540 blsp2_i2c4: i2c@c1b8000 { 2541 compatible = "qcom,i2c-qup-v2.2.1"; 2542 reg = <0x0c1b8000 0x600>; 2543 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2544 2545 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2546 <&gcc GCC_BLSP2_AHB_CLK>; 2547 clock-names = "core", "iface"; 2548 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2549 dma-names = "tx", "rx"; 2550 pinctrl-names = "default", "sleep"; 2551 pinctrl-0 = <&blsp2_i2c4_default>; 2552 pinctrl-1 = <&blsp2_i2c4_sleep>; 2553 clock-frequency = <400000>; 2554 2555 status = "disabled"; 2556 #address-cells = <1>; 2557 #size-cells = <0>; 2558 }; 2559 2560 blsp2_i2c5: i2c@c1b9000 { 2561 compatible = "qcom,i2c-qup-v2.2.1"; 2562 reg = <0x0c1b9000 0x600>; 2563 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2564 2565 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2566 <&gcc GCC_BLSP2_AHB_CLK>; 2567 clock-names = "core", "iface"; 2568 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2569 dma-names = "tx", "rx"; 2570 pinctrl-names = "default", "sleep"; 2571 pinctrl-0 = <&blsp2_i2c5_default>; 2572 pinctrl-1 = <&blsp2_i2c5_sleep>; 2573 clock-frequency = <400000>; 2574 2575 status = "disabled"; 2576 #address-cells = <1>; 2577 #size-cells = <0>; 2578 }; 2579 2580 blsp2_i2c6: i2c@c1ba000 { 2581 compatible = "qcom,i2c-qup-v2.2.1"; 2582 reg = <0x0c1ba000 0x600>; 2583 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2584 2585 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2586 <&gcc GCC_BLSP2_AHB_CLK>; 2587 clock-names = "core", "iface"; 2588 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2589 dma-names = "tx", "rx"; 2590 pinctrl-names = "default", "sleep"; 2591 pinctrl-0 = <&blsp2_i2c6_default>; 2592 pinctrl-1 = <&blsp2_i2c6_sleep>; 2593 clock-frequency = <400000>; 2594 2595 status = "disabled"; 2596 #address-cells = <1>; 2597 #size-cells = <0>; 2598 }; 2599 2600 blsp2_spi1: spi@c1b5000 { 2601 compatible = "qcom,spi-qup-v2.2.1"; 2602 reg = <0x0c1b5000 0x600>; 2603 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2604 2605 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 2606 <&gcc GCC_BLSP2_AHB_CLK>; 2607 clock-names = "core", "iface"; 2608 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2609 dma-names = "tx", "rx"; 2610 pinctrl-names = "default"; 2611 pinctrl-0 = <&blsp2_spi1_default>; 2612 2613 status = "disabled"; 2614 #address-cells = <1>; 2615 #size-cells = <0>; 2616 }; 2617 2618 blsp2_spi2: spi@c1b6000 { 2619 compatible = "qcom,spi-qup-v2.2.1"; 2620 reg = <0x0c1b6000 0x600>; 2621 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2622 2623 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 2624 <&gcc GCC_BLSP2_AHB_CLK>; 2625 clock-names = "core", "iface"; 2626 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2627 dma-names = "tx", "rx"; 2628 pinctrl-names = "default"; 2629 pinctrl-0 = <&blsp2_spi2_default>; 2630 2631 status = "disabled"; 2632 #address-cells = <1>; 2633 #size-cells = <0>; 2634 }; 2635 2636 blsp2_spi3: spi@c1b7000 { 2637 compatible = "qcom,spi-qup-v2.2.1"; 2638 reg = <0x0c1b7000 0x600>; 2639 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2640 2641 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 2642 <&gcc GCC_BLSP2_AHB_CLK>; 2643 clock-names = "core", "iface"; 2644 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2645 dma-names = "tx", "rx"; 2646 pinctrl-names = "default"; 2647 pinctrl-0 = <&blsp2_spi3_default>; 2648 2649 status = "disabled"; 2650 #address-cells = <1>; 2651 #size-cells = <0>; 2652 }; 2653 2654 blsp2_spi4: spi@c1b8000 { 2655 compatible = "qcom,spi-qup-v2.2.1"; 2656 reg = <0x0c1b8000 0x600>; 2657 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2658 2659 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 2660 <&gcc GCC_BLSP2_AHB_CLK>; 2661 clock-names = "core", "iface"; 2662 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2663 dma-names = "tx", "rx"; 2664 pinctrl-names = "default"; 2665 pinctrl-0 = <&blsp2_spi4_default>; 2666 2667 status = "disabled"; 2668 #address-cells = <1>; 2669 #size-cells = <0>; 2670 }; 2671 2672 blsp2_spi5: spi@c1b9000 { 2673 compatible = "qcom,spi-qup-v2.2.1"; 2674 reg = <0x0c1b9000 0x600>; 2675 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2676 2677 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 2678 <&gcc GCC_BLSP2_AHB_CLK>; 2679 clock-names = "core", "iface"; 2680 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2681 dma-names = "tx", "rx"; 2682 pinctrl-names = "default"; 2683 pinctrl-0 = <&blsp2_spi5_default>; 2684 2685 status = "disabled"; 2686 #address-cells = <1>; 2687 #size-cells = <0>; 2688 }; 2689 2690 blsp2_spi6: spi@c1ba000 { 2691 compatible = "qcom,spi-qup-v2.2.1"; 2692 reg = <0x0c1ba000 0x600>; 2693 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2694 2695 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 2696 <&gcc GCC_BLSP2_AHB_CLK>; 2697 clock-names = "core", "iface"; 2698 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2699 dma-names = "tx", "rx"; 2700 pinctrl-names = "default"; 2701 pinctrl-0 = <&blsp2_spi6_default>; 2702 2703 status = "disabled"; 2704 #address-cells = <1>; 2705 #size-cells = <0>; 2706 }; 2707 2708 mmcc: clock-controller@c8c0000 { 2709 compatible = "qcom,mmcc-msm8998"; 2710 #clock-cells = <1>; 2711 #reset-cells = <1>; 2712 #power-domain-cells = <1>; 2713 reg = <0xc8c0000 0x40000>; 2714 2715 clock-names = "xo", 2716 "gpll0", 2717 "dsi0dsi", 2718 "dsi0byte", 2719 "dsi1dsi", 2720 "dsi1byte", 2721 "hdmipll", 2722 "dplink", 2723 "dpvco"; 2724 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2725 <&gcc GCC_MMSS_GPLL0_CLK>, 2726 <0>, 2727 <0>, 2728 <0>, 2729 <0>, 2730 <0>, 2731 <0>, 2732 <0>; 2733 }; 2734 2735 mmss_smmu: iommu@cd00000 { 2736 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 2737 reg = <0x0cd00000 0x40000>; 2738 #iommu-cells = <1>; 2739 2740 clocks = <&mmcc MNOC_AHB_CLK>, 2741 <&mmcc BIMC_SMMU_AHB_CLK>, 2742 <&rpmcc RPM_SMD_MMAXI_CLK>, 2743 <&mmcc BIMC_SMMU_AXI_CLK>; 2744 clock-names = "iface-mm", "iface-smmu", 2745 "bus-mm", "bus-smmu"; 2746 2747 #global-interrupts = <0>; 2748 interrupts = 2749 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2752 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2753 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2754 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2755 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2768 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2769 }; 2770 2771 remoteproc_adsp: remoteproc@17300000 { 2772 compatible = "qcom,msm8998-adsp-pas"; 2773 reg = <0x17300000 0x4040>; 2774 2775 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2776 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2777 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2778 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2779 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2780 interrupt-names = "wdog", "fatal", "ready", 2781 "handover", "stop-ack"; 2782 2783 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2784 clock-names = "xo"; 2785 2786 memory-region = <&adsp_mem>; 2787 2788 qcom,smem-states = <&adsp_smp2p_out 0>; 2789 qcom,smem-state-names = "stop"; 2790 2791 power-domains = <&rpmpd MSM8998_VDDCX>; 2792 power-domain-names = "cx"; 2793 2794 status = "disabled"; 2795 2796 glink-edge { 2797 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2798 label = "lpass"; 2799 qcom,remote-pid = <2>; 2800 mboxes = <&apcs_glb 9>; 2801 }; 2802 }; 2803 2804 apcs_glb: mailbox@17911000 { 2805 compatible = "qcom,msm8998-apcs-hmss-global", 2806 "qcom,msm8994-apcs-kpss-global"; 2807 reg = <0x17911000 0x1000>; 2808 2809 #mbox-cells = <1>; 2810 }; 2811 2812 timer@17920000 { 2813 #address-cells = <1>; 2814 #size-cells = <1>; 2815 ranges; 2816 compatible = "arm,armv7-timer-mem"; 2817 reg = <0x17920000 0x1000>; 2818 2819 frame@17921000 { 2820 frame-number = <0>; 2821 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2822 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2823 reg = <0x17921000 0x1000>, 2824 <0x17922000 0x1000>; 2825 }; 2826 2827 frame@17923000 { 2828 frame-number = <1>; 2829 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2830 reg = <0x17923000 0x1000>; 2831 status = "disabled"; 2832 }; 2833 2834 frame@17924000 { 2835 frame-number = <2>; 2836 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2837 reg = <0x17924000 0x1000>; 2838 status = "disabled"; 2839 }; 2840 2841 frame@17925000 { 2842 frame-number = <3>; 2843 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2844 reg = <0x17925000 0x1000>; 2845 status = "disabled"; 2846 }; 2847 2848 frame@17926000 { 2849 frame-number = <4>; 2850 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2851 reg = <0x17926000 0x1000>; 2852 status = "disabled"; 2853 }; 2854 2855 frame@17927000 { 2856 frame-number = <5>; 2857 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2858 reg = <0x17927000 0x1000>; 2859 status = "disabled"; 2860 }; 2861 2862 frame@17928000 { 2863 frame-number = <6>; 2864 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2865 reg = <0x17928000 0x1000>; 2866 status = "disabled"; 2867 }; 2868 }; 2869 2870 intc: interrupt-controller@17a00000 { 2871 compatible = "arm,gic-v3"; 2872 reg = <0x17a00000 0x10000>, /* GICD */ 2873 <0x17b00000 0x100000>; /* GICR * 8 */ 2874 #interrupt-cells = <3>; 2875 #address-cells = <1>; 2876 #size-cells = <1>; 2877 ranges; 2878 interrupt-controller; 2879 #redistributor-regions = <1>; 2880 redistributor-stride = <0x0 0x20000>; 2881 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2882 }; 2883 2884 wifi: wifi@18800000 { 2885 compatible = "qcom,wcn3990-wifi"; 2886 status = "disabled"; 2887 reg = <0x18800000 0x800000>; 2888 reg-names = "membase"; 2889 memory-region = <&wlan_msa_mem>; 2890 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2891 clock-names = "cxo_ref_clk_pin"; 2892 interrupts = 2893 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2894 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2896 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2897 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2898 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2899 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2900 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2905 iommus = <&anoc2_smmu 0x1900>, 2906 <&anoc2_smmu 0x1901>; 2907 qcom,snoc-host-cap-8bit-quirk; 2908 }; 2909 }; 2910}; 2911