1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6 7/ { 8 interrupt-parent = <&intc>; 9 10 qcom,msm-id = <292 0x0>; 11 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 chosen { }; 16 17 memory { 18 device_type = "memory"; 19 /* We expect the bootloader to fill in the reg */ 20 reg = <0 0 0 0>; 21 }; 22 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 memory@85800000 { 29 reg = <0x0 0x85800000 0x0 0x800000>; 30 no-map; 31 }; 32 33 smem_mem: smem-mem@86000000 { 34 reg = <0x0 0x86000000 0x0 0x200000>; 35 no-map; 36 }; 37 38 memory@86200000 { 39 reg = <0x0 0x86200000 0x0 0x2600000>; 40 no-map; 41 }; 42 43 rmtfs { 44 compatible = "qcom,rmtfs-mem"; 45 46 size = <0x0 0x200000>; 47 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 48 no-map; 49 50 qcom,client-id = <1>; 51 qcom,vmid = <15>; 52 }; 53 }; 54 55 clocks { 56 xo_board { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <19200000>; 60 }; 61 62 sleep_clk { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <32764>; 66 }; 67 }; 68 69 cpus { 70 #address-cells = <2>; 71 #size-cells = <0>; 72 73 CPU0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,armv8"; 76 reg = <0x0 0x0>; 77 enable-method = "psci"; 78 efficiency = <1024>; 79 next-level-cache = <&L2_0>; 80 L2_0: l2-cache { 81 compatible = "arm,arch-cache"; 82 cache-level = <2>; 83 }; 84 L1_I_0: l1-icache { 85 compatible = "arm,arch-cache"; 86 }; 87 L1_D_0: l1-dcache { 88 compatible = "arm,arch-cache"; 89 }; 90 }; 91 92 CPU1: cpu@1 { 93 device_type = "cpu"; 94 compatible = "arm,armv8"; 95 reg = <0x0 0x1>; 96 enable-method = "psci"; 97 efficiency = <1024>; 98 next-level-cache = <&L2_0>; 99 L1_I_1: l1-icache { 100 compatible = "arm,arch-cache"; 101 }; 102 L1_D_1: l1-dcache { 103 compatible = "arm,arch-cache"; 104 }; 105 }; 106 107 CPU2: cpu@2 { 108 device_type = "cpu"; 109 compatible = "arm,armv8"; 110 reg = <0x0 0x2>; 111 enable-method = "psci"; 112 efficiency = <1024>; 113 next-level-cache = <&L2_0>; 114 L1_I_2: l1-icache { 115 compatible = "arm,arch-cache"; 116 }; 117 L1_D_2: l1-dcache { 118 compatible = "arm,arch-cache"; 119 }; 120 }; 121 122 CPU3: cpu@3 { 123 device_type = "cpu"; 124 compatible = "arm,armv8"; 125 reg = <0x0 0x3>; 126 enable-method = "psci"; 127 efficiency = <1024>; 128 next-level-cache = <&L2_0>; 129 L1_I_3: l1-icache { 130 compatible = "arm,arch-cache"; 131 }; 132 L1_D_3: l1-dcache { 133 compatible = "arm,arch-cache"; 134 }; 135 }; 136 137 CPU4: cpu@100 { 138 device_type = "cpu"; 139 compatible = "arm,armv8"; 140 reg = <0x0 0x100>; 141 enable-method = "psci"; 142 efficiency = <1536>; 143 next-level-cache = <&L2_1>; 144 L2_1: l2-cache { 145 compatible = "arm,arch-cache"; 146 cache-level = <2>; 147 }; 148 L1_I_100: l1-icache { 149 compatible = "arm,arch-cache"; 150 }; 151 L1_D_100: l1-dcache { 152 compatible = "arm,arch-cache"; 153 }; 154 }; 155 156 CPU5: cpu@101 { 157 device_type = "cpu"; 158 compatible = "arm,armv8"; 159 reg = <0x0 0x101>; 160 enable-method = "psci"; 161 efficiency = <1536>; 162 next-level-cache = <&L2_1>; 163 L1_I_101: l1-icache { 164 compatible = "arm,arch-cache"; 165 }; 166 L1_D_101: l1-dcache { 167 compatible = "arm,arch-cache"; 168 }; 169 }; 170 171 CPU6: cpu@102 { 172 device_type = "cpu"; 173 compatible = "arm,armv8"; 174 reg = <0x0 0x102>; 175 enable-method = "psci"; 176 efficiency = <1536>; 177 next-level-cache = <&L2_1>; 178 L1_I_102: l1-icache { 179 compatible = "arm,arch-cache"; 180 }; 181 L1_D_102: l1-dcache { 182 compatible = "arm,arch-cache"; 183 }; 184 }; 185 186 CPU7: cpu@103 { 187 device_type = "cpu"; 188 compatible = "arm,armv8"; 189 reg = <0x0 0x103>; 190 enable-method = "psci"; 191 efficiency = <1536>; 192 next-level-cache = <&L2_1>; 193 L1_I_103: l1-icache { 194 compatible = "arm,arch-cache"; 195 }; 196 L1_D_103: l1-dcache { 197 compatible = "arm,arch-cache"; 198 }; 199 }; 200 201 cpu-map { 202 cluster0 { 203 core0 { 204 cpu = <&CPU0>; 205 }; 206 207 core1 { 208 cpu = <&CPU1>; 209 }; 210 211 core2 { 212 cpu = <&CPU2>; 213 }; 214 215 core3 { 216 cpu = <&CPU3>; 217 }; 218 }; 219 220 cluster1 { 221 core0 { 222 cpu = <&CPU4>; 223 }; 224 225 core1 { 226 cpu = <&CPU5>; 227 }; 228 229 core2 { 230 cpu = <&CPU6>; 231 }; 232 233 core3 { 234 cpu = <&CPU7>; 235 }; 236 }; 237 }; 238 }; 239 240 firmware { 241 scm { 242 compatible = "qcom,scm-msm8998"; 243 }; 244 }; 245 246 tcsr_mutex: hwlock { 247 compatible = "qcom,tcsr-mutex"; 248 syscon = <&tcsr_mutex_regs 0 0x1000>; 249 #hwlock-cells = <1>; 250 }; 251 252 psci { 253 compatible = "arm,psci-1.0"; 254 method = "smc"; 255 }; 256 257 rpm-glink { 258 compatible = "qcom,glink-rpm"; 259 260 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 261 qcom,rpm-msg-ram = <&rpm_msg_ram>; 262 mboxes = <&apcs_glb 0>; 263 264 rpm_requests: rpm-requests { 265 compatible = "qcom,rpm-msm8998"; 266 qcom,glink-channels = "rpm_requests"; 267 }; 268 }; 269 270 smem { 271 compatible = "qcom,smem"; 272 memory-region = <&smem_mem>; 273 hwlocks = <&tcsr_mutex 3>; 274 }; 275 276 thermal-zones { 277 cpu-thermal0 { 278 polling-delay-passive = <250>; 279 polling-delay = <1000>; 280 281 thermal-sensors = <&tsens0 6>; 282 283 trips { 284 cpu_alert0: trip0 { 285 temperature = <75000>; 286 hysteresis = <2000>; 287 type = "passive"; 288 }; 289 290 cpu_crit0: trip1 { 291 temperature = <110000>; 292 hysteresis = <2000>; 293 type = "critical"; 294 }; 295 }; 296 }; 297 298 cpu-thermal1 { 299 polling-delay-passive = <250>; 300 polling-delay = <1000>; 301 302 thermal-sensors = <&tsens0 7>; 303 304 trips { 305 cpu_alert1: trip0 { 306 temperature = <75000>; 307 hysteresis = <2000>; 308 type = "passive"; 309 }; 310 311 cpu_crit1: trip1 { 312 temperature = <110000>; 313 hysteresis = <2000>; 314 type = "critical"; 315 }; 316 }; 317 }; 318 319 cpu-thermal2 { 320 polling-delay-passive = <250>; 321 polling-delay = <1000>; 322 323 thermal-sensors = <&tsens0 8>; 324 325 trips { 326 cpu_alert2: trip0 { 327 temperature = <75000>; 328 hysteresis = <2000>; 329 type = "passive"; 330 }; 331 332 cpu_crit2: trip1 { 333 temperature = <110000>; 334 hysteresis = <2000>; 335 type = "critical"; 336 }; 337 }; 338 }; 339 340 cpu-thermal3 { 341 polling-delay-passive = <250>; 342 polling-delay = <1000>; 343 344 thermal-sensors = <&tsens0 9>; 345 346 trips { 347 cpu_alert3: trip0 { 348 temperature = <75000>; 349 hysteresis = <2000>; 350 type = "passive"; 351 }; 352 353 cpu_crit3: trip1 { 354 temperature = <110000>; 355 hysteresis = <2000>; 356 type = "critical"; 357 }; 358 }; 359 }; 360 361 cpu-thermal4 { 362 polling-delay-passive = <250>; 363 polling-delay = <1000>; 364 365 thermal-sensors = <&tsens0 10>; 366 367 trips { 368 cpu_alert4: trip0 { 369 temperature = <75000>; 370 hysteresis = <2000>; 371 type = "passive"; 372 }; 373 374 cpu_crit4: trip1 { 375 temperature = <110000>; 376 hysteresis = <2000>; 377 type = "critical"; 378 }; 379 }; 380 }; 381 382 cpu-thermal5 { 383 polling-delay-passive = <250>; 384 polling-delay = <1000>; 385 386 thermal-sensors = <&tsens0 11>; 387 388 trips { 389 cpu_alert5: trip0 { 390 temperature = <75000>; 391 hysteresis = <2000>; 392 type = "passive"; 393 }; 394 395 cpu_crit5: trip1 { 396 temperature = <110000>; 397 hysteresis = <2000>; 398 type = "critical"; 399 }; 400 }; 401 }; 402 403 cpu-thermal6 { 404 polling-delay-passive = <250>; 405 polling-delay = <1000>; 406 407 thermal-sensors = <&tsens1 0>; 408 409 trips { 410 cpu_alert6: trip0 { 411 temperature = <75000>; 412 hysteresis = <2000>; 413 type = "passive"; 414 }; 415 416 cpu_crit6: trip1 { 417 temperature = <110000>; 418 hysteresis = <2000>; 419 type = "critical"; 420 }; 421 }; 422 }; 423 424 cpu-thermal7 { 425 polling-delay-passive = <250>; 426 polling-delay = <1000>; 427 428 thermal-sensors = <&tsens1 1>; 429 430 trips { 431 cpu_alert7: trip0 { 432 temperature = <75000>; 433 hysteresis = <2000>; 434 type = "passive"; 435 }; 436 437 cpu_crit7: trip1 { 438 temperature = <110000>; 439 hysteresis = <2000>; 440 type = "critical"; 441 }; 442 }; 443 }; 444 445 gpu-thermal { 446 polling-delay-passive = <250>; 447 polling-delay = <1000>; 448 449 thermal-sensors = <&tsens1 3>; 450 }; 451 }; 452 453 timer { 454 compatible = "arm,armv8-timer"; 455 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 456 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 457 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 458 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 459 }; 460 461 soc: soc { 462 #address-cells = <1>; 463 #size-cells = <1>; 464 ranges = <0 0 0 0xffffffff>; 465 compatible = "simple-bus"; 466 467 rpm_msg_ram: memory@68000 { 468 compatible = "qcom,rpm-msg-ram"; 469 reg = <0x778000 0x7000>; 470 }; 471 472 gcc: clock-controller@100000 { 473 compatible = "qcom,gcc-msm8998"; 474 #clock-cells = <1>; 475 #reset-cells = <1>; 476 #power-domain-cells = <1>; 477 reg = <0x100000 0xb0000>; 478 }; 479 480 tlmm: pinctrl@3400000 { 481 compatible = "qcom,msm8998-pinctrl"; 482 reg = <0x3400000 0xc00000>; 483 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 484 gpio-controller; 485 #gpio-cells = <0x2>; 486 interrupt-controller; 487 #interrupt-cells = <0x2>; 488 }; 489 490 spmi_bus: spmi@800f000 { 491 compatible = "qcom,spmi-pmic-arb"; 492 reg = <0x800f000 0x1000>, 493 <0x8400000 0x1000000>, 494 <0x9400000 0x1000000>, 495 <0xa400000 0x220000>, 496 <0x800a000 0x3000>; 497 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 498 interrupt-names = "periph_irq"; 499 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 500 qcom,ee = <0>; 501 qcom,channel = <0>; 502 #address-cells = <2>; 503 #size-cells = <0>; 504 interrupt-controller; 505 #interrupt-cells = <4>; 506 cell-index = <0>; 507 }; 508 509 tsens0: thermal@10aa000 { 510 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 511 reg = <0x10aa000 0x2000>; 512 513 #qcom,sensors = <12>; 514 #thermal-sensor-cells = <1>; 515 }; 516 517 tsens1: thermal@10ad000 { 518 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 519 reg = <0x10ad000 0x2000>; 520 521 #qcom,sensors = <8>; 522 #thermal-sensor-cells = <1>; 523 }; 524 525 tcsr_mutex_regs: syscon@1f40000 { 526 compatible = "syscon"; 527 reg = <0x1f40000 0x20000>; 528 }; 529 530 apcs_glb: mailbox@9820000 { 531 compatible = "qcom,msm8998-apcs-hmss-global"; 532 reg = <0x17911000 0x1000>; 533 534 #mbox-cells = <1>; 535 }; 536 537 blsp2_uart1: serial@c1b0000 { 538 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 539 reg = <0xc1b0000 0x1000>; 540 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 542 <&gcc GCC_BLSP2_AHB_CLK>; 543 clock-names = "core", "iface"; 544 status = "disabled"; 545 }; 546 547 timer@17920000 { 548 #address-cells = <1>; 549 #size-cells = <1>; 550 ranges; 551 compatible = "arm,armv7-timer-mem"; 552 reg = <0x17920000 0x1000>; 553 554 frame@17921000 { 555 frame-number = <0>; 556 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 558 reg = <0x17921000 0x1000>, 559 <0x17922000 0x1000>; 560 }; 561 562 frame@17923000 { 563 frame-number = <1>; 564 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 565 reg = <0x17923000 0x1000>; 566 status = "disabled"; 567 }; 568 569 frame@17924000 { 570 frame-number = <2>; 571 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 572 reg = <0x17924000 0x1000>; 573 status = "disabled"; 574 }; 575 576 frame@17925000 { 577 frame-number = <3>; 578 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 579 reg = <0x17925000 0x1000>; 580 status = "disabled"; 581 }; 582 583 frame@17926000 { 584 frame-number = <4>; 585 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 586 reg = <0x17926000 0x1000>; 587 status = "disabled"; 588 }; 589 590 frame@17927000 { 591 frame-number = <5>; 592 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 593 reg = <0x17927000 0x1000>; 594 status = "disabled"; 595 }; 596 597 frame@17928000 { 598 frame-number = <6>; 599 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 600 reg = <0x17928000 0x1000>; 601 status = "disabled"; 602 }; 603 }; 604 605 intc: interrupt-controller@17a00000 { 606 compatible = "arm,gic-v3"; 607 reg = <0x17a00000 0x10000>, /* GICD */ 608 <0x17b00000 0x100000>; /* GICR * 8 */ 609 #interrupt-cells = <3>; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges; 613 interrupt-controller; 614 #redistributor-regions = <1>; 615 redistributor-stride = <0x0 0x20000>; 616 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 617 }; 618 }; 619}; 620