1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 qcom,msm-id = <292 0x0>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 memory@80000000 { 23 device_type = "memory"; 24 /* We expect the bootloader to fill in the reg */ 25 reg = <0x0 0x80000000 0x0 0x0>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 hyp_mem: memory@85800000 { 34 reg = <0x0 0x85800000 0x0 0x600000>; 35 no-map; 36 }; 37 38 xbl_mem: memory@85e00000 { 39 reg = <0x0 0x85e00000 0x0 0x100000>; 40 no-map; 41 }; 42 43 smem_mem: smem-mem@86000000 { 44 reg = <0x0 0x86000000 0x0 0x200000>; 45 no-map; 46 }; 47 48 tz_mem: memory@86200000 { 49 reg = <0x0 0x86200000 0x0 0x2d00000>; 50 no-map; 51 }; 52 53 rmtfs_mem: memory@88f00000 { 54 compatible = "qcom,rmtfs-mem"; 55 reg = <0x0 0x88f00000 0x0 0x200000>; 56 no-map; 57 58 qcom,client-id = <1>; 59 qcom,vmid = <15>; 60 }; 61 62 spss_mem: memory@8ab00000 { 63 reg = <0x0 0x8ab00000 0x0 0x700000>; 64 no-map; 65 }; 66 67 adsp_mem: memory@8b200000 { 68 reg = <0x0 0x8b200000 0x0 0x1a00000>; 69 no-map; 70 }; 71 72 mpss_mem: memory@8cc00000 { 73 reg = <0x0 0x8cc00000 0x0 0x7000000>; 74 no-map; 75 }; 76 77 venus_mem: memory@93c00000 { 78 reg = <0x0 0x93c00000 0x0 0x500000>; 79 no-map; 80 }; 81 82 mba_mem: memory@94100000 { 83 reg = <0x0 0x94100000 0x0 0x200000>; 84 no-map; 85 }; 86 87 slpi_mem: memory@94300000 { 88 reg = <0x0 0x94300000 0x0 0xf00000>; 89 no-map; 90 }; 91 92 ipa_fw_mem: memory@95200000 { 93 reg = <0x0 0x95200000 0x0 0x10000>; 94 no-map; 95 }; 96 97 ipa_gsi_mem: memory@95210000 { 98 reg = <0x0 0x95210000 0x0 0x5000>; 99 no-map; 100 }; 101 102 gpu_mem: memory@95600000 { 103 reg = <0x0 0x95600000 0x0 0x100000>; 104 no-map; 105 }; 106 107 wlan_msa_mem: memory@95700000 { 108 reg = <0x0 0x95700000 0x0 0x100000>; 109 no-map; 110 }; 111 }; 112 113 clocks { 114 xo: xo-board { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <19200000>; 118 clock-output-names = "xo_board"; 119 }; 120 121 sleep_clk: sleep-clk { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <32764>; 125 }; 126 }; 127 128 cpus { 129 #address-cells = <2>; 130 #size-cells = <0>; 131 132 CPU0: cpu@0 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo280"; 135 reg = <0x0 0x0>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 139 next-level-cache = <&L2_0>; 140 L2_0: l2-cache { 141 compatible = "arm,arch-cache"; 142 cache-level = <2>; 143 }; 144 L1_I_0: l1-icache { 145 compatible = "arm,arch-cache"; 146 }; 147 L1_D_0: l1-dcache { 148 compatible = "arm,arch-cache"; 149 }; 150 }; 151 152 CPU1: cpu@1 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo280"; 155 reg = <0x0 0x1>; 156 enable-method = "psci"; 157 capacity-dmips-mhz = <1024>; 158 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 159 next-level-cache = <&L2_0>; 160 L1_I_1: l1-icache { 161 compatible = "arm,arch-cache"; 162 }; 163 L1_D_1: l1-dcache { 164 compatible = "arm,arch-cache"; 165 }; 166 }; 167 168 CPU2: cpu@2 { 169 device_type = "cpu"; 170 compatible = "qcom,kryo280"; 171 reg = <0x0 0x2>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 175 next-level-cache = <&L2_0>; 176 L1_I_2: l1-icache { 177 compatible = "arm,arch-cache"; 178 }; 179 L1_D_2: l1-dcache { 180 compatible = "arm,arch-cache"; 181 }; 182 }; 183 184 CPU3: cpu@3 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo280"; 187 reg = <0x0 0x3>; 188 enable-method = "psci"; 189 capacity-dmips-mhz = <1024>; 190 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 191 next-level-cache = <&L2_0>; 192 L1_I_3: l1-icache { 193 compatible = "arm,arch-cache"; 194 }; 195 L1_D_3: l1-dcache { 196 compatible = "arm,arch-cache"; 197 }; 198 }; 199 200 CPU4: cpu@100 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo280"; 203 reg = <0x0 0x100>; 204 enable-method = "psci"; 205 capacity-dmips-mhz = <1536>; 206 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 207 next-level-cache = <&L2_1>; 208 L2_1: l2-cache { 209 compatible = "arm,arch-cache"; 210 cache-level = <2>; 211 }; 212 L1_I_100: l1-icache { 213 compatible = "arm,arch-cache"; 214 }; 215 L1_D_100: l1-dcache { 216 compatible = "arm,arch-cache"; 217 }; 218 }; 219 220 CPU5: cpu@101 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo280"; 223 reg = <0x0 0x101>; 224 enable-method = "psci"; 225 capacity-dmips-mhz = <1536>; 226 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 227 next-level-cache = <&L2_1>; 228 L1_I_101: l1-icache { 229 compatible = "arm,arch-cache"; 230 }; 231 L1_D_101: l1-dcache { 232 compatible = "arm,arch-cache"; 233 }; 234 }; 235 236 CPU6: cpu@102 { 237 device_type = "cpu"; 238 compatible = "qcom,kryo280"; 239 reg = <0x0 0x102>; 240 enable-method = "psci"; 241 capacity-dmips-mhz = <1536>; 242 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 243 next-level-cache = <&L2_1>; 244 L1_I_102: l1-icache { 245 compatible = "arm,arch-cache"; 246 }; 247 L1_D_102: l1-dcache { 248 compatible = "arm,arch-cache"; 249 }; 250 }; 251 252 CPU7: cpu@103 { 253 device_type = "cpu"; 254 compatible = "qcom,kryo280"; 255 reg = <0x0 0x103>; 256 enable-method = "psci"; 257 capacity-dmips-mhz = <1536>; 258 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 259 next-level-cache = <&L2_1>; 260 L1_I_103: l1-icache { 261 compatible = "arm,arch-cache"; 262 }; 263 L1_D_103: l1-dcache { 264 compatible = "arm,arch-cache"; 265 }; 266 }; 267 268 cpu-map { 269 cluster0 { 270 core0 { 271 cpu = <&CPU0>; 272 }; 273 274 core1 { 275 cpu = <&CPU1>; 276 }; 277 278 core2 { 279 cpu = <&CPU2>; 280 }; 281 282 core3 { 283 cpu = <&CPU3>; 284 }; 285 }; 286 287 cluster1 { 288 core0 { 289 cpu = <&CPU4>; 290 }; 291 292 core1 { 293 cpu = <&CPU5>; 294 }; 295 296 core2 { 297 cpu = <&CPU6>; 298 }; 299 300 core3 { 301 cpu = <&CPU7>; 302 }; 303 }; 304 }; 305 306 idle-states { 307 entry-method = "psci"; 308 309 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 310 compatible = "arm,idle-state"; 311 idle-state-name = "little-retention"; 312 /* CPU Retention (C2D), L2 Active */ 313 arm,psci-suspend-param = <0x00000002>; 314 entry-latency-us = <81>; 315 exit-latency-us = <86>; 316 min-residency-us = <504>; 317 }; 318 319 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 320 compatible = "arm,idle-state"; 321 idle-state-name = "little-power-collapse"; 322 /* CPU + L2 Power Collapse (C3, D4) */ 323 arm,psci-suspend-param = <0x40000003>; 324 entry-latency-us = <814>; 325 exit-latency-us = <4562>; 326 min-residency-us = <9183>; 327 local-timer-stop; 328 }; 329 330 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 331 compatible = "arm,idle-state"; 332 idle-state-name = "big-retention"; 333 /* CPU Retention (C2D), L2 Active */ 334 arm,psci-suspend-param = <0x00000002>; 335 entry-latency-us = <79>; 336 exit-latency-us = <82>; 337 min-residency-us = <1302>; 338 }; 339 340 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 341 compatible = "arm,idle-state"; 342 idle-state-name = "big-power-collapse"; 343 /* CPU + L2 Power Collapse (C3, D4) */ 344 arm,psci-suspend-param = <0x40000003>; 345 entry-latency-us = <724>; 346 exit-latency-us = <2027>; 347 min-residency-us = <9419>; 348 local-timer-stop; 349 }; 350 }; 351 }; 352 353 firmware { 354 scm { 355 compatible = "qcom,scm-msm8998", "qcom,scm"; 356 }; 357 }; 358 359 tcsr_mutex: hwlock { 360 compatible = "qcom,tcsr-mutex"; 361 syscon = <&tcsr_mutex_regs 0 0x1000>; 362 #hwlock-cells = <1>; 363 }; 364 365 psci { 366 compatible = "arm,psci-1.0"; 367 method = "smc"; 368 }; 369 370 rpm-glink { 371 compatible = "qcom,glink-rpm"; 372 373 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 374 qcom,rpm-msg-ram = <&rpm_msg_ram>; 375 mboxes = <&apcs_glb 0>; 376 377 rpm_requests: rpm-requests { 378 compatible = "qcom,rpm-msm8998"; 379 qcom,glink-channels = "rpm_requests"; 380 381 rpmcc: clock-controller { 382 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 383 #clock-cells = <1>; 384 }; 385 386 rpmpd: power-controller { 387 compatible = "qcom,msm8998-rpmpd"; 388 #power-domain-cells = <1>; 389 operating-points-v2 = <&rpmpd_opp_table>; 390 391 rpmpd_opp_table: opp-table { 392 compatible = "operating-points-v2"; 393 394 rpmpd_opp_ret: opp1 { 395 opp-level = <RPM_SMD_LEVEL_RETENTION>; 396 }; 397 398 rpmpd_opp_ret_plus: opp2 { 399 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 400 }; 401 402 rpmpd_opp_min_svs: opp3 { 403 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 404 }; 405 406 rpmpd_opp_low_svs: opp4 { 407 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 408 }; 409 410 rpmpd_opp_svs: opp5 { 411 opp-level = <RPM_SMD_LEVEL_SVS>; 412 }; 413 414 rpmpd_opp_svs_plus: opp6 { 415 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 416 }; 417 418 rpmpd_opp_nom: opp7 { 419 opp-level = <RPM_SMD_LEVEL_NOM>; 420 }; 421 422 rpmpd_opp_nom_plus: opp8 { 423 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 424 }; 425 426 rpmpd_opp_turbo: opp9 { 427 opp-level = <RPM_SMD_LEVEL_TURBO>; 428 }; 429 430 rpmpd_opp_turbo_plus: opp10 { 431 opp-level = <RPM_SMD_LEVEL_BINNING>; 432 }; 433 }; 434 }; 435 }; 436 }; 437 438 smem { 439 compatible = "qcom,smem"; 440 memory-region = <&smem_mem>; 441 hwlocks = <&tcsr_mutex 3>; 442 }; 443 444 smp2p-lpass { 445 compatible = "qcom,smp2p"; 446 qcom,smem = <443>, <429>; 447 448 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 449 450 mboxes = <&apcs_glb 10>; 451 452 qcom,local-pid = <0>; 453 qcom,remote-pid = <2>; 454 455 adsp_smp2p_out: master-kernel { 456 qcom,entry-name = "master-kernel"; 457 #qcom,smem-state-cells = <1>; 458 }; 459 460 adsp_smp2p_in: slave-kernel { 461 qcom,entry-name = "slave-kernel"; 462 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 }; 466 }; 467 468 smp2p-mpss { 469 compatible = "qcom,smp2p"; 470 qcom,smem = <435>, <428>; 471 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 472 mboxes = <&apcs_glb 14>; 473 qcom,local-pid = <0>; 474 qcom,remote-pid = <1>; 475 476 modem_smp2p_out: master-kernel { 477 qcom,entry-name = "master-kernel"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 modem_smp2p_in: slave-kernel { 482 qcom,entry-name = "slave-kernel"; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 }; 486 }; 487 488 smp2p-slpi { 489 compatible = "qcom,smp2p"; 490 qcom,smem = <481>, <430>; 491 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 492 mboxes = <&apcs_glb 26>; 493 qcom,local-pid = <0>; 494 qcom,remote-pid = <3>; 495 496 slpi_smp2p_out: master-kernel { 497 qcom,entry-name = "master-kernel"; 498 #qcom,smem-state-cells = <1>; 499 }; 500 501 slpi_smp2p_in: slave-kernel { 502 qcom,entry-name = "slave-kernel"; 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 }; 506 }; 507 508 thermal-zones { 509 cpu0-thermal { 510 polling-delay-passive = <250>; 511 polling-delay = <1000>; 512 513 thermal-sensors = <&tsens0 1>; 514 515 trips { 516 cpu0_alert0: trip-point0 { 517 temperature = <75000>; 518 hysteresis = <2000>; 519 type = "passive"; 520 }; 521 522 cpu0_crit: cpu_crit { 523 temperature = <110000>; 524 hysteresis = <2000>; 525 type = "critical"; 526 }; 527 }; 528 }; 529 530 cpu1-thermal { 531 polling-delay-passive = <250>; 532 polling-delay = <1000>; 533 534 thermal-sensors = <&tsens0 2>; 535 536 trips { 537 cpu1_alert0: trip-point0 { 538 temperature = <75000>; 539 hysteresis = <2000>; 540 type = "passive"; 541 }; 542 543 cpu1_crit: cpu_crit { 544 temperature = <110000>; 545 hysteresis = <2000>; 546 type = "critical"; 547 }; 548 }; 549 }; 550 551 cpu2-thermal { 552 polling-delay-passive = <250>; 553 polling-delay = <1000>; 554 555 thermal-sensors = <&tsens0 3>; 556 557 trips { 558 cpu2_alert0: trip-point0 { 559 temperature = <75000>; 560 hysteresis = <2000>; 561 type = "passive"; 562 }; 563 564 cpu2_crit: cpu_crit { 565 temperature = <110000>; 566 hysteresis = <2000>; 567 type = "critical"; 568 }; 569 }; 570 }; 571 572 cpu3-thermal { 573 polling-delay-passive = <250>; 574 polling-delay = <1000>; 575 576 thermal-sensors = <&tsens0 4>; 577 578 trips { 579 cpu3_alert0: trip-point0 { 580 temperature = <75000>; 581 hysteresis = <2000>; 582 type = "passive"; 583 }; 584 585 cpu3_crit: cpu_crit { 586 temperature = <110000>; 587 hysteresis = <2000>; 588 type = "critical"; 589 }; 590 }; 591 }; 592 593 cpu4-thermal { 594 polling-delay-passive = <250>; 595 polling-delay = <1000>; 596 597 thermal-sensors = <&tsens0 7>; 598 599 trips { 600 cpu4_alert0: trip-point0 { 601 temperature = <75000>; 602 hysteresis = <2000>; 603 type = "passive"; 604 }; 605 606 cpu4_crit: cpu_crit { 607 temperature = <110000>; 608 hysteresis = <2000>; 609 type = "critical"; 610 }; 611 }; 612 }; 613 614 cpu5-thermal { 615 polling-delay-passive = <250>; 616 polling-delay = <1000>; 617 618 thermal-sensors = <&tsens0 8>; 619 620 trips { 621 cpu5_alert0: trip-point0 { 622 temperature = <75000>; 623 hysteresis = <2000>; 624 type = "passive"; 625 }; 626 627 cpu5_crit: cpu_crit { 628 temperature = <110000>; 629 hysteresis = <2000>; 630 type = "critical"; 631 }; 632 }; 633 }; 634 635 cpu6-thermal { 636 polling-delay-passive = <250>; 637 polling-delay = <1000>; 638 639 thermal-sensors = <&tsens0 9>; 640 641 trips { 642 cpu6_alert0: trip-point0 { 643 temperature = <75000>; 644 hysteresis = <2000>; 645 type = "passive"; 646 }; 647 648 cpu6_crit: cpu_crit { 649 temperature = <110000>; 650 hysteresis = <2000>; 651 type = "critical"; 652 }; 653 }; 654 }; 655 656 cpu7-thermal { 657 polling-delay-passive = <250>; 658 polling-delay = <1000>; 659 660 thermal-sensors = <&tsens0 10>; 661 662 trips { 663 cpu7_alert0: trip-point0 { 664 temperature = <75000>; 665 hysteresis = <2000>; 666 type = "passive"; 667 }; 668 669 cpu7_crit: cpu_crit { 670 temperature = <110000>; 671 hysteresis = <2000>; 672 type = "critical"; 673 }; 674 }; 675 }; 676 677 gpu-thermal-bottom { 678 polling-delay-passive = <250>; 679 polling-delay = <1000>; 680 681 thermal-sensors = <&tsens0 12>; 682 683 trips { 684 gpu1_alert0: trip-point0 { 685 temperature = <90000>; 686 hysteresis = <2000>; 687 type = "hot"; 688 }; 689 }; 690 }; 691 692 gpu-thermal-top { 693 polling-delay-passive = <250>; 694 polling-delay = <1000>; 695 696 thermal-sensors = <&tsens0 13>; 697 698 trips { 699 gpu2_alert0: trip-point0 { 700 temperature = <90000>; 701 hysteresis = <2000>; 702 type = "hot"; 703 }; 704 }; 705 }; 706 707 clust0-mhm-thermal { 708 polling-delay-passive = <250>; 709 polling-delay = <1000>; 710 711 thermal-sensors = <&tsens0 5>; 712 713 trips { 714 cluster0_mhm_alert0: trip-point0 { 715 temperature = <90000>; 716 hysteresis = <2000>; 717 type = "hot"; 718 }; 719 }; 720 }; 721 722 clust1-mhm-thermal { 723 polling-delay-passive = <250>; 724 polling-delay = <1000>; 725 726 thermal-sensors = <&tsens0 6>; 727 728 trips { 729 cluster1_mhm_alert0: trip-point0 { 730 temperature = <90000>; 731 hysteresis = <2000>; 732 type = "hot"; 733 }; 734 }; 735 }; 736 737 cluster1-l2-thermal { 738 polling-delay-passive = <250>; 739 polling-delay = <1000>; 740 741 thermal-sensors = <&tsens0 11>; 742 743 trips { 744 cluster1_l2_alert0: trip-point0 { 745 temperature = <90000>; 746 hysteresis = <2000>; 747 type = "hot"; 748 }; 749 }; 750 }; 751 752 modem-thermal { 753 polling-delay-passive = <250>; 754 polling-delay = <1000>; 755 756 thermal-sensors = <&tsens1 1>; 757 758 trips { 759 modem_alert0: trip-point0 { 760 temperature = <90000>; 761 hysteresis = <2000>; 762 type = "hot"; 763 }; 764 }; 765 }; 766 767 mem-thermal { 768 polling-delay-passive = <250>; 769 polling-delay = <1000>; 770 771 thermal-sensors = <&tsens1 2>; 772 773 trips { 774 mem_alert0: trip-point0 { 775 temperature = <90000>; 776 hysteresis = <2000>; 777 type = "hot"; 778 }; 779 }; 780 }; 781 782 wlan-thermal { 783 polling-delay-passive = <250>; 784 polling-delay = <1000>; 785 786 thermal-sensors = <&tsens1 3>; 787 788 trips { 789 wlan_alert0: trip-point0 { 790 temperature = <90000>; 791 hysteresis = <2000>; 792 type = "hot"; 793 }; 794 }; 795 }; 796 797 q6-dsp-thermal { 798 polling-delay-passive = <250>; 799 polling-delay = <1000>; 800 801 thermal-sensors = <&tsens1 4>; 802 803 trips { 804 q6_dsp_alert0: trip-point0 { 805 temperature = <90000>; 806 hysteresis = <2000>; 807 type = "hot"; 808 }; 809 }; 810 }; 811 812 camera-thermal { 813 polling-delay-passive = <250>; 814 polling-delay = <1000>; 815 816 thermal-sensors = <&tsens1 5>; 817 818 trips { 819 camera_alert0: trip-point0 { 820 temperature = <90000>; 821 hysteresis = <2000>; 822 type = "hot"; 823 }; 824 }; 825 }; 826 827 multimedia-thermal { 828 polling-delay-passive = <250>; 829 polling-delay = <1000>; 830 831 thermal-sensors = <&tsens1 6>; 832 833 trips { 834 multimedia_alert0: trip-point0 { 835 temperature = <90000>; 836 hysteresis = <2000>; 837 type = "hot"; 838 }; 839 }; 840 }; 841 }; 842 843 timer { 844 compatible = "arm,armv8-timer"; 845 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 846 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 847 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 848 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 849 }; 850 851 soc: soc { 852 #address-cells = <1>; 853 #size-cells = <1>; 854 ranges = <0 0 0 0xffffffff>; 855 compatible = "simple-bus"; 856 857 gcc: clock-controller@100000 { 858 compatible = "qcom,gcc-msm8998"; 859 #clock-cells = <1>; 860 #reset-cells = <1>; 861 #power-domain-cells = <1>; 862 reg = <0x00100000 0xb0000>; 863 864 clock-names = "xo", "sleep_clk"; 865 clocks = <&xo>, <&sleep_clk>; 866 }; 867 868 rpm_msg_ram: sram@778000 { 869 compatible = "qcom,rpm-msg-ram"; 870 reg = <0x00778000 0x7000>; 871 }; 872 873 qfprom: qfprom@784000 { 874 compatible = "qcom,qfprom"; 875 reg = <0x00784000 0x621c>; 876 #address-cells = <1>; 877 #size-cells = <1>; 878 879 qusb2_hstx_trim: hstx-trim@23a { 880 reg = <0x23a 0x1>; 881 bits = <0 4>; 882 }; 883 }; 884 885 tsens0: thermal@10ab000 { 886 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 887 reg = <0x010ab000 0x1000>, /* TM */ 888 <0x010aa000 0x1000>; /* SROT */ 889 #qcom,sensors = <14>; 890 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 892 interrupt-names = "uplow", "critical"; 893 #thermal-sensor-cells = <1>; 894 }; 895 896 tsens1: thermal@10ae000 { 897 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 898 reg = <0x010ae000 0x1000>, /* TM */ 899 <0x010ad000 0x1000>; /* SROT */ 900 #qcom,sensors = <8>; 901 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "uplow", "critical"; 904 #thermal-sensor-cells = <1>; 905 }; 906 907 anoc1_smmu: iommu@1680000 { 908 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 909 reg = <0x01680000 0x10000>; 910 #iommu-cells = <1>; 911 912 #global-interrupts = <0>; 913 interrupts = 914 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 915 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 916 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 917 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 918 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 919 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 920 }; 921 922 anoc2_smmu: iommu@16c0000 { 923 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 924 reg = <0x016c0000 0x40000>; 925 #iommu-cells = <1>; 926 927 #global-interrupts = <0>; 928 interrupts = 929 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 930 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 931 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 932 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 933 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 934 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 935 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 936 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 937 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 938 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 939 }; 940 941 pcie0: pci@1c00000 { 942 compatible = "qcom,pcie-msm8996"; 943 reg = <0x01c00000 0x2000>, 944 <0x1b000000 0xf1d>, 945 <0x1b000f20 0xa8>, 946 <0x1b100000 0x100000>; 947 reg-names = "parf", "dbi", "elbi", "config"; 948 device_type = "pci"; 949 linux,pci-domain = <0>; 950 bus-range = <0x00 0xff>; 951 #address-cells = <3>; 952 #size-cells = <2>; 953 num-lanes = <1>; 954 phys = <&pciephy>; 955 phy-names = "pciephy"; 956 status = "disabled"; 957 958 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, 959 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 960 961 #interrupt-cells = <1>; 962 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 963 interrupt-names = "msi"; 964 interrupt-map-mask = <0 0 0 0x7>; 965 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 966 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 967 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 968 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 969 970 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 971 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 972 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 973 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 974 <&gcc GCC_PCIE_0_AUX_CLK>; 975 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 976 977 power-domains = <&gcc PCIE_0_GDSC>; 978 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 979 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 980 }; 981 982 pcie_phy: phy@1c06000 { 983 compatible = "qcom,msm8998-qmp-pcie-phy"; 984 reg = <0x01c06000 0x18c>; 985 #address-cells = <1>; 986 #size-cells = <1>; 987 status = "disabled"; 988 ranges; 989 990 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 991 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 992 <&gcc GCC_PCIE_CLKREF_CLK>; 993 clock-names = "aux", "cfg_ahb", "ref"; 994 995 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 996 reset-names = "phy", "common"; 997 998 vdda-phy-supply = <&vreg_l1a_0p875>; 999 vdda-pll-supply = <&vreg_l2a_1p2>; 1000 1001 pciephy: phy@1c06800 { 1002 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 1003 #phy-cells = <0>; 1004 1005 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1006 clock-names = "pipe0"; 1007 clock-output-names = "pcie_0_pipe_clk_src"; 1008 #clock-cells = <0>; 1009 }; 1010 }; 1011 1012 ufshc: ufshc@1da4000 { 1013 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1014 reg = <0x01da4000 0x2500>; 1015 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1016 phys = <&ufsphy_lanes>; 1017 phy-names = "ufsphy"; 1018 lanes-per-direction = <2>; 1019 power-domains = <&gcc UFS_GDSC>; 1020 status = "disabled"; 1021 #reset-cells = <1>; 1022 1023 clock-names = 1024 "core_clk", 1025 "bus_aggr_clk", 1026 "iface_clk", 1027 "core_clk_unipro", 1028 "ref_clk", 1029 "tx_lane0_sync_clk", 1030 "rx_lane0_sync_clk", 1031 "rx_lane1_sync_clk"; 1032 clocks = 1033 <&gcc GCC_UFS_AXI_CLK>, 1034 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1035 <&gcc GCC_UFS_AHB_CLK>, 1036 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1037 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1038 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1039 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1040 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1041 freq-table-hz = 1042 <50000000 200000000>, 1043 <0 0>, 1044 <0 0>, 1045 <37500000 150000000>, 1046 <0 0>, 1047 <0 0>, 1048 <0 0>, 1049 <0 0>; 1050 1051 resets = <&gcc GCC_UFS_BCR>; 1052 reset-names = "rst"; 1053 }; 1054 1055 ufsphy: phy@1da7000 { 1056 compatible = "qcom,msm8998-qmp-ufs-phy"; 1057 reg = <0x01da7000 0x18c>; 1058 #address-cells = <1>; 1059 #size-cells = <1>; 1060 status = "disabled"; 1061 ranges; 1062 1063 clock-names = 1064 "ref", 1065 "ref_aux"; 1066 clocks = 1067 <&gcc GCC_UFS_CLKREF_CLK>, 1068 <&gcc GCC_UFS_PHY_AUX_CLK>; 1069 1070 reset-names = "ufsphy"; 1071 resets = <&ufshc 0>; 1072 1073 ufsphy_lanes: phy@1da7400 { 1074 reg = <0x01da7400 0x128>, 1075 <0x01da7600 0x1fc>, 1076 <0x01da7c00 0x1dc>, 1077 <0x01da7800 0x128>, 1078 <0x01da7a00 0x1fc>; 1079 #phy-cells = <0>; 1080 }; 1081 }; 1082 1083 tcsr_mutex_regs: syscon@1f40000 { 1084 compatible = "syscon"; 1085 reg = <0x01f40000 0x40000>; 1086 }; 1087 1088 tlmm: pinctrl@3400000 { 1089 compatible = "qcom,msm8998-pinctrl"; 1090 reg = <0x03400000 0xc00000>; 1091 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1092 gpio-controller; 1093 #gpio-cells = <0x2>; 1094 interrupt-controller; 1095 #interrupt-cells = <0x2>; 1096 1097 sdc2_clk_on: sdc2_clk_on { 1098 config { 1099 pins = "sdc2_clk"; 1100 bias-disable; 1101 drive-strength = <16>; 1102 }; 1103 }; 1104 1105 sdc2_clk_off: sdc2_clk_off { 1106 config { 1107 pins = "sdc2_clk"; 1108 bias-disable; 1109 drive-strength = <2>; 1110 }; 1111 }; 1112 1113 sdc2_cmd_on: sdc2_cmd_on { 1114 config { 1115 pins = "sdc2_cmd"; 1116 bias-pull-up; 1117 drive-strength = <10>; 1118 }; 1119 }; 1120 1121 sdc2_cmd_off: sdc2_cmd_off { 1122 config { 1123 pins = "sdc2_cmd"; 1124 bias-pull-up; 1125 drive-strength = <2>; 1126 }; 1127 }; 1128 1129 sdc2_data_on: sdc2_data_on { 1130 config { 1131 pins = "sdc2_data"; 1132 bias-pull-up; 1133 drive-strength = <10>; 1134 }; 1135 }; 1136 1137 sdc2_data_off: sdc2_data_off { 1138 config { 1139 pins = "sdc2_data"; 1140 bias-pull-up; 1141 drive-strength = <2>; 1142 }; 1143 }; 1144 1145 sdc2_cd_on: sdc2_cd_on { 1146 mux { 1147 pins = "gpio95"; 1148 function = "gpio"; 1149 }; 1150 1151 config { 1152 pins = "gpio95"; 1153 bias-pull-up; 1154 drive-strength = <2>; 1155 }; 1156 }; 1157 1158 sdc2_cd_off: sdc2_cd_off { 1159 mux { 1160 pins = "gpio95"; 1161 function = "gpio"; 1162 }; 1163 1164 config { 1165 pins = "gpio95"; 1166 bias-pull-up; 1167 drive-strength = <2>; 1168 }; 1169 }; 1170 1171 blsp1_uart3_on: blsp1_uart3_on { 1172 tx { 1173 pins = "gpio45"; 1174 function = "blsp_uart3_a"; 1175 drive-strength = <2>; 1176 bias-disable; 1177 }; 1178 1179 rx { 1180 pins = "gpio46"; 1181 function = "blsp_uart3_a"; 1182 drive-strength = <2>; 1183 bias-disable; 1184 }; 1185 1186 cts { 1187 pins = "gpio47"; 1188 function = "blsp_uart3_a"; 1189 drive-strength = <2>; 1190 bias-disable; 1191 }; 1192 1193 rfr { 1194 pins = "gpio48"; 1195 function = "blsp_uart3_a"; 1196 drive-strength = <2>; 1197 bias-disable; 1198 }; 1199 }; 1200 1201 blsp1_i2c1_default: blsp1-i2c1-default { 1202 pins = "gpio2", "gpio3"; 1203 function = "blsp_i2c1"; 1204 drive-strength = <2>; 1205 bias-disable; 1206 }; 1207 1208 blsp1_i2c1_sleep: blsp1-i2c1-sleep { 1209 pins = "gpio2", "gpio3"; 1210 function = "blsp_i2c1"; 1211 drive-strength = <2>; 1212 bias-pull-up; 1213 }; 1214 1215 blsp1_i2c2_default: blsp1-i2c2-default { 1216 pins = "gpio32", "gpio33"; 1217 function = "blsp_i2c2"; 1218 drive-strength = <2>; 1219 bias-disable; 1220 }; 1221 1222 blsp1_i2c2_sleep: blsp1-i2c2-sleep { 1223 pins = "gpio32", "gpio33"; 1224 function = "blsp_i2c2"; 1225 drive-strength = <2>; 1226 bias-pull-up; 1227 }; 1228 1229 blsp1_i2c3_default: blsp1-i2c3-default { 1230 pins = "gpio47", "gpio48"; 1231 function = "blsp_i2c3"; 1232 drive-strength = <2>; 1233 bias-disable; 1234 }; 1235 1236 blsp1_i2c3_sleep: blsp1-i2c3-sleep { 1237 pins = "gpio47", "gpio48"; 1238 function = "blsp_i2c3"; 1239 drive-strength = <2>; 1240 bias-pull-up; 1241 }; 1242 1243 blsp1_i2c4_default: blsp1-i2c4-default { 1244 pins = "gpio10", "gpio11"; 1245 function = "blsp_i2c4"; 1246 drive-strength = <2>; 1247 bias-disable; 1248 }; 1249 1250 blsp1_i2c4_sleep: blsp1-i2c4-sleep { 1251 pins = "gpio10", "gpio11"; 1252 function = "blsp_i2c4"; 1253 drive-strength = <2>; 1254 bias-pull-up; 1255 }; 1256 1257 blsp1_i2c5_default: blsp1-i2c5-default { 1258 pins = "gpio87", "gpio88"; 1259 function = "blsp_i2c5"; 1260 drive-strength = <2>; 1261 bias-disable; 1262 }; 1263 1264 blsp1_i2c5_sleep: blsp1-i2c5-sleep { 1265 pins = "gpio87", "gpio88"; 1266 function = "blsp_i2c5"; 1267 drive-strength = <2>; 1268 bias-pull-up; 1269 }; 1270 1271 blsp1_i2c6_default: blsp1-i2c6-default { 1272 pins = "gpio43", "gpio44"; 1273 function = "blsp_i2c6"; 1274 drive-strength = <2>; 1275 bias-disable; 1276 }; 1277 1278 blsp1_i2c6_sleep: blsp1-i2c6-sleep { 1279 pins = "gpio43", "gpio44"; 1280 function = "blsp_i2c6"; 1281 drive-strength = <2>; 1282 bias-pull-up; 1283 }; 1284 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1285 blsp2_i2c1_default: blsp2-i2c1-default { 1286 pins = "gpio55", "gpio56"; 1287 function = "blsp_i2c7"; 1288 drive-strength = <2>; 1289 bias-disable; 1290 }; 1291 1292 blsp2_i2c1_sleep: blsp2-i2c1-sleep { 1293 pins = "gpio55", "gpio56"; 1294 function = "blsp_i2c7"; 1295 drive-strength = <2>; 1296 bias-pull-up; 1297 }; 1298 1299 blsp2_i2c2_default: blsp2-i2c2-default { 1300 pins = "gpio6", "gpio7"; 1301 function = "blsp_i2c8"; 1302 drive-strength = <2>; 1303 bias-disable; 1304 }; 1305 1306 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1307 pins = "gpio6", "gpio7"; 1308 function = "blsp_i2c8"; 1309 drive-strength = <2>; 1310 bias-pull-up; 1311 }; 1312 1313 blsp2_i2c3_default: blsp2-i2c3-default { 1314 pins = "gpio51", "gpio52"; 1315 function = "blsp_i2c9"; 1316 drive-strength = <2>; 1317 bias-disable; 1318 }; 1319 1320 blsp2_i2c3_sleep: blsp2-i2c3-sleep { 1321 pins = "gpio51", "gpio52"; 1322 function = "blsp_i2c9"; 1323 drive-strength = <2>; 1324 bias-pull-up; 1325 }; 1326 1327 blsp2_i2c4_default: blsp2-i2c4-default { 1328 pins = "gpio67", "gpio68"; 1329 function = "blsp_i2c10"; 1330 drive-strength = <2>; 1331 bias-disable; 1332 }; 1333 1334 blsp2_i2c4_sleep: blsp2-i2c4-sleep { 1335 pins = "gpio67", "gpio68"; 1336 function = "blsp_i2c10"; 1337 drive-strength = <2>; 1338 bias-pull-up; 1339 }; 1340 1341 blsp2_i2c5_default: blsp2-i2c5-default { 1342 pins = "gpio60", "gpio61"; 1343 function = "blsp_i2c11"; 1344 drive-strength = <2>; 1345 bias-disable; 1346 }; 1347 1348 blsp2_i2c5_sleep: blsp2-i2c5-sleep { 1349 pins = "gpio60", "gpio61"; 1350 function = "blsp_i2c11"; 1351 drive-strength = <2>; 1352 bias-pull-up; 1353 }; 1354 1355 blsp2_i2c6_default: blsp2-i2c6-default { 1356 pins = "gpio83", "gpio84"; 1357 function = "blsp_i2c12"; 1358 drive-strength = <2>; 1359 bias-disable; 1360 }; 1361 1362 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1363 pins = "gpio83", "gpio84"; 1364 function = "blsp_i2c12"; 1365 drive-strength = <2>; 1366 bias-pull-up; 1367 }; 1368 }; 1369 1370 remoteproc_mss: remoteproc@4080000 { 1371 compatible = "qcom,msm8998-mss-pil"; 1372 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1373 reg-names = "qdsp6", "rmb"; 1374 1375 interrupts-extended = 1376 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1377 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1378 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1379 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1380 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1381 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1382 interrupt-names = "wdog", "fatal", "ready", 1383 "handover", "stop-ack", 1384 "shutdown-ack"; 1385 1386 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1387 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1388 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1389 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1390 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1391 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1392 <&rpmcc RPM_SMD_QDSS_CLK>, 1393 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1394 clock-names = "iface", "bus", "mem", "gpll0_mss", 1395 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1396 1397 qcom,smem-states = <&modem_smp2p_out 0>; 1398 qcom,smem-state-names = "stop"; 1399 1400 resets = <&gcc GCC_MSS_RESTART>; 1401 reset-names = "mss_restart"; 1402 1403 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1404 1405 power-domains = <&rpmpd MSM8998_VDDCX>, 1406 <&rpmpd MSM8998_VDDMX>; 1407 power-domain-names = "cx", "mx"; 1408 1409 status = "disabled"; 1410 1411 mba { 1412 memory-region = <&mba_mem>; 1413 }; 1414 1415 mpss { 1416 memory-region = <&mpss_mem>; 1417 }; 1418 1419 glink-edge { 1420 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1421 label = "modem"; 1422 qcom,remote-pid = <1>; 1423 mboxes = <&apcs_glb 15>; 1424 }; 1425 }; 1426 1427 adreno_gpu: gpu@5000000 { 1428 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1429 reg = <0x05000000 0x40000>; 1430 reg-names = "kgsl_3d0_reg_memory"; 1431 1432 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1433 <&gpucc RBBMTIMER_CLK>, 1434 <&gcc GCC_BIMC_GFX_CLK>, 1435 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1436 <&gpucc RBCPR_CLK>, 1437 <&gpucc GFX3D_CLK>; 1438 clock-names = "iface", 1439 "rbbmtimer", 1440 "mem", 1441 "mem_iface", 1442 "rbcpr", 1443 "core"; 1444 1445 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1446 iommus = <&adreno_smmu 0>; 1447 operating-points-v2 = <&gpu_opp_table>; 1448 power-domains = <&rpmpd MSM8998_VDDMX>; 1449 #stream-id-cells = <16>; 1450 status = "disabled"; 1451 1452 gpu_opp_table: opp-table { 1453 compatible = "operating-points-v2"; 1454 opp-710000097 { 1455 opp-hz = /bits/ 64 <710000097>; 1456 opp-level = <RPM_SMD_LEVEL_TURBO>; 1457 opp-supported-hw = <0xFF>; 1458 }; 1459 1460 opp-670000048 { 1461 opp-hz = /bits/ 64 <670000048>; 1462 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1463 opp-supported-hw = <0xFF>; 1464 }; 1465 1466 opp-596000097 { 1467 opp-hz = /bits/ 64 <596000097>; 1468 opp-level = <RPM_SMD_LEVEL_NOM>; 1469 opp-supported-hw = <0xFF>; 1470 }; 1471 1472 opp-515000097 { 1473 opp-hz = /bits/ 64 <515000097>; 1474 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1475 opp-supported-hw = <0xFF>; 1476 }; 1477 1478 opp-414000000 { 1479 opp-hz = /bits/ 64 <414000000>; 1480 opp-level = <RPM_SMD_LEVEL_SVS>; 1481 opp-supported-hw = <0xFF>; 1482 }; 1483 1484 opp-342000000 { 1485 opp-hz = /bits/ 64 <342000000>; 1486 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1487 opp-supported-hw = <0xFF>; 1488 }; 1489 1490 opp-257000000 { 1491 opp-hz = /bits/ 64 <257000000>; 1492 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1493 opp-supported-hw = <0xFF>; 1494 }; 1495 }; 1496 }; 1497 1498 adreno_smmu: iommu@5040000 { 1499 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1500 reg = <0x05040000 0x10000>; 1501 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1502 <&gcc GCC_BIMC_GFX_CLK>, 1503 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1504 clock-names = "iface", "mem", "mem_iface"; 1505 1506 #global-interrupts = <0>; 1507 #iommu-cells = <1>; 1508 interrupts = 1509 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1512 /* 1513 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1514 * GPU-CX for SMMU but we need both of them up for Adreno. 1515 * Contemporarily, we also need to manage the VDDMX rpmpd 1516 * domain in the Adreno driver. 1517 * Enable GPU CX/GX GDSCs here so that we can manage the 1518 * SoC VDDMX RPM Power Domain in the Adreno driver. 1519 */ 1520 power-domains = <&gpucc GPU_GX_GDSC>; 1521 status = "disabled"; 1522 }; 1523 1524 gpucc: clock-controller@5065000 { 1525 compatible = "qcom,msm8998-gpucc"; 1526 #clock-cells = <1>; 1527 #reset-cells = <1>; 1528 #power-domain-cells = <1>; 1529 reg = <0x05065000 0x9000>; 1530 1531 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1532 <&gcc GPLL0_OUT_MAIN>; 1533 clock-names = "xo", 1534 "gpll0"; 1535 }; 1536 1537 remoteproc_slpi: remoteproc@5800000 { 1538 compatible = "qcom,msm8998-slpi-pas"; 1539 reg = <0x05800000 0x4040>; 1540 1541 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1542 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1543 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1544 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1545 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1546 interrupt-names = "wdog", "fatal", "ready", 1547 "handover", "stop-ack"; 1548 1549 px-supply = <&vreg_lvs2a_1p8>; 1550 1551 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1552 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1553 clock-names = "xo", "aggre2"; 1554 1555 memory-region = <&slpi_mem>; 1556 1557 qcom,smem-states = <&slpi_smp2p_out 0>; 1558 qcom,smem-state-names = "stop"; 1559 1560 power-domains = <&rpmpd MSM8998_SSCCX>; 1561 power-domain-names = "ssc_cx"; 1562 1563 status = "disabled"; 1564 1565 glink-edge { 1566 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1567 label = "dsps"; 1568 qcom,remote-pid = <3>; 1569 mboxes = <&apcs_glb 27>; 1570 }; 1571 }; 1572 1573 stm: stm@6002000 { 1574 compatible = "arm,coresight-stm", "arm,primecell"; 1575 reg = <0x06002000 0x1000>, 1576 <0x16280000 0x180000>; 1577 reg-names = "stm-base", "stm-data-base"; 1578 status = "disabled"; 1579 1580 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1581 clock-names = "apb_pclk", "atclk"; 1582 1583 out-ports { 1584 port { 1585 stm_out: endpoint { 1586 remote-endpoint = <&funnel0_in7>; 1587 }; 1588 }; 1589 }; 1590 }; 1591 1592 funnel1: funnel@6041000 { 1593 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1594 reg = <0x06041000 0x1000>; 1595 status = "disabled"; 1596 1597 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1598 clock-names = "apb_pclk", "atclk"; 1599 1600 out-ports { 1601 port { 1602 funnel0_out: endpoint { 1603 remote-endpoint = 1604 <&merge_funnel_in0>; 1605 }; 1606 }; 1607 }; 1608 1609 in-ports { 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 1613 port@7 { 1614 reg = <7>; 1615 funnel0_in7: endpoint { 1616 remote-endpoint = <&stm_out>; 1617 }; 1618 }; 1619 }; 1620 }; 1621 1622 funnel2: funnel@6042000 { 1623 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1624 reg = <0x06042000 0x1000>; 1625 status = "disabled"; 1626 1627 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1628 clock-names = "apb_pclk", "atclk"; 1629 1630 out-ports { 1631 port { 1632 funnel1_out: endpoint { 1633 remote-endpoint = 1634 <&merge_funnel_in1>; 1635 }; 1636 }; 1637 }; 1638 1639 in-ports { 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 1643 port@6 { 1644 reg = <6>; 1645 funnel1_in6: endpoint { 1646 remote-endpoint = 1647 <&apss_merge_funnel_out>; 1648 }; 1649 }; 1650 }; 1651 }; 1652 1653 funnel3: funnel@6045000 { 1654 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1655 reg = <0x06045000 0x1000>; 1656 status = "disabled"; 1657 1658 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1659 clock-names = "apb_pclk", "atclk"; 1660 1661 out-ports { 1662 port { 1663 merge_funnel_out: endpoint { 1664 remote-endpoint = 1665 <&etf_in>; 1666 }; 1667 }; 1668 }; 1669 1670 in-ports { 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 1674 port@0 { 1675 reg = <0>; 1676 merge_funnel_in0: endpoint { 1677 remote-endpoint = 1678 <&funnel0_out>; 1679 }; 1680 }; 1681 1682 port@1 { 1683 reg = <1>; 1684 merge_funnel_in1: endpoint { 1685 remote-endpoint = 1686 <&funnel1_out>; 1687 }; 1688 }; 1689 }; 1690 }; 1691 1692 replicator1: replicator@6046000 { 1693 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1694 reg = <0x06046000 0x1000>; 1695 status = "disabled"; 1696 1697 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1698 clock-names = "apb_pclk", "atclk"; 1699 1700 out-ports { 1701 port { 1702 replicator_out: endpoint { 1703 remote-endpoint = <&etr_in>; 1704 }; 1705 }; 1706 }; 1707 1708 in-ports { 1709 port { 1710 replicator_in: endpoint { 1711 remote-endpoint = <&etf_out>; 1712 }; 1713 }; 1714 }; 1715 }; 1716 1717 etf: etf@6047000 { 1718 compatible = "arm,coresight-tmc", "arm,primecell"; 1719 reg = <0x06047000 0x1000>; 1720 status = "disabled"; 1721 1722 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1723 clock-names = "apb_pclk", "atclk"; 1724 1725 out-ports { 1726 port { 1727 etf_out: endpoint { 1728 remote-endpoint = 1729 <&replicator_in>; 1730 }; 1731 }; 1732 }; 1733 1734 in-ports { 1735 port { 1736 etf_in: endpoint { 1737 remote-endpoint = 1738 <&merge_funnel_out>; 1739 }; 1740 }; 1741 }; 1742 }; 1743 1744 etr: etr@6048000 { 1745 compatible = "arm,coresight-tmc", "arm,primecell"; 1746 reg = <0x06048000 0x1000>; 1747 status = "disabled"; 1748 1749 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1750 clock-names = "apb_pclk", "atclk"; 1751 arm,scatter-gather; 1752 1753 in-ports { 1754 port { 1755 etr_in: endpoint { 1756 remote-endpoint = 1757 <&replicator_out>; 1758 }; 1759 }; 1760 }; 1761 }; 1762 1763 etm1: etm@7840000 { 1764 compatible = "arm,coresight-etm4x", "arm,primecell"; 1765 reg = <0x07840000 0x1000>; 1766 status = "disabled"; 1767 1768 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1769 clock-names = "apb_pclk", "atclk"; 1770 1771 cpu = <&CPU0>; 1772 1773 out-ports { 1774 port { 1775 etm0_out: endpoint { 1776 remote-endpoint = 1777 <&apss_funnel_in0>; 1778 }; 1779 }; 1780 }; 1781 }; 1782 1783 etm2: etm@7940000 { 1784 compatible = "arm,coresight-etm4x", "arm,primecell"; 1785 reg = <0x07940000 0x1000>; 1786 status = "disabled"; 1787 1788 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1789 clock-names = "apb_pclk", "atclk"; 1790 1791 cpu = <&CPU1>; 1792 1793 out-ports { 1794 port { 1795 etm1_out: endpoint { 1796 remote-endpoint = 1797 <&apss_funnel_in1>; 1798 }; 1799 }; 1800 }; 1801 }; 1802 1803 etm3: etm@7a40000 { 1804 compatible = "arm,coresight-etm4x", "arm,primecell"; 1805 reg = <0x07a40000 0x1000>; 1806 status = "disabled"; 1807 1808 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1809 clock-names = "apb_pclk", "atclk"; 1810 1811 cpu = <&CPU2>; 1812 1813 out-ports { 1814 port { 1815 etm2_out: endpoint { 1816 remote-endpoint = 1817 <&apss_funnel_in2>; 1818 }; 1819 }; 1820 }; 1821 }; 1822 1823 etm4: etm@7b40000 { 1824 compatible = "arm,coresight-etm4x", "arm,primecell"; 1825 reg = <0x07b40000 0x1000>; 1826 status = "disabled"; 1827 1828 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1829 clock-names = "apb_pclk", "atclk"; 1830 1831 cpu = <&CPU3>; 1832 1833 out-ports { 1834 port { 1835 etm3_out: endpoint { 1836 remote-endpoint = 1837 <&apss_funnel_in3>; 1838 }; 1839 }; 1840 }; 1841 }; 1842 1843 funnel4: funnel@7b60000 { /* APSS Funnel */ 1844 compatible = "arm,coresight-etm4x", "arm,primecell"; 1845 reg = <0x07b60000 0x1000>; 1846 status = "disabled"; 1847 1848 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1849 clock-names = "apb_pclk", "atclk"; 1850 1851 out-ports { 1852 port { 1853 apss_funnel_out: endpoint { 1854 remote-endpoint = 1855 <&apss_merge_funnel_in>; 1856 }; 1857 }; 1858 }; 1859 1860 in-ports { 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 1864 port@0 { 1865 reg = <0>; 1866 apss_funnel_in0: endpoint { 1867 remote-endpoint = 1868 <&etm0_out>; 1869 }; 1870 }; 1871 1872 port@1 { 1873 reg = <1>; 1874 apss_funnel_in1: endpoint { 1875 remote-endpoint = 1876 <&etm1_out>; 1877 }; 1878 }; 1879 1880 port@2 { 1881 reg = <2>; 1882 apss_funnel_in2: endpoint { 1883 remote-endpoint = 1884 <&etm2_out>; 1885 }; 1886 }; 1887 1888 port@3 { 1889 reg = <3>; 1890 apss_funnel_in3: endpoint { 1891 remote-endpoint = 1892 <&etm3_out>; 1893 }; 1894 }; 1895 1896 port@4 { 1897 reg = <4>; 1898 apss_funnel_in4: endpoint { 1899 remote-endpoint = 1900 <&etm4_out>; 1901 }; 1902 }; 1903 1904 port@5 { 1905 reg = <5>; 1906 apss_funnel_in5: endpoint { 1907 remote-endpoint = 1908 <&etm5_out>; 1909 }; 1910 }; 1911 1912 port@6 { 1913 reg = <6>; 1914 apss_funnel_in6: endpoint { 1915 remote-endpoint = 1916 <&etm6_out>; 1917 }; 1918 }; 1919 1920 port@7 { 1921 reg = <7>; 1922 apss_funnel_in7: endpoint { 1923 remote-endpoint = 1924 <&etm7_out>; 1925 }; 1926 }; 1927 }; 1928 }; 1929 1930 funnel5: funnel@7b70000 { 1931 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1932 reg = <0x07b70000 0x1000>; 1933 status = "disabled"; 1934 1935 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1936 clock-names = "apb_pclk", "atclk"; 1937 1938 out-ports { 1939 port { 1940 apss_merge_funnel_out: endpoint { 1941 remote-endpoint = 1942 <&funnel1_in6>; 1943 }; 1944 }; 1945 }; 1946 1947 in-ports { 1948 port { 1949 apss_merge_funnel_in: endpoint { 1950 remote-endpoint = 1951 <&apss_funnel_out>; 1952 }; 1953 }; 1954 }; 1955 }; 1956 1957 etm5: etm@7c40000 { 1958 compatible = "arm,coresight-etm4x", "arm,primecell"; 1959 reg = <0x07c40000 0x1000>; 1960 status = "disabled"; 1961 1962 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1963 clock-names = "apb_pclk", "atclk"; 1964 1965 cpu = <&CPU4>; 1966 1967 port{ 1968 etm4_out: endpoint { 1969 remote-endpoint = <&apss_funnel_in4>; 1970 }; 1971 }; 1972 }; 1973 1974 etm6: etm@7d40000 { 1975 compatible = "arm,coresight-etm4x", "arm,primecell"; 1976 reg = <0x07d40000 0x1000>; 1977 status = "disabled"; 1978 1979 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1980 clock-names = "apb_pclk", "atclk"; 1981 1982 cpu = <&CPU5>; 1983 1984 port{ 1985 etm5_out: endpoint { 1986 remote-endpoint = <&apss_funnel_in5>; 1987 }; 1988 }; 1989 }; 1990 1991 etm7: etm@7e40000 { 1992 compatible = "arm,coresight-etm4x", "arm,primecell"; 1993 reg = <0x07e40000 0x1000>; 1994 status = "disabled"; 1995 1996 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1997 clock-names = "apb_pclk", "atclk"; 1998 1999 cpu = <&CPU6>; 2000 2001 port{ 2002 etm6_out: endpoint { 2003 remote-endpoint = <&apss_funnel_in6>; 2004 }; 2005 }; 2006 }; 2007 2008 etm8: etm@7f40000 { 2009 compatible = "arm,coresight-etm4x", "arm,primecell"; 2010 reg = <0x07f40000 0x1000>; 2011 status = "disabled"; 2012 2013 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2014 clock-names = "apb_pclk", "atclk"; 2015 2016 cpu = <&CPU7>; 2017 2018 port{ 2019 etm7_out: endpoint { 2020 remote-endpoint = <&apss_funnel_in7>; 2021 }; 2022 }; 2023 }; 2024 2025 sram@290000 { 2026 compatible = "qcom,rpm-stats"; 2027 reg = <0x00290000 0x10000>; 2028 }; 2029 2030 spmi_bus: spmi@800f000 { 2031 compatible = "qcom,spmi-pmic-arb"; 2032 reg = <0x0800f000 0x1000>, 2033 <0x08400000 0x1000000>, 2034 <0x09400000 0x1000000>, 2035 <0x0a400000 0x220000>, 2036 <0x0800a000 0x3000>; 2037 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2038 interrupt-names = "periph_irq"; 2039 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2040 qcom,ee = <0>; 2041 qcom,channel = <0>; 2042 #address-cells = <2>; 2043 #size-cells = <0>; 2044 interrupt-controller; 2045 #interrupt-cells = <4>; 2046 cell-index = <0>; 2047 }; 2048 2049 usb3: usb@a8f8800 { 2050 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2051 reg = <0x0a8f8800 0x400>; 2052 status = "disabled"; 2053 #address-cells = <1>; 2054 #size-cells = <1>; 2055 ranges; 2056 2057 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2058 <&gcc GCC_USB30_MASTER_CLK>, 2059 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2060 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2061 <&gcc GCC_USB30_SLEEP_CLK>; 2062 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2063 "sleep"; 2064 2065 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2066 <&gcc GCC_USB30_MASTER_CLK>; 2067 assigned-clock-rates = <19200000>, <120000000>; 2068 2069 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2071 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2072 2073 power-domains = <&gcc USB_30_GDSC>; 2074 2075 resets = <&gcc GCC_USB_30_BCR>; 2076 2077 usb3_dwc3: dwc3@a800000 { 2078 compatible = "snps,dwc3"; 2079 reg = <0x0a800000 0xcd00>; 2080 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2081 snps,dis_u2_susphy_quirk; 2082 snps,dis_enblslpm_quirk; 2083 phys = <&qusb2phy>, <&usb1_ssphy>; 2084 phy-names = "usb2-phy", "usb3-phy"; 2085 snps,has-lpm-erratum; 2086 snps,hird-threshold = /bits/ 8 <0x10>; 2087 }; 2088 }; 2089 2090 usb3phy: phy@c010000 { 2091 compatible = "qcom,msm8998-qmp-usb3-phy"; 2092 reg = <0x0c010000 0x18c>; 2093 status = "disabled"; 2094 #address-cells = <1>; 2095 #size-cells = <1>; 2096 ranges; 2097 2098 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2099 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2100 <&gcc GCC_USB3_CLKREF_CLK>; 2101 clock-names = "aux", "cfg_ahb", "ref"; 2102 2103 resets = <&gcc GCC_USB3_PHY_BCR>, 2104 <&gcc GCC_USB3PHY_PHY_BCR>; 2105 reset-names = "phy", "common"; 2106 2107 usb1_ssphy: phy@c010200 { 2108 reg = <0xc010200 0x128>, 2109 <0xc010400 0x200>, 2110 <0xc010c00 0x20c>, 2111 <0xc010600 0x128>, 2112 <0xc010800 0x200>; 2113 #phy-cells = <0>; 2114 #clock-cells = <1>; 2115 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2116 clock-names = "pipe0"; 2117 clock-output-names = "usb3_phy_pipe_clk_src"; 2118 }; 2119 }; 2120 2121 qusb2phy: phy@c012000 { 2122 compatible = "qcom,msm8998-qusb2-phy"; 2123 reg = <0x0c012000 0x2a8>; 2124 status = "disabled"; 2125 #phy-cells = <0>; 2126 2127 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2128 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2129 clock-names = "cfg_ahb", "ref"; 2130 2131 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2132 2133 nvmem-cells = <&qusb2_hstx_trim>; 2134 }; 2135 2136 sdhc2: sdhci@c0a4900 { 2137 compatible = "qcom,sdhci-msm-v4"; 2138 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2139 reg-names = "hc_mem", "core_mem"; 2140 2141 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2143 interrupt-names = "hc_irq", "pwr_irq"; 2144 2145 clock-names = "iface", "core", "xo"; 2146 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2147 <&gcc GCC_SDCC2_APPS_CLK>, 2148 <&xo>; 2149 bus-width = <4>; 2150 status = "disabled"; 2151 }; 2152 2153 blsp1_dma: dma-controller@c144000 { 2154 compatible = "qcom,bam-v1.7.0"; 2155 reg = <0x0c144000 0x25000>; 2156 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2157 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2158 clock-names = "bam_clk"; 2159 #dma-cells = <1>; 2160 qcom,ee = <0>; 2161 qcom,controlled-remotely; 2162 num-channels = <18>; 2163 qcom,num-ees = <4>; 2164 }; 2165 2166 blsp1_uart3: serial@c171000 { 2167 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2168 reg = <0x0c171000 0x1000>; 2169 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2170 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2171 <&gcc GCC_BLSP1_AHB_CLK>; 2172 clock-names = "core", "iface"; 2173 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2174 dma-names = "tx", "rx"; 2175 pinctrl-names = "default"; 2176 pinctrl-0 = <&blsp1_uart3_on>; 2177 status = "disabled"; 2178 }; 2179 2180 blsp1_i2c1: i2c@c175000 { 2181 compatible = "qcom,i2c-qup-v2.2.1"; 2182 reg = <0x0c175000 0x600>; 2183 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2184 2185 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2186 <&gcc GCC_BLSP1_AHB_CLK>; 2187 clock-names = "core", "iface"; 2188 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2189 dma-names = "tx", "rx"; 2190 pinctrl-names = "default", "sleep"; 2191 pinctrl-0 = <&blsp1_i2c1_default>; 2192 pinctrl-1 = <&blsp1_i2c1_sleep>; 2193 clock-frequency = <400000>; 2194 2195 status = "disabled"; 2196 #address-cells = <1>; 2197 #size-cells = <0>; 2198 }; 2199 2200 blsp1_i2c2: i2c@c176000 { 2201 compatible = "qcom,i2c-qup-v2.2.1"; 2202 reg = <0x0c176000 0x600>; 2203 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2204 2205 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2206 <&gcc GCC_BLSP1_AHB_CLK>; 2207 clock-names = "core", "iface"; 2208 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2209 dma-names = "tx", "rx"; 2210 pinctrl-names = "default", "sleep"; 2211 pinctrl-0 = <&blsp1_i2c2_default>; 2212 pinctrl-1 = <&blsp1_i2c2_sleep>; 2213 clock-frequency = <400000>; 2214 2215 status = "disabled"; 2216 #address-cells = <1>; 2217 #size-cells = <0>; 2218 }; 2219 2220 blsp1_i2c3: i2c@c177000 { 2221 compatible = "qcom,i2c-qup-v2.2.1"; 2222 reg = <0x0c177000 0x600>; 2223 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2224 2225 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2226 <&gcc GCC_BLSP1_AHB_CLK>; 2227 clock-names = "core", "iface"; 2228 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2229 dma-names = "tx", "rx"; 2230 pinctrl-names = "default", "sleep"; 2231 pinctrl-0 = <&blsp1_i2c3_default>; 2232 pinctrl-1 = <&blsp1_i2c3_sleep>; 2233 clock-frequency = <400000>; 2234 2235 status = "disabled"; 2236 #address-cells = <1>; 2237 #size-cells = <0>; 2238 }; 2239 2240 blsp1_i2c4: i2c@c178000 { 2241 compatible = "qcom,i2c-qup-v2.2.1"; 2242 reg = <0x0c178000 0x600>; 2243 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2244 2245 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2246 <&gcc GCC_BLSP1_AHB_CLK>; 2247 clock-names = "core", "iface"; 2248 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2249 dma-names = "tx", "rx"; 2250 pinctrl-names = "default", "sleep"; 2251 pinctrl-0 = <&blsp1_i2c4_default>; 2252 pinctrl-1 = <&blsp1_i2c4_sleep>; 2253 clock-frequency = <400000>; 2254 2255 status = "disabled"; 2256 #address-cells = <1>; 2257 #size-cells = <0>; 2258 }; 2259 2260 blsp1_i2c5: i2c@c179000 { 2261 compatible = "qcom,i2c-qup-v2.2.1"; 2262 reg = <0x0c179000 0x600>; 2263 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2264 2265 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2266 <&gcc GCC_BLSP1_AHB_CLK>; 2267 clock-names = "core", "iface"; 2268 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2269 dma-names = "tx", "rx"; 2270 pinctrl-names = "default", "sleep"; 2271 pinctrl-0 = <&blsp1_i2c5_default>; 2272 pinctrl-1 = <&blsp1_i2c5_sleep>; 2273 clock-frequency = <400000>; 2274 2275 status = "disabled"; 2276 #address-cells = <1>; 2277 #size-cells = <0>; 2278 }; 2279 2280 blsp1_i2c6: i2c@c17a000 { 2281 compatible = "qcom,i2c-qup-v2.2.1"; 2282 reg = <0x0c17a000 0x600>; 2283 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2284 2285 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2286 <&gcc GCC_BLSP1_AHB_CLK>; 2287 clock-names = "core", "iface"; 2288 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2289 dma-names = "tx", "rx"; 2290 pinctrl-names = "default", "sleep"; 2291 pinctrl-0 = <&blsp1_i2c6_default>; 2292 pinctrl-1 = <&blsp1_i2c6_sleep>; 2293 clock-frequency = <400000>; 2294 2295 status = "disabled"; 2296 #address-cells = <1>; 2297 #size-cells = <0>; 2298 }; 2299 2300 blsp2_dma: dma-controller@c184000 { 2301 compatible = "qcom,bam-v1.7.0"; 2302 reg = <0x0c184000 0x25000>; 2303 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2304 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2305 clock-names = "bam_clk"; 2306 #dma-cells = <1>; 2307 qcom,ee = <0>; 2308 qcom,controlled-remotely; 2309 num-channels = <18>; 2310 qcom,num-ees = <4>; 2311 }; 2312 2313 blsp2_uart1: serial@c1b0000 { 2314 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2315 reg = <0x0c1b0000 0x1000>; 2316 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2317 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2318 <&gcc GCC_BLSP2_AHB_CLK>; 2319 clock-names = "core", "iface"; 2320 status = "disabled"; 2321 }; 2322 2323 blsp2_i2c1: i2c@c1b5000 { 2324 compatible = "qcom,i2c-qup-v2.2.1"; 2325 reg = <0x0c1b5000 0x600>; 2326 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2327 2328 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2329 <&gcc GCC_BLSP2_AHB_CLK>; 2330 clock-names = "core", "iface"; 2331 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2332 dma-names = "tx", "rx"; 2333 pinctrl-names = "default", "sleep"; 2334 pinctrl-0 = <&blsp2_i2c1_default>; 2335 pinctrl-1 = <&blsp2_i2c1_sleep>; 2336 clock-frequency = <400000>; 2337 2338 status = "disabled"; 2339 #address-cells = <1>; 2340 #size-cells = <0>; 2341 }; 2342 2343 blsp2_i2c2: i2c@c1b6000 { 2344 compatible = "qcom,i2c-qup-v2.2.1"; 2345 reg = <0x0c1b6000 0x600>; 2346 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2347 2348 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2349 <&gcc GCC_BLSP2_AHB_CLK>; 2350 clock-names = "core", "iface"; 2351 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2352 dma-names = "tx", "rx"; 2353 pinctrl-names = "default", "sleep"; 2354 pinctrl-0 = <&blsp2_i2c2_default>; 2355 pinctrl-1 = <&blsp2_i2c2_sleep>; 2356 clock-frequency = <400000>; 2357 2358 status = "disabled"; 2359 #address-cells = <1>; 2360 #size-cells = <0>; 2361 }; 2362 2363 blsp2_i2c3: i2c@c1b7000 { 2364 compatible = "qcom,i2c-qup-v2.2.1"; 2365 reg = <0x0c1b7000 0x600>; 2366 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2367 2368 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2369 <&gcc GCC_BLSP2_AHB_CLK>; 2370 clock-names = "core", "iface"; 2371 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2372 dma-names = "tx", "rx"; 2373 pinctrl-names = "default", "sleep"; 2374 pinctrl-0 = <&blsp2_i2c3_default>; 2375 pinctrl-1 = <&blsp2_i2c3_sleep>; 2376 clock-frequency = <400000>; 2377 2378 status = "disabled"; 2379 #address-cells = <1>; 2380 #size-cells = <0>; 2381 }; 2382 2383 blsp2_i2c4: i2c@c1b8000 { 2384 compatible = "qcom,i2c-qup-v2.2.1"; 2385 reg = <0x0c1b8000 0x600>; 2386 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2387 2388 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2389 <&gcc GCC_BLSP2_AHB_CLK>; 2390 clock-names = "core", "iface"; 2391 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2392 dma-names = "tx", "rx"; 2393 pinctrl-names = "default", "sleep"; 2394 pinctrl-0 = <&blsp2_i2c4_default>; 2395 pinctrl-1 = <&blsp2_i2c4_sleep>; 2396 clock-frequency = <400000>; 2397 2398 status = "disabled"; 2399 #address-cells = <1>; 2400 #size-cells = <0>; 2401 }; 2402 2403 blsp2_i2c5: i2c@c1b9000 { 2404 compatible = "qcom,i2c-qup-v2.2.1"; 2405 reg = <0x0c1b9000 0x600>; 2406 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2407 2408 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2409 <&gcc GCC_BLSP2_AHB_CLK>; 2410 clock-names = "core", "iface"; 2411 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2412 dma-names = "tx", "rx"; 2413 pinctrl-names = "default", "sleep"; 2414 pinctrl-0 = <&blsp2_i2c5_default>; 2415 pinctrl-1 = <&blsp2_i2c5_sleep>; 2416 clock-frequency = <400000>; 2417 2418 status = "disabled"; 2419 #address-cells = <1>; 2420 #size-cells = <0>; 2421 }; 2422 2423 blsp2_i2c6: i2c@c1ba000 { 2424 compatible = "qcom,i2c-qup-v2.2.1"; 2425 reg = <0x0c1ba000 0x600>; 2426 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2427 2428 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2429 <&gcc GCC_BLSP2_AHB_CLK>; 2430 clock-names = "core", "iface"; 2431 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2432 dma-names = "tx", "rx"; 2433 pinctrl-names = "default", "sleep"; 2434 pinctrl-0 = <&blsp2_i2c6_default>; 2435 pinctrl-1 = <&blsp2_i2c6_sleep>; 2436 clock-frequency = <400000>; 2437 2438 status = "disabled"; 2439 #address-cells = <1>; 2440 #size-cells = <0>; 2441 }; 2442 2443 mmcc: clock-controller@c8c0000 { 2444 compatible = "qcom,mmcc-msm8998"; 2445 #clock-cells = <1>; 2446 #reset-cells = <1>; 2447 #power-domain-cells = <1>; 2448 reg = <0xc8c0000 0x40000>; 2449 status = "disabled"; 2450 2451 clock-names = "xo", 2452 "gpll0", 2453 "dsi0dsi", 2454 "dsi0byte", 2455 "dsi1dsi", 2456 "dsi1byte", 2457 "hdmipll", 2458 "dplink", 2459 "dpvco", 2460 "core_bi_pll_test_se"; 2461 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2462 <&gcc GCC_MMSS_GPLL0_CLK>, 2463 <0>, 2464 <0>, 2465 <0>, 2466 <0>, 2467 <0>, 2468 <0>, 2469 <0>, 2470 <0>; 2471 }; 2472 2473 mmss_smmu: iommu@cd00000 { 2474 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 2475 reg = <0x0cd00000 0x40000>; 2476 #iommu-cells = <1>; 2477 2478 clocks = <&mmcc MNOC_AHB_CLK>, 2479 <&mmcc BIMC_SMMU_AHB_CLK>, 2480 <&rpmcc RPM_SMD_MMAXI_CLK>, 2481 <&mmcc BIMC_SMMU_AXI_CLK>; 2482 clock-names = "iface-mm", "iface-smmu", 2483 "bus-mm", "bus-smmu"; 2484 status = "disabled"; 2485 2486 #global-interrupts = <0>; 2487 interrupts = 2488 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2508 }; 2509 2510 remoteproc_adsp: remoteproc@17300000 { 2511 compatible = "qcom,msm8998-adsp-pas"; 2512 reg = <0x17300000 0x4040>; 2513 2514 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2515 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2516 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2517 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2518 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2519 interrupt-names = "wdog", "fatal", "ready", 2520 "handover", "stop-ack"; 2521 2522 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2523 clock-names = "xo"; 2524 2525 memory-region = <&adsp_mem>; 2526 2527 qcom,smem-states = <&adsp_smp2p_out 0>; 2528 qcom,smem-state-names = "stop"; 2529 2530 power-domains = <&rpmpd MSM8998_VDDCX>; 2531 power-domain-names = "cx"; 2532 2533 status = "disabled"; 2534 2535 glink-edge { 2536 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2537 label = "lpass"; 2538 qcom,remote-pid = <2>; 2539 mboxes = <&apcs_glb 9>; 2540 }; 2541 }; 2542 2543 apcs_glb: mailbox@17911000 { 2544 compatible = "qcom,msm8998-apcs-hmss-global"; 2545 reg = <0x17911000 0x1000>; 2546 2547 #mbox-cells = <1>; 2548 }; 2549 2550 timer@17920000 { 2551 #address-cells = <1>; 2552 #size-cells = <1>; 2553 ranges; 2554 compatible = "arm,armv7-timer-mem"; 2555 reg = <0x17920000 0x1000>; 2556 2557 frame@17921000 { 2558 frame-number = <0>; 2559 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2560 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2561 reg = <0x17921000 0x1000>, 2562 <0x17922000 0x1000>; 2563 }; 2564 2565 frame@17923000 { 2566 frame-number = <1>; 2567 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2568 reg = <0x17923000 0x1000>; 2569 status = "disabled"; 2570 }; 2571 2572 frame@17924000 { 2573 frame-number = <2>; 2574 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2575 reg = <0x17924000 0x1000>; 2576 status = "disabled"; 2577 }; 2578 2579 frame@17925000 { 2580 frame-number = <3>; 2581 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2582 reg = <0x17925000 0x1000>; 2583 status = "disabled"; 2584 }; 2585 2586 frame@17926000 { 2587 frame-number = <4>; 2588 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2589 reg = <0x17926000 0x1000>; 2590 status = "disabled"; 2591 }; 2592 2593 frame@17927000 { 2594 frame-number = <5>; 2595 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2596 reg = <0x17927000 0x1000>; 2597 status = "disabled"; 2598 }; 2599 2600 frame@17928000 { 2601 frame-number = <6>; 2602 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2603 reg = <0x17928000 0x1000>; 2604 status = "disabled"; 2605 }; 2606 }; 2607 2608 intc: interrupt-controller@17a00000 { 2609 compatible = "arm,gic-v3"; 2610 reg = <0x17a00000 0x10000>, /* GICD */ 2611 <0x17b00000 0x100000>; /* GICR * 8 */ 2612 #interrupt-cells = <3>; 2613 #address-cells = <1>; 2614 #size-cells = <1>; 2615 ranges; 2616 interrupt-controller; 2617 #redistributor-regions = <1>; 2618 redistributor-stride = <0x0 0x20000>; 2619 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2620 }; 2621 2622 wifi: wifi@18800000 { 2623 compatible = "qcom,wcn3990-wifi"; 2624 status = "disabled"; 2625 reg = <0x18800000 0x800000>; 2626 reg-names = "membase"; 2627 memory-region = <&wlan_msa_mem>; 2628 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2629 clock-names = "cxo_ref_clk_pin"; 2630 interrupts = 2631 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2632 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2633 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2635 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2636 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2637 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2638 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2639 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2640 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2641 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2642 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2643 iommus = <&anoc2_smmu 0x1900>, 2644 <&anoc2_smmu 0x1901>; 2645 qcom,snoc-host-cap-8bit-quirk; 2646 }; 2647 }; 2648}; 2649