1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 qcom,msm-id = <292 0x0>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 memory@80000000 { 23 device_type = "memory"; 24 /* We expect the bootloader to fill in the reg */ 25 reg = <0x0 0x80000000 0x0 0x0>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 hyp_mem: memory@85800000 { 34 reg = <0x0 0x85800000 0x0 0x600000>; 35 no-map; 36 }; 37 38 xbl_mem: memory@85e00000 { 39 reg = <0x0 0x85e00000 0x0 0x100000>; 40 no-map; 41 }; 42 43 smem_mem: smem-mem@86000000 { 44 reg = <0x0 0x86000000 0x0 0x200000>; 45 no-map; 46 }; 47 48 tz_mem: memory@86200000 { 49 reg = <0x0 0x86200000 0x0 0x2d00000>; 50 no-map; 51 }; 52 53 rmtfs_mem: memory@88f00000 { 54 compatible = "qcom,rmtfs-mem"; 55 reg = <0x0 0x88f00000 0x0 0x200000>; 56 no-map; 57 58 qcom,client-id = <1>; 59 qcom,vmid = <15>; 60 }; 61 62 spss_mem: memory@8ab00000 { 63 reg = <0x0 0x8ab00000 0x0 0x700000>; 64 no-map; 65 }; 66 67 adsp_mem: memory@8b200000 { 68 reg = <0x0 0x8b200000 0x0 0x1a00000>; 69 no-map; 70 }; 71 72 mpss_mem: memory@8cc00000 { 73 reg = <0x0 0x8cc00000 0x0 0x7000000>; 74 no-map; 75 }; 76 77 venus_mem: memory@93c00000 { 78 reg = <0x0 0x93c00000 0x0 0x500000>; 79 no-map; 80 }; 81 82 mba_mem: memory@94100000 { 83 reg = <0x0 0x94100000 0x0 0x200000>; 84 no-map; 85 }; 86 87 slpi_mem: memory@94300000 { 88 reg = <0x0 0x94300000 0x0 0xf00000>; 89 no-map; 90 }; 91 92 ipa_fw_mem: memory@95200000 { 93 reg = <0x0 0x95200000 0x0 0x10000>; 94 no-map; 95 }; 96 97 ipa_gsi_mem: memory@95210000 { 98 reg = <0x0 0x95210000 0x0 0x5000>; 99 no-map; 100 }; 101 102 gpu_mem: memory@95600000 { 103 reg = <0x0 0x95600000 0x0 0x100000>; 104 no-map; 105 }; 106 107 wlan_msa_mem: memory@95700000 { 108 reg = <0x0 0x95700000 0x0 0x100000>; 109 no-map; 110 }; 111 }; 112 113 clocks { 114 xo: xo-board { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <19200000>; 118 clock-output-names = "xo_board"; 119 }; 120 121 sleep_clk: sleep-clk { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <32764>; 125 }; 126 }; 127 128 cpus { 129 #address-cells = <2>; 130 #size-cells = <0>; 131 132 CPU0: cpu@0 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo280"; 135 reg = <0x0 0x0>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 139 next-level-cache = <&L2_0>; 140 L2_0: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 }; 144 }; 145 146 CPU1: cpu@1 { 147 device_type = "cpu"; 148 compatible = "qcom,kryo280"; 149 reg = <0x0 0x1>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <1024>; 152 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 153 next-level-cache = <&L2_0>; 154 }; 155 156 CPU2: cpu@2 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo280"; 159 reg = <0x0 0x2>; 160 enable-method = "psci"; 161 capacity-dmips-mhz = <1024>; 162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 163 next-level-cache = <&L2_0>; 164 }; 165 166 CPU3: cpu@3 { 167 device_type = "cpu"; 168 compatible = "qcom,kryo280"; 169 reg = <0x0 0x3>; 170 enable-method = "psci"; 171 capacity-dmips-mhz = <1024>; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 173 next-level-cache = <&L2_0>; 174 }; 175 176 CPU4: cpu@100 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo280"; 179 reg = <0x0 0x100>; 180 enable-method = "psci"; 181 capacity-dmips-mhz = <1536>; 182 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 183 next-level-cache = <&L2_1>; 184 L2_1: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 }; 188 }; 189 190 CPU5: cpu@101 { 191 device_type = "cpu"; 192 compatible = "qcom,kryo280"; 193 reg = <0x0 0x101>; 194 enable-method = "psci"; 195 capacity-dmips-mhz = <1536>; 196 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 197 next-level-cache = <&L2_1>; 198 }; 199 200 CPU6: cpu@102 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo280"; 203 reg = <0x0 0x102>; 204 enable-method = "psci"; 205 capacity-dmips-mhz = <1536>; 206 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 207 next-level-cache = <&L2_1>; 208 }; 209 210 CPU7: cpu@103 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo280"; 213 reg = <0x0 0x103>; 214 enable-method = "psci"; 215 capacity-dmips-mhz = <1536>; 216 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 217 next-level-cache = <&L2_1>; 218 }; 219 220 cpu-map { 221 cluster0 { 222 core0 { 223 cpu = <&CPU0>; 224 }; 225 226 core1 { 227 cpu = <&CPU1>; 228 }; 229 230 core2 { 231 cpu = <&CPU2>; 232 }; 233 234 core3 { 235 cpu = <&CPU3>; 236 }; 237 }; 238 239 cluster1 { 240 core0 { 241 cpu = <&CPU4>; 242 }; 243 244 core1 { 245 cpu = <&CPU5>; 246 }; 247 248 core2 { 249 cpu = <&CPU6>; 250 }; 251 252 core3 { 253 cpu = <&CPU7>; 254 }; 255 }; 256 }; 257 258 idle-states { 259 entry-method = "psci"; 260 261 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "little-retention"; 264 /* CPU Retention (C2D), L2 Active */ 265 arm,psci-suspend-param = <0x00000002>; 266 entry-latency-us = <81>; 267 exit-latency-us = <86>; 268 min-residency-us = <504>; 269 }; 270 271 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "little-power-collapse"; 274 /* CPU + L2 Power Collapse (C3, D4) */ 275 arm,psci-suspend-param = <0x40000003>; 276 entry-latency-us = <814>; 277 exit-latency-us = <4562>; 278 min-residency-us = <9183>; 279 local-timer-stop; 280 }; 281 282 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "big-retention"; 285 /* CPU Retention (C2D), L2 Active */ 286 arm,psci-suspend-param = <0x00000002>; 287 entry-latency-us = <79>; 288 exit-latency-us = <82>; 289 min-residency-us = <1302>; 290 }; 291 292 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 293 compatible = "arm,idle-state"; 294 idle-state-name = "big-power-collapse"; 295 /* CPU + L2 Power Collapse (C3, D4) */ 296 arm,psci-suspend-param = <0x40000003>; 297 entry-latency-us = <724>; 298 exit-latency-us = <2027>; 299 min-residency-us = <9419>; 300 local-timer-stop; 301 }; 302 }; 303 }; 304 305 firmware { 306 scm { 307 compatible = "qcom,scm-msm8998", "qcom,scm"; 308 }; 309 }; 310 311 tcsr_mutex: hwlock { 312 compatible = "qcom,tcsr-mutex"; 313 syscon = <&tcsr_mutex_regs 0 0x1000>; 314 #hwlock-cells = <1>; 315 }; 316 317 psci { 318 compatible = "arm,psci-1.0"; 319 method = "smc"; 320 }; 321 322 rpm-glink { 323 compatible = "qcom,glink-rpm"; 324 325 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 326 qcom,rpm-msg-ram = <&rpm_msg_ram>; 327 mboxes = <&apcs_glb 0>; 328 329 rpm_requests: rpm-requests { 330 compatible = "qcom,rpm-msm8998"; 331 qcom,glink-channels = "rpm_requests"; 332 333 rpmcc: clock-controller { 334 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 335 #clock-cells = <1>; 336 }; 337 338 rpmpd: power-controller { 339 compatible = "qcom,msm8998-rpmpd"; 340 #power-domain-cells = <1>; 341 operating-points-v2 = <&rpmpd_opp_table>; 342 343 rpmpd_opp_table: opp-table { 344 compatible = "operating-points-v2"; 345 346 rpmpd_opp_ret: opp1 { 347 opp-level = <RPM_SMD_LEVEL_RETENTION>; 348 }; 349 350 rpmpd_opp_ret_plus: opp2 { 351 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 352 }; 353 354 rpmpd_opp_min_svs: opp3 { 355 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 356 }; 357 358 rpmpd_opp_low_svs: opp4 { 359 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 360 }; 361 362 rpmpd_opp_svs: opp5 { 363 opp-level = <RPM_SMD_LEVEL_SVS>; 364 }; 365 366 rpmpd_opp_svs_plus: opp6 { 367 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 368 }; 369 370 rpmpd_opp_nom: opp7 { 371 opp-level = <RPM_SMD_LEVEL_NOM>; 372 }; 373 374 rpmpd_opp_nom_plus: opp8 { 375 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 376 }; 377 378 rpmpd_opp_turbo: opp9 { 379 opp-level = <RPM_SMD_LEVEL_TURBO>; 380 }; 381 382 rpmpd_opp_turbo_plus: opp10 { 383 opp-level = <RPM_SMD_LEVEL_BINNING>; 384 }; 385 }; 386 }; 387 }; 388 }; 389 390 smem { 391 compatible = "qcom,smem"; 392 memory-region = <&smem_mem>; 393 hwlocks = <&tcsr_mutex 3>; 394 }; 395 396 smp2p-lpass { 397 compatible = "qcom,smp2p"; 398 qcom,smem = <443>, <429>; 399 400 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 401 402 mboxes = <&apcs_glb 10>; 403 404 qcom,local-pid = <0>; 405 qcom,remote-pid = <2>; 406 407 adsp_smp2p_out: master-kernel { 408 qcom,entry-name = "master-kernel"; 409 #qcom,smem-state-cells = <1>; 410 }; 411 412 adsp_smp2p_in: slave-kernel { 413 qcom,entry-name = "slave-kernel"; 414 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 smp2p-mpss { 421 compatible = "qcom,smp2p"; 422 qcom,smem = <435>, <428>; 423 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 424 mboxes = <&apcs_glb 14>; 425 qcom,local-pid = <0>; 426 qcom,remote-pid = <1>; 427 428 modem_smp2p_out: master-kernel { 429 qcom,entry-name = "master-kernel"; 430 #qcom,smem-state-cells = <1>; 431 }; 432 433 modem_smp2p_in: slave-kernel { 434 qcom,entry-name = "slave-kernel"; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 }; 438 }; 439 440 smp2p-slpi { 441 compatible = "qcom,smp2p"; 442 qcom,smem = <481>, <430>; 443 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 444 mboxes = <&apcs_glb 26>; 445 qcom,local-pid = <0>; 446 qcom,remote-pid = <3>; 447 448 slpi_smp2p_out: master-kernel { 449 qcom,entry-name = "master-kernel"; 450 #qcom,smem-state-cells = <1>; 451 }; 452 453 slpi_smp2p_in: slave-kernel { 454 qcom,entry-name = "slave-kernel"; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 }; 458 }; 459 460 thermal-zones { 461 cpu0-thermal { 462 polling-delay-passive = <250>; 463 polling-delay = <1000>; 464 465 thermal-sensors = <&tsens0 1>; 466 467 trips { 468 cpu0_alert0: trip-point0 { 469 temperature = <75000>; 470 hysteresis = <2000>; 471 type = "passive"; 472 }; 473 474 cpu0_crit: cpu_crit { 475 temperature = <110000>; 476 hysteresis = <2000>; 477 type = "critical"; 478 }; 479 }; 480 }; 481 482 cpu1-thermal { 483 polling-delay-passive = <250>; 484 polling-delay = <1000>; 485 486 thermal-sensors = <&tsens0 2>; 487 488 trips { 489 cpu1_alert0: trip-point0 { 490 temperature = <75000>; 491 hysteresis = <2000>; 492 type = "passive"; 493 }; 494 495 cpu1_crit: cpu_crit { 496 temperature = <110000>; 497 hysteresis = <2000>; 498 type = "critical"; 499 }; 500 }; 501 }; 502 503 cpu2-thermal { 504 polling-delay-passive = <250>; 505 polling-delay = <1000>; 506 507 thermal-sensors = <&tsens0 3>; 508 509 trips { 510 cpu2_alert0: trip-point0 { 511 temperature = <75000>; 512 hysteresis = <2000>; 513 type = "passive"; 514 }; 515 516 cpu2_crit: cpu_crit { 517 temperature = <110000>; 518 hysteresis = <2000>; 519 type = "critical"; 520 }; 521 }; 522 }; 523 524 cpu3-thermal { 525 polling-delay-passive = <250>; 526 polling-delay = <1000>; 527 528 thermal-sensors = <&tsens0 4>; 529 530 trips { 531 cpu3_alert0: trip-point0 { 532 temperature = <75000>; 533 hysteresis = <2000>; 534 type = "passive"; 535 }; 536 537 cpu3_crit: cpu_crit { 538 temperature = <110000>; 539 hysteresis = <2000>; 540 type = "critical"; 541 }; 542 }; 543 }; 544 545 cpu4-thermal { 546 polling-delay-passive = <250>; 547 polling-delay = <1000>; 548 549 thermal-sensors = <&tsens0 7>; 550 551 trips { 552 cpu4_alert0: trip-point0 { 553 temperature = <75000>; 554 hysteresis = <2000>; 555 type = "passive"; 556 }; 557 558 cpu4_crit: cpu_crit { 559 temperature = <110000>; 560 hysteresis = <2000>; 561 type = "critical"; 562 }; 563 }; 564 }; 565 566 cpu5-thermal { 567 polling-delay-passive = <250>; 568 polling-delay = <1000>; 569 570 thermal-sensors = <&tsens0 8>; 571 572 trips { 573 cpu5_alert0: trip-point0 { 574 temperature = <75000>; 575 hysteresis = <2000>; 576 type = "passive"; 577 }; 578 579 cpu5_crit: cpu_crit { 580 temperature = <110000>; 581 hysteresis = <2000>; 582 type = "critical"; 583 }; 584 }; 585 }; 586 587 cpu6-thermal { 588 polling-delay-passive = <250>; 589 polling-delay = <1000>; 590 591 thermal-sensors = <&tsens0 9>; 592 593 trips { 594 cpu6_alert0: trip-point0 { 595 temperature = <75000>; 596 hysteresis = <2000>; 597 type = "passive"; 598 }; 599 600 cpu6_crit: cpu_crit { 601 temperature = <110000>; 602 hysteresis = <2000>; 603 type = "critical"; 604 }; 605 }; 606 }; 607 608 cpu7-thermal { 609 polling-delay-passive = <250>; 610 polling-delay = <1000>; 611 612 thermal-sensors = <&tsens0 10>; 613 614 trips { 615 cpu7_alert0: trip-point0 { 616 temperature = <75000>; 617 hysteresis = <2000>; 618 type = "passive"; 619 }; 620 621 cpu7_crit: cpu_crit { 622 temperature = <110000>; 623 hysteresis = <2000>; 624 type = "critical"; 625 }; 626 }; 627 }; 628 629 gpu-bottom-thermal { 630 polling-delay-passive = <250>; 631 polling-delay = <1000>; 632 633 thermal-sensors = <&tsens0 12>; 634 635 trips { 636 gpu1_alert0: trip-point0 { 637 temperature = <90000>; 638 hysteresis = <2000>; 639 type = "hot"; 640 }; 641 }; 642 }; 643 644 gpu-top-thermal { 645 polling-delay-passive = <250>; 646 polling-delay = <1000>; 647 648 thermal-sensors = <&tsens0 13>; 649 650 trips { 651 gpu2_alert0: trip-point0 { 652 temperature = <90000>; 653 hysteresis = <2000>; 654 type = "hot"; 655 }; 656 }; 657 }; 658 659 clust0-mhm-thermal { 660 polling-delay-passive = <250>; 661 polling-delay = <1000>; 662 663 thermal-sensors = <&tsens0 5>; 664 665 trips { 666 cluster0_mhm_alert0: trip-point0 { 667 temperature = <90000>; 668 hysteresis = <2000>; 669 type = "hot"; 670 }; 671 }; 672 }; 673 674 clust1-mhm-thermal { 675 polling-delay-passive = <250>; 676 polling-delay = <1000>; 677 678 thermal-sensors = <&tsens0 6>; 679 680 trips { 681 cluster1_mhm_alert0: trip-point0 { 682 temperature = <90000>; 683 hysteresis = <2000>; 684 type = "hot"; 685 }; 686 }; 687 }; 688 689 cluster1-l2-thermal { 690 polling-delay-passive = <250>; 691 polling-delay = <1000>; 692 693 thermal-sensors = <&tsens0 11>; 694 695 trips { 696 cluster1_l2_alert0: trip-point0 { 697 temperature = <90000>; 698 hysteresis = <2000>; 699 type = "hot"; 700 }; 701 }; 702 }; 703 704 modem-thermal { 705 polling-delay-passive = <250>; 706 polling-delay = <1000>; 707 708 thermal-sensors = <&tsens1 1>; 709 710 trips { 711 modem_alert0: trip-point0 { 712 temperature = <90000>; 713 hysteresis = <2000>; 714 type = "hot"; 715 }; 716 }; 717 }; 718 719 mem-thermal { 720 polling-delay-passive = <250>; 721 polling-delay = <1000>; 722 723 thermal-sensors = <&tsens1 2>; 724 725 trips { 726 mem_alert0: trip-point0 { 727 temperature = <90000>; 728 hysteresis = <2000>; 729 type = "hot"; 730 }; 731 }; 732 }; 733 734 wlan-thermal { 735 polling-delay-passive = <250>; 736 polling-delay = <1000>; 737 738 thermal-sensors = <&tsens1 3>; 739 740 trips { 741 wlan_alert0: trip-point0 { 742 temperature = <90000>; 743 hysteresis = <2000>; 744 type = "hot"; 745 }; 746 }; 747 }; 748 749 q6-dsp-thermal { 750 polling-delay-passive = <250>; 751 polling-delay = <1000>; 752 753 thermal-sensors = <&tsens1 4>; 754 755 trips { 756 q6_dsp_alert0: trip-point0 { 757 temperature = <90000>; 758 hysteresis = <2000>; 759 type = "hot"; 760 }; 761 }; 762 }; 763 764 camera-thermal { 765 polling-delay-passive = <250>; 766 polling-delay = <1000>; 767 768 thermal-sensors = <&tsens1 5>; 769 770 trips { 771 camera_alert0: trip-point0 { 772 temperature = <90000>; 773 hysteresis = <2000>; 774 type = "hot"; 775 }; 776 }; 777 }; 778 779 multimedia-thermal { 780 polling-delay-passive = <250>; 781 polling-delay = <1000>; 782 783 thermal-sensors = <&tsens1 6>; 784 785 trips { 786 multimedia_alert0: trip-point0 { 787 temperature = <90000>; 788 hysteresis = <2000>; 789 type = "hot"; 790 }; 791 }; 792 }; 793 }; 794 795 timer { 796 compatible = "arm,armv8-timer"; 797 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 798 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 799 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 800 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 801 }; 802 803 soc: soc { 804 #address-cells = <1>; 805 #size-cells = <1>; 806 ranges = <0 0 0 0xffffffff>; 807 compatible = "simple-bus"; 808 809 gcc: clock-controller@100000 { 810 compatible = "qcom,gcc-msm8998"; 811 #clock-cells = <1>; 812 #reset-cells = <1>; 813 #power-domain-cells = <1>; 814 reg = <0x00100000 0xb0000>; 815 816 clock-names = "xo", "sleep_clk"; 817 clocks = <&xo>, <&sleep_clk>; 818 }; 819 820 rpm_msg_ram: sram@778000 { 821 compatible = "qcom,rpm-msg-ram"; 822 reg = <0x00778000 0x7000>; 823 }; 824 825 qfprom: qfprom@784000 { 826 compatible = "qcom,qfprom"; 827 reg = <0x00784000 0x621c>; 828 #address-cells = <1>; 829 #size-cells = <1>; 830 831 qusb2_hstx_trim: hstx-trim@23a { 832 reg = <0x23a 0x1>; 833 bits = <0 4>; 834 }; 835 }; 836 837 tsens0: thermal@10ab000 { 838 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 839 reg = <0x010ab000 0x1000>, /* TM */ 840 <0x010aa000 0x1000>; /* SROT */ 841 #qcom,sensors = <14>; 842 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 844 interrupt-names = "uplow", "critical"; 845 #thermal-sensor-cells = <1>; 846 }; 847 848 tsens1: thermal@10ae000 { 849 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 850 reg = <0x010ae000 0x1000>, /* TM */ 851 <0x010ad000 0x1000>; /* SROT */ 852 #qcom,sensors = <8>; 853 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "uplow", "critical"; 856 #thermal-sensor-cells = <1>; 857 }; 858 859 anoc1_smmu: iommu@1680000 { 860 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 861 reg = <0x01680000 0x10000>; 862 #iommu-cells = <1>; 863 864 #global-interrupts = <0>; 865 interrupts = 866 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 867 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 868 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 869 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 870 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 871 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 872 }; 873 874 anoc2_smmu: iommu@16c0000 { 875 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 876 reg = <0x016c0000 0x40000>; 877 #iommu-cells = <1>; 878 879 #global-interrupts = <0>; 880 interrupts = 881 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 882 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 883 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 884 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 885 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 886 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 887 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 888 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 889 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 890 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 891 }; 892 893 pcie0: pci@1c00000 { 894 compatible = "qcom,pcie-msm8996"; 895 reg = <0x01c00000 0x2000>, 896 <0x1b000000 0xf1d>, 897 <0x1b000f20 0xa8>, 898 <0x1b100000 0x100000>; 899 reg-names = "parf", "dbi", "elbi", "config"; 900 device_type = "pci"; 901 linux,pci-domain = <0>; 902 bus-range = <0x00 0xff>; 903 #address-cells = <3>; 904 #size-cells = <2>; 905 num-lanes = <1>; 906 phys = <&pciephy>; 907 phy-names = "pciephy"; 908 status = "disabled"; 909 910 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, 911 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 912 913 #interrupt-cells = <1>; 914 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "msi"; 916 interrupt-map-mask = <0 0 0 0x7>; 917 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 918 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 919 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 920 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 921 922 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 923 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 924 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 925 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 926 <&gcc GCC_PCIE_0_AUX_CLK>; 927 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 928 929 power-domains = <&gcc PCIE_0_GDSC>; 930 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 931 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 932 }; 933 934 pcie_phy: phy@1c06000 { 935 compatible = "qcom,msm8998-qmp-pcie-phy"; 936 reg = <0x01c06000 0x18c>; 937 #address-cells = <1>; 938 #size-cells = <1>; 939 status = "disabled"; 940 ranges; 941 942 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 943 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 944 <&gcc GCC_PCIE_CLKREF_CLK>; 945 clock-names = "aux", "cfg_ahb", "ref"; 946 947 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 948 reset-names = "phy", "common"; 949 950 vdda-phy-supply = <&vreg_l1a_0p875>; 951 vdda-pll-supply = <&vreg_l2a_1p2>; 952 953 pciephy: phy@1c06800 { 954 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 955 #phy-cells = <0>; 956 957 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 958 clock-names = "pipe0"; 959 clock-output-names = "pcie_0_pipe_clk_src"; 960 #clock-cells = <0>; 961 }; 962 }; 963 964 ufshc: ufshc@1da4000 { 965 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 966 reg = <0x01da4000 0x2500>; 967 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 968 phys = <&ufsphy_lanes>; 969 phy-names = "ufsphy"; 970 lanes-per-direction = <2>; 971 power-domains = <&gcc UFS_GDSC>; 972 status = "disabled"; 973 #reset-cells = <1>; 974 975 clock-names = 976 "core_clk", 977 "bus_aggr_clk", 978 "iface_clk", 979 "core_clk_unipro", 980 "ref_clk", 981 "tx_lane0_sync_clk", 982 "rx_lane0_sync_clk", 983 "rx_lane1_sync_clk"; 984 clocks = 985 <&gcc GCC_UFS_AXI_CLK>, 986 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 987 <&gcc GCC_UFS_AHB_CLK>, 988 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 989 <&rpmcc RPM_SMD_LN_BB_CLK1>, 990 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 991 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 992 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 993 freq-table-hz = 994 <50000000 200000000>, 995 <0 0>, 996 <0 0>, 997 <37500000 150000000>, 998 <0 0>, 999 <0 0>, 1000 <0 0>, 1001 <0 0>; 1002 1003 resets = <&gcc GCC_UFS_BCR>; 1004 reset-names = "rst"; 1005 }; 1006 1007 ufsphy: phy@1da7000 { 1008 compatible = "qcom,msm8998-qmp-ufs-phy"; 1009 reg = <0x01da7000 0x18c>; 1010 #address-cells = <1>; 1011 #size-cells = <1>; 1012 status = "disabled"; 1013 ranges; 1014 1015 clock-names = 1016 "ref", 1017 "ref_aux"; 1018 clocks = 1019 <&gcc GCC_UFS_CLKREF_CLK>, 1020 <&gcc GCC_UFS_PHY_AUX_CLK>; 1021 1022 reset-names = "ufsphy"; 1023 resets = <&ufshc 0>; 1024 1025 ufsphy_lanes: phy@1da7400 { 1026 reg = <0x01da7400 0x128>, 1027 <0x01da7600 0x1fc>, 1028 <0x01da7c00 0x1dc>, 1029 <0x01da7800 0x128>, 1030 <0x01da7a00 0x1fc>; 1031 #phy-cells = <0>; 1032 }; 1033 }; 1034 1035 tcsr_mutex_regs: syscon@1f40000 { 1036 compatible = "syscon"; 1037 reg = <0x01f40000 0x40000>; 1038 }; 1039 1040 tlmm: pinctrl@3400000 { 1041 compatible = "qcom,msm8998-pinctrl"; 1042 reg = <0x03400000 0xc00000>; 1043 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1044 gpio-controller; 1045 #gpio-cells = <0x2>; 1046 interrupt-controller; 1047 #interrupt-cells = <0x2>; 1048 1049 sdc2_clk_on: sdc2_clk_on { 1050 config { 1051 pins = "sdc2_clk"; 1052 bias-disable; 1053 drive-strength = <16>; 1054 }; 1055 }; 1056 1057 sdc2_clk_off: sdc2_clk_off { 1058 config { 1059 pins = "sdc2_clk"; 1060 bias-disable; 1061 drive-strength = <2>; 1062 }; 1063 }; 1064 1065 sdc2_cmd_on: sdc2_cmd_on { 1066 config { 1067 pins = "sdc2_cmd"; 1068 bias-pull-up; 1069 drive-strength = <10>; 1070 }; 1071 }; 1072 1073 sdc2_cmd_off: sdc2_cmd_off { 1074 config { 1075 pins = "sdc2_cmd"; 1076 bias-pull-up; 1077 drive-strength = <2>; 1078 }; 1079 }; 1080 1081 sdc2_data_on: sdc2_data_on { 1082 config { 1083 pins = "sdc2_data"; 1084 bias-pull-up; 1085 drive-strength = <10>; 1086 }; 1087 }; 1088 1089 sdc2_data_off: sdc2_data_off { 1090 config { 1091 pins = "sdc2_data"; 1092 bias-pull-up; 1093 drive-strength = <2>; 1094 }; 1095 }; 1096 1097 sdc2_cd_on: sdc2_cd_on { 1098 mux { 1099 pins = "gpio95"; 1100 function = "gpio"; 1101 }; 1102 1103 config { 1104 pins = "gpio95"; 1105 bias-pull-up; 1106 drive-strength = <2>; 1107 }; 1108 }; 1109 1110 sdc2_cd_off: sdc2_cd_off { 1111 mux { 1112 pins = "gpio95"; 1113 function = "gpio"; 1114 }; 1115 1116 config { 1117 pins = "gpio95"; 1118 bias-pull-up; 1119 drive-strength = <2>; 1120 }; 1121 }; 1122 1123 blsp1_uart3_on: blsp1_uart3_on { 1124 tx { 1125 pins = "gpio45"; 1126 function = "blsp_uart3_a"; 1127 drive-strength = <2>; 1128 bias-disable; 1129 }; 1130 1131 rx { 1132 pins = "gpio46"; 1133 function = "blsp_uart3_a"; 1134 drive-strength = <2>; 1135 bias-disable; 1136 }; 1137 1138 cts { 1139 pins = "gpio47"; 1140 function = "blsp_uart3_a"; 1141 drive-strength = <2>; 1142 bias-disable; 1143 }; 1144 1145 rfr { 1146 pins = "gpio48"; 1147 function = "blsp_uart3_a"; 1148 drive-strength = <2>; 1149 bias-disable; 1150 }; 1151 }; 1152 1153 blsp1_i2c1_default: blsp1-i2c1-default { 1154 pins = "gpio2", "gpio3"; 1155 function = "blsp_i2c1"; 1156 drive-strength = <2>; 1157 bias-disable; 1158 }; 1159 1160 blsp1_i2c1_sleep: blsp1-i2c1-sleep { 1161 pins = "gpio2", "gpio3"; 1162 function = "blsp_i2c1"; 1163 drive-strength = <2>; 1164 bias-pull-up; 1165 }; 1166 1167 blsp1_i2c2_default: blsp1-i2c2-default { 1168 pins = "gpio32", "gpio33"; 1169 function = "blsp_i2c2"; 1170 drive-strength = <2>; 1171 bias-disable; 1172 }; 1173 1174 blsp1_i2c2_sleep: blsp1-i2c2-sleep { 1175 pins = "gpio32", "gpio33"; 1176 function = "blsp_i2c2"; 1177 drive-strength = <2>; 1178 bias-pull-up; 1179 }; 1180 1181 blsp1_i2c3_default: blsp1-i2c3-default { 1182 pins = "gpio47", "gpio48"; 1183 function = "blsp_i2c3"; 1184 drive-strength = <2>; 1185 bias-disable; 1186 }; 1187 1188 blsp1_i2c3_sleep: blsp1-i2c3-sleep { 1189 pins = "gpio47", "gpio48"; 1190 function = "blsp_i2c3"; 1191 drive-strength = <2>; 1192 bias-pull-up; 1193 }; 1194 1195 blsp1_i2c4_default: blsp1-i2c4-default { 1196 pins = "gpio10", "gpio11"; 1197 function = "blsp_i2c4"; 1198 drive-strength = <2>; 1199 bias-disable; 1200 }; 1201 1202 blsp1_i2c4_sleep: blsp1-i2c4-sleep { 1203 pins = "gpio10", "gpio11"; 1204 function = "blsp_i2c4"; 1205 drive-strength = <2>; 1206 bias-pull-up; 1207 }; 1208 1209 blsp1_i2c5_default: blsp1-i2c5-default { 1210 pins = "gpio87", "gpio88"; 1211 function = "blsp_i2c5"; 1212 drive-strength = <2>; 1213 bias-disable; 1214 }; 1215 1216 blsp1_i2c5_sleep: blsp1-i2c5-sleep { 1217 pins = "gpio87", "gpio88"; 1218 function = "blsp_i2c5"; 1219 drive-strength = <2>; 1220 bias-pull-up; 1221 }; 1222 1223 blsp1_i2c6_default: blsp1-i2c6-default { 1224 pins = "gpio43", "gpio44"; 1225 function = "blsp_i2c6"; 1226 drive-strength = <2>; 1227 bias-disable; 1228 }; 1229 1230 blsp1_i2c6_sleep: blsp1-i2c6-sleep { 1231 pins = "gpio43", "gpio44"; 1232 function = "blsp_i2c6"; 1233 drive-strength = <2>; 1234 bias-pull-up; 1235 }; 1236 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1237 blsp2_i2c1_default: blsp2-i2c1-default { 1238 pins = "gpio55", "gpio56"; 1239 function = "blsp_i2c7"; 1240 drive-strength = <2>; 1241 bias-disable; 1242 }; 1243 1244 blsp2_i2c1_sleep: blsp2-i2c1-sleep { 1245 pins = "gpio55", "gpio56"; 1246 function = "blsp_i2c7"; 1247 drive-strength = <2>; 1248 bias-pull-up; 1249 }; 1250 1251 blsp2_i2c2_default: blsp2-i2c2-default { 1252 pins = "gpio6", "gpio7"; 1253 function = "blsp_i2c8"; 1254 drive-strength = <2>; 1255 bias-disable; 1256 }; 1257 1258 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1259 pins = "gpio6", "gpio7"; 1260 function = "blsp_i2c8"; 1261 drive-strength = <2>; 1262 bias-pull-up; 1263 }; 1264 1265 blsp2_i2c3_default: blsp2-i2c3-default { 1266 pins = "gpio51", "gpio52"; 1267 function = "blsp_i2c9"; 1268 drive-strength = <2>; 1269 bias-disable; 1270 }; 1271 1272 blsp2_i2c3_sleep: blsp2-i2c3-sleep { 1273 pins = "gpio51", "gpio52"; 1274 function = "blsp_i2c9"; 1275 drive-strength = <2>; 1276 bias-pull-up; 1277 }; 1278 1279 blsp2_i2c4_default: blsp2-i2c4-default { 1280 pins = "gpio67", "gpio68"; 1281 function = "blsp_i2c10"; 1282 drive-strength = <2>; 1283 bias-disable; 1284 }; 1285 1286 blsp2_i2c4_sleep: blsp2-i2c4-sleep { 1287 pins = "gpio67", "gpio68"; 1288 function = "blsp_i2c10"; 1289 drive-strength = <2>; 1290 bias-pull-up; 1291 }; 1292 1293 blsp2_i2c5_default: blsp2-i2c5-default { 1294 pins = "gpio60", "gpio61"; 1295 function = "blsp_i2c11"; 1296 drive-strength = <2>; 1297 bias-disable; 1298 }; 1299 1300 blsp2_i2c5_sleep: blsp2-i2c5-sleep { 1301 pins = "gpio60", "gpio61"; 1302 function = "blsp_i2c11"; 1303 drive-strength = <2>; 1304 bias-pull-up; 1305 }; 1306 1307 blsp2_i2c6_default: blsp2-i2c6-default { 1308 pins = "gpio83", "gpio84"; 1309 function = "blsp_i2c12"; 1310 drive-strength = <2>; 1311 bias-disable; 1312 }; 1313 1314 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1315 pins = "gpio83", "gpio84"; 1316 function = "blsp_i2c12"; 1317 drive-strength = <2>; 1318 bias-pull-up; 1319 }; 1320 }; 1321 1322 remoteproc_mss: remoteproc@4080000 { 1323 compatible = "qcom,msm8998-mss-pil"; 1324 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1325 reg-names = "qdsp6", "rmb"; 1326 1327 interrupts-extended = 1328 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1329 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1330 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1331 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1332 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1333 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1334 interrupt-names = "wdog", "fatal", "ready", 1335 "handover", "stop-ack", 1336 "shutdown-ack"; 1337 1338 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1339 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1340 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1341 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1342 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1343 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1344 <&rpmcc RPM_SMD_QDSS_CLK>, 1345 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1346 clock-names = "iface", "bus", "mem", "gpll0_mss", 1347 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1348 1349 qcom,smem-states = <&modem_smp2p_out 0>; 1350 qcom,smem-state-names = "stop"; 1351 1352 resets = <&gcc GCC_MSS_RESTART>; 1353 reset-names = "mss_restart"; 1354 1355 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1356 1357 power-domains = <&rpmpd MSM8998_VDDCX>, 1358 <&rpmpd MSM8998_VDDMX>; 1359 power-domain-names = "cx", "mx"; 1360 1361 status = "disabled"; 1362 1363 mba { 1364 memory-region = <&mba_mem>; 1365 }; 1366 1367 mpss { 1368 memory-region = <&mpss_mem>; 1369 }; 1370 1371 glink-edge { 1372 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1373 label = "modem"; 1374 qcom,remote-pid = <1>; 1375 mboxes = <&apcs_glb 15>; 1376 }; 1377 }; 1378 1379 adreno_gpu: gpu@5000000 { 1380 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1381 reg = <0x05000000 0x40000>; 1382 reg-names = "kgsl_3d0_reg_memory"; 1383 1384 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1385 <&gpucc RBBMTIMER_CLK>, 1386 <&gcc GCC_BIMC_GFX_CLK>, 1387 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1388 <&gpucc RBCPR_CLK>, 1389 <&gpucc GFX3D_CLK>; 1390 clock-names = "iface", 1391 "rbbmtimer", 1392 "mem", 1393 "mem_iface", 1394 "rbcpr", 1395 "core"; 1396 1397 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1398 iommus = <&adreno_smmu 0>; 1399 operating-points-v2 = <&gpu_opp_table>; 1400 power-domains = <&rpmpd MSM8998_VDDMX>; 1401 status = "disabled"; 1402 1403 gpu_opp_table: opp-table { 1404 compatible = "operating-points-v2"; 1405 opp-710000097 { 1406 opp-hz = /bits/ 64 <710000097>; 1407 opp-level = <RPM_SMD_LEVEL_TURBO>; 1408 opp-supported-hw = <0xFF>; 1409 }; 1410 1411 opp-670000048 { 1412 opp-hz = /bits/ 64 <670000048>; 1413 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1414 opp-supported-hw = <0xFF>; 1415 }; 1416 1417 opp-596000097 { 1418 opp-hz = /bits/ 64 <596000097>; 1419 opp-level = <RPM_SMD_LEVEL_NOM>; 1420 opp-supported-hw = <0xFF>; 1421 }; 1422 1423 opp-515000097 { 1424 opp-hz = /bits/ 64 <515000097>; 1425 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1426 opp-supported-hw = <0xFF>; 1427 }; 1428 1429 opp-414000000 { 1430 opp-hz = /bits/ 64 <414000000>; 1431 opp-level = <RPM_SMD_LEVEL_SVS>; 1432 opp-supported-hw = <0xFF>; 1433 }; 1434 1435 opp-342000000 { 1436 opp-hz = /bits/ 64 <342000000>; 1437 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1438 opp-supported-hw = <0xFF>; 1439 }; 1440 1441 opp-257000000 { 1442 opp-hz = /bits/ 64 <257000000>; 1443 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1444 opp-supported-hw = <0xFF>; 1445 }; 1446 }; 1447 }; 1448 1449 adreno_smmu: iommu@5040000 { 1450 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1451 reg = <0x05040000 0x10000>; 1452 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1453 <&gcc GCC_BIMC_GFX_CLK>, 1454 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1455 clock-names = "iface", "mem", "mem_iface"; 1456 1457 #global-interrupts = <0>; 1458 #iommu-cells = <1>; 1459 interrupts = 1460 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1463 /* 1464 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1465 * GPU-CX for SMMU but we need both of them up for Adreno. 1466 * Contemporarily, we also need to manage the VDDMX rpmpd 1467 * domain in the Adreno driver. 1468 * Enable GPU CX/GX GDSCs here so that we can manage the 1469 * SoC VDDMX RPM Power Domain in the Adreno driver. 1470 */ 1471 power-domains = <&gpucc GPU_GX_GDSC>; 1472 status = "disabled"; 1473 }; 1474 1475 gpucc: clock-controller@5065000 { 1476 compatible = "qcom,msm8998-gpucc"; 1477 #clock-cells = <1>; 1478 #reset-cells = <1>; 1479 #power-domain-cells = <1>; 1480 reg = <0x05065000 0x9000>; 1481 1482 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1483 <&gcc GPLL0_OUT_MAIN>; 1484 clock-names = "xo", 1485 "gpll0"; 1486 }; 1487 1488 remoteproc_slpi: remoteproc@5800000 { 1489 compatible = "qcom,msm8998-slpi-pas"; 1490 reg = <0x05800000 0x4040>; 1491 1492 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1493 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1494 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1495 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1496 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1497 interrupt-names = "wdog", "fatal", "ready", 1498 "handover", "stop-ack"; 1499 1500 px-supply = <&vreg_lvs2a_1p8>; 1501 1502 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1503 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1504 clock-names = "xo", "aggre2"; 1505 1506 memory-region = <&slpi_mem>; 1507 1508 qcom,smem-states = <&slpi_smp2p_out 0>; 1509 qcom,smem-state-names = "stop"; 1510 1511 power-domains = <&rpmpd MSM8998_SSCCX>; 1512 power-domain-names = "ssc_cx"; 1513 1514 status = "disabled"; 1515 1516 glink-edge { 1517 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1518 label = "dsps"; 1519 qcom,remote-pid = <3>; 1520 mboxes = <&apcs_glb 27>; 1521 }; 1522 }; 1523 1524 stm: stm@6002000 { 1525 compatible = "arm,coresight-stm", "arm,primecell"; 1526 reg = <0x06002000 0x1000>, 1527 <0x16280000 0x180000>; 1528 reg-names = "stm-base", "stm-data-base"; 1529 status = "disabled"; 1530 1531 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1532 clock-names = "apb_pclk", "atclk"; 1533 1534 out-ports { 1535 port { 1536 stm_out: endpoint { 1537 remote-endpoint = <&funnel0_in7>; 1538 }; 1539 }; 1540 }; 1541 }; 1542 1543 funnel1: funnel@6041000 { 1544 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1545 reg = <0x06041000 0x1000>; 1546 status = "disabled"; 1547 1548 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1549 clock-names = "apb_pclk", "atclk"; 1550 1551 out-ports { 1552 port { 1553 funnel0_out: endpoint { 1554 remote-endpoint = 1555 <&merge_funnel_in0>; 1556 }; 1557 }; 1558 }; 1559 1560 in-ports { 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 1564 port@7 { 1565 reg = <7>; 1566 funnel0_in7: endpoint { 1567 remote-endpoint = <&stm_out>; 1568 }; 1569 }; 1570 }; 1571 }; 1572 1573 funnel2: funnel@6042000 { 1574 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1575 reg = <0x06042000 0x1000>; 1576 status = "disabled"; 1577 1578 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1579 clock-names = "apb_pclk", "atclk"; 1580 1581 out-ports { 1582 port { 1583 funnel1_out: endpoint { 1584 remote-endpoint = 1585 <&merge_funnel_in1>; 1586 }; 1587 }; 1588 }; 1589 1590 in-ports { 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 1594 port@6 { 1595 reg = <6>; 1596 funnel1_in6: endpoint { 1597 remote-endpoint = 1598 <&apss_merge_funnel_out>; 1599 }; 1600 }; 1601 }; 1602 }; 1603 1604 funnel3: funnel@6045000 { 1605 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1606 reg = <0x06045000 0x1000>; 1607 status = "disabled"; 1608 1609 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1610 clock-names = "apb_pclk", "atclk"; 1611 1612 out-ports { 1613 port { 1614 merge_funnel_out: endpoint { 1615 remote-endpoint = 1616 <&etf_in>; 1617 }; 1618 }; 1619 }; 1620 1621 in-ports { 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 1625 port@0 { 1626 reg = <0>; 1627 merge_funnel_in0: endpoint { 1628 remote-endpoint = 1629 <&funnel0_out>; 1630 }; 1631 }; 1632 1633 port@1 { 1634 reg = <1>; 1635 merge_funnel_in1: endpoint { 1636 remote-endpoint = 1637 <&funnel1_out>; 1638 }; 1639 }; 1640 }; 1641 }; 1642 1643 replicator1: replicator@6046000 { 1644 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1645 reg = <0x06046000 0x1000>; 1646 status = "disabled"; 1647 1648 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1649 clock-names = "apb_pclk", "atclk"; 1650 1651 out-ports { 1652 port { 1653 replicator_out: endpoint { 1654 remote-endpoint = <&etr_in>; 1655 }; 1656 }; 1657 }; 1658 1659 in-ports { 1660 port { 1661 replicator_in: endpoint { 1662 remote-endpoint = <&etf_out>; 1663 }; 1664 }; 1665 }; 1666 }; 1667 1668 etf: etf@6047000 { 1669 compatible = "arm,coresight-tmc", "arm,primecell"; 1670 reg = <0x06047000 0x1000>; 1671 status = "disabled"; 1672 1673 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1674 clock-names = "apb_pclk", "atclk"; 1675 1676 out-ports { 1677 port { 1678 etf_out: endpoint { 1679 remote-endpoint = 1680 <&replicator_in>; 1681 }; 1682 }; 1683 }; 1684 1685 in-ports { 1686 port { 1687 etf_in: endpoint { 1688 remote-endpoint = 1689 <&merge_funnel_out>; 1690 }; 1691 }; 1692 }; 1693 }; 1694 1695 etr: etr@6048000 { 1696 compatible = "arm,coresight-tmc", "arm,primecell"; 1697 reg = <0x06048000 0x1000>; 1698 status = "disabled"; 1699 1700 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1701 clock-names = "apb_pclk", "atclk"; 1702 arm,scatter-gather; 1703 1704 in-ports { 1705 port { 1706 etr_in: endpoint { 1707 remote-endpoint = 1708 <&replicator_out>; 1709 }; 1710 }; 1711 }; 1712 }; 1713 1714 etm1: etm@7840000 { 1715 compatible = "arm,coresight-etm4x", "arm,primecell"; 1716 reg = <0x07840000 0x1000>; 1717 status = "disabled"; 1718 1719 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1720 clock-names = "apb_pclk", "atclk"; 1721 1722 cpu = <&CPU0>; 1723 1724 out-ports { 1725 port { 1726 etm0_out: endpoint { 1727 remote-endpoint = 1728 <&apss_funnel_in0>; 1729 }; 1730 }; 1731 }; 1732 }; 1733 1734 etm2: etm@7940000 { 1735 compatible = "arm,coresight-etm4x", "arm,primecell"; 1736 reg = <0x07940000 0x1000>; 1737 status = "disabled"; 1738 1739 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1740 clock-names = "apb_pclk", "atclk"; 1741 1742 cpu = <&CPU1>; 1743 1744 out-ports { 1745 port { 1746 etm1_out: endpoint { 1747 remote-endpoint = 1748 <&apss_funnel_in1>; 1749 }; 1750 }; 1751 }; 1752 }; 1753 1754 etm3: etm@7a40000 { 1755 compatible = "arm,coresight-etm4x", "arm,primecell"; 1756 reg = <0x07a40000 0x1000>; 1757 status = "disabled"; 1758 1759 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1760 clock-names = "apb_pclk", "atclk"; 1761 1762 cpu = <&CPU2>; 1763 1764 out-ports { 1765 port { 1766 etm2_out: endpoint { 1767 remote-endpoint = 1768 <&apss_funnel_in2>; 1769 }; 1770 }; 1771 }; 1772 }; 1773 1774 etm4: etm@7b40000 { 1775 compatible = "arm,coresight-etm4x", "arm,primecell"; 1776 reg = <0x07b40000 0x1000>; 1777 status = "disabled"; 1778 1779 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1780 clock-names = "apb_pclk", "atclk"; 1781 1782 cpu = <&CPU3>; 1783 1784 out-ports { 1785 port { 1786 etm3_out: endpoint { 1787 remote-endpoint = 1788 <&apss_funnel_in3>; 1789 }; 1790 }; 1791 }; 1792 }; 1793 1794 funnel4: funnel@7b60000 { /* APSS Funnel */ 1795 compatible = "arm,coresight-etm4x", "arm,primecell"; 1796 reg = <0x07b60000 0x1000>; 1797 status = "disabled"; 1798 1799 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1800 clock-names = "apb_pclk", "atclk"; 1801 1802 out-ports { 1803 port { 1804 apss_funnel_out: endpoint { 1805 remote-endpoint = 1806 <&apss_merge_funnel_in>; 1807 }; 1808 }; 1809 }; 1810 1811 in-ports { 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 1815 port@0 { 1816 reg = <0>; 1817 apss_funnel_in0: endpoint { 1818 remote-endpoint = 1819 <&etm0_out>; 1820 }; 1821 }; 1822 1823 port@1 { 1824 reg = <1>; 1825 apss_funnel_in1: endpoint { 1826 remote-endpoint = 1827 <&etm1_out>; 1828 }; 1829 }; 1830 1831 port@2 { 1832 reg = <2>; 1833 apss_funnel_in2: endpoint { 1834 remote-endpoint = 1835 <&etm2_out>; 1836 }; 1837 }; 1838 1839 port@3 { 1840 reg = <3>; 1841 apss_funnel_in3: endpoint { 1842 remote-endpoint = 1843 <&etm3_out>; 1844 }; 1845 }; 1846 1847 port@4 { 1848 reg = <4>; 1849 apss_funnel_in4: endpoint { 1850 remote-endpoint = 1851 <&etm4_out>; 1852 }; 1853 }; 1854 1855 port@5 { 1856 reg = <5>; 1857 apss_funnel_in5: endpoint { 1858 remote-endpoint = 1859 <&etm5_out>; 1860 }; 1861 }; 1862 1863 port@6 { 1864 reg = <6>; 1865 apss_funnel_in6: endpoint { 1866 remote-endpoint = 1867 <&etm6_out>; 1868 }; 1869 }; 1870 1871 port@7 { 1872 reg = <7>; 1873 apss_funnel_in7: endpoint { 1874 remote-endpoint = 1875 <&etm7_out>; 1876 }; 1877 }; 1878 }; 1879 }; 1880 1881 funnel5: funnel@7b70000 { 1882 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1883 reg = <0x07b70000 0x1000>; 1884 status = "disabled"; 1885 1886 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1887 clock-names = "apb_pclk", "atclk"; 1888 1889 out-ports { 1890 port { 1891 apss_merge_funnel_out: endpoint { 1892 remote-endpoint = 1893 <&funnel1_in6>; 1894 }; 1895 }; 1896 }; 1897 1898 in-ports { 1899 port { 1900 apss_merge_funnel_in: endpoint { 1901 remote-endpoint = 1902 <&apss_funnel_out>; 1903 }; 1904 }; 1905 }; 1906 }; 1907 1908 etm5: etm@7c40000 { 1909 compatible = "arm,coresight-etm4x", "arm,primecell"; 1910 reg = <0x07c40000 0x1000>; 1911 status = "disabled"; 1912 1913 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1914 clock-names = "apb_pclk", "atclk"; 1915 1916 cpu = <&CPU4>; 1917 1918 port{ 1919 etm4_out: endpoint { 1920 remote-endpoint = <&apss_funnel_in4>; 1921 }; 1922 }; 1923 }; 1924 1925 etm6: etm@7d40000 { 1926 compatible = "arm,coresight-etm4x", "arm,primecell"; 1927 reg = <0x07d40000 0x1000>; 1928 status = "disabled"; 1929 1930 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1931 clock-names = "apb_pclk", "atclk"; 1932 1933 cpu = <&CPU5>; 1934 1935 port{ 1936 etm5_out: endpoint { 1937 remote-endpoint = <&apss_funnel_in5>; 1938 }; 1939 }; 1940 }; 1941 1942 etm7: etm@7e40000 { 1943 compatible = "arm,coresight-etm4x", "arm,primecell"; 1944 reg = <0x07e40000 0x1000>; 1945 status = "disabled"; 1946 1947 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1948 clock-names = "apb_pclk", "atclk"; 1949 1950 cpu = <&CPU6>; 1951 1952 port{ 1953 etm6_out: endpoint { 1954 remote-endpoint = <&apss_funnel_in6>; 1955 }; 1956 }; 1957 }; 1958 1959 etm8: etm@7f40000 { 1960 compatible = "arm,coresight-etm4x", "arm,primecell"; 1961 reg = <0x07f40000 0x1000>; 1962 status = "disabled"; 1963 1964 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1965 clock-names = "apb_pclk", "atclk"; 1966 1967 cpu = <&CPU7>; 1968 1969 port{ 1970 etm7_out: endpoint { 1971 remote-endpoint = <&apss_funnel_in7>; 1972 }; 1973 }; 1974 }; 1975 1976 sram@290000 { 1977 compatible = "qcom,rpm-stats"; 1978 reg = <0x00290000 0x10000>; 1979 }; 1980 1981 spmi_bus: spmi@800f000 { 1982 compatible = "qcom,spmi-pmic-arb"; 1983 reg = <0x0800f000 0x1000>, 1984 <0x08400000 0x1000000>, 1985 <0x09400000 0x1000000>, 1986 <0x0a400000 0x220000>, 1987 <0x0800a000 0x3000>; 1988 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1989 interrupt-names = "periph_irq"; 1990 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1991 qcom,ee = <0>; 1992 qcom,channel = <0>; 1993 #address-cells = <2>; 1994 #size-cells = <0>; 1995 interrupt-controller; 1996 #interrupt-cells = <4>; 1997 cell-index = <0>; 1998 }; 1999 2000 usb3: usb@a8f8800 { 2001 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2002 reg = <0x0a8f8800 0x400>; 2003 status = "disabled"; 2004 #address-cells = <1>; 2005 #size-cells = <1>; 2006 ranges; 2007 2008 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2009 <&gcc GCC_USB30_MASTER_CLK>, 2010 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2011 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2012 <&gcc GCC_USB30_SLEEP_CLK>; 2013 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2014 "sleep"; 2015 2016 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2017 <&gcc GCC_USB30_MASTER_CLK>; 2018 assigned-clock-rates = <19200000>, <120000000>; 2019 2020 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2022 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2023 2024 power-domains = <&gcc USB_30_GDSC>; 2025 2026 resets = <&gcc GCC_USB_30_BCR>; 2027 2028 usb3_dwc3: dwc3@a800000 { 2029 compatible = "snps,dwc3"; 2030 reg = <0x0a800000 0xcd00>; 2031 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2032 snps,dis_u2_susphy_quirk; 2033 snps,dis_enblslpm_quirk; 2034 phys = <&qusb2phy>, <&usb1_ssphy>; 2035 phy-names = "usb2-phy", "usb3-phy"; 2036 snps,has-lpm-erratum; 2037 snps,hird-threshold = /bits/ 8 <0x10>; 2038 }; 2039 }; 2040 2041 usb3phy: phy@c010000 { 2042 compatible = "qcom,msm8998-qmp-usb3-phy"; 2043 reg = <0x0c010000 0x18c>; 2044 status = "disabled"; 2045 #address-cells = <1>; 2046 #size-cells = <1>; 2047 ranges; 2048 2049 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2050 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2051 <&gcc GCC_USB3_CLKREF_CLK>; 2052 clock-names = "aux", "cfg_ahb", "ref"; 2053 2054 resets = <&gcc GCC_USB3_PHY_BCR>, 2055 <&gcc GCC_USB3PHY_PHY_BCR>; 2056 reset-names = "phy", "common"; 2057 2058 usb1_ssphy: phy@c010200 { 2059 reg = <0xc010200 0x128>, 2060 <0xc010400 0x200>, 2061 <0xc010c00 0x20c>, 2062 <0xc010600 0x128>, 2063 <0xc010800 0x200>; 2064 #phy-cells = <0>; 2065 #clock-cells = <1>; 2066 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2067 clock-names = "pipe0"; 2068 clock-output-names = "usb3_phy_pipe_clk_src"; 2069 }; 2070 }; 2071 2072 qusb2phy: phy@c012000 { 2073 compatible = "qcom,msm8998-qusb2-phy"; 2074 reg = <0x0c012000 0x2a8>; 2075 status = "disabled"; 2076 #phy-cells = <0>; 2077 2078 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2079 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2080 clock-names = "cfg_ahb", "ref"; 2081 2082 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2083 2084 nvmem-cells = <&qusb2_hstx_trim>; 2085 }; 2086 2087 sdhc2: sdhci@c0a4900 { 2088 compatible = "qcom,sdhci-msm-v4"; 2089 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2090 reg-names = "hc_mem", "core_mem"; 2091 2092 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2094 interrupt-names = "hc_irq", "pwr_irq"; 2095 2096 clock-names = "iface", "core", "xo"; 2097 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2098 <&gcc GCC_SDCC2_APPS_CLK>, 2099 <&xo>; 2100 bus-width = <4>; 2101 status = "disabled"; 2102 }; 2103 2104 blsp1_dma: dma-controller@c144000 { 2105 compatible = "qcom,bam-v1.7.0"; 2106 reg = <0x0c144000 0x25000>; 2107 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2108 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2109 clock-names = "bam_clk"; 2110 #dma-cells = <1>; 2111 qcom,ee = <0>; 2112 qcom,controlled-remotely; 2113 num-channels = <18>; 2114 qcom,num-ees = <4>; 2115 }; 2116 2117 blsp1_uart3: serial@c171000 { 2118 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2119 reg = <0x0c171000 0x1000>; 2120 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2121 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2122 <&gcc GCC_BLSP1_AHB_CLK>; 2123 clock-names = "core", "iface"; 2124 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2125 dma-names = "tx", "rx"; 2126 pinctrl-names = "default"; 2127 pinctrl-0 = <&blsp1_uart3_on>; 2128 status = "disabled"; 2129 }; 2130 2131 blsp1_i2c1: i2c@c175000 { 2132 compatible = "qcom,i2c-qup-v2.2.1"; 2133 reg = <0x0c175000 0x600>; 2134 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2135 2136 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2137 <&gcc GCC_BLSP1_AHB_CLK>; 2138 clock-names = "core", "iface"; 2139 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2140 dma-names = "tx", "rx"; 2141 pinctrl-names = "default", "sleep"; 2142 pinctrl-0 = <&blsp1_i2c1_default>; 2143 pinctrl-1 = <&blsp1_i2c1_sleep>; 2144 clock-frequency = <400000>; 2145 2146 status = "disabled"; 2147 #address-cells = <1>; 2148 #size-cells = <0>; 2149 }; 2150 2151 blsp1_i2c2: i2c@c176000 { 2152 compatible = "qcom,i2c-qup-v2.2.1"; 2153 reg = <0x0c176000 0x600>; 2154 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2155 2156 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2157 <&gcc GCC_BLSP1_AHB_CLK>; 2158 clock-names = "core", "iface"; 2159 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2160 dma-names = "tx", "rx"; 2161 pinctrl-names = "default", "sleep"; 2162 pinctrl-0 = <&blsp1_i2c2_default>; 2163 pinctrl-1 = <&blsp1_i2c2_sleep>; 2164 clock-frequency = <400000>; 2165 2166 status = "disabled"; 2167 #address-cells = <1>; 2168 #size-cells = <0>; 2169 }; 2170 2171 blsp1_i2c3: i2c@c177000 { 2172 compatible = "qcom,i2c-qup-v2.2.1"; 2173 reg = <0x0c177000 0x600>; 2174 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2175 2176 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2177 <&gcc GCC_BLSP1_AHB_CLK>; 2178 clock-names = "core", "iface"; 2179 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2180 dma-names = "tx", "rx"; 2181 pinctrl-names = "default", "sleep"; 2182 pinctrl-0 = <&blsp1_i2c3_default>; 2183 pinctrl-1 = <&blsp1_i2c3_sleep>; 2184 clock-frequency = <400000>; 2185 2186 status = "disabled"; 2187 #address-cells = <1>; 2188 #size-cells = <0>; 2189 }; 2190 2191 blsp1_i2c4: i2c@c178000 { 2192 compatible = "qcom,i2c-qup-v2.2.1"; 2193 reg = <0x0c178000 0x600>; 2194 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2195 2196 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2197 <&gcc GCC_BLSP1_AHB_CLK>; 2198 clock-names = "core", "iface"; 2199 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2200 dma-names = "tx", "rx"; 2201 pinctrl-names = "default", "sleep"; 2202 pinctrl-0 = <&blsp1_i2c4_default>; 2203 pinctrl-1 = <&blsp1_i2c4_sleep>; 2204 clock-frequency = <400000>; 2205 2206 status = "disabled"; 2207 #address-cells = <1>; 2208 #size-cells = <0>; 2209 }; 2210 2211 blsp1_i2c5: i2c@c179000 { 2212 compatible = "qcom,i2c-qup-v2.2.1"; 2213 reg = <0x0c179000 0x600>; 2214 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2215 2216 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2217 <&gcc GCC_BLSP1_AHB_CLK>; 2218 clock-names = "core", "iface"; 2219 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2220 dma-names = "tx", "rx"; 2221 pinctrl-names = "default", "sleep"; 2222 pinctrl-0 = <&blsp1_i2c5_default>; 2223 pinctrl-1 = <&blsp1_i2c5_sleep>; 2224 clock-frequency = <400000>; 2225 2226 status = "disabled"; 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 }; 2230 2231 blsp1_i2c6: i2c@c17a000 { 2232 compatible = "qcom,i2c-qup-v2.2.1"; 2233 reg = <0x0c17a000 0x600>; 2234 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2235 2236 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2237 <&gcc GCC_BLSP1_AHB_CLK>; 2238 clock-names = "core", "iface"; 2239 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2240 dma-names = "tx", "rx"; 2241 pinctrl-names = "default", "sleep"; 2242 pinctrl-0 = <&blsp1_i2c6_default>; 2243 pinctrl-1 = <&blsp1_i2c6_sleep>; 2244 clock-frequency = <400000>; 2245 2246 status = "disabled"; 2247 #address-cells = <1>; 2248 #size-cells = <0>; 2249 }; 2250 2251 blsp2_dma: dma-controller@c184000 { 2252 compatible = "qcom,bam-v1.7.0"; 2253 reg = <0x0c184000 0x25000>; 2254 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2256 clock-names = "bam_clk"; 2257 #dma-cells = <1>; 2258 qcom,ee = <0>; 2259 qcom,controlled-remotely; 2260 num-channels = <18>; 2261 qcom,num-ees = <4>; 2262 }; 2263 2264 blsp2_uart1: serial@c1b0000 { 2265 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2266 reg = <0x0c1b0000 0x1000>; 2267 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2268 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2269 <&gcc GCC_BLSP2_AHB_CLK>; 2270 clock-names = "core", "iface"; 2271 status = "disabled"; 2272 }; 2273 2274 blsp2_i2c1: i2c@c1b5000 { 2275 compatible = "qcom,i2c-qup-v2.2.1"; 2276 reg = <0x0c1b5000 0x600>; 2277 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2278 2279 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2280 <&gcc GCC_BLSP2_AHB_CLK>; 2281 clock-names = "core", "iface"; 2282 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2283 dma-names = "tx", "rx"; 2284 pinctrl-names = "default", "sleep"; 2285 pinctrl-0 = <&blsp2_i2c1_default>; 2286 pinctrl-1 = <&blsp2_i2c1_sleep>; 2287 clock-frequency = <400000>; 2288 2289 status = "disabled"; 2290 #address-cells = <1>; 2291 #size-cells = <0>; 2292 }; 2293 2294 blsp2_i2c2: i2c@c1b6000 { 2295 compatible = "qcom,i2c-qup-v2.2.1"; 2296 reg = <0x0c1b6000 0x600>; 2297 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2298 2299 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2300 <&gcc GCC_BLSP2_AHB_CLK>; 2301 clock-names = "core", "iface"; 2302 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2303 dma-names = "tx", "rx"; 2304 pinctrl-names = "default", "sleep"; 2305 pinctrl-0 = <&blsp2_i2c2_default>; 2306 pinctrl-1 = <&blsp2_i2c2_sleep>; 2307 clock-frequency = <400000>; 2308 2309 status = "disabled"; 2310 #address-cells = <1>; 2311 #size-cells = <0>; 2312 }; 2313 2314 blsp2_i2c3: i2c@c1b7000 { 2315 compatible = "qcom,i2c-qup-v2.2.1"; 2316 reg = <0x0c1b7000 0x600>; 2317 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2318 2319 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2320 <&gcc GCC_BLSP2_AHB_CLK>; 2321 clock-names = "core", "iface"; 2322 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2323 dma-names = "tx", "rx"; 2324 pinctrl-names = "default", "sleep"; 2325 pinctrl-0 = <&blsp2_i2c3_default>; 2326 pinctrl-1 = <&blsp2_i2c3_sleep>; 2327 clock-frequency = <400000>; 2328 2329 status = "disabled"; 2330 #address-cells = <1>; 2331 #size-cells = <0>; 2332 }; 2333 2334 blsp2_i2c4: i2c@c1b8000 { 2335 compatible = "qcom,i2c-qup-v2.2.1"; 2336 reg = <0x0c1b8000 0x600>; 2337 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2338 2339 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2340 <&gcc GCC_BLSP2_AHB_CLK>; 2341 clock-names = "core", "iface"; 2342 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2343 dma-names = "tx", "rx"; 2344 pinctrl-names = "default", "sleep"; 2345 pinctrl-0 = <&blsp2_i2c4_default>; 2346 pinctrl-1 = <&blsp2_i2c4_sleep>; 2347 clock-frequency = <400000>; 2348 2349 status = "disabled"; 2350 #address-cells = <1>; 2351 #size-cells = <0>; 2352 }; 2353 2354 blsp2_i2c5: i2c@c1b9000 { 2355 compatible = "qcom,i2c-qup-v2.2.1"; 2356 reg = <0x0c1b9000 0x600>; 2357 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2358 2359 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2360 <&gcc GCC_BLSP2_AHB_CLK>; 2361 clock-names = "core", "iface"; 2362 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2363 dma-names = "tx", "rx"; 2364 pinctrl-names = "default", "sleep"; 2365 pinctrl-0 = <&blsp2_i2c5_default>; 2366 pinctrl-1 = <&blsp2_i2c5_sleep>; 2367 clock-frequency = <400000>; 2368 2369 status = "disabled"; 2370 #address-cells = <1>; 2371 #size-cells = <0>; 2372 }; 2373 2374 blsp2_i2c6: i2c@c1ba000 { 2375 compatible = "qcom,i2c-qup-v2.2.1"; 2376 reg = <0x0c1ba000 0x600>; 2377 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2378 2379 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2380 <&gcc GCC_BLSP2_AHB_CLK>; 2381 clock-names = "core", "iface"; 2382 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2383 dma-names = "tx", "rx"; 2384 pinctrl-names = "default", "sleep"; 2385 pinctrl-0 = <&blsp2_i2c6_default>; 2386 pinctrl-1 = <&blsp2_i2c6_sleep>; 2387 clock-frequency = <400000>; 2388 2389 status = "disabled"; 2390 #address-cells = <1>; 2391 #size-cells = <0>; 2392 }; 2393 2394 mmcc: clock-controller@c8c0000 { 2395 compatible = "qcom,mmcc-msm8998"; 2396 #clock-cells = <1>; 2397 #reset-cells = <1>; 2398 #power-domain-cells = <1>; 2399 reg = <0xc8c0000 0x40000>; 2400 status = "disabled"; 2401 2402 clock-names = "xo", 2403 "gpll0", 2404 "dsi0dsi", 2405 "dsi0byte", 2406 "dsi1dsi", 2407 "dsi1byte", 2408 "hdmipll", 2409 "dplink", 2410 "dpvco", 2411 "core_bi_pll_test_se"; 2412 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2413 <&gcc GCC_MMSS_GPLL0_CLK>, 2414 <0>, 2415 <0>, 2416 <0>, 2417 <0>, 2418 <0>, 2419 <0>, 2420 <0>, 2421 <0>; 2422 }; 2423 2424 mmss_smmu: iommu@cd00000 { 2425 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 2426 reg = <0x0cd00000 0x40000>; 2427 #iommu-cells = <1>; 2428 2429 clocks = <&mmcc MNOC_AHB_CLK>, 2430 <&mmcc BIMC_SMMU_AHB_CLK>, 2431 <&rpmcc RPM_SMD_MMAXI_CLK>, 2432 <&mmcc BIMC_SMMU_AXI_CLK>; 2433 clock-names = "iface-mm", "iface-smmu", 2434 "bus-mm", "bus-smmu"; 2435 status = "disabled"; 2436 2437 #global-interrupts = <0>; 2438 interrupts = 2439 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2455 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2459 }; 2460 2461 remoteproc_adsp: remoteproc@17300000 { 2462 compatible = "qcom,msm8998-adsp-pas"; 2463 reg = <0x17300000 0x4040>; 2464 2465 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2466 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2467 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2468 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2469 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2470 interrupt-names = "wdog", "fatal", "ready", 2471 "handover", "stop-ack"; 2472 2473 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2474 clock-names = "xo"; 2475 2476 memory-region = <&adsp_mem>; 2477 2478 qcom,smem-states = <&adsp_smp2p_out 0>; 2479 qcom,smem-state-names = "stop"; 2480 2481 power-domains = <&rpmpd MSM8998_VDDCX>; 2482 power-domain-names = "cx"; 2483 2484 status = "disabled"; 2485 2486 glink-edge { 2487 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2488 label = "lpass"; 2489 qcom,remote-pid = <2>; 2490 mboxes = <&apcs_glb 9>; 2491 }; 2492 }; 2493 2494 apcs_glb: mailbox@17911000 { 2495 compatible = "qcom,msm8998-apcs-hmss-global"; 2496 reg = <0x17911000 0x1000>; 2497 2498 #mbox-cells = <1>; 2499 }; 2500 2501 timer@17920000 { 2502 #address-cells = <1>; 2503 #size-cells = <1>; 2504 ranges; 2505 compatible = "arm,armv7-timer-mem"; 2506 reg = <0x17920000 0x1000>; 2507 2508 frame@17921000 { 2509 frame-number = <0>; 2510 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2512 reg = <0x17921000 0x1000>, 2513 <0x17922000 0x1000>; 2514 }; 2515 2516 frame@17923000 { 2517 frame-number = <1>; 2518 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2519 reg = <0x17923000 0x1000>; 2520 status = "disabled"; 2521 }; 2522 2523 frame@17924000 { 2524 frame-number = <2>; 2525 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2526 reg = <0x17924000 0x1000>; 2527 status = "disabled"; 2528 }; 2529 2530 frame@17925000 { 2531 frame-number = <3>; 2532 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2533 reg = <0x17925000 0x1000>; 2534 status = "disabled"; 2535 }; 2536 2537 frame@17926000 { 2538 frame-number = <4>; 2539 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2540 reg = <0x17926000 0x1000>; 2541 status = "disabled"; 2542 }; 2543 2544 frame@17927000 { 2545 frame-number = <5>; 2546 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2547 reg = <0x17927000 0x1000>; 2548 status = "disabled"; 2549 }; 2550 2551 frame@17928000 { 2552 frame-number = <6>; 2553 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2554 reg = <0x17928000 0x1000>; 2555 status = "disabled"; 2556 }; 2557 }; 2558 2559 intc: interrupt-controller@17a00000 { 2560 compatible = "arm,gic-v3"; 2561 reg = <0x17a00000 0x10000>, /* GICD */ 2562 <0x17b00000 0x100000>; /* GICR * 8 */ 2563 #interrupt-cells = <3>; 2564 #address-cells = <1>; 2565 #size-cells = <1>; 2566 ranges; 2567 interrupt-controller; 2568 #redistributor-regions = <1>; 2569 redistributor-stride = <0x0 0x20000>; 2570 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2571 }; 2572 2573 wifi: wifi@18800000 { 2574 compatible = "qcom,wcn3990-wifi"; 2575 status = "disabled"; 2576 reg = <0x18800000 0x800000>; 2577 reg-names = "membase"; 2578 memory-region = <&wlan_msa_mem>; 2579 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2580 clock-names = "cxo_ref_clk_pin"; 2581 interrupts = 2582 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2594 iommus = <&anoc2_smmu 0x1900>, 2595 <&anoc2_smmu 0x1901>; 2596 qcom,snoc-host-cap-8bit-quirk; 2597 }; 2598 }; 2599}; 2600