1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6 7/ { 8 interrupt-parent = <&intc>; 9 10 qcom,msm-id = <292 0x0>; 11 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 chosen { }; 16 17 memory { 18 device_type = "memory"; 19 /* We expect the bootloader to fill in the reg */ 20 reg = <0 0 0 0>; 21 }; 22 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 memory@85800000 { 29 reg = <0x0 0x85800000 0x0 0x800000>; 30 no-map; 31 }; 32 33 smem_mem: smem-mem@86000000 { 34 reg = <0x0 0x86000000 0x0 0x200000>; 35 no-map; 36 }; 37 38 memory@86200000 { 39 reg = <0x0 0x86200000 0x0 0x2600000>; 40 no-map; 41 }; 42 43 rmtfs { 44 compatible = "qcom,rmtfs-mem"; 45 46 size = <0x0 0x200000>; 47 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 48 no-map; 49 50 qcom,client-id = <1>; 51 qcom,vmid = <15>; 52 }; 53 }; 54 55 clocks { 56 xo_board { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <19200000>; 60 }; 61 62 sleep_clk { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <32764>; 66 }; 67 }; 68 69 cpus { 70 #address-cells = <2>; 71 #size-cells = <0>; 72 73 CPU0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,armv8"; 76 reg = <0x0 0x0>; 77 enable-method = "psci"; 78 efficiency = <1024>; 79 next-level-cache = <&L2_0>; 80 L2_0: l2-cache { 81 compatible = "arm,arch-cache"; 82 cache-level = <2>; 83 }; 84 L1_I_0: l1-icache { 85 compatible = "arm,arch-cache"; 86 }; 87 L1_D_0: l1-dcache { 88 compatible = "arm,arch-cache"; 89 }; 90 }; 91 92 CPU1: cpu@1 { 93 device_type = "cpu"; 94 compatible = "arm,armv8"; 95 reg = <0x0 0x1>; 96 enable-method = "psci"; 97 efficiency = <1024>; 98 next-level-cache = <&L2_0>; 99 L1_I_1: l1-icache { 100 compatible = "arm,arch-cache"; 101 }; 102 L1_D_1: l1-dcache { 103 compatible = "arm,arch-cache"; 104 }; 105 }; 106 107 CPU2: cpu@2 { 108 device_type = "cpu"; 109 compatible = "arm,armv8"; 110 reg = <0x0 0x2>; 111 enable-method = "psci"; 112 efficiency = <1024>; 113 next-level-cache = <&L2_0>; 114 L1_I_2: l1-icache { 115 compatible = "arm,arch-cache"; 116 }; 117 L1_D_2: l1-dcache { 118 compatible = "arm,arch-cache"; 119 }; 120 }; 121 122 CPU3: cpu@3 { 123 device_type = "cpu"; 124 compatible = "arm,armv8"; 125 reg = <0x0 0x3>; 126 enable-method = "psci"; 127 efficiency = <1024>; 128 next-level-cache = <&L2_0>; 129 L1_I_3: l1-icache { 130 compatible = "arm,arch-cache"; 131 }; 132 L1_D_3: l1-dcache { 133 compatible = "arm,arch-cache"; 134 }; 135 }; 136 137 CPU4: cpu@100 { 138 device_type = "cpu"; 139 compatible = "arm,armv8"; 140 reg = <0x0 0x100>; 141 enable-method = "psci"; 142 efficiency = <1536>; 143 next-level-cache = <&L2_1>; 144 L2_1: l2-cache { 145 compatible = "arm,arch-cache"; 146 cache-level = <2>; 147 }; 148 L1_I_100: l1-icache { 149 compatible = "arm,arch-cache"; 150 }; 151 L1_D_100: l1-dcache { 152 compatible = "arm,arch-cache"; 153 }; 154 }; 155 156 CPU5: cpu@101 { 157 device_type = "cpu"; 158 compatible = "arm,armv8"; 159 reg = <0x0 0x101>; 160 enable-method = "psci"; 161 efficiency = <1536>; 162 next-level-cache = <&L2_1>; 163 L1_I_101: l1-icache { 164 compatible = "arm,arch-cache"; 165 }; 166 L1_D_101: l1-dcache { 167 compatible = "arm,arch-cache"; 168 }; 169 }; 170 171 CPU6: cpu@102 { 172 device_type = "cpu"; 173 compatible = "arm,armv8"; 174 reg = <0x0 0x102>; 175 enable-method = "psci"; 176 efficiency = <1536>; 177 next-level-cache = <&L2_1>; 178 L1_I_102: l1-icache { 179 compatible = "arm,arch-cache"; 180 }; 181 L1_D_102: l1-dcache { 182 compatible = "arm,arch-cache"; 183 }; 184 }; 185 186 CPU7: cpu@103 { 187 device_type = "cpu"; 188 compatible = "arm,armv8"; 189 reg = <0x0 0x103>; 190 enable-method = "psci"; 191 efficiency = <1536>; 192 next-level-cache = <&L2_1>; 193 L1_I_103: l1-icache { 194 compatible = "arm,arch-cache"; 195 }; 196 L1_D_103: l1-dcache { 197 compatible = "arm,arch-cache"; 198 }; 199 }; 200 201 cpu-map { 202 cluster0 { 203 core0 { 204 cpu = <&CPU0>; 205 }; 206 207 core1 { 208 cpu = <&CPU1>; 209 }; 210 211 core2 { 212 cpu = <&CPU2>; 213 }; 214 215 core3 { 216 cpu = <&CPU3>; 217 }; 218 }; 219 220 cluster1 { 221 core0 { 222 cpu = <&CPU4>; 223 }; 224 225 core1 { 226 cpu = <&CPU5>; 227 }; 228 229 core2 { 230 cpu = <&CPU6>; 231 }; 232 233 core3 { 234 cpu = <&CPU7>; 235 }; 236 }; 237 }; 238 }; 239 240 firmware { 241 scm { 242 compatible = "qcom,scm-msm8998"; 243 }; 244 }; 245 246 tcsr_mutex: hwlock { 247 compatible = "qcom,tcsr-mutex"; 248 syscon = <&tcsr_mutex_regs 0 0x1000>; 249 #hwlock-cells = <1>; 250 }; 251 252 psci { 253 compatible = "arm,psci-1.0"; 254 method = "smc"; 255 }; 256 257 rpm-glink { 258 compatible = "qcom,glink-rpm"; 259 260 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 261 qcom,rpm-msg-ram = <&rpm_msg_ram>; 262 mboxes = <&apcs_glb 0>; 263 264 rpm_requests: rpm-requests { 265 compatible = "qcom,rpm-msm8998"; 266 qcom,glink-channels = "rpm_requests"; 267 }; 268 }; 269 270 smem { 271 compatible = "qcom,smem"; 272 memory-region = <&smem_mem>; 273 hwlocks = <&tcsr_mutex 3>; 274 }; 275 276 smp2p-lpass { 277 compatible = "qcom,smp2p"; 278 qcom,smem = <443>, <429>; 279 280 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 281 282 mboxes = <&apcs_glb 10>; 283 284 qcom,local-pid = <0>; 285 qcom,remote-pid = <2>; 286 287 adsp_smp2p_out: master-kernel { 288 qcom,entry-name = "master-kernel"; 289 #qcom,smem-state-cells = <1>; 290 }; 291 292 adsp_smp2p_in: slave-kernel { 293 qcom,entry-name = "slave-kernel"; 294 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 }; 298 }; 299 300 smp2p-mpss { 301 compatible = "qcom,smp2p"; 302 qcom,smem = <435>, <428>; 303 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 304 mboxes = <&apcs_glb 14>; 305 qcom,local-pid = <0>; 306 qcom,remote-pid = <1>; 307 308 modem_smp2p_out: master-kernel { 309 qcom,entry-name = "master-kernel"; 310 #qcom,smem-state-cells = <1>; 311 }; 312 313 modem_smp2p_in: slave-kernel { 314 qcom,entry-name = "slave-kernel"; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 }; 318 }; 319 320 smp2p-slpi { 321 compatible = "qcom,smp2p"; 322 qcom,smem = <481>, <430>; 323 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 324 mboxes = <&apcs_glb 26>; 325 qcom,local-pid = <0>; 326 qcom,remote-pid = <3>; 327 328 slpi_smp2p_out: master-kernel { 329 qcom,entry-name = "master-kernel"; 330 #qcom,smem-state-cells = <1>; 331 }; 332 333 slpi_smp2p_in: slave-kernel { 334 qcom,entry-name = "slave-kernel"; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 }; 338 }; 339 340 thermal-zones { 341 cpu-thermal0 { 342 polling-delay-passive = <250>; 343 polling-delay = <1000>; 344 345 thermal-sensors = <&tsens0 6>; 346 347 trips { 348 cpu_alert0: trip0 { 349 temperature = <75000>; 350 hysteresis = <2000>; 351 type = "passive"; 352 }; 353 354 cpu_crit0: trip1 { 355 temperature = <110000>; 356 hysteresis = <2000>; 357 type = "critical"; 358 }; 359 }; 360 }; 361 362 cpu-thermal1 { 363 polling-delay-passive = <250>; 364 polling-delay = <1000>; 365 366 thermal-sensors = <&tsens0 7>; 367 368 trips { 369 cpu_alert1: trip0 { 370 temperature = <75000>; 371 hysteresis = <2000>; 372 type = "passive"; 373 }; 374 375 cpu_crit1: trip1 { 376 temperature = <110000>; 377 hysteresis = <2000>; 378 type = "critical"; 379 }; 380 }; 381 }; 382 383 cpu-thermal2 { 384 polling-delay-passive = <250>; 385 polling-delay = <1000>; 386 387 thermal-sensors = <&tsens0 8>; 388 389 trips { 390 cpu_alert2: trip0 { 391 temperature = <75000>; 392 hysteresis = <2000>; 393 type = "passive"; 394 }; 395 396 cpu_crit2: trip1 { 397 temperature = <110000>; 398 hysteresis = <2000>; 399 type = "critical"; 400 }; 401 }; 402 }; 403 404 cpu-thermal3 { 405 polling-delay-passive = <250>; 406 polling-delay = <1000>; 407 408 thermal-sensors = <&tsens0 9>; 409 410 trips { 411 cpu_alert3: trip0 { 412 temperature = <75000>; 413 hysteresis = <2000>; 414 type = "passive"; 415 }; 416 417 cpu_crit3: trip1 { 418 temperature = <110000>; 419 hysteresis = <2000>; 420 type = "critical"; 421 }; 422 }; 423 }; 424 425 cpu-thermal4 { 426 polling-delay-passive = <250>; 427 polling-delay = <1000>; 428 429 thermal-sensors = <&tsens0 10>; 430 431 trips { 432 cpu_alert4: trip0 { 433 temperature = <75000>; 434 hysteresis = <2000>; 435 type = "passive"; 436 }; 437 438 cpu_crit4: trip1 { 439 temperature = <110000>; 440 hysteresis = <2000>; 441 type = "critical"; 442 }; 443 }; 444 }; 445 446 cpu-thermal5 { 447 polling-delay-passive = <250>; 448 polling-delay = <1000>; 449 450 thermal-sensors = <&tsens0 11>; 451 452 trips { 453 cpu_alert5: trip0 { 454 temperature = <75000>; 455 hysteresis = <2000>; 456 type = "passive"; 457 }; 458 459 cpu_crit5: trip1 { 460 temperature = <110000>; 461 hysteresis = <2000>; 462 type = "critical"; 463 }; 464 }; 465 }; 466 467 cpu-thermal6 { 468 polling-delay-passive = <250>; 469 polling-delay = <1000>; 470 471 thermal-sensors = <&tsens1 0>; 472 473 trips { 474 cpu_alert6: trip0 { 475 temperature = <75000>; 476 hysteresis = <2000>; 477 type = "passive"; 478 }; 479 480 cpu_crit6: trip1 { 481 temperature = <110000>; 482 hysteresis = <2000>; 483 type = "critical"; 484 }; 485 }; 486 }; 487 488 cpu-thermal7 { 489 polling-delay-passive = <250>; 490 polling-delay = <1000>; 491 492 thermal-sensors = <&tsens1 1>; 493 494 trips { 495 cpu_alert7: trip0 { 496 temperature = <75000>; 497 hysteresis = <2000>; 498 type = "passive"; 499 }; 500 501 cpu_crit7: trip1 { 502 temperature = <110000>; 503 hysteresis = <2000>; 504 type = "critical"; 505 }; 506 }; 507 }; 508 509 gpu-thermal { 510 polling-delay-passive = <250>; 511 polling-delay = <1000>; 512 513 thermal-sensors = <&tsens1 3>; 514 }; 515 }; 516 517 timer { 518 compatible = "arm,armv8-timer"; 519 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 520 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 521 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 522 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 523 }; 524 525 soc: soc { 526 #address-cells = <1>; 527 #size-cells = <1>; 528 ranges = <0 0 0 0xffffffff>; 529 compatible = "simple-bus"; 530 531 rpm_msg_ram: memory@68000 { 532 compatible = "qcom,rpm-msg-ram"; 533 reg = <0x778000 0x7000>; 534 }; 535 536 qfprom: qfprom@780000 { 537 compatible = "qcom,qfprom"; 538 reg = <0x780000 0x621c>; 539 #address-cells = <1>; 540 #size-cells = <1>; 541 }; 542 543 gcc: clock-controller@100000 { 544 compatible = "qcom,gcc-msm8998"; 545 #clock-cells = <1>; 546 #reset-cells = <1>; 547 #power-domain-cells = <1>; 548 reg = <0x100000 0xb0000>; 549 }; 550 551 tlmm: pinctrl@3400000 { 552 compatible = "qcom,msm8998-pinctrl"; 553 reg = <0x3400000 0xc00000>; 554 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 555 gpio-controller; 556 #gpio-cells = <0x2>; 557 interrupt-controller; 558 #interrupt-cells = <0x2>; 559 }; 560 561 spmi_bus: spmi@800f000 { 562 compatible = "qcom,spmi-pmic-arb"; 563 reg = <0x800f000 0x1000>, 564 <0x8400000 0x1000000>, 565 <0x9400000 0x1000000>, 566 <0xa400000 0x220000>, 567 <0x800a000 0x3000>; 568 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 569 interrupt-names = "periph_irq"; 570 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 571 qcom,ee = <0>; 572 qcom,channel = <0>; 573 #address-cells = <2>; 574 #size-cells = <0>; 575 interrupt-controller; 576 #interrupt-cells = <4>; 577 cell-index = <0>; 578 }; 579 580 tsens0: thermal@10aa000 { 581 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 582 reg = <0x10aa000 0x2000>; 583 584 #qcom,sensors = <12>; 585 #thermal-sensor-cells = <1>; 586 }; 587 588 tsens1: thermal@10ad000 { 589 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 590 reg = <0x10ad000 0x2000>; 591 592 #qcom,sensors = <8>; 593 #thermal-sensor-cells = <1>; 594 }; 595 596 tcsr_mutex_regs: syscon@1f40000 { 597 compatible = "syscon"; 598 reg = <0x1f40000 0x20000>; 599 }; 600 601 apcs_glb: mailbox@9820000 { 602 compatible = "qcom,msm8998-apcs-hmss-global"; 603 reg = <0x17911000 0x1000>; 604 605 #mbox-cells = <1>; 606 }; 607 608 blsp2_uart1: serial@c1b0000 { 609 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 610 reg = <0xc1b0000 0x1000>; 611 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 613 <&gcc GCC_BLSP2_AHB_CLK>; 614 clock-names = "core", "iface"; 615 status = "disabled"; 616 }; 617 618 timer@17920000 { 619 #address-cells = <1>; 620 #size-cells = <1>; 621 ranges; 622 compatible = "arm,armv7-timer-mem"; 623 reg = <0x17920000 0x1000>; 624 625 frame@17921000 { 626 frame-number = <0>; 627 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 629 reg = <0x17921000 0x1000>, 630 <0x17922000 0x1000>; 631 }; 632 633 frame@17923000 { 634 frame-number = <1>; 635 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 636 reg = <0x17923000 0x1000>; 637 status = "disabled"; 638 }; 639 640 frame@17924000 { 641 frame-number = <2>; 642 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 643 reg = <0x17924000 0x1000>; 644 status = "disabled"; 645 }; 646 647 frame@17925000 { 648 frame-number = <3>; 649 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 650 reg = <0x17925000 0x1000>; 651 status = "disabled"; 652 }; 653 654 frame@17926000 { 655 frame-number = <4>; 656 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 657 reg = <0x17926000 0x1000>; 658 status = "disabled"; 659 }; 660 661 frame@17927000 { 662 frame-number = <5>; 663 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 664 reg = <0x17927000 0x1000>; 665 status = "disabled"; 666 }; 667 668 frame@17928000 { 669 frame-number = <6>; 670 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 671 reg = <0x17928000 0x1000>; 672 status = "disabled"; 673 }; 674 }; 675 676 intc: interrupt-controller@17a00000 { 677 compatible = "arm,gic-v3"; 678 reg = <0x17a00000 0x10000>, /* GICD */ 679 <0x17b00000 0x100000>; /* GICR * 8 */ 680 #interrupt-cells = <3>; 681 #address-cells = <1>; 682 #size-cells = <1>; 683 ranges; 684 interrupt-controller; 685 #redistributor-regions = <1>; 686 redistributor-stride = <0x0 0x20000>; 687 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 688 }; 689 }; 690}; 691