1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/gpio/gpio.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 qcom,msm-id = <292 0x0>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 memory { 22 device_type = "memory"; 23 /* We expect the bootloader to fill in the reg */ 24 reg = <0 0 0 0>; 25 }; 26 27 reserved-memory { 28 #address-cells = <2>; 29 #size-cells = <2>; 30 ranges; 31 32 hyp_mem: memory@85800000 { 33 reg = <0x0 0x85800000 0x0 0x600000>; 34 no-map; 35 }; 36 37 xbl_mem: memory@85e00000 { 38 reg = <0x0 0x85e00000 0x0 0x100000>; 39 no-map; 40 }; 41 42 smem_mem: smem-mem@86000000 { 43 reg = <0x0 0x86000000 0x0 0x200000>; 44 no-map; 45 }; 46 47 tz_mem: memory@86200000 { 48 reg = <0x0 0x86200000 0x0 0x2d00000>; 49 no-map; 50 }; 51 52 rmtfs_mem: memory@88f00000 { 53 compatible = "qcom,rmtfs-mem"; 54 reg = <0x0 0x88f00000 0x0 0x200000>; 55 no-map; 56 57 qcom,client-id = <1>; 58 qcom,vmid = <15>; 59 }; 60 61 spss_mem: memory@8ab00000 { 62 reg = <0x0 0x8ab00000 0x0 0x700000>; 63 no-map; 64 }; 65 66 adsp_mem: memory@8b200000 { 67 reg = <0x0 0x8b200000 0x0 0x1a00000>; 68 no-map; 69 }; 70 71 mpss_mem: memory@8cc00000 { 72 reg = <0x0 0x8cc00000 0x0 0x7000000>; 73 no-map; 74 }; 75 76 venus_mem: memory@93c00000 { 77 reg = <0x0 0x93c00000 0x0 0x500000>; 78 no-map; 79 }; 80 81 mba_mem: memory@94100000 { 82 reg = <0x0 0x94100000 0x0 0x200000>; 83 no-map; 84 }; 85 86 slpi_mem: memory@94300000 { 87 reg = <0x0 0x94300000 0x0 0xf00000>; 88 no-map; 89 }; 90 91 ipa_fw_mem: memory@95200000 { 92 reg = <0x0 0x95200000 0x0 0x10000>; 93 no-map; 94 }; 95 96 ipa_gsi_mem: memory@95210000 { 97 reg = <0x0 0x95210000 0x0 0x5000>; 98 no-map; 99 }; 100 101 gpu_mem: memory@95600000 { 102 reg = <0x0 0x95600000 0x0 0x100000>; 103 no-map; 104 }; 105 106 wlan_msa_mem: memory@95700000 { 107 reg = <0x0 0x95700000 0x0 0x100000>; 108 no-map; 109 }; 110 }; 111 112 clocks { 113 xo: xo-board { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <19200000>; 117 clock-output-names = "xo_board"; 118 }; 119 120 sleep_clk { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <32764>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <2>; 129 #size-cells = <0>; 130 131 CPU0: cpu@0 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo280"; 134 reg = <0x0 0x0>; 135 enable-method = "psci"; 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 137 next-level-cache = <&L2_0>; 138 L2_0: l2-cache { 139 compatible = "arm,arch-cache"; 140 cache-level = <2>; 141 }; 142 L1_I_0: l1-icache { 143 compatible = "arm,arch-cache"; 144 }; 145 L1_D_0: l1-dcache { 146 compatible = "arm,arch-cache"; 147 }; 148 }; 149 150 CPU1: cpu@1 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo280"; 153 reg = <0x0 0x1>; 154 enable-method = "psci"; 155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 156 next-level-cache = <&L2_0>; 157 L1_I_1: l1-icache { 158 compatible = "arm,arch-cache"; 159 }; 160 L1_D_1: l1-dcache { 161 compatible = "arm,arch-cache"; 162 }; 163 }; 164 165 CPU2: cpu@2 { 166 device_type = "cpu"; 167 compatible = "qcom,kryo280"; 168 reg = <0x0 0x2>; 169 enable-method = "psci"; 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 171 next-level-cache = <&L2_0>; 172 L1_I_2: l1-icache { 173 compatible = "arm,arch-cache"; 174 }; 175 L1_D_2: l1-dcache { 176 compatible = "arm,arch-cache"; 177 }; 178 }; 179 180 CPU3: cpu@3 { 181 device_type = "cpu"; 182 compatible = "qcom,kryo280"; 183 reg = <0x0 0x3>; 184 enable-method = "psci"; 185 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 186 next-level-cache = <&L2_0>; 187 L1_I_3: l1-icache { 188 compatible = "arm,arch-cache"; 189 }; 190 L1_D_3: l1-dcache { 191 compatible = "arm,arch-cache"; 192 }; 193 }; 194 195 CPU4: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo280"; 198 reg = <0x0 0x100>; 199 enable-method = "psci"; 200 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 201 next-level-cache = <&L2_1>; 202 L2_1: l2-cache { 203 compatible = "arm,arch-cache"; 204 cache-level = <2>; 205 }; 206 L1_I_100: l1-icache { 207 compatible = "arm,arch-cache"; 208 }; 209 L1_D_100: l1-dcache { 210 compatible = "arm,arch-cache"; 211 }; 212 }; 213 214 CPU5: cpu@101 { 215 device_type = "cpu"; 216 compatible = "qcom,kryo280"; 217 reg = <0x0 0x101>; 218 enable-method = "psci"; 219 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 220 next-level-cache = <&L2_1>; 221 L1_I_101: l1-icache { 222 compatible = "arm,arch-cache"; 223 }; 224 L1_D_101: l1-dcache { 225 compatible = "arm,arch-cache"; 226 }; 227 }; 228 229 CPU6: cpu@102 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo280"; 232 reg = <0x0 0x102>; 233 enable-method = "psci"; 234 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 235 next-level-cache = <&L2_1>; 236 L1_I_102: l1-icache { 237 compatible = "arm,arch-cache"; 238 }; 239 L1_D_102: l1-dcache { 240 compatible = "arm,arch-cache"; 241 }; 242 }; 243 244 CPU7: cpu@103 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo280"; 247 reg = <0x0 0x103>; 248 enable-method = "psci"; 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 250 next-level-cache = <&L2_1>; 251 L1_I_103: l1-icache { 252 compatible = "arm,arch-cache"; 253 }; 254 L1_D_103: l1-dcache { 255 compatible = "arm,arch-cache"; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&CPU0>; 263 }; 264 265 core1 { 266 cpu = <&CPU1>; 267 }; 268 269 core2 { 270 cpu = <&CPU2>; 271 }; 272 273 core3 { 274 cpu = <&CPU3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&CPU4>; 281 }; 282 283 core1 { 284 cpu = <&CPU5>; 285 }; 286 287 core2 { 288 cpu = <&CPU6>; 289 }; 290 291 core3 { 292 cpu = <&CPU7>; 293 }; 294 }; 295 }; 296 297 idle-states { 298 entry-method = "psci"; 299 300 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "little-retention"; 303 arm,psci-suspend-param = <0x00000002>; 304 entry-latency-us = <81>; 305 exit-latency-us = <86>; 306 min-residency-us = <200>; 307 }; 308 309 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 310 compatible = "arm,idle-state"; 311 idle-state-name = "little-power-collapse"; 312 arm,psci-suspend-param = <0x40000003>; 313 entry-latency-us = <273>; 314 exit-latency-us = <612>; 315 min-residency-us = <1000>; 316 local-timer-stop; 317 }; 318 319 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 320 compatible = "arm,idle-state"; 321 idle-state-name = "big-retention"; 322 arm,psci-suspend-param = <0x00000002>; 323 entry-latency-us = <79>; 324 exit-latency-us = <82>; 325 min-residency-us = <200>; 326 }; 327 328 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 329 compatible = "arm,idle-state"; 330 idle-state-name = "big-power-collapse"; 331 arm,psci-suspend-param = <0x40000003>; 332 entry-latency-us = <336>; 333 exit-latency-us = <525>; 334 min-residency-us = <1000>; 335 local-timer-stop; 336 }; 337 }; 338 }; 339 340 firmware { 341 scm { 342 compatible = "qcom,scm-msm8998", "qcom,scm"; 343 }; 344 }; 345 346 tcsr_mutex: hwlock { 347 compatible = "qcom,tcsr-mutex"; 348 syscon = <&tcsr_mutex_regs 0 0x1000>; 349 #hwlock-cells = <1>; 350 }; 351 352 psci { 353 compatible = "arm,psci-1.0"; 354 method = "smc"; 355 }; 356 357 rpm-glink { 358 compatible = "qcom,glink-rpm"; 359 360 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 361 qcom,rpm-msg-ram = <&rpm_msg_ram>; 362 mboxes = <&apcs_glb 0>; 363 364 rpm_requests: rpm-requests { 365 compatible = "qcom,rpm-msm8998"; 366 qcom,glink-channels = "rpm_requests"; 367 368 rpmcc: clock-controller { 369 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 370 #clock-cells = <1>; 371 }; 372 373 rpmpd: power-controller { 374 compatible = "qcom,msm8998-rpmpd"; 375 #power-domain-cells = <1>; 376 operating-points-v2 = <&rpmpd_opp_table>; 377 378 rpmpd_opp_table: opp-table { 379 compatible = "operating-points-v2"; 380 381 rpmpd_opp_ret: opp1 { 382 opp-level = <16>; 383 }; 384 385 rpmpd_opp_ret_plus: opp2 { 386 opp-level = <32>; 387 }; 388 389 rpmpd_opp_min_svs: opp3 { 390 opp-level = <48>; 391 }; 392 393 rpmpd_opp_low_svs: opp4 { 394 opp-level = <64>; 395 }; 396 397 rpmpd_opp_svs: opp5 { 398 opp-level = <128>; 399 }; 400 401 rpmpd_opp_svs_plus: opp6 { 402 opp-level = <192>; 403 }; 404 405 rpmpd_opp_nom: opp7 { 406 opp-level = <256>; 407 }; 408 409 rpmpd_opp_nom_plus: opp8 { 410 opp-level = <320>; 411 }; 412 413 rpmpd_opp_turbo: opp9 { 414 opp-level = <384>; 415 }; 416 417 rpmpd_opp_turbo_plus: opp10 { 418 opp-level = <512>; 419 }; 420 }; 421 }; 422 }; 423 }; 424 425 smem { 426 compatible = "qcom,smem"; 427 memory-region = <&smem_mem>; 428 hwlocks = <&tcsr_mutex 3>; 429 }; 430 431 smp2p-lpass { 432 compatible = "qcom,smp2p"; 433 qcom,smem = <443>, <429>; 434 435 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 436 437 mboxes = <&apcs_glb 10>; 438 439 qcom,local-pid = <0>; 440 qcom,remote-pid = <2>; 441 442 adsp_smp2p_out: master-kernel { 443 qcom,entry-name = "master-kernel"; 444 #qcom,smem-state-cells = <1>; 445 }; 446 447 adsp_smp2p_in: slave-kernel { 448 qcom,entry-name = "slave-kernel"; 449 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 }; 453 }; 454 455 smp2p-mpss { 456 compatible = "qcom,smp2p"; 457 qcom,smem = <435>, <428>; 458 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 459 mboxes = <&apcs_glb 14>; 460 qcom,local-pid = <0>; 461 qcom,remote-pid = <1>; 462 463 modem_smp2p_out: master-kernel { 464 qcom,entry-name = "master-kernel"; 465 #qcom,smem-state-cells = <1>; 466 }; 467 468 modem_smp2p_in: slave-kernel { 469 qcom,entry-name = "slave-kernel"; 470 interrupt-controller; 471 #interrupt-cells = <2>; 472 }; 473 }; 474 475 smp2p-slpi { 476 compatible = "qcom,smp2p"; 477 qcom,smem = <481>, <430>; 478 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 479 mboxes = <&apcs_glb 26>; 480 qcom,local-pid = <0>; 481 qcom,remote-pid = <3>; 482 483 slpi_smp2p_out: master-kernel { 484 qcom,entry-name = "master-kernel"; 485 #qcom,smem-state-cells = <1>; 486 }; 487 488 slpi_smp2p_in: slave-kernel { 489 qcom,entry-name = "slave-kernel"; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 }; 493 }; 494 495 thermal-zones { 496 cpu0-thermal { 497 polling-delay-passive = <250>; 498 polling-delay = <1000>; 499 500 thermal-sensors = <&tsens0 1>; 501 502 trips { 503 cpu0_alert0: trip-point0 { 504 temperature = <75000>; 505 hysteresis = <2000>; 506 type = "passive"; 507 }; 508 509 cpu0_crit: cpu_crit { 510 temperature = <110000>; 511 hysteresis = <2000>; 512 type = "critical"; 513 }; 514 }; 515 }; 516 517 cpu1-thermal { 518 polling-delay-passive = <250>; 519 polling-delay = <1000>; 520 521 thermal-sensors = <&tsens0 2>; 522 523 trips { 524 cpu1_alert0: trip-point0 { 525 temperature = <75000>; 526 hysteresis = <2000>; 527 type = "passive"; 528 }; 529 530 cpu1_crit: cpu_crit { 531 temperature = <110000>; 532 hysteresis = <2000>; 533 type = "critical"; 534 }; 535 }; 536 }; 537 538 cpu2-thermal { 539 polling-delay-passive = <250>; 540 polling-delay = <1000>; 541 542 thermal-sensors = <&tsens0 3>; 543 544 trips { 545 cpu2_alert0: trip-point0 { 546 temperature = <75000>; 547 hysteresis = <2000>; 548 type = "passive"; 549 }; 550 551 cpu2_crit: cpu_crit { 552 temperature = <110000>; 553 hysteresis = <2000>; 554 type = "critical"; 555 }; 556 }; 557 }; 558 559 cpu3-thermal { 560 polling-delay-passive = <250>; 561 polling-delay = <1000>; 562 563 thermal-sensors = <&tsens0 4>; 564 565 trips { 566 cpu3_alert0: trip-point0 { 567 temperature = <75000>; 568 hysteresis = <2000>; 569 type = "passive"; 570 }; 571 572 cpu3_crit: cpu_crit { 573 temperature = <110000>; 574 hysteresis = <2000>; 575 type = "critical"; 576 }; 577 }; 578 }; 579 580 cpu4-thermal { 581 polling-delay-passive = <250>; 582 polling-delay = <1000>; 583 584 thermal-sensors = <&tsens0 7>; 585 586 trips { 587 cpu4_alert0: trip-point0 { 588 temperature = <75000>; 589 hysteresis = <2000>; 590 type = "passive"; 591 }; 592 593 cpu4_crit: cpu_crit { 594 temperature = <110000>; 595 hysteresis = <2000>; 596 type = "critical"; 597 }; 598 }; 599 }; 600 601 cpu5-thermal { 602 polling-delay-passive = <250>; 603 polling-delay = <1000>; 604 605 thermal-sensors = <&tsens0 8>; 606 607 trips { 608 cpu5_alert0: trip-point0 { 609 temperature = <75000>; 610 hysteresis = <2000>; 611 type = "passive"; 612 }; 613 614 cpu5_crit: cpu_crit { 615 temperature = <110000>; 616 hysteresis = <2000>; 617 type = "critical"; 618 }; 619 }; 620 }; 621 622 cpu6-thermal { 623 polling-delay-passive = <250>; 624 polling-delay = <1000>; 625 626 thermal-sensors = <&tsens0 9>; 627 628 trips { 629 cpu6_alert0: trip-point0 { 630 temperature = <75000>; 631 hysteresis = <2000>; 632 type = "passive"; 633 }; 634 635 cpu6_crit: cpu_crit { 636 temperature = <110000>; 637 hysteresis = <2000>; 638 type = "critical"; 639 }; 640 }; 641 }; 642 643 cpu7-thermal { 644 polling-delay-passive = <250>; 645 polling-delay = <1000>; 646 647 thermal-sensors = <&tsens0 10>; 648 649 trips { 650 cpu7_alert0: trip-point0 { 651 temperature = <75000>; 652 hysteresis = <2000>; 653 type = "passive"; 654 }; 655 656 cpu7_crit: cpu_crit { 657 temperature = <110000>; 658 hysteresis = <2000>; 659 type = "critical"; 660 }; 661 }; 662 }; 663 664 gpu-thermal-bottom { 665 polling-delay-passive = <250>; 666 polling-delay = <1000>; 667 668 thermal-sensors = <&tsens0 12>; 669 670 trips { 671 gpu1_alert0: trip-point0 { 672 temperature = <90000>; 673 hysteresis = <2000>; 674 type = "hot"; 675 }; 676 }; 677 }; 678 679 gpu-thermal-top { 680 polling-delay-passive = <250>; 681 polling-delay = <1000>; 682 683 thermal-sensors = <&tsens0 13>; 684 685 trips { 686 gpu2_alert0: trip-point0 { 687 temperature = <90000>; 688 hysteresis = <2000>; 689 type = "hot"; 690 }; 691 }; 692 }; 693 694 clust0-mhm-thermal { 695 polling-delay-passive = <250>; 696 polling-delay = <1000>; 697 698 thermal-sensors = <&tsens0 5>; 699 700 trips { 701 cluster0_mhm_alert0: trip-point0 { 702 temperature = <90000>; 703 hysteresis = <2000>; 704 type = "hot"; 705 }; 706 }; 707 }; 708 709 clust1-mhm-thermal { 710 polling-delay-passive = <250>; 711 polling-delay = <1000>; 712 713 thermal-sensors = <&tsens0 6>; 714 715 trips { 716 cluster1_mhm_alert0: trip-point0 { 717 temperature = <90000>; 718 hysteresis = <2000>; 719 type = "hot"; 720 }; 721 }; 722 }; 723 724 cluster1-l2-thermal { 725 polling-delay-passive = <250>; 726 polling-delay = <1000>; 727 728 thermal-sensors = <&tsens0 11>; 729 730 trips { 731 cluster1_l2_alert0: trip-point0 { 732 temperature = <90000>; 733 hysteresis = <2000>; 734 type = "hot"; 735 }; 736 }; 737 }; 738 739 modem-thermal { 740 polling-delay-passive = <250>; 741 polling-delay = <1000>; 742 743 thermal-sensors = <&tsens1 1>; 744 745 trips { 746 modem_alert0: trip-point0 { 747 temperature = <90000>; 748 hysteresis = <2000>; 749 type = "hot"; 750 }; 751 }; 752 }; 753 754 mem-thermal { 755 polling-delay-passive = <250>; 756 polling-delay = <1000>; 757 758 thermal-sensors = <&tsens1 2>; 759 760 trips { 761 mem_alert0: trip-point0 { 762 temperature = <90000>; 763 hysteresis = <2000>; 764 type = "hot"; 765 }; 766 }; 767 }; 768 769 wlan-thermal { 770 polling-delay-passive = <250>; 771 polling-delay = <1000>; 772 773 thermal-sensors = <&tsens1 3>; 774 775 trips { 776 wlan_alert0: trip-point0 { 777 temperature = <90000>; 778 hysteresis = <2000>; 779 type = "hot"; 780 }; 781 }; 782 }; 783 784 q6-dsp-thermal { 785 polling-delay-passive = <250>; 786 polling-delay = <1000>; 787 788 thermal-sensors = <&tsens1 4>; 789 790 trips { 791 q6_dsp_alert0: trip-point0 { 792 temperature = <90000>; 793 hysteresis = <2000>; 794 type = "hot"; 795 }; 796 }; 797 }; 798 799 camera-thermal { 800 polling-delay-passive = <250>; 801 polling-delay = <1000>; 802 803 thermal-sensors = <&tsens1 5>; 804 805 trips { 806 camera_alert0: trip-point0 { 807 temperature = <90000>; 808 hysteresis = <2000>; 809 type = "hot"; 810 }; 811 }; 812 }; 813 814 multimedia-thermal { 815 polling-delay-passive = <250>; 816 polling-delay = <1000>; 817 818 thermal-sensors = <&tsens1 6>; 819 820 trips { 821 multimedia_alert0: trip-point0 { 822 temperature = <90000>; 823 hysteresis = <2000>; 824 type = "hot"; 825 }; 826 }; 827 }; 828 }; 829 830 timer { 831 compatible = "arm,armv8-timer"; 832 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 833 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 834 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 835 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 836 }; 837 838 soc: soc { 839 #address-cells = <1>; 840 #size-cells = <1>; 841 ranges = <0 0 0 0xffffffff>; 842 compatible = "simple-bus"; 843 844 gcc: clock-controller@100000 { 845 compatible = "qcom,gcc-msm8998"; 846 #clock-cells = <1>; 847 #reset-cells = <1>; 848 #power-domain-cells = <1>; 849 reg = <0x00100000 0xb0000>; 850 }; 851 852 rpm_msg_ram: memory@778000 { 853 compatible = "qcom,rpm-msg-ram"; 854 reg = <0x00778000 0x7000>; 855 }; 856 857 qfprom: qfprom@780000 { 858 compatible = "qcom,qfprom"; 859 reg = <0x00780000 0x621c>; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 863 qusb2_hstx_trim: hstx-trim@423a { 864 reg = <0x423a 0x1>; 865 bits = <0 4>; 866 }; 867 }; 868 869 tsens0: thermal@10ab000 { 870 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 871 reg = <0x010ab000 0x1000>, /* TM */ 872 <0x010aa000 0x1000>; /* SROT */ 873 #qcom,sensors = <14>; 874 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-names = "uplow", "critical"; 877 #thermal-sensor-cells = <1>; 878 }; 879 880 tsens1: thermal@10ae000 { 881 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 882 reg = <0x010ae000 0x1000>, /* TM */ 883 <0x010ad000 0x1000>; /* SROT */ 884 #qcom,sensors = <8>; 885 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "uplow", "critical"; 888 #thermal-sensor-cells = <1>; 889 }; 890 891 anoc1_smmu: iommu@1680000 { 892 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 893 reg = <0x01680000 0x10000>; 894 #iommu-cells = <1>; 895 896 #global-interrupts = <0>; 897 interrupts = 898 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 899 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 900 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 902 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 903 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 904 }; 905 906 anoc2_smmu: iommu@16c0000 { 907 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 908 reg = <0x016c0000 0x40000>; 909 #iommu-cells = <1>; 910 911 #global-interrupts = <0>; 912 interrupts = 913 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 914 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 915 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 916 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 917 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 918 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 919 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 920 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 921 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 922 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 923 }; 924 925 pcie0: pci@1c00000 { 926 compatible = "qcom,pcie-msm8996"; 927 reg = <0x01c00000 0x2000>, 928 <0x1b000000 0xf1d>, 929 <0x1b000f20 0xa8>, 930 <0x1b100000 0x100000>; 931 reg-names = "parf", "dbi", "elbi", "config"; 932 device_type = "pci"; 933 linux,pci-domain = <0>; 934 bus-range = <0x00 0xff>; 935 #address-cells = <3>; 936 #size-cells = <2>; 937 num-lanes = <1>; 938 phys = <&pciephy>; 939 phy-names = "pciephy"; 940 941 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, 942 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 943 944 #interrupt-cells = <1>; 945 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 946 interrupt-names = "msi"; 947 interrupt-map-mask = <0 0 0 0x7>; 948 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, 949 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, 950 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, 951 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; 952 953 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 954 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 955 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 956 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 957 <&gcc GCC_PCIE_0_AUX_CLK>; 958 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 959 960 power-domains = <&gcc PCIE_0_GDSC>; 961 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 962 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 963 }; 964 965 phy@1c06000 { 966 compatible = "qcom,msm8998-qmp-pcie-phy"; 967 reg = <0x01c06000 0x18c>; 968 #address-cells = <1>; 969 #size-cells = <1>; 970 ranges; 971 972 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 973 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 974 <&gcc GCC_PCIE_CLKREF_CLK>; 975 clock-names = "aux", "cfg_ahb", "ref"; 976 977 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 978 reset-names = "phy", "common"; 979 980 vdda-phy-supply = <&vreg_l1a_0p875>; 981 vdda-pll-supply = <&vreg_l2a_1p2>; 982 983 pciephy: lane@1c06800 { 984 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 985 #phy-cells = <0>; 986 987 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 988 clock-names = "pipe0"; 989 clock-output-names = "pcie_0_pipe_clk_src"; 990 #clock-cells = <0>; 991 }; 992 }; 993 994 ufshc: ufshc@1da4000 { 995 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 996 reg = <0x01da4000 0x2500>; 997 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 998 phys = <&ufsphy_lanes>; 999 phy-names = "ufsphy"; 1000 lanes-per-direction = <2>; 1001 power-domains = <&gcc UFS_GDSC>; 1002 #reset-cells = <1>; 1003 1004 clock-names = 1005 "core_clk", 1006 "bus_aggr_clk", 1007 "iface_clk", 1008 "core_clk_unipro", 1009 "ref_clk", 1010 "tx_lane0_sync_clk", 1011 "rx_lane0_sync_clk", 1012 "rx_lane1_sync_clk"; 1013 clocks = 1014 <&gcc GCC_UFS_AXI_CLK>, 1015 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1016 <&gcc GCC_UFS_AHB_CLK>, 1017 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1018 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1019 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1020 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1021 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1022 freq-table-hz = 1023 <50000000 200000000>, 1024 <0 0>, 1025 <0 0>, 1026 <37500000 150000000>, 1027 <0 0>, 1028 <0 0>, 1029 <0 0>, 1030 <0 0>; 1031 1032 resets = <&gcc GCC_UFS_BCR>; 1033 reset-names = "rst"; 1034 }; 1035 1036 ufsphy: phy@1da7000 { 1037 compatible = "qcom,msm8998-qmp-ufs-phy"; 1038 reg = <0x01da7000 0x18c>; 1039 #address-cells = <1>; 1040 #size-cells = <1>; 1041 ranges; 1042 1043 clock-names = 1044 "ref", 1045 "ref_aux"; 1046 clocks = 1047 <&gcc GCC_UFS_CLKREF_CLK>, 1048 <&gcc GCC_UFS_PHY_AUX_CLK>; 1049 1050 reset-names = "ufsphy"; 1051 resets = <&ufshc 0>; 1052 1053 ufsphy_lanes: lanes@1da7400 { 1054 reg = <0x01da7400 0x128>, 1055 <0x01da7600 0x1fc>, 1056 <0x01da7c00 0x1dc>, 1057 <0x01da7800 0x128>, 1058 <0x01da7a00 0x1fc>; 1059 #phy-cells = <0>; 1060 }; 1061 }; 1062 1063 tcsr_mutex_regs: syscon@1f40000 { 1064 compatible = "syscon"; 1065 reg = <0x01f40000 0x40000>; 1066 }; 1067 1068 tlmm: pinctrl@3400000 { 1069 compatible = "qcom,msm8998-pinctrl"; 1070 reg = <0x03400000 0xc00000>; 1071 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1072 gpio-controller; 1073 #gpio-cells = <0x2>; 1074 interrupt-controller; 1075 #interrupt-cells = <0x2>; 1076 }; 1077 1078 remoteproc_mss: remoteproc@4080000 { 1079 compatible = "qcom,msm8998-mss-pil"; 1080 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1081 reg-names = "qdsp6", "rmb"; 1082 1083 interrupts-extended = 1084 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1085 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1086 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1087 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1088 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1089 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1090 interrupt-names = "wdog", "fatal", "ready", 1091 "handover", "stop-ack", 1092 "shutdown-ack"; 1093 1094 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1095 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1096 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1097 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1098 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1099 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1100 <&rpmcc RPM_SMD_QDSS_CLK>, 1101 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1102 clock-names = "iface", "bus", "mem", "gpll0_mss", 1103 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1104 1105 qcom,smem-states = <&modem_smp2p_out 0>; 1106 qcom,smem-state-names = "stop"; 1107 1108 resets = <&gcc GCC_MSS_RESTART>; 1109 reset-names = "mss_restart"; 1110 1111 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1112 1113 power-domains = <&rpmpd MSM8998_VDDCX>, 1114 <&rpmpd MSM8998_VDDMX>; 1115 power-domain-names = "cx", "mx"; 1116 1117 mba { 1118 memory-region = <&mba_mem>; 1119 }; 1120 1121 mpss { 1122 memory-region = <&mpss_mem>; 1123 }; 1124 1125 glink-edge { 1126 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1127 label = "modem"; 1128 qcom,remote-pid = <1>; 1129 mboxes = <&apcs_glb 15>; 1130 }; 1131 }; 1132 1133 gpucc: clock-controller@5065000 { 1134 compatible = "qcom,msm8998-gpucc"; 1135 #clock-cells = <1>; 1136 #reset-cells = <1>; 1137 #power-domain-cells = <1>; 1138 reg = <0x05065000 0x9000>; 1139 1140 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1141 <&gcc GPLL0_OUT_MAIN>; 1142 clock-names = "xo", 1143 "gpll0"; 1144 }; 1145 1146 remoteproc_slpi: remoteproc@5800000 { 1147 compatible = "qcom,msm8998-slpi-pas"; 1148 reg = <0x05800000 0x4040>; 1149 1150 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1151 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1152 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1153 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1154 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1155 interrupt-names = "wdog", "fatal", "ready", 1156 "handover", "stop-ack"; 1157 1158 px-supply = <&vreg_lvs2a_1p8>; 1159 1160 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1161 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1162 clock-names = "xo", "aggre2"; 1163 1164 memory-region = <&slpi_mem>; 1165 1166 qcom,smem-states = <&slpi_smp2p_out 0>; 1167 qcom,smem-state-names = "stop"; 1168 1169 power-domains = <&rpmpd MSM8998_SSCCX>; 1170 power-domain-names = "ssc_cx"; 1171 1172 status = "disabled"; 1173 1174 glink-edge { 1175 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1176 label = "dsps"; 1177 qcom,remote-pid = <3>; 1178 mboxes = <&apcs_glb 27>; 1179 }; 1180 }; 1181 1182 stm: stm@6002000 { 1183 compatible = "arm,coresight-stm", "arm,primecell"; 1184 reg = <0x06002000 0x1000>, 1185 <0x16280000 0x180000>; 1186 reg-names = "stm-base", "stm-data-base"; 1187 status = "disabled"; 1188 1189 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1190 clock-names = "apb_pclk", "atclk"; 1191 1192 out-ports { 1193 port { 1194 stm_out: endpoint { 1195 remote-endpoint = <&funnel0_in7>; 1196 }; 1197 }; 1198 }; 1199 }; 1200 1201 funnel1: funnel@6041000 { 1202 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1203 reg = <0x06041000 0x1000>; 1204 status = "disabled"; 1205 1206 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1207 clock-names = "apb_pclk", "atclk"; 1208 1209 out-ports { 1210 port { 1211 funnel0_out: endpoint { 1212 remote-endpoint = 1213 <&merge_funnel_in0>; 1214 }; 1215 }; 1216 }; 1217 1218 in-ports { 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 1222 port@7 { 1223 reg = <7>; 1224 funnel0_in7: endpoint { 1225 remote-endpoint = <&stm_out>; 1226 }; 1227 }; 1228 }; 1229 }; 1230 1231 funnel2: funnel@6042000 { 1232 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1233 reg = <0x06042000 0x1000>; 1234 status = "disabled"; 1235 1236 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1237 clock-names = "apb_pclk", "atclk"; 1238 1239 out-ports { 1240 port { 1241 funnel1_out: endpoint { 1242 remote-endpoint = 1243 <&merge_funnel_in1>; 1244 }; 1245 }; 1246 }; 1247 1248 in-ports { 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 1252 port@6 { 1253 reg = <6>; 1254 funnel1_in6: endpoint { 1255 remote-endpoint = 1256 <&apss_merge_funnel_out>; 1257 }; 1258 }; 1259 }; 1260 }; 1261 1262 funnel3: funnel@6045000 { 1263 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1264 reg = <0x06045000 0x1000>; 1265 status = "disabled"; 1266 1267 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1268 clock-names = "apb_pclk", "atclk"; 1269 1270 out-ports { 1271 port { 1272 merge_funnel_out: endpoint { 1273 remote-endpoint = 1274 <&etf_in>; 1275 }; 1276 }; 1277 }; 1278 1279 in-ports { 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 1283 port@0 { 1284 reg = <0>; 1285 merge_funnel_in0: endpoint { 1286 remote-endpoint = 1287 <&funnel0_out>; 1288 }; 1289 }; 1290 1291 port@1 { 1292 reg = <1>; 1293 merge_funnel_in1: endpoint { 1294 remote-endpoint = 1295 <&funnel1_out>; 1296 }; 1297 }; 1298 }; 1299 }; 1300 1301 replicator1: replicator@6046000 { 1302 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1303 reg = <0x06046000 0x1000>; 1304 status = "disabled"; 1305 1306 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1307 clock-names = "apb_pclk", "atclk"; 1308 1309 out-ports { 1310 port { 1311 replicator_out: endpoint { 1312 remote-endpoint = <&etr_in>; 1313 }; 1314 }; 1315 }; 1316 1317 in-ports { 1318 port { 1319 replicator_in: endpoint { 1320 remote-endpoint = <&etf_out>; 1321 }; 1322 }; 1323 }; 1324 }; 1325 1326 etf: etf@6047000 { 1327 compatible = "arm,coresight-tmc", "arm,primecell"; 1328 reg = <0x06047000 0x1000>; 1329 status = "disabled"; 1330 1331 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1332 clock-names = "apb_pclk", "atclk"; 1333 1334 out-ports { 1335 port { 1336 etf_out: endpoint { 1337 remote-endpoint = 1338 <&replicator_in>; 1339 }; 1340 }; 1341 }; 1342 1343 in-ports { 1344 port { 1345 etf_in: endpoint { 1346 remote-endpoint = 1347 <&merge_funnel_out>; 1348 }; 1349 }; 1350 }; 1351 }; 1352 1353 etr: etr@6048000 { 1354 compatible = "arm,coresight-tmc", "arm,primecell"; 1355 reg = <0x06048000 0x1000>; 1356 status = "disabled"; 1357 1358 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1359 clock-names = "apb_pclk", "atclk"; 1360 arm,scatter-gather; 1361 1362 in-ports { 1363 port { 1364 etr_in: endpoint { 1365 remote-endpoint = 1366 <&replicator_out>; 1367 }; 1368 }; 1369 }; 1370 }; 1371 1372 etm1: etm@7840000 { 1373 compatible = "arm,coresight-etm4x", "arm,primecell"; 1374 reg = <0x07840000 0x1000>; 1375 status = "disabled"; 1376 1377 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1378 clock-names = "apb_pclk", "atclk"; 1379 1380 cpu = <&CPU0>; 1381 1382 out-ports { 1383 port { 1384 etm0_out: endpoint { 1385 remote-endpoint = 1386 <&apss_funnel_in0>; 1387 }; 1388 }; 1389 }; 1390 }; 1391 1392 etm2: etm@7940000 { 1393 compatible = "arm,coresight-etm4x", "arm,primecell"; 1394 reg = <0x07940000 0x1000>; 1395 status = "disabled"; 1396 1397 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1398 clock-names = "apb_pclk", "atclk"; 1399 1400 cpu = <&CPU1>; 1401 1402 out-ports { 1403 port { 1404 etm1_out: endpoint { 1405 remote-endpoint = 1406 <&apss_funnel_in1>; 1407 }; 1408 }; 1409 }; 1410 }; 1411 1412 etm3: etm@7a40000 { 1413 compatible = "arm,coresight-etm4x", "arm,primecell"; 1414 reg = <0x07a40000 0x1000>; 1415 status = "disabled"; 1416 1417 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1418 clock-names = "apb_pclk", "atclk"; 1419 1420 cpu = <&CPU2>; 1421 1422 out-ports { 1423 port { 1424 etm2_out: endpoint { 1425 remote-endpoint = 1426 <&apss_funnel_in2>; 1427 }; 1428 }; 1429 }; 1430 }; 1431 1432 etm4: etm@7b40000 { 1433 compatible = "arm,coresight-etm4x", "arm,primecell"; 1434 reg = <0x07b40000 0x1000>; 1435 status = "disabled"; 1436 1437 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1438 clock-names = "apb_pclk", "atclk"; 1439 1440 cpu = <&CPU3>; 1441 1442 out-ports { 1443 port { 1444 etm3_out: endpoint { 1445 remote-endpoint = 1446 <&apss_funnel_in3>; 1447 }; 1448 }; 1449 }; 1450 }; 1451 1452 funnel4: funnel@7b60000 { /* APSS Funnel */ 1453 compatible = "arm,coresight-etm4x", "arm,primecell"; 1454 reg = <0x07b60000 0x1000>; 1455 status = "disabled"; 1456 1457 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1458 clock-names = "apb_pclk", "atclk"; 1459 1460 out-ports { 1461 port { 1462 apss_funnel_out: endpoint { 1463 remote-endpoint = 1464 <&apss_merge_funnel_in>; 1465 }; 1466 }; 1467 }; 1468 1469 in-ports { 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 1473 port@0 { 1474 reg = <0>; 1475 apss_funnel_in0: endpoint { 1476 remote-endpoint = 1477 <&etm0_out>; 1478 }; 1479 }; 1480 1481 port@1 { 1482 reg = <1>; 1483 apss_funnel_in1: endpoint { 1484 remote-endpoint = 1485 <&etm1_out>; 1486 }; 1487 }; 1488 1489 port@2 { 1490 reg = <2>; 1491 apss_funnel_in2: endpoint { 1492 remote-endpoint = 1493 <&etm2_out>; 1494 }; 1495 }; 1496 1497 port@3 { 1498 reg = <3>; 1499 apss_funnel_in3: endpoint { 1500 remote-endpoint = 1501 <&etm3_out>; 1502 }; 1503 }; 1504 1505 port@4 { 1506 reg = <4>; 1507 apss_funnel_in4: endpoint { 1508 remote-endpoint = 1509 <&etm4_out>; 1510 }; 1511 }; 1512 1513 port@5 { 1514 reg = <5>; 1515 apss_funnel_in5: endpoint { 1516 remote-endpoint = 1517 <&etm5_out>; 1518 }; 1519 }; 1520 1521 port@6 { 1522 reg = <6>; 1523 apss_funnel_in6: endpoint { 1524 remote-endpoint = 1525 <&etm6_out>; 1526 }; 1527 }; 1528 1529 port@7 { 1530 reg = <7>; 1531 apss_funnel_in7: endpoint { 1532 remote-endpoint = 1533 <&etm7_out>; 1534 }; 1535 }; 1536 }; 1537 }; 1538 1539 funnel5: funnel@7b70000 { 1540 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1541 reg = <0x07b70000 0x1000>; 1542 status = "disabled"; 1543 1544 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1545 clock-names = "apb_pclk", "atclk"; 1546 1547 out-ports { 1548 port { 1549 apss_merge_funnel_out: endpoint { 1550 remote-endpoint = 1551 <&funnel1_in6>; 1552 }; 1553 }; 1554 }; 1555 1556 in-ports { 1557 port { 1558 apss_merge_funnel_in: endpoint { 1559 remote-endpoint = 1560 <&apss_funnel_out>; 1561 }; 1562 }; 1563 }; 1564 }; 1565 1566 etm5: etm@7c40000 { 1567 compatible = "arm,coresight-etm4x", "arm,primecell"; 1568 reg = <0x07c40000 0x1000>; 1569 status = "disabled"; 1570 1571 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1572 clock-names = "apb_pclk", "atclk"; 1573 1574 cpu = <&CPU4>; 1575 1576 port{ 1577 etm4_out: endpoint { 1578 remote-endpoint = <&apss_funnel_in4>; 1579 }; 1580 }; 1581 }; 1582 1583 etm6: etm@7d40000 { 1584 compatible = "arm,coresight-etm4x", "arm,primecell"; 1585 reg = <0x07d40000 0x1000>; 1586 status = "disabled"; 1587 1588 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1589 clock-names = "apb_pclk", "atclk"; 1590 1591 cpu = <&CPU5>; 1592 1593 port{ 1594 etm5_out: endpoint { 1595 remote-endpoint = <&apss_funnel_in5>; 1596 }; 1597 }; 1598 }; 1599 1600 etm7: etm@7e40000 { 1601 compatible = "arm,coresight-etm4x", "arm,primecell"; 1602 reg = <0x07e40000 0x1000>; 1603 status = "disabled"; 1604 1605 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1606 clock-names = "apb_pclk", "atclk"; 1607 1608 cpu = <&CPU6>; 1609 1610 port{ 1611 etm6_out: endpoint { 1612 remote-endpoint = <&apss_funnel_in6>; 1613 }; 1614 }; 1615 }; 1616 1617 etm8: etm@7f40000 { 1618 compatible = "arm,coresight-etm4x", "arm,primecell"; 1619 reg = <0x07f40000 0x1000>; 1620 status = "disabled"; 1621 1622 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1623 clock-names = "apb_pclk", "atclk"; 1624 1625 cpu = <&CPU7>; 1626 1627 port{ 1628 etm7_out: endpoint { 1629 remote-endpoint = <&apss_funnel_in7>; 1630 }; 1631 }; 1632 }; 1633 1634 spmi_bus: spmi@800f000 { 1635 compatible = "qcom,spmi-pmic-arb"; 1636 reg = <0x0800f000 0x1000>, 1637 <0x08400000 0x1000000>, 1638 <0x09400000 0x1000000>, 1639 <0x0a400000 0x220000>, 1640 <0x0800a000 0x3000>; 1641 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1642 interrupt-names = "periph_irq"; 1643 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1644 qcom,ee = <0>; 1645 qcom,channel = <0>; 1646 #address-cells = <2>; 1647 #size-cells = <0>; 1648 interrupt-controller; 1649 #interrupt-cells = <4>; 1650 cell-index = <0>; 1651 }; 1652 1653 usb3: usb@a8f8800 { 1654 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 1655 reg = <0x0a8f8800 0x400>; 1656 status = "disabled"; 1657 #address-cells = <1>; 1658 #size-cells = <1>; 1659 ranges; 1660 1661 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1662 <&gcc GCC_USB30_MASTER_CLK>, 1663 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 1664 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1665 <&gcc GCC_USB30_SLEEP_CLK>; 1666 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1667 "sleep"; 1668 1669 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1670 <&gcc GCC_USB30_MASTER_CLK>; 1671 assigned-clock-rates = <19200000>, <120000000>; 1672 1673 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1675 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1676 1677 power-domains = <&gcc USB_30_GDSC>; 1678 1679 resets = <&gcc GCC_USB_30_BCR>; 1680 1681 usb3_dwc3: dwc3@a800000 { 1682 compatible = "snps,dwc3"; 1683 reg = <0x0a800000 0xcd00>; 1684 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1685 snps,dis_u2_susphy_quirk; 1686 snps,dis_enblslpm_quirk; 1687 phys = <&qusb2phy>, <&usb1_ssphy>; 1688 phy-names = "usb2-phy", "usb3-phy"; 1689 snps,has-lpm-erratum; 1690 snps,hird-threshold = /bits/ 8 <0x10>; 1691 }; 1692 }; 1693 1694 usb3phy: phy@c010000 { 1695 compatible = "qcom,msm8998-qmp-usb3-phy"; 1696 reg = <0x0c010000 0x18c>; 1697 status = "disabled"; 1698 #clock-cells = <1>; 1699 #address-cells = <1>; 1700 #size-cells = <1>; 1701 ranges; 1702 1703 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1704 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1705 <&gcc GCC_USB3_CLKREF_CLK>; 1706 clock-names = "aux", "cfg_ahb", "ref"; 1707 1708 resets = <&gcc GCC_USB3_PHY_BCR>, 1709 <&gcc GCC_USB3PHY_PHY_BCR>; 1710 reset-names = "phy", "common"; 1711 1712 usb1_ssphy: lane@c010200 { 1713 reg = <0xc010200 0x128>, 1714 <0xc010400 0x200>, 1715 <0xc010c00 0x20c>, 1716 <0xc010600 0x128>, 1717 <0xc010800 0x200>; 1718 #phy-cells = <0>; 1719 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1720 clock-names = "pipe0"; 1721 clock-output-names = "usb3_phy_pipe_clk_src"; 1722 }; 1723 }; 1724 1725 qusb2phy: phy@c012000 { 1726 compatible = "qcom,msm8998-qusb2-phy"; 1727 reg = <0x0c012000 0x2a8>; 1728 status = "disabled"; 1729 #phy-cells = <0>; 1730 1731 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1732 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1733 clock-names = "cfg_ahb", "ref"; 1734 1735 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1736 1737 nvmem-cells = <&qusb2_hstx_trim>; 1738 }; 1739 1740 sdhc2: sdhci@c0a4900 { 1741 compatible = "qcom,sdhci-msm-v4"; 1742 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 1743 reg-names = "hc_mem", "core_mem"; 1744 1745 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1747 interrupt-names = "hc_irq", "pwr_irq"; 1748 1749 clock-names = "iface", "core", "xo"; 1750 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1751 <&gcc GCC_SDCC2_APPS_CLK>, 1752 <&xo>; 1753 bus-width = <4>; 1754 status = "disabled"; 1755 }; 1756 1757 blsp1_dma: dma@c144000 { 1758 compatible = "qcom,bam-v1.7.0"; 1759 reg = <0x0c144000 0x25000>; 1760 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1761 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1762 clock-names = "bam_clk"; 1763 #dma-cells = <1>; 1764 qcom,ee = <0>; 1765 qcom,controlled-remotely; 1766 num-channels = <18>; 1767 qcom,num-ees = <4>; 1768 }; 1769 1770 blsp1_uart3: serial@c171000 { 1771 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1772 reg = <0x0c171000 0x1000>; 1773 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1774 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 1775 <&gcc GCC_BLSP1_AHB_CLK>; 1776 clock-names = "core", "iface"; 1777 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1778 dma-names = "tx", "rx"; 1779 pinctrl-names = "default"; 1780 pinctrl-0 = <&blsp1_uart3_on>; 1781 status = "disabled"; 1782 }; 1783 1784 blsp1_i2c1: i2c@c175000 { 1785 compatible = "qcom,i2c-qup-v2.2.1"; 1786 reg = <0x0c175000 0x600>; 1787 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1788 1789 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1790 <&gcc GCC_BLSP1_AHB_CLK>; 1791 clock-names = "core", "iface"; 1792 clock-frequency = <400000>; 1793 1794 status = "disabled"; 1795 #address-cells = <1>; 1796 #size-cells = <0>; 1797 }; 1798 1799 blsp1_i2c2: i2c@c176000 { 1800 compatible = "qcom,i2c-qup-v2.2.1"; 1801 reg = <0x0c176000 0x600>; 1802 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1803 1804 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1805 <&gcc GCC_BLSP1_AHB_CLK>; 1806 clock-names = "core", "iface"; 1807 clock-frequency = <400000>; 1808 1809 status = "disabled"; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 }; 1813 1814 blsp1_i2c3: i2c@c177000 { 1815 compatible = "qcom,i2c-qup-v2.2.1"; 1816 reg = <0x0c177000 0x600>; 1817 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1818 1819 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1820 <&gcc GCC_BLSP1_AHB_CLK>; 1821 clock-names = "core", "iface"; 1822 clock-frequency = <400000>; 1823 1824 status = "disabled"; 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 }; 1828 1829 blsp1_i2c4: i2c@c178000 { 1830 compatible = "qcom,i2c-qup-v2.2.1"; 1831 reg = <0x0c178000 0x600>; 1832 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1833 1834 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1835 <&gcc GCC_BLSP1_AHB_CLK>; 1836 clock-names = "core", "iface"; 1837 clock-frequency = <400000>; 1838 1839 status = "disabled"; 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 }; 1843 1844 blsp1_i2c5: i2c@c179000 { 1845 compatible = "qcom,i2c-qup-v2.2.1"; 1846 reg = <0x0c179000 0x600>; 1847 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1848 1849 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1850 <&gcc GCC_BLSP1_AHB_CLK>; 1851 clock-names = "core", "iface"; 1852 clock-frequency = <400000>; 1853 1854 status = "disabled"; 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 }; 1858 1859 blsp1_i2c6: i2c@c17a000 { 1860 compatible = "qcom,i2c-qup-v2.2.1"; 1861 reg = <0x0c17a000 0x600>; 1862 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1863 1864 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1865 <&gcc GCC_BLSP1_AHB_CLK>; 1866 clock-names = "core", "iface"; 1867 clock-frequency = <400000>; 1868 1869 status = "disabled"; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 }; 1873 1874 blsp2_uart1: serial@c1b0000 { 1875 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1876 reg = <0x0c1b0000 0x1000>; 1877 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1878 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1879 <&gcc GCC_BLSP2_AHB_CLK>; 1880 clock-names = "core", "iface"; 1881 status = "disabled"; 1882 }; 1883 1884 blsp2_i2c0: i2c@c1b5000 { 1885 compatible = "qcom,i2c-qup-v2.2.1"; 1886 reg = <0x0c1b5000 0x600>; 1887 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1888 1889 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1890 <&gcc GCC_BLSP2_AHB_CLK>; 1891 clock-names = "core", "iface"; 1892 clock-frequency = <400000>; 1893 1894 status = "disabled"; 1895 #address-cells = <1>; 1896 #size-cells = <0>; 1897 }; 1898 1899 blsp2_i2c1: i2c@c1b6000 { 1900 compatible = "qcom,i2c-qup-v2.2.1"; 1901 reg = <0x0c1b6000 0x600>; 1902 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1903 1904 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1905 <&gcc GCC_BLSP2_AHB_CLK>; 1906 clock-names = "core", "iface"; 1907 clock-frequency = <400000>; 1908 1909 status = "disabled"; 1910 #address-cells = <1>; 1911 #size-cells = <0>; 1912 }; 1913 1914 blsp2_i2c2: i2c@c1b7000 { 1915 compatible = "qcom,i2c-qup-v2.2.1"; 1916 reg = <0x0c1b7000 0x600>; 1917 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1918 1919 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1920 <&gcc GCC_BLSP2_AHB_CLK>; 1921 clock-names = "core", "iface"; 1922 clock-frequency = <400000>; 1923 1924 status = "disabled"; 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 }; 1928 1929 blsp2_i2c3: i2c@c1b8000 { 1930 compatible = "qcom,i2c-qup-v2.2.1"; 1931 reg = <0x0c1b8000 0x600>; 1932 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1933 1934 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1935 <&gcc GCC_BLSP2_AHB_CLK>; 1936 clock-names = "core", "iface"; 1937 clock-frequency = <400000>; 1938 1939 status = "disabled"; 1940 #address-cells = <1>; 1941 #size-cells = <0>; 1942 }; 1943 1944 blsp2_i2c4: i2c@c1b9000 { 1945 compatible = "qcom,i2c-qup-v2.2.1"; 1946 reg = <0x0c1b9000 0x600>; 1947 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1948 1949 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 1950 <&gcc GCC_BLSP2_AHB_CLK>; 1951 clock-names = "core", "iface"; 1952 clock-frequency = <400000>; 1953 1954 status = "disabled"; 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 }; 1958 1959 blsp2_i2c5: i2c@c1ba000 { 1960 compatible = "qcom,i2c-qup-v2.2.1"; 1961 reg = <0x0c1ba000 0x600>; 1962 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1963 1964 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 1965 <&gcc GCC_BLSP2_AHB_CLK>; 1966 clock-names = "core", "iface"; 1967 clock-frequency = <400000>; 1968 1969 status = "disabled"; 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 }; 1973 1974 remoteproc_adsp: remoteproc@17300000 { 1975 compatible = "qcom,msm8998-adsp-pas"; 1976 reg = <0x17300000 0x4040>; 1977 1978 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 1979 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1980 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1981 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1982 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1983 interrupt-names = "wdog", "fatal", "ready", 1984 "handover", "stop-ack"; 1985 1986 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1987 clock-names = "xo"; 1988 1989 memory-region = <&adsp_mem>; 1990 1991 qcom,smem-states = <&adsp_smp2p_out 0>; 1992 qcom,smem-state-names = "stop"; 1993 1994 power-domains = <&rpmpd MSM8998_VDDCX>; 1995 power-domain-names = "cx"; 1996 1997 status = "disabled"; 1998 1999 glink-edge { 2000 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2001 label = "lpass"; 2002 qcom,remote-pid = <2>; 2003 mboxes = <&apcs_glb 9>; 2004 }; 2005 }; 2006 2007 apcs_glb: mailbox@17911000 { 2008 compatible = "qcom,msm8998-apcs-hmss-global"; 2009 reg = <0x17911000 0x1000>; 2010 2011 #mbox-cells = <1>; 2012 }; 2013 2014 timer@17920000 { 2015 #address-cells = <1>; 2016 #size-cells = <1>; 2017 ranges; 2018 compatible = "arm,armv7-timer-mem"; 2019 reg = <0x17920000 0x1000>; 2020 2021 frame@17921000 { 2022 frame-number = <0>; 2023 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2025 reg = <0x17921000 0x1000>, 2026 <0x17922000 0x1000>; 2027 }; 2028 2029 frame@17923000 { 2030 frame-number = <1>; 2031 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2032 reg = <0x17923000 0x1000>; 2033 status = "disabled"; 2034 }; 2035 2036 frame@17924000 { 2037 frame-number = <2>; 2038 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2039 reg = <0x17924000 0x1000>; 2040 status = "disabled"; 2041 }; 2042 2043 frame@17925000 { 2044 frame-number = <3>; 2045 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2046 reg = <0x17925000 0x1000>; 2047 status = "disabled"; 2048 }; 2049 2050 frame@17926000 { 2051 frame-number = <4>; 2052 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2053 reg = <0x17926000 0x1000>; 2054 status = "disabled"; 2055 }; 2056 2057 frame@17927000 { 2058 frame-number = <5>; 2059 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2060 reg = <0x17927000 0x1000>; 2061 status = "disabled"; 2062 }; 2063 2064 frame@17928000 { 2065 frame-number = <6>; 2066 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2067 reg = <0x17928000 0x1000>; 2068 status = "disabled"; 2069 }; 2070 }; 2071 2072 intc: interrupt-controller@17a00000 { 2073 compatible = "arm,gic-v3"; 2074 reg = <0x17a00000 0x10000>, /* GICD */ 2075 <0x17b00000 0x100000>; /* GICR * 8 */ 2076 #interrupt-cells = <3>; 2077 #address-cells = <1>; 2078 #size-cells = <1>; 2079 ranges; 2080 interrupt-controller; 2081 #redistributor-regions = <1>; 2082 redistributor-stride = <0x0 0x20000>; 2083 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2084 }; 2085 2086 wifi: wifi@18800000 { 2087 compatible = "qcom,wcn3990-wifi"; 2088 status = "disabled"; 2089 reg = <0x18800000 0x800000>; 2090 reg-names = "membase"; 2091 memory-region = <&wlan_msa_mem>; 2092 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2093 clock-names = "cxo_ref_clk_pin"; 2094 interrupts = 2095 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2107 iommus = <&anoc2_smmu 0x1900>, 2108 <&anoc2_smmu 0x1901>; 2109 qcom,snoc-host-cap-8bit-quirk; 2110 }; 2111 }; 2112}; 2113 2114#include "msm8998-pins.dtsi" 2115