1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 qcom,msm-id = <292 0x0>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 memory@80000000 { 23 device_type = "memory"; 24 /* We expect the bootloader to fill in the reg */ 25 reg = <0x0 0x80000000 0x0 0x0>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 hyp_mem: memory@85800000 { 34 reg = <0x0 0x85800000 0x0 0x600000>; 35 no-map; 36 }; 37 38 xbl_mem: memory@85e00000 { 39 reg = <0x0 0x85e00000 0x0 0x100000>; 40 no-map; 41 }; 42 43 smem_mem: smem-mem@86000000 { 44 reg = <0x0 0x86000000 0x0 0x200000>; 45 no-map; 46 }; 47 48 tz_mem: memory@86200000 { 49 reg = <0x0 0x86200000 0x0 0x2d00000>; 50 no-map; 51 }; 52 53 rmtfs_mem: memory@88f00000 { 54 compatible = "qcom,rmtfs-mem"; 55 reg = <0x0 0x88f00000 0x0 0x200000>; 56 no-map; 57 58 qcom,client-id = <1>; 59 qcom,vmid = <15>; 60 }; 61 62 spss_mem: memory@8ab00000 { 63 reg = <0x0 0x8ab00000 0x0 0x700000>; 64 no-map; 65 }; 66 67 adsp_mem: memory@8b200000 { 68 reg = <0x0 0x8b200000 0x0 0x1a00000>; 69 no-map; 70 }; 71 72 mpss_mem: memory@8cc00000 { 73 reg = <0x0 0x8cc00000 0x0 0x7000000>; 74 no-map; 75 }; 76 77 venus_mem: memory@93c00000 { 78 reg = <0x0 0x93c00000 0x0 0x500000>; 79 no-map; 80 }; 81 82 mba_mem: memory@94100000 { 83 reg = <0x0 0x94100000 0x0 0x200000>; 84 no-map; 85 }; 86 87 slpi_mem: memory@94300000 { 88 reg = <0x0 0x94300000 0x0 0xf00000>; 89 no-map; 90 }; 91 92 ipa_fw_mem: memory@95200000 { 93 reg = <0x0 0x95200000 0x0 0x10000>; 94 no-map; 95 }; 96 97 ipa_gsi_mem: memory@95210000 { 98 reg = <0x0 0x95210000 0x0 0x5000>; 99 no-map; 100 }; 101 102 gpu_mem: memory@95600000 { 103 reg = <0x0 0x95600000 0x0 0x100000>; 104 no-map; 105 }; 106 107 wlan_msa_mem: memory@95700000 { 108 reg = <0x0 0x95700000 0x0 0x100000>; 109 no-map; 110 }; 111 112 mdata_mem: mpss-metadata { 113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 114 size = <0x0 0x4000>; 115 no-map; 116 }; 117 }; 118 119 clocks { 120 xo: xo-board { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <19200000>; 124 clock-output-names = "xo_board"; 125 }; 126 127 sleep_clk: sleep-clk { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <32764>; 131 }; 132 }; 133 134 cpus { 135 #address-cells = <2>; 136 #size-cells = <0>; 137 138 CPU0: cpu@0 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo280"; 141 reg = <0x0 0x0>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 145 next-level-cache = <&L2_0>; 146 L2_0: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 }; 151 }; 152 153 CPU1: cpu@1 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo280"; 156 reg = <0x0 0x1>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <1024>; 159 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 160 next-level-cache = <&L2_0>; 161 }; 162 163 CPU2: cpu@2 { 164 device_type = "cpu"; 165 compatible = "qcom,kryo280"; 166 reg = <0x0 0x2>; 167 enable-method = "psci"; 168 capacity-dmips-mhz = <1024>; 169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 170 next-level-cache = <&L2_0>; 171 }; 172 173 CPU3: cpu@3 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo280"; 176 reg = <0x0 0x3>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <1024>; 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 180 next-level-cache = <&L2_0>; 181 }; 182 183 CPU4: cpu@100 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo280"; 186 reg = <0x0 0x100>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1536>; 189 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 190 next-level-cache = <&L2_1>; 191 L2_1: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 }; 196 }; 197 198 CPU5: cpu@101 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo280"; 201 reg = <0x0 0x101>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1536>; 204 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 205 next-level-cache = <&L2_1>; 206 }; 207 208 CPU6: cpu@102 { 209 device_type = "cpu"; 210 compatible = "qcom,kryo280"; 211 reg = <0x0 0x102>; 212 enable-method = "psci"; 213 capacity-dmips-mhz = <1536>; 214 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 215 next-level-cache = <&L2_1>; 216 }; 217 218 CPU7: cpu@103 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo280"; 221 reg = <0x0 0x103>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1536>; 224 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 225 next-level-cache = <&L2_1>; 226 }; 227 228 cpu-map { 229 cluster0 { 230 core0 { 231 cpu = <&CPU0>; 232 }; 233 234 core1 { 235 cpu = <&CPU1>; 236 }; 237 238 core2 { 239 cpu = <&CPU2>; 240 }; 241 242 core3 { 243 cpu = <&CPU3>; 244 }; 245 }; 246 247 cluster1 { 248 core0 { 249 cpu = <&CPU4>; 250 }; 251 252 core1 { 253 cpu = <&CPU5>; 254 }; 255 256 core2 { 257 cpu = <&CPU6>; 258 }; 259 260 core3 { 261 cpu = <&CPU7>; 262 }; 263 }; 264 }; 265 266 idle-states { 267 entry-method = "psci"; 268 269 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 270 compatible = "arm,idle-state"; 271 idle-state-name = "little-retention"; 272 /* CPU Retention (C2D), L2 Active */ 273 arm,psci-suspend-param = <0x00000002>; 274 entry-latency-us = <81>; 275 exit-latency-us = <86>; 276 min-residency-us = <504>; 277 }; 278 279 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "little-power-collapse"; 282 /* CPU + L2 Power Collapse (C3, D4) */ 283 arm,psci-suspend-param = <0x40000003>; 284 entry-latency-us = <814>; 285 exit-latency-us = <4562>; 286 min-residency-us = <9183>; 287 local-timer-stop; 288 }; 289 290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 idle-state-name = "big-retention"; 293 /* CPU Retention (C2D), L2 Active */ 294 arm,psci-suspend-param = <0x00000002>; 295 entry-latency-us = <79>; 296 exit-latency-us = <82>; 297 min-residency-us = <1302>; 298 }; 299 300 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "big-power-collapse"; 303 /* CPU + L2 Power Collapse (C3, D4) */ 304 arm,psci-suspend-param = <0x40000003>; 305 entry-latency-us = <724>; 306 exit-latency-us = <2027>; 307 min-residency-us = <9419>; 308 local-timer-stop; 309 }; 310 }; 311 }; 312 313 firmware { 314 scm { 315 compatible = "qcom,scm-msm8998", "qcom,scm"; 316 }; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 }; 323 324 rpm: remoteproc { 325 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; 326 327 glink-edge { 328 compatible = "qcom,glink-rpm"; 329 330 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 331 qcom,rpm-msg-ram = <&rpm_msg_ram>; 332 mboxes = <&apcs_glb 0>; 333 334 rpm_requests: rpm-requests { 335 compatible = "qcom,rpm-msm8998"; 336 qcom,glink-channels = "rpm_requests"; 337 338 rpmcc: clock-controller { 339 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 340 clocks = <&xo>; 341 clock-names = "xo"; 342 #clock-cells = <1>; 343 }; 344 345 rpmpd: power-controller { 346 compatible = "qcom,msm8998-rpmpd"; 347 #power-domain-cells = <1>; 348 operating-points-v2 = <&rpmpd_opp_table>; 349 350 rpmpd_opp_table: opp-table { 351 compatible = "operating-points-v2"; 352 353 rpmpd_opp_ret: opp1 { 354 opp-level = <RPM_SMD_LEVEL_RETENTION>; 355 }; 356 357 rpmpd_opp_ret_plus: opp2 { 358 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 359 }; 360 361 rpmpd_opp_min_svs: opp3 { 362 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 363 }; 364 365 rpmpd_opp_low_svs: opp4 { 366 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 367 }; 368 369 rpmpd_opp_svs: opp5 { 370 opp-level = <RPM_SMD_LEVEL_SVS>; 371 }; 372 373 rpmpd_opp_svs_plus: opp6 { 374 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 375 }; 376 377 rpmpd_opp_nom: opp7 { 378 opp-level = <RPM_SMD_LEVEL_NOM>; 379 }; 380 381 rpmpd_opp_nom_plus: opp8 { 382 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 383 }; 384 385 rpmpd_opp_turbo: opp9 { 386 opp-level = <RPM_SMD_LEVEL_TURBO>; 387 }; 388 389 rpmpd_opp_turbo_plus: opp10 { 390 opp-level = <RPM_SMD_LEVEL_BINNING>; 391 }; 392 }; 393 }; 394 }; 395 }; 396 }; 397 398 smem { 399 compatible = "qcom,smem"; 400 memory-region = <&smem_mem>; 401 hwlocks = <&tcsr_mutex 3>; 402 }; 403 404 smp2p-lpass { 405 compatible = "qcom,smp2p"; 406 qcom,smem = <443>, <429>; 407 408 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 409 410 mboxes = <&apcs_glb 10>; 411 412 qcom,local-pid = <0>; 413 qcom,remote-pid = <2>; 414 415 adsp_smp2p_out: master-kernel { 416 qcom,entry-name = "master-kernel"; 417 #qcom,smem-state-cells = <1>; 418 }; 419 420 adsp_smp2p_in: slave-kernel { 421 qcom,entry-name = "slave-kernel"; 422 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 }; 426 }; 427 428 smp2p-mpss { 429 compatible = "qcom,smp2p"; 430 qcom,smem = <435>, <428>; 431 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 432 mboxes = <&apcs_glb 14>; 433 qcom,local-pid = <0>; 434 qcom,remote-pid = <1>; 435 436 modem_smp2p_out: master-kernel { 437 qcom,entry-name = "master-kernel"; 438 #qcom,smem-state-cells = <1>; 439 }; 440 441 modem_smp2p_in: slave-kernel { 442 qcom,entry-name = "slave-kernel"; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 }; 446 }; 447 448 smp2p-slpi { 449 compatible = "qcom,smp2p"; 450 qcom,smem = <481>, <430>; 451 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 452 mboxes = <&apcs_glb 26>; 453 qcom,local-pid = <0>; 454 qcom,remote-pid = <3>; 455 456 slpi_smp2p_out: master-kernel { 457 qcom,entry-name = "master-kernel"; 458 #qcom,smem-state-cells = <1>; 459 }; 460 461 slpi_smp2p_in: slave-kernel { 462 qcom,entry-name = "slave-kernel"; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 }; 466 }; 467 468 thermal-zones { 469 cpu0-thermal { 470 polling-delay-passive = <250>; 471 polling-delay = <1000>; 472 473 thermal-sensors = <&tsens0 1>; 474 475 trips { 476 cpu0_alert0: trip-point0 { 477 temperature = <75000>; 478 hysteresis = <2000>; 479 type = "passive"; 480 }; 481 482 cpu0_crit: cpu-crit { 483 temperature = <110000>; 484 hysteresis = <2000>; 485 type = "critical"; 486 }; 487 }; 488 }; 489 490 cpu1-thermal { 491 polling-delay-passive = <250>; 492 polling-delay = <1000>; 493 494 thermal-sensors = <&tsens0 2>; 495 496 trips { 497 cpu1_alert0: trip-point0 { 498 temperature = <75000>; 499 hysteresis = <2000>; 500 type = "passive"; 501 }; 502 503 cpu1_crit: cpu-crit { 504 temperature = <110000>; 505 hysteresis = <2000>; 506 type = "critical"; 507 }; 508 }; 509 }; 510 511 cpu2-thermal { 512 polling-delay-passive = <250>; 513 polling-delay = <1000>; 514 515 thermal-sensors = <&tsens0 3>; 516 517 trips { 518 cpu2_alert0: trip-point0 { 519 temperature = <75000>; 520 hysteresis = <2000>; 521 type = "passive"; 522 }; 523 524 cpu2_crit: cpu-crit { 525 temperature = <110000>; 526 hysteresis = <2000>; 527 type = "critical"; 528 }; 529 }; 530 }; 531 532 cpu3-thermal { 533 polling-delay-passive = <250>; 534 polling-delay = <1000>; 535 536 thermal-sensors = <&tsens0 4>; 537 538 trips { 539 cpu3_alert0: trip-point0 { 540 temperature = <75000>; 541 hysteresis = <2000>; 542 type = "passive"; 543 }; 544 545 cpu3_crit: cpu-crit { 546 temperature = <110000>; 547 hysteresis = <2000>; 548 type = "critical"; 549 }; 550 }; 551 }; 552 553 cpu4-thermal { 554 polling-delay-passive = <250>; 555 polling-delay = <1000>; 556 557 thermal-sensors = <&tsens0 7>; 558 559 trips { 560 cpu4_alert0: trip-point0 { 561 temperature = <75000>; 562 hysteresis = <2000>; 563 type = "passive"; 564 }; 565 566 cpu4_crit: cpu-crit { 567 temperature = <110000>; 568 hysteresis = <2000>; 569 type = "critical"; 570 }; 571 }; 572 }; 573 574 cpu5-thermal { 575 polling-delay-passive = <250>; 576 polling-delay = <1000>; 577 578 thermal-sensors = <&tsens0 8>; 579 580 trips { 581 cpu5_alert0: trip-point0 { 582 temperature = <75000>; 583 hysteresis = <2000>; 584 type = "passive"; 585 }; 586 587 cpu5_crit: cpu-crit { 588 temperature = <110000>; 589 hysteresis = <2000>; 590 type = "critical"; 591 }; 592 }; 593 }; 594 595 cpu6-thermal { 596 polling-delay-passive = <250>; 597 polling-delay = <1000>; 598 599 thermal-sensors = <&tsens0 9>; 600 601 trips { 602 cpu6_alert0: trip-point0 { 603 temperature = <75000>; 604 hysteresis = <2000>; 605 type = "passive"; 606 }; 607 608 cpu6_crit: cpu-crit { 609 temperature = <110000>; 610 hysteresis = <2000>; 611 type = "critical"; 612 }; 613 }; 614 }; 615 616 cpu7-thermal { 617 polling-delay-passive = <250>; 618 polling-delay = <1000>; 619 620 thermal-sensors = <&tsens0 10>; 621 622 trips { 623 cpu7_alert0: trip-point0 { 624 temperature = <75000>; 625 hysteresis = <2000>; 626 type = "passive"; 627 }; 628 629 cpu7_crit: cpu-crit { 630 temperature = <110000>; 631 hysteresis = <2000>; 632 type = "critical"; 633 }; 634 }; 635 }; 636 637 gpu-bottom-thermal { 638 polling-delay-passive = <250>; 639 polling-delay = <1000>; 640 641 thermal-sensors = <&tsens0 12>; 642 643 trips { 644 gpu1_alert0: trip-point0 { 645 temperature = <90000>; 646 hysteresis = <2000>; 647 type = "hot"; 648 }; 649 }; 650 }; 651 652 gpu-top-thermal { 653 polling-delay-passive = <250>; 654 polling-delay = <1000>; 655 656 thermal-sensors = <&tsens0 13>; 657 658 trips { 659 gpu2_alert0: trip-point0 { 660 temperature = <90000>; 661 hysteresis = <2000>; 662 type = "hot"; 663 }; 664 }; 665 }; 666 667 clust0-mhm-thermal { 668 polling-delay-passive = <250>; 669 polling-delay = <1000>; 670 671 thermal-sensors = <&tsens0 5>; 672 673 trips { 674 cluster0_mhm_alert0: trip-point0 { 675 temperature = <90000>; 676 hysteresis = <2000>; 677 type = "hot"; 678 }; 679 }; 680 }; 681 682 clust1-mhm-thermal { 683 polling-delay-passive = <250>; 684 polling-delay = <1000>; 685 686 thermal-sensors = <&tsens0 6>; 687 688 trips { 689 cluster1_mhm_alert0: trip-point0 { 690 temperature = <90000>; 691 hysteresis = <2000>; 692 type = "hot"; 693 }; 694 }; 695 }; 696 697 cluster1-l2-thermal { 698 polling-delay-passive = <250>; 699 polling-delay = <1000>; 700 701 thermal-sensors = <&tsens0 11>; 702 703 trips { 704 cluster1_l2_alert0: trip-point0 { 705 temperature = <90000>; 706 hysteresis = <2000>; 707 type = "hot"; 708 }; 709 }; 710 }; 711 712 modem-thermal { 713 polling-delay-passive = <250>; 714 polling-delay = <1000>; 715 716 thermal-sensors = <&tsens1 1>; 717 718 trips { 719 modem_alert0: trip-point0 { 720 temperature = <90000>; 721 hysteresis = <2000>; 722 type = "hot"; 723 }; 724 }; 725 }; 726 727 mem-thermal { 728 polling-delay-passive = <250>; 729 polling-delay = <1000>; 730 731 thermal-sensors = <&tsens1 2>; 732 733 trips { 734 mem_alert0: trip-point0 { 735 temperature = <90000>; 736 hysteresis = <2000>; 737 type = "hot"; 738 }; 739 }; 740 }; 741 742 wlan-thermal { 743 polling-delay-passive = <250>; 744 polling-delay = <1000>; 745 746 thermal-sensors = <&tsens1 3>; 747 748 trips { 749 wlan_alert0: trip-point0 { 750 temperature = <90000>; 751 hysteresis = <2000>; 752 type = "hot"; 753 }; 754 }; 755 }; 756 757 q6-dsp-thermal { 758 polling-delay-passive = <250>; 759 polling-delay = <1000>; 760 761 thermal-sensors = <&tsens1 4>; 762 763 trips { 764 q6_dsp_alert0: trip-point0 { 765 temperature = <90000>; 766 hysteresis = <2000>; 767 type = "hot"; 768 }; 769 }; 770 }; 771 772 camera-thermal { 773 polling-delay-passive = <250>; 774 polling-delay = <1000>; 775 776 thermal-sensors = <&tsens1 5>; 777 778 trips { 779 camera_alert0: trip-point0 { 780 temperature = <90000>; 781 hysteresis = <2000>; 782 type = "hot"; 783 }; 784 }; 785 }; 786 787 multimedia-thermal { 788 polling-delay-passive = <250>; 789 polling-delay = <1000>; 790 791 thermal-sensors = <&tsens1 6>; 792 793 trips { 794 multimedia_alert0: trip-point0 { 795 temperature = <90000>; 796 hysteresis = <2000>; 797 type = "hot"; 798 }; 799 }; 800 }; 801 }; 802 803 timer { 804 compatible = "arm,armv8-timer"; 805 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 806 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 807 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 808 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 809 }; 810 811 soc: soc@0 { 812 #address-cells = <1>; 813 #size-cells = <1>; 814 ranges = <0 0 0 0xffffffff>; 815 compatible = "simple-bus"; 816 817 gcc: clock-controller@100000 { 818 compatible = "qcom,gcc-msm8998"; 819 #clock-cells = <1>; 820 #reset-cells = <1>; 821 #power-domain-cells = <1>; 822 reg = <0x00100000 0xb0000>; 823 824 clock-names = "xo", "sleep_clk"; 825 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 826 827 /* 828 * The hypervisor typically configures the memory region where these clocks 829 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 830 * these clocks on a device with such configuration (e.g. because they are 831 * enabled but unused during boot-up), the device will most likely decide 832 * to reboot. 833 * In light of that, we are conservative here and we list all such clocks 834 * as protected. The board dts (or a user-supplied dts) can override the 835 * list of protected clocks if it differs from the norm, and it is in fact 836 * desired for the HLOS to manage these clocks 837 */ 838 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 839 <SSC_XO>, 840 <SSC_CNOC_AHBS_CLK>; 841 }; 842 843 rpm_msg_ram: sram@778000 { 844 compatible = "qcom,rpm-msg-ram"; 845 reg = <0x00778000 0x7000>; 846 }; 847 848 qfprom: qfprom@784000 { 849 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 850 reg = <0x00784000 0x621c>; 851 #address-cells = <1>; 852 #size-cells = <1>; 853 854 qusb2_hstx_trim: hstx-trim@23a { 855 reg = <0x23a 0x1>; 856 bits = <0 4>; 857 }; 858 }; 859 860 tsens0: thermal@10ab000 { 861 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 862 reg = <0x010ab000 0x1000>, /* TM */ 863 <0x010aa000 0x1000>; /* SROT */ 864 #qcom,sensors = <14>; 865 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-names = "uplow", "critical"; 868 #thermal-sensor-cells = <1>; 869 }; 870 871 tsens1: thermal@10ae000 { 872 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 873 reg = <0x010ae000 0x1000>, /* TM */ 874 <0x010ad000 0x1000>; /* SROT */ 875 #qcom,sensors = <8>; 876 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 878 interrupt-names = "uplow", "critical"; 879 #thermal-sensor-cells = <1>; 880 }; 881 882 anoc1_smmu: iommu@1680000 { 883 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 884 reg = <0x01680000 0x10000>; 885 #iommu-cells = <1>; 886 887 #global-interrupts = <0>; 888 interrupts = 889 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 890 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 891 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 892 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 893 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 894 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 895 }; 896 897 anoc2_smmu: iommu@16c0000 { 898 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 899 reg = <0x016c0000 0x40000>; 900 #iommu-cells = <1>; 901 902 #global-interrupts = <0>; 903 interrupts = 904 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 905 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 906 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 907 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 908 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 909 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 910 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 911 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 912 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 913 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 914 }; 915 916 pcie0: pci@1c00000 { 917 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 918 reg = <0x01c00000 0x2000>, 919 <0x1b000000 0xf1d>, 920 <0x1b000f20 0xa8>, 921 <0x1b100000 0x100000>; 922 reg-names = "parf", "dbi", "elbi", "config"; 923 device_type = "pci"; 924 linux,pci-domain = <0>; 925 bus-range = <0x00 0xff>; 926 #address-cells = <3>; 927 #size-cells = <2>; 928 num-lanes = <1>; 929 phys = <&pciephy>; 930 phy-names = "pciephy"; 931 status = "disabled"; 932 933 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 934 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 935 936 #interrupt-cells = <1>; 937 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 938 interrupt-names = "msi"; 939 interrupt-map-mask = <0 0 0 0x7>; 940 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 941 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 942 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 943 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 944 945 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 946 <&gcc GCC_PCIE_0_AUX_CLK>, 947 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 948 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 949 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 950 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 951 952 power-domains = <&gcc PCIE_0_GDSC>; 953 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 954 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 955 }; 956 957 pcie_phy: phy@1c06000 { 958 compatible = "qcom,msm8998-qmp-pcie-phy"; 959 reg = <0x01c06000 0x18c>; 960 #address-cells = <1>; 961 #size-cells = <1>; 962 status = "disabled"; 963 ranges; 964 965 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 966 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 967 <&gcc GCC_PCIE_CLKREF_CLK>; 968 clock-names = "aux", "cfg_ahb", "ref"; 969 970 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 971 reset-names = "phy", "common"; 972 973 vdda-phy-supply = <&vreg_l1a_0p875>; 974 vdda-pll-supply = <&vreg_l2a_1p2>; 975 976 pciephy: phy@1c06800 { 977 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 978 #phy-cells = <0>; 979 980 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 981 clock-names = "pipe0"; 982 clock-output-names = "pcie_0_pipe_clk_src"; 983 #clock-cells = <0>; 984 }; 985 }; 986 987 ufshc: ufshc@1da4000 { 988 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 989 reg = <0x01da4000 0x2500>; 990 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 991 phys = <&ufsphy_lanes>; 992 phy-names = "ufsphy"; 993 lanes-per-direction = <2>; 994 power-domains = <&gcc UFS_GDSC>; 995 status = "disabled"; 996 #reset-cells = <1>; 997 998 clock-names = 999 "core_clk", 1000 "bus_aggr_clk", 1001 "iface_clk", 1002 "core_clk_unipro", 1003 "ref_clk", 1004 "tx_lane0_sync_clk", 1005 "rx_lane0_sync_clk", 1006 "rx_lane1_sync_clk"; 1007 clocks = 1008 <&gcc GCC_UFS_AXI_CLK>, 1009 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1010 <&gcc GCC_UFS_AHB_CLK>, 1011 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1012 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1013 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1014 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1015 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1016 freq-table-hz = 1017 <50000000 200000000>, 1018 <0 0>, 1019 <0 0>, 1020 <37500000 150000000>, 1021 <0 0>, 1022 <0 0>, 1023 <0 0>, 1024 <0 0>; 1025 1026 resets = <&gcc GCC_UFS_BCR>; 1027 reset-names = "rst"; 1028 }; 1029 1030 ufsphy: phy@1da7000 { 1031 compatible = "qcom,msm8998-qmp-ufs-phy"; 1032 reg = <0x01da7000 0x18c>; 1033 #address-cells = <1>; 1034 #size-cells = <1>; 1035 status = "disabled"; 1036 ranges; 1037 1038 clock-names = 1039 "ref", 1040 "ref_aux"; 1041 clocks = 1042 <&gcc GCC_UFS_CLKREF_CLK>, 1043 <&gcc GCC_UFS_PHY_AUX_CLK>; 1044 1045 reset-names = "ufsphy"; 1046 resets = <&ufshc 0>; 1047 1048 ufsphy_lanes: phy@1da7400 { 1049 reg = <0x01da7400 0x128>, 1050 <0x01da7600 0x1fc>, 1051 <0x01da7c00 0x1dc>, 1052 <0x01da7800 0x128>, 1053 <0x01da7a00 0x1fc>; 1054 #phy-cells = <0>; 1055 }; 1056 }; 1057 1058 tcsr_mutex: hwlock@1f40000 { 1059 compatible = "qcom,tcsr-mutex"; 1060 reg = <0x01f40000 0x20000>; 1061 #hwlock-cells = <1>; 1062 }; 1063 1064 tcsr_regs_1: syscon@1f60000 { 1065 compatible = "qcom,msm8998-tcsr", "syscon"; 1066 reg = <0x01f60000 0x20000>; 1067 }; 1068 1069 tlmm: pinctrl@3400000 { 1070 compatible = "qcom,msm8998-pinctrl"; 1071 reg = <0x03400000 0xc00000>; 1072 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1073 gpio-ranges = <&tlmm 0 0 150>; 1074 gpio-controller; 1075 #gpio-cells = <2>; 1076 interrupt-controller; 1077 #interrupt-cells = <2>; 1078 1079 sdc2_on: sdc2-on-state { 1080 clk-pins { 1081 pins = "sdc2_clk"; 1082 drive-strength = <16>; 1083 bias-disable; 1084 }; 1085 1086 cmd-pins { 1087 pins = "sdc2_cmd"; 1088 drive-strength = <10>; 1089 bias-pull-up; 1090 }; 1091 1092 data-pins { 1093 pins = "sdc2_data"; 1094 drive-strength = <10>; 1095 bias-pull-up; 1096 }; 1097 }; 1098 1099 sdc2_off: sdc2-off-state { 1100 clk-pins { 1101 pins = "sdc2_clk"; 1102 drive-strength = <2>; 1103 bias-disable; 1104 }; 1105 1106 cmd-pins { 1107 pins = "sdc2_cmd"; 1108 drive-strength = <2>; 1109 bias-pull-up; 1110 }; 1111 1112 data-pins { 1113 pins = "sdc2_data"; 1114 drive-strength = <2>; 1115 bias-pull-up; 1116 }; 1117 }; 1118 1119 sdc2_cd: sdc2-cd-state { 1120 pins = "gpio95"; 1121 function = "gpio"; 1122 bias-pull-up; 1123 drive-strength = <2>; 1124 }; 1125 1126 blsp1_uart3_on: blsp1-uart3-on-state { 1127 tx-pins { 1128 pins = "gpio45"; 1129 function = "blsp_uart3_a"; 1130 drive-strength = <2>; 1131 bias-disable; 1132 }; 1133 1134 rx-pins { 1135 pins = "gpio46"; 1136 function = "blsp_uart3_a"; 1137 drive-strength = <2>; 1138 bias-disable; 1139 }; 1140 1141 cts-pins { 1142 pins = "gpio47"; 1143 function = "blsp_uart3_a"; 1144 drive-strength = <2>; 1145 bias-disable; 1146 }; 1147 1148 rfr-pins { 1149 pins = "gpio48"; 1150 function = "blsp_uart3_a"; 1151 drive-strength = <2>; 1152 bias-disable; 1153 }; 1154 }; 1155 1156 blsp1_i2c1_default: blsp1-i2c1-default-state { 1157 pins = "gpio2", "gpio3"; 1158 function = "blsp_i2c1"; 1159 drive-strength = <2>; 1160 bias-disable; 1161 }; 1162 1163 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1164 pins = "gpio2", "gpio3"; 1165 function = "blsp_i2c1"; 1166 drive-strength = <2>; 1167 bias-pull-up; 1168 }; 1169 1170 blsp1_i2c2_default: blsp1-i2c2-default-state { 1171 pins = "gpio32", "gpio33"; 1172 function = "blsp_i2c2"; 1173 drive-strength = <2>; 1174 bias-disable; 1175 }; 1176 1177 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1178 pins = "gpio32", "gpio33"; 1179 function = "blsp_i2c2"; 1180 drive-strength = <2>; 1181 bias-pull-up; 1182 }; 1183 1184 blsp1_i2c3_default: blsp1-i2c3-default-state { 1185 pins = "gpio47", "gpio48"; 1186 function = "blsp_i2c3"; 1187 drive-strength = <2>; 1188 bias-disable; 1189 }; 1190 1191 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1192 pins = "gpio47", "gpio48"; 1193 function = "blsp_i2c3"; 1194 drive-strength = <2>; 1195 bias-pull-up; 1196 }; 1197 1198 blsp1_i2c4_default: blsp1-i2c4-default-state { 1199 pins = "gpio10", "gpio11"; 1200 function = "blsp_i2c4"; 1201 drive-strength = <2>; 1202 bias-disable; 1203 }; 1204 1205 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1206 pins = "gpio10", "gpio11"; 1207 function = "blsp_i2c4"; 1208 drive-strength = <2>; 1209 bias-pull-up; 1210 }; 1211 1212 blsp1_i2c5_default: blsp1-i2c5-default-state { 1213 pins = "gpio87", "gpio88"; 1214 function = "blsp_i2c5"; 1215 drive-strength = <2>; 1216 bias-disable; 1217 }; 1218 1219 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1220 pins = "gpio87", "gpio88"; 1221 function = "blsp_i2c5"; 1222 drive-strength = <2>; 1223 bias-pull-up; 1224 }; 1225 1226 blsp1_i2c6_default: blsp1-i2c6-default-state { 1227 pins = "gpio43", "gpio44"; 1228 function = "blsp_i2c6"; 1229 drive-strength = <2>; 1230 bias-disable; 1231 }; 1232 1233 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1234 pins = "gpio43", "gpio44"; 1235 function = "blsp_i2c6"; 1236 drive-strength = <2>; 1237 bias-pull-up; 1238 }; 1239 1240 blsp1_spi_b_default: blsp1-spi-b-default-state { 1241 pins = "gpio23", "gpio28"; 1242 function = "blsp1_spi_b"; 1243 drive-strength = <6>; 1244 bias-disable; 1245 }; 1246 1247 blsp1_spi1_default: blsp1-spi1-default-state { 1248 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1249 function = "blsp_spi1"; 1250 drive-strength = <6>; 1251 bias-disable; 1252 }; 1253 1254 blsp1_spi2_default: blsp1-spi2-default-state { 1255 pins = "gpio31", "gpio34", "gpio32", "gpio33"; 1256 function = "blsp_spi2"; 1257 drive-strength = <6>; 1258 bias-disable; 1259 }; 1260 1261 blsp1_spi3_default: blsp1-spi3-default-state { 1262 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 1263 function = "blsp_spi2"; 1264 drive-strength = <6>; 1265 bias-disable; 1266 }; 1267 1268 blsp1_spi4_default: blsp1-spi4-default-state { 1269 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1270 function = "blsp_spi4"; 1271 drive-strength = <6>; 1272 bias-disable; 1273 }; 1274 1275 blsp1_spi5_default: blsp1-spi5-default-state { 1276 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1277 function = "blsp_spi5"; 1278 drive-strength = <6>; 1279 bias-disable; 1280 }; 1281 1282 blsp1_spi6_default: blsp1-spi6-default-state { 1283 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1284 function = "blsp_spi6"; 1285 drive-strength = <6>; 1286 bias-disable; 1287 }; 1288 1289 1290 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1291 blsp2_i2c1_default: blsp2-i2c1-default-state { 1292 pins = "gpio55", "gpio56"; 1293 function = "blsp_i2c7"; 1294 drive-strength = <2>; 1295 bias-disable; 1296 }; 1297 1298 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1299 pins = "gpio55", "gpio56"; 1300 function = "blsp_i2c7"; 1301 drive-strength = <2>; 1302 bias-pull-up; 1303 }; 1304 1305 blsp2_i2c2_default: blsp2-i2c2-default-state { 1306 pins = "gpio6", "gpio7"; 1307 function = "blsp_i2c8"; 1308 drive-strength = <2>; 1309 bias-disable; 1310 }; 1311 1312 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1313 pins = "gpio6", "gpio7"; 1314 function = "blsp_i2c8"; 1315 drive-strength = <2>; 1316 bias-pull-up; 1317 }; 1318 1319 blsp2_i2c3_default: blsp2-i2c3-default-state { 1320 pins = "gpio51", "gpio52"; 1321 function = "blsp_i2c9"; 1322 drive-strength = <2>; 1323 bias-disable; 1324 }; 1325 1326 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1327 pins = "gpio51", "gpio52"; 1328 function = "blsp_i2c9"; 1329 drive-strength = <2>; 1330 bias-pull-up; 1331 }; 1332 1333 blsp2_i2c4_default: blsp2-i2c4-default-state { 1334 pins = "gpio67", "gpio68"; 1335 function = "blsp_i2c10"; 1336 drive-strength = <2>; 1337 bias-disable; 1338 }; 1339 1340 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1341 pins = "gpio67", "gpio68"; 1342 function = "blsp_i2c10"; 1343 drive-strength = <2>; 1344 bias-pull-up; 1345 }; 1346 1347 blsp2_i2c5_default: blsp2-i2c5-default-state { 1348 pins = "gpio60", "gpio61"; 1349 function = "blsp_i2c11"; 1350 drive-strength = <2>; 1351 bias-disable; 1352 }; 1353 1354 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1355 pins = "gpio60", "gpio61"; 1356 function = "blsp_i2c11"; 1357 drive-strength = <2>; 1358 bias-pull-up; 1359 }; 1360 1361 blsp2_i2c6_default: blsp2-i2c6-default-state { 1362 pins = "gpio83", "gpio84"; 1363 function = "blsp_i2c12"; 1364 drive-strength = <2>; 1365 bias-disable; 1366 }; 1367 1368 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1369 pins = "gpio83", "gpio84"; 1370 function = "blsp_i2c12"; 1371 drive-strength = <2>; 1372 bias-pull-up; 1373 }; 1374 1375 blsp2_spi1_default: blsp2-spi1-default-state { 1376 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1377 function = "blsp_spi7"; 1378 drive-strength = <6>; 1379 bias-disable; 1380 }; 1381 1382 blsp2_spi2_default: blsp2-spi2-default-state { 1383 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1384 function = "blsp_spi8"; 1385 drive-strength = <6>; 1386 bias-disable; 1387 }; 1388 1389 blsp2_spi3_default: blsp2-spi3-default-state { 1390 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1391 function = "blsp_spi9"; 1392 drive-strength = <6>; 1393 bias-disable; 1394 }; 1395 1396 blsp2_spi4_default: blsp2-spi4-default-state { 1397 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 1398 function = "blsp_spi10"; 1399 drive-strength = <6>; 1400 bias-disable; 1401 }; 1402 1403 blsp2_spi5_default: blsp2-spi5-default-state { 1404 pins = "gpio58", "gpio59", "gpio60", "gpio61"; 1405 function = "blsp_spi11"; 1406 drive-strength = <6>; 1407 bias-disable; 1408 }; 1409 1410 blsp2_spi6_default: blsp2-spi6-default-state { 1411 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 1412 function = "blsp_spi12"; 1413 drive-strength = <6>; 1414 bias-disable; 1415 }; 1416 }; 1417 1418 remoteproc_mss: remoteproc@4080000 { 1419 compatible = "qcom,msm8998-mss-pil"; 1420 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1421 reg-names = "qdsp6", "rmb"; 1422 1423 interrupts-extended = 1424 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1425 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1426 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1427 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1428 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1429 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1430 interrupt-names = "wdog", "fatal", "ready", 1431 "handover", "stop-ack", 1432 "shutdown-ack"; 1433 1434 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1435 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1436 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1437 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1438 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1439 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1440 <&rpmcc RPM_SMD_QDSS_CLK>, 1441 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1442 clock-names = "iface", "bus", "mem", "gpll0_mss", 1443 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1444 1445 qcom,smem-states = <&modem_smp2p_out 0>; 1446 qcom,smem-state-names = "stop"; 1447 1448 resets = <&gcc GCC_MSS_RESTART>; 1449 reset-names = "mss_restart"; 1450 1451 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1452 1453 power-domains = <&rpmpd MSM8998_VDDCX>, 1454 <&rpmpd MSM8998_VDDMX>; 1455 power-domain-names = "cx", "mx"; 1456 1457 status = "disabled"; 1458 1459 mba { 1460 memory-region = <&mba_mem>; 1461 }; 1462 1463 mpss { 1464 memory-region = <&mpss_mem>; 1465 }; 1466 1467 metadata { 1468 memory-region = <&mdata_mem>; 1469 }; 1470 1471 glink-edge { 1472 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1473 label = "modem"; 1474 qcom,remote-pid = <1>; 1475 mboxes = <&apcs_glb 15>; 1476 }; 1477 }; 1478 1479 adreno_gpu: gpu@5000000 { 1480 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1481 reg = <0x05000000 0x40000>; 1482 reg-names = "kgsl_3d0_reg_memory"; 1483 1484 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1485 <&gpucc RBBMTIMER_CLK>, 1486 <&gcc GCC_BIMC_GFX_CLK>, 1487 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1488 <&gpucc RBCPR_CLK>, 1489 <&gpucc GFX3D_CLK>; 1490 clock-names = "iface", 1491 "rbbmtimer", 1492 "mem", 1493 "mem_iface", 1494 "rbcpr", 1495 "core"; 1496 1497 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1498 iommus = <&adreno_smmu 0>; 1499 operating-points-v2 = <&gpu_opp_table>; 1500 power-domains = <&rpmpd MSM8998_VDDMX>; 1501 status = "disabled"; 1502 1503 gpu_opp_table: opp-table { 1504 compatible = "operating-points-v2"; 1505 opp-710000097 { 1506 opp-hz = /bits/ 64 <710000097>; 1507 opp-level = <RPM_SMD_LEVEL_TURBO>; 1508 opp-supported-hw = <0xff>; 1509 }; 1510 1511 opp-670000048 { 1512 opp-hz = /bits/ 64 <670000048>; 1513 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1514 opp-supported-hw = <0xff>; 1515 }; 1516 1517 opp-596000097 { 1518 opp-hz = /bits/ 64 <596000097>; 1519 opp-level = <RPM_SMD_LEVEL_NOM>; 1520 opp-supported-hw = <0xff>; 1521 }; 1522 1523 opp-515000097 { 1524 opp-hz = /bits/ 64 <515000097>; 1525 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1526 opp-supported-hw = <0xff>; 1527 }; 1528 1529 opp-414000000 { 1530 opp-hz = /bits/ 64 <414000000>; 1531 opp-level = <RPM_SMD_LEVEL_SVS>; 1532 opp-supported-hw = <0xff>; 1533 }; 1534 1535 opp-342000000 { 1536 opp-hz = /bits/ 64 <342000000>; 1537 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1538 opp-supported-hw = <0xff>; 1539 }; 1540 1541 opp-257000000 { 1542 opp-hz = /bits/ 64 <257000000>; 1543 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1544 opp-supported-hw = <0xff>; 1545 }; 1546 }; 1547 }; 1548 1549 adreno_smmu: iommu@5040000 { 1550 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1551 reg = <0x05040000 0x10000>; 1552 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1553 <&gcc GCC_BIMC_GFX_CLK>, 1554 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1555 clock-names = "iface", "mem", "mem_iface"; 1556 1557 #global-interrupts = <0>; 1558 #iommu-cells = <1>; 1559 interrupts = 1560 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1563 /* 1564 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1565 * GPU-CX for SMMU but we need both of them up for Adreno. 1566 * Contemporarily, we also need to manage the VDDMX rpmpd 1567 * domain in the Adreno driver. 1568 * Enable GPU CX/GX GDSCs here so that we can manage the 1569 * SoC VDDMX RPM Power Domain in the Adreno driver. 1570 */ 1571 power-domains = <&gpucc GPU_GX_GDSC>; 1572 status = "disabled"; 1573 }; 1574 1575 gpucc: clock-controller@5065000 { 1576 compatible = "qcom,msm8998-gpucc"; 1577 #clock-cells = <1>; 1578 #reset-cells = <1>; 1579 #power-domain-cells = <1>; 1580 reg = <0x05065000 0x9000>; 1581 1582 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1583 <&gcc GCC_GPU_GPLL0_CLK>; 1584 clock-names = "xo", 1585 "gpll0"; 1586 }; 1587 1588 remoteproc_slpi: remoteproc@5800000 { 1589 compatible = "qcom,msm8998-slpi-pas"; 1590 reg = <0x05800000 0x4040>; 1591 1592 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1593 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1594 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1595 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1596 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1597 interrupt-names = "wdog", "fatal", "ready", 1598 "handover", "stop-ack"; 1599 1600 px-supply = <&vreg_lvs2a_1p8>; 1601 1602 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1603 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1604 clock-names = "xo", "aggre2"; 1605 1606 memory-region = <&slpi_mem>; 1607 1608 qcom,smem-states = <&slpi_smp2p_out 0>; 1609 qcom,smem-state-names = "stop"; 1610 1611 power-domains = <&rpmpd MSM8998_SSCCX>; 1612 power-domain-names = "ssc_cx"; 1613 1614 status = "disabled"; 1615 1616 glink-edge { 1617 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1618 label = "dsps"; 1619 qcom,remote-pid = <3>; 1620 mboxes = <&apcs_glb 27>; 1621 }; 1622 }; 1623 1624 stm: stm@6002000 { 1625 compatible = "arm,coresight-stm", "arm,primecell"; 1626 reg = <0x06002000 0x1000>, 1627 <0x16280000 0x180000>; 1628 reg-names = "stm-base", "stm-stimulus-base"; 1629 status = "disabled"; 1630 1631 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1632 clock-names = "apb_pclk", "atclk"; 1633 1634 out-ports { 1635 port { 1636 stm_out: endpoint { 1637 remote-endpoint = <&funnel0_in7>; 1638 }; 1639 }; 1640 }; 1641 }; 1642 1643 funnel1: funnel@6041000 { 1644 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1645 reg = <0x06041000 0x1000>; 1646 status = "disabled"; 1647 1648 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1649 clock-names = "apb_pclk", "atclk"; 1650 1651 out-ports { 1652 port { 1653 funnel0_out: endpoint { 1654 remote-endpoint = 1655 <&merge_funnel_in0>; 1656 }; 1657 }; 1658 }; 1659 1660 in-ports { 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 1664 port@7 { 1665 reg = <7>; 1666 funnel0_in7: endpoint { 1667 remote-endpoint = <&stm_out>; 1668 }; 1669 }; 1670 }; 1671 }; 1672 1673 funnel2: funnel@6042000 { 1674 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1675 reg = <0x06042000 0x1000>; 1676 status = "disabled"; 1677 1678 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1679 clock-names = "apb_pclk", "atclk"; 1680 1681 out-ports { 1682 port { 1683 funnel1_out: endpoint { 1684 remote-endpoint = 1685 <&merge_funnel_in1>; 1686 }; 1687 }; 1688 }; 1689 1690 in-ports { 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 1694 port@6 { 1695 reg = <6>; 1696 funnel1_in6: endpoint { 1697 remote-endpoint = 1698 <&apss_merge_funnel_out>; 1699 }; 1700 }; 1701 }; 1702 }; 1703 1704 funnel3: funnel@6045000 { 1705 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1706 reg = <0x06045000 0x1000>; 1707 status = "disabled"; 1708 1709 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1710 clock-names = "apb_pclk", "atclk"; 1711 1712 out-ports { 1713 port { 1714 merge_funnel_out: endpoint { 1715 remote-endpoint = 1716 <&etf_in>; 1717 }; 1718 }; 1719 }; 1720 1721 in-ports { 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 1725 port@0 { 1726 reg = <0>; 1727 merge_funnel_in0: endpoint { 1728 remote-endpoint = 1729 <&funnel0_out>; 1730 }; 1731 }; 1732 1733 port@1 { 1734 reg = <1>; 1735 merge_funnel_in1: endpoint { 1736 remote-endpoint = 1737 <&funnel1_out>; 1738 }; 1739 }; 1740 }; 1741 }; 1742 1743 replicator1: replicator@6046000 { 1744 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1745 reg = <0x06046000 0x1000>; 1746 status = "disabled"; 1747 1748 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1749 clock-names = "apb_pclk", "atclk"; 1750 1751 out-ports { 1752 port { 1753 replicator_out: endpoint { 1754 remote-endpoint = <&etr_in>; 1755 }; 1756 }; 1757 }; 1758 1759 in-ports { 1760 port { 1761 replicator_in: endpoint { 1762 remote-endpoint = <&etf_out>; 1763 }; 1764 }; 1765 }; 1766 }; 1767 1768 etf: etf@6047000 { 1769 compatible = "arm,coresight-tmc", "arm,primecell"; 1770 reg = <0x06047000 0x1000>; 1771 status = "disabled"; 1772 1773 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1774 clock-names = "apb_pclk", "atclk"; 1775 1776 out-ports { 1777 port { 1778 etf_out: endpoint { 1779 remote-endpoint = 1780 <&replicator_in>; 1781 }; 1782 }; 1783 }; 1784 1785 in-ports { 1786 port { 1787 etf_in: endpoint { 1788 remote-endpoint = 1789 <&merge_funnel_out>; 1790 }; 1791 }; 1792 }; 1793 }; 1794 1795 etr: etr@6048000 { 1796 compatible = "arm,coresight-tmc", "arm,primecell"; 1797 reg = <0x06048000 0x1000>; 1798 status = "disabled"; 1799 1800 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1801 clock-names = "apb_pclk", "atclk"; 1802 arm,scatter-gather; 1803 1804 in-ports { 1805 port { 1806 etr_in: endpoint { 1807 remote-endpoint = 1808 <&replicator_out>; 1809 }; 1810 }; 1811 }; 1812 }; 1813 1814 etm1: etm@7840000 { 1815 compatible = "arm,coresight-etm4x", "arm,primecell"; 1816 reg = <0x07840000 0x1000>; 1817 status = "disabled"; 1818 1819 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1820 clock-names = "apb_pclk", "atclk"; 1821 1822 cpu = <&CPU0>; 1823 1824 out-ports { 1825 port { 1826 etm0_out: endpoint { 1827 remote-endpoint = 1828 <&apss_funnel_in0>; 1829 }; 1830 }; 1831 }; 1832 }; 1833 1834 etm2: etm@7940000 { 1835 compatible = "arm,coresight-etm4x", "arm,primecell"; 1836 reg = <0x07940000 0x1000>; 1837 status = "disabled"; 1838 1839 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1840 clock-names = "apb_pclk", "atclk"; 1841 1842 cpu = <&CPU1>; 1843 1844 out-ports { 1845 port { 1846 etm1_out: endpoint { 1847 remote-endpoint = 1848 <&apss_funnel_in1>; 1849 }; 1850 }; 1851 }; 1852 }; 1853 1854 etm3: etm@7a40000 { 1855 compatible = "arm,coresight-etm4x", "arm,primecell"; 1856 reg = <0x07a40000 0x1000>; 1857 status = "disabled"; 1858 1859 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1860 clock-names = "apb_pclk", "atclk"; 1861 1862 cpu = <&CPU2>; 1863 1864 out-ports { 1865 port { 1866 etm2_out: endpoint { 1867 remote-endpoint = 1868 <&apss_funnel_in2>; 1869 }; 1870 }; 1871 }; 1872 }; 1873 1874 etm4: etm@7b40000 { 1875 compatible = "arm,coresight-etm4x", "arm,primecell"; 1876 reg = <0x07b40000 0x1000>; 1877 status = "disabled"; 1878 1879 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1880 clock-names = "apb_pclk", "atclk"; 1881 1882 cpu = <&CPU3>; 1883 1884 out-ports { 1885 port { 1886 etm3_out: endpoint { 1887 remote-endpoint = 1888 <&apss_funnel_in3>; 1889 }; 1890 }; 1891 }; 1892 }; 1893 1894 funnel4: funnel@7b60000 { /* APSS Funnel */ 1895 compatible = "arm,coresight-etm4x", "arm,primecell"; 1896 reg = <0x07b60000 0x1000>; 1897 status = "disabled"; 1898 1899 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1900 clock-names = "apb_pclk", "atclk"; 1901 1902 out-ports { 1903 port { 1904 apss_funnel_out: endpoint { 1905 remote-endpoint = 1906 <&apss_merge_funnel_in>; 1907 }; 1908 }; 1909 }; 1910 1911 in-ports { 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 1915 port@0 { 1916 reg = <0>; 1917 apss_funnel_in0: endpoint { 1918 remote-endpoint = 1919 <&etm0_out>; 1920 }; 1921 }; 1922 1923 port@1 { 1924 reg = <1>; 1925 apss_funnel_in1: endpoint { 1926 remote-endpoint = 1927 <&etm1_out>; 1928 }; 1929 }; 1930 1931 port@2 { 1932 reg = <2>; 1933 apss_funnel_in2: endpoint { 1934 remote-endpoint = 1935 <&etm2_out>; 1936 }; 1937 }; 1938 1939 port@3 { 1940 reg = <3>; 1941 apss_funnel_in3: endpoint { 1942 remote-endpoint = 1943 <&etm3_out>; 1944 }; 1945 }; 1946 1947 port@4 { 1948 reg = <4>; 1949 apss_funnel_in4: endpoint { 1950 remote-endpoint = 1951 <&etm4_out>; 1952 }; 1953 }; 1954 1955 port@5 { 1956 reg = <5>; 1957 apss_funnel_in5: endpoint { 1958 remote-endpoint = 1959 <&etm5_out>; 1960 }; 1961 }; 1962 1963 port@6 { 1964 reg = <6>; 1965 apss_funnel_in6: endpoint { 1966 remote-endpoint = 1967 <&etm6_out>; 1968 }; 1969 }; 1970 1971 port@7 { 1972 reg = <7>; 1973 apss_funnel_in7: endpoint { 1974 remote-endpoint = 1975 <&etm7_out>; 1976 }; 1977 }; 1978 }; 1979 }; 1980 1981 funnel5: funnel@7b70000 { 1982 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1983 reg = <0x07b70000 0x1000>; 1984 status = "disabled"; 1985 1986 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1987 clock-names = "apb_pclk", "atclk"; 1988 1989 out-ports { 1990 port { 1991 apss_merge_funnel_out: endpoint { 1992 remote-endpoint = 1993 <&funnel1_in6>; 1994 }; 1995 }; 1996 }; 1997 1998 in-ports { 1999 port { 2000 apss_merge_funnel_in: endpoint { 2001 remote-endpoint = 2002 <&apss_funnel_out>; 2003 }; 2004 }; 2005 }; 2006 }; 2007 2008 etm5: etm@7c40000 { 2009 compatible = "arm,coresight-etm4x", "arm,primecell"; 2010 reg = <0x07c40000 0x1000>; 2011 status = "disabled"; 2012 2013 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2014 clock-names = "apb_pclk", "atclk"; 2015 2016 cpu = <&CPU4>; 2017 2018 port { 2019 etm4_out: endpoint { 2020 remote-endpoint = <&apss_funnel_in4>; 2021 }; 2022 }; 2023 }; 2024 2025 etm6: etm@7d40000 { 2026 compatible = "arm,coresight-etm4x", "arm,primecell"; 2027 reg = <0x07d40000 0x1000>; 2028 status = "disabled"; 2029 2030 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2031 clock-names = "apb_pclk", "atclk"; 2032 2033 cpu = <&CPU5>; 2034 2035 port { 2036 etm5_out: endpoint { 2037 remote-endpoint = <&apss_funnel_in5>; 2038 }; 2039 }; 2040 }; 2041 2042 etm7: etm@7e40000 { 2043 compatible = "arm,coresight-etm4x", "arm,primecell"; 2044 reg = <0x07e40000 0x1000>; 2045 status = "disabled"; 2046 2047 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2048 clock-names = "apb_pclk", "atclk"; 2049 2050 cpu = <&CPU6>; 2051 2052 port { 2053 etm6_out: endpoint { 2054 remote-endpoint = <&apss_funnel_in6>; 2055 }; 2056 }; 2057 }; 2058 2059 etm8: etm@7f40000 { 2060 compatible = "arm,coresight-etm4x", "arm,primecell"; 2061 reg = <0x07f40000 0x1000>; 2062 status = "disabled"; 2063 2064 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2065 clock-names = "apb_pclk", "atclk"; 2066 2067 cpu = <&CPU7>; 2068 2069 port { 2070 etm7_out: endpoint { 2071 remote-endpoint = <&apss_funnel_in7>; 2072 }; 2073 }; 2074 }; 2075 2076 sram@290000 { 2077 compatible = "qcom,rpm-stats"; 2078 reg = <0x00290000 0x10000>; 2079 }; 2080 2081 spmi_bus: spmi@800f000 { 2082 compatible = "qcom,spmi-pmic-arb"; 2083 reg = <0x0800f000 0x1000>, 2084 <0x08400000 0x1000000>, 2085 <0x09400000 0x1000000>, 2086 <0x0a400000 0x220000>, 2087 <0x0800a000 0x3000>; 2088 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2089 interrupt-names = "periph_irq"; 2090 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2091 qcom,ee = <0>; 2092 qcom,channel = <0>; 2093 #address-cells = <2>; 2094 #size-cells = <0>; 2095 interrupt-controller; 2096 #interrupt-cells = <4>; 2097 }; 2098 2099 usb3: usb@a8f8800 { 2100 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2101 reg = <0x0a8f8800 0x400>; 2102 status = "disabled"; 2103 #address-cells = <1>; 2104 #size-cells = <1>; 2105 ranges; 2106 2107 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2108 <&gcc GCC_USB30_MASTER_CLK>, 2109 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2110 <&gcc GCC_USB30_SLEEP_CLK>, 2111 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2112 clock-names = "cfg_noc", 2113 "core", 2114 "iface", 2115 "sleep", 2116 "mock_utmi"; 2117 2118 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2119 <&gcc GCC_USB30_MASTER_CLK>; 2120 assigned-clock-rates = <19200000>, <120000000>; 2121 2122 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2124 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2125 2126 power-domains = <&gcc USB_30_GDSC>; 2127 2128 resets = <&gcc GCC_USB_30_BCR>; 2129 2130 usb3_dwc3: usb@a800000 { 2131 compatible = "snps,dwc3"; 2132 reg = <0x0a800000 0xcd00>; 2133 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2134 snps,dis_u2_susphy_quirk; 2135 snps,dis_enblslpm_quirk; 2136 phys = <&qusb2phy>, <&usb1_ssphy>; 2137 phy-names = "usb2-phy", "usb3-phy"; 2138 snps,has-lpm-erratum; 2139 snps,hird-threshold = /bits/ 8 <0x10>; 2140 }; 2141 }; 2142 2143 usb3phy: phy@c010000 { 2144 compatible = "qcom,msm8998-qmp-usb3-phy"; 2145 reg = <0x0c010000 0x18c>; 2146 status = "disabled"; 2147 #address-cells = <1>; 2148 #size-cells = <1>; 2149 ranges; 2150 2151 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2152 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2153 <&gcc GCC_USB3_CLKREF_CLK>; 2154 clock-names = "aux", "cfg_ahb", "ref"; 2155 2156 resets = <&gcc GCC_USB3_PHY_BCR>, 2157 <&gcc GCC_USB3PHY_PHY_BCR>; 2158 reset-names = "phy", "common"; 2159 2160 usb1_ssphy: phy@c010200 { 2161 reg = <0xc010200 0x128>, 2162 <0xc010400 0x200>, 2163 <0xc010c00 0x20c>, 2164 <0xc010600 0x128>, 2165 <0xc010800 0x200>; 2166 #phy-cells = <0>; 2167 #clock-cells = <0>; 2168 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2169 clock-names = "pipe0"; 2170 clock-output-names = "usb3_phy_pipe_clk_src"; 2171 }; 2172 }; 2173 2174 qusb2phy: phy@c012000 { 2175 compatible = "qcom,msm8998-qusb2-phy"; 2176 reg = <0x0c012000 0x2a8>; 2177 status = "disabled"; 2178 #phy-cells = <0>; 2179 2180 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2181 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2182 clock-names = "cfg_ahb", "ref"; 2183 2184 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2185 2186 nvmem-cells = <&qusb2_hstx_trim>; 2187 }; 2188 2189 sdhc2: mmc@c0a4900 { 2190 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2191 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2192 reg-names = "hc", "core"; 2193 2194 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2196 interrupt-names = "hc_irq", "pwr_irq"; 2197 2198 clock-names = "iface", "core", "xo"; 2199 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2200 <&gcc GCC_SDCC2_APPS_CLK>, 2201 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2202 bus-width = <4>; 2203 status = "disabled"; 2204 }; 2205 2206 blsp1_dma: dma-controller@c144000 { 2207 compatible = "qcom,bam-v1.7.0"; 2208 reg = <0x0c144000 0x25000>; 2209 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2210 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2211 clock-names = "bam_clk"; 2212 #dma-cells = <1>; 2213 qcom,ee = <0>; 2214 qcom,controlled-remotely; 2215 num-channels = <18>; 2216 qcom,num-ees = <4>; 2217 }; 2218 2219 blsp1_uart3: serial@c171000 { 2220 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2221 reg = <0x0c171000 0x1000>; 2222 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2223 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2224 <&gcc GCC_BLSP1_AHB_CLK>; 2225 clock-names = "core", "iface"; 2226 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2227 dma-names = "tx", "rx"; 2228 pinctrl-names = "default"; 2229 pinctrl-0 = <&blsp1_uart3_on>; 2230 status = "disabled"; 2231 }; 2232 2233 blsp1_i2c1: i2c@c175000 { 2234 compatible = "qcom,i2c-qup-v2.2.1"; 2235 reg = <0x0c175000 0x600>; 2236 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2237 2238 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2239 <&gcc GCC_BLSP1_AHB_CLK>; 2240 clock-names = "core", "iface"; 2241 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2242 dma-names = "tx", "rx"; 2243 pinctrl-names = "default", "sleep"; 2244 pinctrl-0 = <&blsp1_i2c1_default>; 2245 pinctrl-1 = <&blsp1_i2c1_sleep>; 2246 clock-frequency = <400000>; 2247 2248 status = "disabled"; 2249 #address-cells = <1>; 2250 #size-cells = <0>; 2251 }; 2252 2253 blsp1_i2c2: i2c@c176000 { 2254 compatible = "qcom,i2c-qup-v2.2.1"; 2255 reg = <0x0c176000 0x600>; 2256 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2257 2258 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2259 <&gcc GCC_BLSP1_AHB_CLK>; 2260 clock-names = "core", "iface"; 2261 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2262 dma-names = "tx", "rx"; 2263 pinctrl-names = "default", "sleep"; 2264 pinctrl-0 = <&blsp1_i2c2_default>; 2265 pinctrl-1 = <&blsp1_i2c2_sleep>; 2266 clock-frequency = <400000>; 2267 2268 status = "disabled"; 2269 #address-cells = <1>; 2270 #size-cells = <0>; 2271 }; 2272 2273 blsp1_i2c3: i2c@c177000 { 2274 compatible = "qcom,i2c-qup-v2.2.1"; 2275 reg = <0x0c177000 0x600>; 2276 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2277 2278 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2279 <&gcc GCC_BLSP1_AHB_CLK>; 2280 clock-names = "core", "iface"; 2281 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2282 dma-names = "tx", "rx"; 2283 pinctrl-names = "default", "sleep"; 2284 pinctrl-0 = <&blsp1_i2c3_default>; 2285 pinctrl-1 = <&blsp1_i2c3_sleep>; 2286 clock-frequency = <400000>; 2287 2288 status = "disabled"; 2289 #address-cells = <1>; 2290 #size-cells = <0>; 2291 }; 2292 2293 blsp1_i2c4: i2c@c178000 { 2294 compatible = "qcom,i2c-qup-v2.2.1"; 2295 reg = <0x0c178000 0x600>; 2296 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2297 2298 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2299 <&gcc GCC_BLSP1_AHB_CLK>; 2300 clock-names = "core", "iface"; 2301 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2302 dma-names = "tx", "rx"; 2303 pinctrl-names = "default", "sleep"; 2304 pinctrl-0 = <&blsp1_i2c4_default>; 2305 pinctrl-1 = <&blsp1_i2c4_sleep>; 2306 clock-frequency = <400000>; 2307 2308 status = "disabled"; 2309 #address-cells = <1>; 2310 #size-cells = <0>; 2311 }; 2312 2313 blsp1_i2c5: i2c@c179000 { 2314 compatible = "qcom,i2c-qup-v2.2.1"; 2315 reg = <0x0c179000 0x600>; 2316 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2317 2318 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2319 <&gcc GCC_BLSP1_AHB_CLK>; 2320 clock-names = "core", "iface"; 2321 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2322 dma-names = "tx", "rx"; 2323 pinctrl-names = "default", "sleep"; 2324 pinctrl-0 = <&blsp1_i2c5_default>; 2325 pinctrl-1 = <&blsp1_i2c5_sleep>; 2326 clock-frequency = <400000>; 2327 2328 status = "disabled"; 2329 #address-cells = <1>; 2330 #size-cells = <0>; 2331 }; 2332 2333 blsp1_i2c6: i2c@c17a000 { 2334 compatible = "qcom,i2c-qup-v2.2.1"; 2335 reg = <0x0c17a000 0x600>; 2336 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2337 2338 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2339 <&gcc GCC_BLSP1_AHB_CLK>; 2340 clock-names = "core", "iface"; 2341 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2342 dma-names = "tx", "rx"; 2343 pinctrl-names = "default", "sleep"; 2344 pinctrl-0 = <&blsp1_i2c6_default>; 2345 pinctrl-1 = <&blsp1_i2c6_sleep>; 2346 clock-frequency = <400000>; 2347 2348 status = "disabled"; 2349 #address-cells = <1>; 2350 #size-cells = <0>; 2351 }; 2352 2353 blsp1_spi1: spi@c175000 { 2354 compatible = "qcom,spi-qup-v2.2.1"; 2355 reg = <0x0c175000 0x600>; 2356 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2357 2358 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2359 <&gcc GCC_BLSP1_AHB_CLK>; 2360 clock-names = "core", "iface"; 2361 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2362 dma-names = "tx", "rx"; 2363 pinctrl-names = "default"; 2364 pinctrl-0 = <&blsp1_spi1_default>; 2365 2366 status = "disabled"; 2367 #address-cells = <1>; 2368 #size-cells = <0>; 2369 }; 2370 2371 blsp1_spi2: spi@c176000 { 2372 compatible = "qcom,spi-qup-v2.2.1"; 2373 reg = <0x0c176000 0x600>; 2374 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2375 2376 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2377 <&gcc GCC_BLSP1_AHB_CLK>; 2378 clock-names = "core", "iface"; 2379 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2380 dma-names = "tx", "rx"; 2381 pinctrl-names = "default"; 2382 pinctrl-0 = <&blsp1_spi2_default>; 2383 2384 status = "disabled"; 2385 #address-cells = <1>; 2386 #size-cells = <0>; 2387 }; 2388 2389 blsp1_spi3: spi@c177000 { 2390 compatible = "qcom,spi-qup-v2.2.1"; 2391 reg = <0x0c177000 0x600>; 2392 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2393 2394 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2395 <&gcc GCC_BLSP1_AHB_CLK>; 2396 clock-names = "core", "iface"; 2397 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2398 dma-names = "tx", "rx"; 2399 pinctrl-names = "default"; 2400 pinctrl-0 = <&blsp1_spi3_default>; 2401 2402 status = "disabled"; 2403 #address-cells = <1>; 2404 #size-cells = <0>; 2405 }; 2406 2407 blsp1_spi4: spi@c178000 { 2408 compatible = "qcom,spi-qup-v2.2.1"; 2409 reg = <0x0c178000 0x600>; 2410 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2411 2412 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2413 <&gcc GCC_BLSP1_AHB_CLK>; 2414 clock-names = "core", "iface"; 2415 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2416 dma-names = "tx", "rx"; 2417 pinctrl-names = "default"; 2418 pinctrl-0 = <&blsp1_spi4_default>; 2419 2420 status = "disabled"; 2421 #address-cells = <1>; 2422 #size-cells = <0>; 2423 }; 2424 2425 blsp1_spi5: spi@c179000 { 2426 compatible = "qcom,spi-qup-v2.2.1"; 2427 reg = <0x0c179000 0x600>; 2428 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2429 2430 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2431 <&gcc GCC_BLSP1_AHB_CLK>; 2432 clock-names = "core", "iface"; 2433 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2434 dma-names = "tx", "rx"; 2435 pinctrl-names = "default"; 2436 pinctrl-0 = <&blsp1_spi5_default>; 2437 2438 status = "disabled"; 2439 #address-cells = <1>; 2440 #size-cells = <0>; 2441 }; 2442 2443 blsp1_spi6: spi@c17a000 { 2444 compatible = "qcom,spi-qup-v2.2.1"; 2445 reg = <0x0c17a000 0x600>; 2446 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2447 2448 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2449 <&gcc GCC_BLSP1_AHB_CLK>; 2450 clock-names = "core", "iface"; 2451 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2452 dma-names = "tx", "rx"; 2453 pinctrl-names = "default"; 2454 pinctrl-0 = <&blsp1_spi6_default>; 2455 2456 status = "disabled"; 2457 #address-cells = <1>; 2458 #size-cells = <0>; 2459 }; 2460 2461 blsp2_dma: dma-controller@c184000 { 2462 compatible = "qcom,bam-v1.7.0"; 2463 reg = <0x0c184000 0x25000>; 2464 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2465 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2466 clock-names = "bam_clk"; 2467 #dma-cells = <1>; 2468 qcom,ee = <0>; 2469 qcom,controlled-remotely; 2470 num-channels = <18>; 2471 qcom,num-ees = <4>; 2472 }; 2473 2474 blsp2_uart1: serial@c1b0000 { 2475 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2476 reg = <0x0c1b0000 0x1000>; 2477 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2478 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2479 <&gcc GCC_BLSP2_AHB_CLK>; 2480 clock-names = "core", "iface"; 2481 status = "disabled"; 2482 }; 2483 2484 blsp2_i2c1: i2c@c1b5000 { 2485 compatible = "qcom,i2c-qup-v2.2.1"; 2486 reg = <0x0c1b5000 0x600>; 2487 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2488 2489 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2490 <&gcc GCC_BLSP2_AHB_CLK>; 2491 clock-names = "core", "iface"; 2492 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2493 dma-names = "tx", "rx"; 2494 pinctrl-names = "default", "sleep"; 2495 pinctrl-0 = <&blsp2_i2c1_default>; 2496 pinctrl-1 = <&blsp2_i2c1_sleep>; 2497 clock-frequency = <400000>; 2498 2499 status = "disabled"; 2500 #address-cells = <1>; 2501 #size-cells = <0>; 2502 }; 2503 2504 blsp2_i2c2: i2c@c1b6000 { 2505 compatible = "qcom,i2c-qup-v2.2.1"; 2506 reg = <0x0c1b6000 0x600>; 2507 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2508 2509 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2510 <&gcc GCC_BLSP2_AHB_CLK>; 2511 clock-names = "core", "iface"; 2512 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2513 dma-names = "tx", "rx"; 2514 pinctrl-names = "default", "sleep"; 2515 pinctrl-0 = <&blsp2_i2c2_default>; 2516 pinctrl-1 = <&blsp2_i2c2_sleep>; 2517 clock-frequency = <400000>; 2518 2519 status = "disabled"; 2520 #address-cells = <1>; 2521 #size-cells = <0>; 2522 }; 2523 2524 blsp2_i2c3: i2c@c1b7000 { 2525 compatible = "qcom,i2c-qup-v2.2.1"; 2526 reg = <0x0c1b7000 0x600>; 2527 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2528 2529 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2530 <&gcc GCC_BLSP2_AHB_CLK>; 2531 clock-names = "core", "iface"; 2532 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2533 dma-names = "tx", "rx"; 2534 pinctrl-names = "default", "sleep"; 2535 pinctrl-0 = <&blsp2_i2c3_default>; 2536 pinctrl-1 = <&blsp2_i2c3_sleep>; 2537 clock-frequency = <400000>; 2538 2539 status = "disabled"; 2540 #address-cells = <1>; 2541 #size-cells = <0>; 2542 }; 2543 2544 blsp2_i2c4: i2c@c1b8000 { 2545 compatible = "qcom,i2c-qup-v2.2.1"; 2546 reg = <0x0c1b8000 0x600>; 2547 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2548 2549 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2550 <&gcc GCC_BLSP2_AHB_CLK>; 2551 clock-names = "core", "iface"; 2552 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2553 dma-names = "tx", "rx"; 2554 pinctrl-names = "default", "sleep"; 2555 pinctrl-0 = <&blsp2_i2c4_default>; 2556 pinctrl-1 = <&blsp2_i2c4_sleep>; 2557 clock-frequency = <400000>; 2558 2559 status = "disabled"; 2560 #address-cells = <1>; 2561 #size-cells = <0>; 2562 }; 2563 2564 blsp2_i2c5: i2c@c1b9000 { 2565 compatible = "qcom,i2c-qup-v2.2.1"; 2566 reg = <0x0c1b9000 0x600>; 2567 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2568 2569 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2570 <&gcc GCC_BLSP2_AHB_CLK>; 2571 clock-names = "core", "iface"; 2572 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2573 dma-names = "tx", "rx"; 2574 pinctrl-names = "default", "sleep"; 2575 pinctrl-0 = <&blsp2_i2c5_default>; 2576 pinctrl-1 = <&blsp2_i2c5_sleep>; 2577 clock-frequency = <400000>; 2578 2579 status = "disabled"; 2580 #address-cells = <1>; 2581 #size-cells = <0>; 2582 }; 2583 2584 blsp2_i2c6: i2c@c1ba000 { 2585 compatible = "qcom,i2c-qup-v2.2.1"; 2586 reg = <0x0c1ba000 0x600>; 2587 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2588 2589 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2590 <&gcc GCC_BLSP2_AHB_CLK>; 2591 clock-names = "core", "iface"; 2592 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2593 dma-names = "tx", "rx"; 2594 pinctrl-names = "default", "sleep"; 2595 pinctrl-0 = <&blsp2_i2c6_default>; 2596 pinctrl-1 = <&blsp2_i2c6_sleep>; 2597 clock-frequency = <400000>; 2598 2599 status = "disabled"; 2600 #address-cells = <1>; 2601 #size-cells = <0>; 2602 }; 2603 2604 blsp2_spi1: spi@c1b5000 { 2605 compatible = "qcom,spi-qup-v2.2.1"; 2606 reg = <0x0c1b5000 0x600>; 2607 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2608 2609 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 2610 <&gcc GCC_BLSP2_AHB_CLK>; 2611 clock-names = "core", "iface"; 2612 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2613 dma-names = "tx", "rx"; 2614 pinctrl-names = "default"; 2615 pinctrl-0 = <&blsp2_spi1_default>; 2616 2617 status = "disabled"; 2618 #address-cells = <1>; 2619 #size-cells = <0>; 2620 }; 2621 2622 blsp2_spi2: spi@c1b6000 { 2623 compatible = "qcom,spi-qup-v2.2.1"; 2624 reg = <0x0c1b6000 0x600>; 2625 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2626 2627 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 2628 <&gcc GCC_BLSP2_AHB_CLK>; 2629 clock-names = "core", "iface"; 2630 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2631 dma-names = "tx", "rx"; 2632 pinctrl-names = "default"; 2633 pinctrl-0 = <&blsp2_spi2_default>; 2634 2635 status = "disabled"; 2636 #address-cells = <1>; 2637 #size-cells = <0>; 2638 }; 2639 2640 blsp2_spi3: spi@c1b7000 { 2641 compatible = "qcom,spi-qup-v2.2.1"; 2642 reg = <0x0c1b7000 0x600>; 2643 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2644 2645 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 2646 <&gcc GCC_BLSP2_AHB_CLK>; 2647 clock-names = "core", "iface"; 2648 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2649 dma-names = "tx", "rx"; 2650 pinctrl-names = "default"; 2651 pinctrl-0 = <&blsp2_spi3_default>; 2652 2653 status = "disabled"; 2654 #address-cells = <1>; 2655 #size-cells = <0>; 2656 }; 2657 2658 blsp2_spi4: spi@c1b8000 { 2659 compatible = "qcom,spi-qup-v2.2.1"; 2660 reg = <0x0c1b8000 0x600>; 2661 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2662 2663 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 2664 <&gcc GCC_BLSP2_AHB_CLK>; 2665 clock-names = "core", "iface"; 2666 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2667 dma-names = "tx", "rx"; 2668 pinctrl-names = "default"; 2669 pinctrl-0 = <&blsp2_spi4_default>; 2670 2671 status = "disabled"; 2672 #address-cells = <1>; 2673 #size-cells = <0>; 2674 }; 2675 2676 blsp2_spi5: spi@c1b9000 { 2677 compatible = "qcom,spi-qup-v2.2.1"; 2678 reg = <0x0c1b9000 0x600>; 2679 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2680 2681 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 2682 <&gcc GCC_BLSP2_AHB_CLK>; 2683 clock-names = "core", "iface"; 2684 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2685 dma-names = "tx", "rx"; 2686 pinctrl-names = "default"; 2687 pinctrl-0 = <&blsp2_spi5_default>; 2688 2689 status = "disabled"; 2690 #address-cells = <1>; 2691 #size-cells = <0>; 2692 }; 2693 2694 blsp2_spi6: spi@c1ba000 { 2695 compatible = "qcom,spi-qup-v2.2.1"; 2696 reg = <0x0c1ba000 0x600>; 2697 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2698 2699 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 2700 <&gcc GCC_BLSP2_AHB_CLK>; 2701 clock-names = "core", "iface"; 2702 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2703 dma-names = "tx", "rx"; 2704 pinctrl-names = "default"; 2705 pinctrl-0 = <&blsp2_spi6_default>; 2706 2707 status = "disabled"; 2708 #address-cells = <1>; 2709 #size-cells = <0>; 2710 }; 2711 2712 mmcc: clock-controller@c8c0000 { 2713 compatible = "qcom,mmcc-msm8998"; 2714 #clock-cells = <1>; 2715 #reset-cells = <1>; 2716 #power-domain-cells = <1>; 2717 reg = <0xc8c0000 0x40000>; 2718 2719 clock-names = "xo", 2720 "gpll0", 2721 "dsi0dsi", 2722 "dsi0byte", 2723 "dsi1dsi", 2724 "dsi1byte", 2725 "hdmipll", 2726 "dplink", 2727 "dpvco", 2728 "gpll0_div"; 2729 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2730 <&gcc GCC_MMSS_GPLL0_CLK>, 2731 <0>, 2732 <0>, 2733 <0>, 2734 <0>, 2735 <0>, 2736 <0>, 2737 <0>, 2738 <&gcc GCC_MMSS_GPLL0_DIV_CLK>; 2739 }; 2740 2741 mmss_smmu: iommu@cd00000 { 2742 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 2743 reg = <0x0cd00000 0x40000>; 2744 #iommu-cells = <1>; 2745 2746 clocks = <&mmcc MNOC_AHB_CLK>, 2747 <&mmcc BIMC_SMMU_AHB_CLK>, 2748 <&mmcc BIMC_SMMU_AXI_CLK>; 2749 clock-names = "iface-mm", 2750 "iface-smmu", 2751 "bus-smmu"; 2752 2753 #global-interrupts = <0>; 2754 interrupts = 2755 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2768 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2769 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2770 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2771 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2772 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2773 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2775 2776 power-domains = <&mmcc BIMC_SMMU_GDSC>; 2777 }; 2778 2779 remoteproc_adsp: remoteproc@17300000 { 2780 compatible = "qcom,msm8998-adsp-pas"; 2781 reg = <0x17300000 0x4040>; 2782 2783 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2784 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2785 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2786 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2787 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2788 interrupt-names = "wdog", "fatal", "ready", 2789 "handover", "stop-ack"; 2790 2791 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2792 clock-names = "xo"; 2793 2794 memory-region = <&adsp_mem>; 2795 2796 qcom,smem-states = <&adsp_smp2p_out 0>; 2797 qcom,smem-state-names = "stop"; 2798 2799 power-domains = <&rpmpd MSM8998_VDDCX>; 2800 power-domain-names = "cx"; 2801 2802 status = "disabled"; 2803 2804 glink-edge { 2805 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2806 label = "lpass"; 2807 qcom,remote-pid = <2>; 2808 mboxes = <&apcs_glb 9>; 2809 }; 2810 }; 2811 2812 apcs_glb: mailbox@17911000 { 2813 compatible = "qcom,msm8998-apcs-hmss-global", 2814 "qcom,msm8994-apcs-kpss-global"; 2815 reg = <0x17911000 0x1000>; 2816 2817 #mbox-cells = <1>; 2818 }; 2819 2820 timer@17920000 { 2821 #address-cells = <1>; 2822 #size-cells = <1>; 2823 ranges; 2824 compatible = "arm,armv7-timer-mem"; 2825 reg = <0x17920000 0x1000>; 2826 2827 frame@17921000 { 2828 frame-number = <0>; 2829 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2830 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2831 reg = <0x17921000 0x1000>, 2832 <0x17922000 0x1000>; 2833 }; 2834 2835 frame@17923000 { 2836 frame-number = <1>; 2837 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2838 reg = <0x17923000 0x1000>; 2839 status = "disabled"; 2840 }; 2841 2842 frame@17924000 { 2843 frame-number = <2>; 2844 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2845 reg = <0x17924000 0x1000>; 2846 status = "disabled"; 2847 }; 2848 2849 frame@17925000 { 2850 frame-number = <3>; 2851 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2852 reg = <0x17925000 0x1000>; 2853 status = "disabled"; 2854 }; 2855 2856 frame@17926000 { 2857 frame-number = <4>; 2858 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2859 reg = <0x17926000 0x1000>; 2860 status = "disabled"; 2861 }; 2862 2863 frame@17927000 { 2864 frame-number = <5>; 2865 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2866 reg = <0x17927000 0x1000>; 2867 status = "disabled"; 2868 }; 2869 2870 frame@17928000 { 2871 frame-number = <6>; 2872 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2873 reg = <0x17928000 0x1000>; 2874 status = "disabled"; 2875 }; 2876 }; 2877 2878 intc: interrupt-controller@17a00000 { 2879 compatible = "arm,gic-v3"; 2880 reg = <0x17a00000 0x10000>, /* GICD */ 2881 <0x17b00000 0x100000>; /* GICR * 8 */ 2882 #interrupt-cells = <3>; 2883 #address-cells = <1>; 2884 #size-cells = <1>; 2885 ranges; 2886 interrupt-controller; 2887 #redistributor-regions = <1>; 2888 redistributor-stride = <0x0 0x20000>; 2889 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2890 }; 2891 2892 wifi: wifi@18800000 { 2893 compatible = "qcom,wcn3990-wifi"; 2894 status = "disabled"; 2895 reg = <0x18800000 0x800000>; 2896 reg-names = "membase"; 2897 memory-region = <&wlan_msa_mem>; 2898 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2899 clock-names = "cxo_ref_clk_pin"; 2900 interrupts = 2901 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2905 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2906 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2908 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2909 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2910 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2911 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2912 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2913 iommus = <&anoc2_smmu 0x1900>, 2914 <&anoc2_smmu 0x1901>; 2915 qcom,snoc-host-cap-8bit-quirk; 2916 }; 2917 }; 2918}; 2919