1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/gpio/gpio.h> 8 9/ { 10 interrupt-parent = <&intc>; 11 12 qcom,msm-id = <292 0x0>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 memory { 20 device_type = "memory"; 21 /* We expect the bootloader to fill in the reg */ 22 reg = <0 0 0 0>; 23 }; 24 25 reserved-memory { 26 #address-cells = <2>; 27 #size-cells = <2>; 28 ranges; 29 30 memory@85800000 { 31 reg = <0x0 0x85800000 0x0 0x800000>; 32 no-map; 33 }; 34 35 smem_mem: smem-mem@86000000 { 36 reg = <0x0 0x86000000 0x0 0x200000>; 37 no-map; 38 }; 39 40 memory@86200000 { 41 reg = <0x0 0x86200000 0x0 0x2d00000>; 42 no-map; 43 }; 44 45 rmtfs { 46 compatible = "qcom,rmtfs-mem"; 47 48 size = <0x0 0x200000>; 49 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 50 no-map; 51 52 qcom,client-id = <1>; 53 qcom,vmid = <15>; 54 }; 55 }; 56 57 clocks { 58 xo: xo-board { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <19200000>; 62 clock-output-names = "xo_board"; 63 }; 64 65 sleep_clk { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <32764>; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <2>; 74 #size-cells = <0>; 75 76 CPU0: cpu@0 { 77 device_type = "cpu"; 78 compatible = "arm,armv8"; 79 reg = <0x0 0x0>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_0>; 82 L2_0: l2-cache { 83 compatible = "arm,arch-cache"; 84 cache-level = <2>; 85 }; 86 L1_I_0: l1-icache { 87 compatible = "arm,arch-cache"; 88 }; 89 L1_D_0: l1-dcache { 90 compatible = "arm,arch-cache"; 91 }; 92 }; 93 94 CPU1: cpu@1 { 95 device_type = "cpu"; 96 compatible = "arm,armv8"; 97 reg = <0x0 0x1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_0>; 100 L1_I_1: l1-icache { 101 compatible = "arm,arch-cache"; 102 }; 103 L1_D_1: l1-dcache { 104 compatible = "arm,arch-cache"; 105 }; 106 }; 107 108 CPU2: cpu@2 { 109 device_type = "cpu"; 110 compatible = "arm,armv8"; 111 reg = <0x0 0x2>; 112 enable-method = "psci"; 113 next-level-cache = <&L2_0>; 114 L1_I_2: l1-icache { 115 compatible = "arm,arch-cache"; 116 }; 117 L1_D_2: l1-dcache { 118 compatible = "arm,arch-cache"; 119 }; 120 }; 121 122 CPU3: cpu@3 { 123 device_type = "cpu"; 124 compatible = "arm,armv8"; 125 reg = <0x0 0x3>; 126 enable-method = "psci"; 127 next-level-cache = <&L2_0>; 128 L1_I_3: l1-icache { 129 compatible = "arm,arch-cache"; 130 }; 131 L1_D_3: l1-dcache { 132 compatible = "arm,arch-cache"; 133 }; 134 }; 135 136 CPU4: cpu@100 { 137 device_type = "cpu"; 138 compatible = "arm,armv8"; 139 reg = <0x0 0x100>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_1>; 142 L2_1: l2-cache { 143 compatible = "arm,arch-cache"; 144 cache-level = <2>; 145 }; 146 L1_I_100: l1-icache { 147 compatible = "arm,arch-cache"; 148 }; 149 L1_D_100: l1-dcache { 150 compatible = "arm,arch-cache"; 151 }; 152 }; 153 154 CPU5: cpu@101 { 155 device_type = "cpu"; 156 compatible = "arm,armv8"; 157 reg = <0x0 0x101>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_1>; 160 L1_I_101: l1-icache { 161 compatible = "arm,arch-cache"; 162 }; 163 L1_D_101: l1-dcache { 164 compatible = "arm,arch-cache"; 165 }; 166 }; 167 168 CPU6: cpu@102 { 169 device_type = "cpu"; 170 compatible = "arm,armv8"; 171 reg = <0x0 0x102>; 172 enable-method = "psci"; 173 next-level-cache = <&L2_1>; 174 L1_I_102: l1-icache { 175 compatible = "arm,arch-cache"; 176 }; 177 L1_D_102: l1-dcache { 178 compatible = "arm,arch-cache"; 179 }; 180 }; 181 182 CPU7: cpu@103 { 183 device_type = "cpu"; 184 compatible = "arm,armv8"; 185 reg = <0x0 0x103>; 186 enable-method = "psci"; 187 next-level-cache = <&L2_1>; 188 L1_I_103: l1-icache { 189 compatible = "arm,arch-cache"; 190 }; 191 L1_D_103: l1-dcache { 192 compatible = "arm,arch-cache"; 193 }; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 }; 214 215 cluster1 { 216 core0 { 217 cpu = <&CPU4>; 218 }; 219 220 core1 { 221 cpu = <&CPU5>; 222 }; 223 224 core2 { 225 cpu = <&CPU6>; 226 }; 227 228 core3 { 229 cpu = <&CPU7>; 230 }; 231 }; 232 }; 233 }; 234 235 firmware { 236 scm { 237 compatible = "qcom,scm-msm8998", "qcom,scm"; 238 }; 239 }; 240 241 tcsr_mutex: hwlock { 242 compatible = "qcom,tcsr-mutex"; 243 syscon = <&tcsr_mutex_regs 0 0x1000>; 244 #hwlock-cells = <1>; 245 }; 246 247 psci { 248 compatible = "arm,psci-1.0"; 249 method = "smc"; 250 }; 251 252 rpm-glink { 253 compatible = "qcom,glink-rpm"; 254 255 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 256 qcom,rpm-msg-ram = <&rpm_msg_ram>; 257 mboxes = <&apcs_glb 0>; 258 259 rpm_requests: rpm-requests { 260 compatible = "qcom,rpm-msm8998"; 261 qcom,glink-channels = "rpm_requests"; 262 263 rpmcc: clock-controller { 264 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 265 #clock-cells = <1>; 266 }; 267 }; 268 }; 269 270 smem { 271 compatible = "qcom,smem"; 272 memory-region = <&smem_mem>; 273 hwlocks = <&tcsr_mutex 3>; 274 }; 275 276 smp2p-lpass { 277 compatible = "qcom,smp2p"; 278 qcom,smem = <443>, <429>; 279 280 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 281 282 mboxes = <&apcs_glb 10>; 283 284 qcom,local-pid = <0>; 285 qcom,remote-pid = <2>; 286 287 adsp_smp2p_out: master-kernel { 288 qcom,entry-name = "master-kernel"; 289 #qcom,smem-state-cells = <1>; 290 }; 291 292 adsp_smp2p_in: slave-kernel { 293 qcom,entry-name = "slave-kernel"; 294 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 }; 298 }; 299 300 smp2p-mpss { 301 compatible = "qcom,smp2p"; 302 qcom,smem = <435>, <428>; 303 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 304 mboxes = <&apcs_glb 14>; 305 qcom,local-pid = <0>; 306 qcom,remote-pid = <1>; 307 308 modem_smp2p_out: master-kernel { 309 qcom,entry-name = "master-kernel"; 310 #qcom,smem-state-cells = <1>; 311 }; 312 313 modem_smp2p_in: slave-kernel { 314 qcom,entry-name = "slave-kernel"; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 }; 318 }; 319 320 smp2p-slpi { 321 compatible = "qcom,smp2p"; 322 qcom,smem = <481>, <430>; 323 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 324 mboxes = <&apcs_glb 26>; 325 qcom,local-pid = <0>; 326 qcom,remote-pid = <3>; 327 328 slpi_smp2p_out: master-kernel { 329 qcom,entry-name = "master-kernel"; 330 #qcom,smem-state-cells = <1>; 331 }; 332 333 slpi_smp2p_in: slave-kernel { 334 qcom,entry-name = "slave-kernel"; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 }; 338 }; 339 340 thermal-zones { 341 cpu0-thermal { 342 polling-delay-passive = <250>; 343 polling-delay = <1000>; 344 345 thermal-sensors = <&tsens0 1>; 346 347 trips { 348 cpu0_alert0: trip-point@0 { 349 temperature = <75000>; 350 hysteresis = <2000>; 351 type = "passive"; 352 }; 353 354 cpu0_crit: cpu_crit { 355 temperature = <110000>; 356 hysteresis = <2000>; 357 type = "critical"; 358 }; 359 }; 360 }; 361 362 cpu1-thermal { 363 polling-delay-passive = <250>; 364 polling-delay = <1000>; 365 366 thermal-sensors = <&tsens0 2>; 367 368 trips { 369 cpu1_alert0: trip-point@0 { 370 temperature = <75000>; 371 hysteresis = <2000>; 372 type = "passive"; 373 }; 374 375 cpu1_crit: cpu_crit { 376 temperature = <110000>; 377 hysteresis = <2000>; 378 type = "critical"; 379 }; 380 }; 381 }; 382 383 cpu2-thermal { 384 polling-delay-passive = <250>; 385 polling-delay = <1000>; 386 387 thermal-sensors = <&tsens0 3>; 388 389 trips { 390 cpu2_alert0: trip-point@0 { 391 temperature = <75000>; 392 hysteresis = <2000>; 393 type = "passive"; 394 }; 395 396 cpu2_crit: cpu_crit { 397 temperature = <110000>; 398 hysteresis = <2000>; 399 type = "critical"; 400 }; 401 }; 402 }; 403 404 cpu3-thermal { 405 polling-delay-passive = <250>; 406 polling-delay = <1000>; 407 408 thermal-sensors = <&tsens0 4>; 409 410 trips { 411 cpu3_alert0: trip-point@0 { 412 temperature = <75000>; 413 hysteresis = <2000>; 414 type = "passive"; 415 }; 416 417 cpu3_crit: cpu_crit { 418 temperature = <110000>; 419 hysteresis = <2000>; 420 type = "critical"; 421 }; 422 }; 423 }; 424 425 cpu4-thermal { 426 polling-delay-passive = <250>; 427 polling-delay = <1000>; 428 429 thermal-sensors = <&tsens0 7>; 430 431 trips { 432 cpu4_alert0: trip-point@0 { 433 temperature = <75000>; 434 hysteresis = <2000>; 435 type = "passive"; 436 }; 437 438 cpu4_crit: cpu_crit { 439 temperature = <110000>; 440 hysteresis = <2000>; 441 type = "critical"; 442 }; 443 }; 444 }; 445 446 cpu5-thermal { 447 polling-delay-passive = <250>; 448 polling-delay = <1000>; 449 450 thermal-sensors = <&tsens0 8>; 451 452 trips { 453 cpu5_alert0: trip-point@0 { 454 temperature = <75000>; 455 hysteresis = <2000>; 456 type = "passive"; 457 }; 458 459 cpu5_crit: cpu_crit { 460 temperature = <110000>; 461 hysteresis = <2000>; 462 type = "critical"; 463 }; 464 }; 465 }; 466 467 cpu6-thermal { 468 polling-delay-passive = <250>; 469 polling-delay = <1000>; 470 471 thermal-sensors = <&tsens0 9>; 472 473 trips { 474 cpu6_alert0: trip-point@0 { 475 temperature = <75000>; 476 hysteresis = <2000>; 477 type = "passive"; 478 }; 479 480 cpu6_crit: cpu_crit { 481 temperature = <110000>; 482 hysteresis = <2000>; 483 type = "critical"; 484 }; 485 }; 486 }; 487 488 cpu7-thermal { 489 polling-delay-passive = <250>; 490 polling-delay = <1000>; 491 492 thermal-sensors = <&tsens0 10>; 493 494 trips { 495 cpu7_alert0: trip-point@0 { 496 temperature = <75000>; 497 hysteresis = <2000>; 498 type = "passive"; 499 }; 500 501 cpu7_crit: cpu_crit { 502 temperature = <110000>; 503 hysteresis = <2000>; 504 type = "critical"; 505 }; 506 }; 507 }; 508 509 gpu-thermal-bottom { 510 polling-delay-passive = <250>; 511 polling-delay = <1000>; 512 513 thermal-sensors = <&tsens0 12>; 514 515 trips { 516 gpu1_alert0: trip-point@0 { 517 temperature = <90000>; 518 hysteresis = <2000>; 519 type = "hot"; 520 }; 521 }; 522 }; 523 524 gpu-thermal-top { 525 polling-delay-passive = <250>; 526 polling-delay = <1000>; 527 528 thermal-sensors = <&tsens0 13>; 529 530 trips { 531 gpu2_alert0: trip-point@0 { 532 temperature = <90000>; 533 hysteresis = <2000>; 534 type = "hot"; 535 }; 536 }; 537 }; 538 539 clust0-mhm-thermal { 540 polling-delay-passive = <250>; 541 polling-delay = <1000>; 542 543 thermal-sensors = <&tsens0 5>; 544 545 trips { 546 cluster0_mhm_alert0: trip-point@0 { 547 temperature = <90000>; 548 hysteresis = <2000>; 549 type = "hot"; 550 }; 551 }; 552 }; 553 554 clust1-mhm-thermal { 555 polling-delay-passive = <250>; 556 polling-delay = <1000>; 557 558 thermal-sensors = <&tsens0 6>; 559 560 trips { 561 cluster1_mhm_alert0: trip-point@0 { 562 temperature = <90000>; 563 hysteresis = <2000>; 564 type = "hot"; 565 }; 566 }; 567 }; 568 569 cluster1-l2-thermal { 570 polling-delay-passive = <250>; 571 polling-delay = <1000>; 572 573 thermal-sensors = <&tsens0 11>; 574 575 trips { 576 cluster1_l2_alert0: trip-point@0 { 577 temperature = <90000>; 578 hysteresis = <2000>; 579 type = "hot"; 580 }; 581 }; 582 }; 583 584 modem-thermal { 585 polling-delay-passive = <250>; 586 polling-delay = <1000>; 587 588 thermal-sensors = <&tsens1 1>; 589 590 trips { 591 modem_alert0: trip-point@0 { 592 temperature = <90000>; 593 hysteresis = <2000>; 594 type = "hot"; 595 }; 596 }; 597 }; 598 599 mem-thermal { 600 polling-delay-passive = <250>; 601 polling-delay = <1000>; 602 603 thermal-sensors = <&tsens1 2>; 604 605 trips { 606 mem_alert0: trip-point@0 { 607 temperature = <90000>; 608 hysteresis = <2000>; 609 type = "hot"; 610 }; 611 }; 612 }; 613 614 wlan-thermal { 615 polling-delay-passive = <250>; 616 polling-delay = <1000>; 617 618 thermal-sensors = <&tsens1 3>; 619 620 trips { 621 wlan_alert0: trip-point@0 { 622 temperature = <90000>; 623 hysteresis = <2000>; 624 type = "hot"; 625 }; 626 }; 627 }; 628 629 q6-dsp-thermal { 630 polling-delay-passive = <250>; 631 polling-delay = <1000>; 632 633 thermal-sensors = <&tsens1 4>; 634 635 trips { 636 q6_dsp_alert0: trip-point@0 { 637 temperature = <90000>; 638 hysteresis = <2000>; 639 type = "hot"; 640 }; 641 }; 642 }; 643 644 camera-thermal { 645 polling-delay-passive = <250>; 646 polling-delay = <1000>; 647 648 thermal-sensors = <&tsens1 5>; 649 650 trips { 651 camera_alert0: trip-point@0 { 652 temperature = <90000>; 653 hysteresis = <2000>; 654 type = "hot"; 655 }; 656 }; 657 }; 658 659 multimedia-thermal { 660 polling-delay-passive = <250>; 661 polling-delay = <1000>; 662 663 thermal-sensors = <&tsens1 6>; 664 665 trips { 666 multimedia_alert0: trip-point@0 { 667 temperature = <90000>; 668 hysteresis = <2000>; 669 type = "hot"; 670 }; 671 }; 672 }; 673 }; 674 675 timer { 676 compatible = "arm,armv8-timer"; 677 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 678 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 679 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 680 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 681 }; 682 683 soc: soc { 684 #address-cells = <1>; 685 #size-cells = <1>; 686 ranges = <0 0 0 0xffffffff>; 687 compatible = "simple-bus"; 688 689 rpm_msg_ram: memory@68000 { 690 compatible = "qcom,rpm-msg-ram"; 691 reg = <0x778000 0x7000>; 692 }; 693 694 qfprom: qfprom@780000 { 695 compatible = "qcom,qfprom"; 696 reg = <0x780000 0x621c>; 697 #address-cells = <1>; 698 #size-cells = <1>; 699 700 qusb2_hstx_trim: hstx-trim@423a { 701 reg = <0x423a 0x1>; 702 bits = <0 4>; 703 }; 704 }; 705 706 gcc: clock-controller@100000 { 707 compatible = "qcom,gcc-msm8998"; 708 #clock-cells = <1>; 709 #reset-cells = <1>; 710 #power-domain-cells = <1>; 711 reg = <0x100000 0xb0000>; 712 }; 713 714 tlmm: pinctrl@3400000 { 715 compatible = "qcom,msm8998-pinctrl"; 716 reg = <0x3400000 0xc00000>; 717 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 718 gpio-controller; 719 #gpio-cells = <0x2>; 720 interrupt-controller; 721 #interrupt-cells = <0x2>; 722 }; 723 724 spmi_bus: spmi@800f000 { 725 compatible = "qcom,spmi-pmic-arb"; 726 reg = <0x800f000 0x1000>, 727 <0x8400000 0x1000000>, 728 <0x9400000 0x1000000>, 729 <0xa400000 0x220000>, 730 <0x800a000 0x3000>; 731 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 732 interrupt-names = "periph_irq"; 733 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 734 qcom,ee = <0>; 735 qcom,channel = <0>; 736 #address-cells = <2>; 737 #size-cells = <0>; 738 interrupt-controller; 739 #interrupt-cells = <4>; 740 cell-index = <0>; 741 }; 742 743 tsens0: thermal@10ab000 { 744 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 745 reg = <0x10ab000 0x1000>, /* TM */ 746 <0x10aa000 0x1000>; /* SROT */ 747 748 #qcom,sensors = <14>; 749 #thermal-sensor-cells = <1>; 750 }; 751 752 tsens1: thermal@10ae000 { 753 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 754 reg = <0x10ae000 0x1000>, /* TM */ 755 <0x10ad000 0x1000>; /* SROT */ 756 757 #qcom,sensors = <8>; 758 #thermal-sensor-cells = <1>; 759 }; 760 761 tcsr_mutex_regs: syscon@1f40000 { 762 compatible = "syscon"; 763 reg = <0x1f40000 0x20000>; 764 }; 765 766 apcs_glb: mailbox@9820000 { 767 compatible = "qcom,msm8998-apcs-hmss-global"; 768 reg = <0x17911000 0x1000>; 769 770 #mbox-cells = <1>; 771 }; 772 773 usb3: usb@a8f8800 { 774 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 775 reg = <0x0a8f8800 0x400>; 776 status = "disabled"; 777 #address-cells = <1>; 778 #size-cells = <1>; 779 ranges; 780 781 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 782 <&gcc GCC_USB30_MASTER_CLK>, 783 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 784 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 785 <&gcc GCC_USB30_SLEEP_CLK>; 786 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 787 "sleep"; 788 789 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 790 <&gcc GCC_USB30_MASTER_CLK>; 791 assigned-clock-rates = <19200000>, <120000000>; 792 793 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 795 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 796 797 power-domains = <&gcc USB_30_GDSC>; 798 799 resets = <&gcc GCC_USB_30_BCR>; 800 801 usb3_dwc3: dwc3@a800000 { 802 compatible = "snps,dwc3"; 803 reg = <0x0a800000 0xcd00>; 804 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 805 snps,dis_u2_susphy_quirk; 806 snps,dis_enblslpm_quirk; 807 phys = <&qusb2phy>, <&usb1_ssphy>; 808 phy-names = "usb2-phy", "usb3-phy"; 809 snps,has-lpm-erratum; 810 snps,hird-threshold = /bits/ 8 <0x10>; 811 }; 812 }; 813 814 usb3phy: phy@c010000 { 815 compatible = "qcom,msm8998-qmp-usb3-phy"; 816 reg = <0x0c010000 0x18c>; 817 status = "disabled"; 818 #clock-cells = <1>; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 ranges; 822 823 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 824 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 825 <&gcc GCC_USB3_CLKREF_CLK>; 826 clock-names = "aux", "cfg_ahb", "ref"; 827 828 resets = <&gcc GCC_USB3_PHY_BCR>, 829 <&gcc GCC_USB3PHY_PHY_BCR>; 830 reset-names = "phy", "common"; 831 832 usb1_ssphy: lane@c010200 { 833 reg = <0xc010200 0x128>, 834 <0xc010400 0x200>, 835 <0xc010c00 0x20c>, 836 <0xc010600 0x128>, 837 <0xc010800 0x200>; 838 #phy-cells = <0>; 839 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 840 clock-names = "pipe0"; 841 clock-output-names = "usb3_phy_pipe_clk_src"; 842 }; 843 }; 844 845 qusb2phy: phy@c012000 { 846 compatible = "qcom,msm8998-qusb2-phy"; 847 reg = <0x0c012000 0x2a8>; 848 status = "disabled"; 849 #phy-cells = <0>; 850 851 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 852 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 853 clock-names = "cfg_ahb", "ref"; 854 855 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 856 857 nvmem-cells = <&qusb2_hstx_trim>; 858 }; 859 860 sdhc2: sdhci@c0a4900 { 861 compatible = "qcom,sdhci-msm-v4"; 862 reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; 863 reg-names = "hc_mem", "core_mem"; 864 865 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-names = "hc_irq", "pwr_irq"; 868 869 clock-names = "iface", "core", "xo"; 870 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 871 <&gcc GCC_SDCC2_APPS_CLK>, 872 <&xo>; 873 bus-width = <4>; 874 status = "disabled"; 875 }; 876 877 blsp1_i2c1: i2c@c175000 { 878 compatible = "qcom,i2c-qup-v2.2.1"; 879 reg = <0x0c175000 0x600>; 880 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 881 882 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 883 <&gcc GCC_BLSP1_AHB_CLK>; 884 clock-names = "core", "iface"; 885 clock-frequency = <400000>; 886 887 status = "disabled"; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 }; 891 892 blsp1_i2c2: i2c@c176000 { 893 compatible = "qcom,i2c-qup-v2.2.1"; 894 reg = <0x0c176000 0x600>; 895 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 896 897 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 898 <&gcc GCC_BLSP1_AHB_CLK>; 899 clock-names = "core", "iface"; 900 clock-frequency = <400000>; 901 902 status = "disabled"; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 }; 906 907 blsp1_i2c3: i2c@c177000 { 908 compatible = "qcom,i2c-qup-v2.2.1"; 909 reg = <0x0c177000 0x600>; 910 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 911 912 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 913 <&gcc GCC_BLSP1_AHB_CLK>; 914 clock-names = "core", "iface"; 915 clock-frequency = <400000>; 916 917 status = "disabled"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 }; 921 922 blsp1_i2c4: i2c@c178000 { 923 compatible = "qcom,i2c-qup-v2.2.1"; 924 reg = <0x0c178000 0x600>; 925 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 926 927 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 928 <&gcc GCC_BLSP1_AHB_CLK>; 929 clock-names = "core", "iface"; 930 clock-frequency = <400000>; 931 932 status = "disabled"; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 }; 936 937 blsp1_i2c5: i2c@c179000 { 938 compatible = "qcom,i2c-qup-v2.2.1"; 939 reg = <0x0c179000 0x600>; 940 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 941 942 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 943 <&gcc GCC_BLSP1_AHB_CLK>; 944 clock-names = "core", "iface"; 945 clock-frequency = <400000>; 946 947 status = "disabled"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 }; 951 952 blsp1_i2c6: i2c@c17a000 { 953 compatible = "qcom,i2c-qup-v2.2.1"; 954 reg = <0x0c17a000 0x600>; 955 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 956 957 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 958 <&gcc GCC_BLSP1_AHB_CLK>; 959 clock-names = "core", "iface"; 960 clock-frequency = <400000>; 961 962 status = "disabled"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 }; 966 967 blsp2_i2c0: i2c@c1b5000 { 968 compatible = "qcom,i2c-qup-v2.2.1"; 969 reg = <0x0c1b5000 0x600>; 970 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 971 972 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 973 <&gcc GCC_BLSP2_AHB_CLK>; 974 clock-names = "core", "iface"; 975 clock-frequency = <400000>; 976 977 status = "disabled"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 }; 981 982 blsp2_i2c1: i2c@c1b6000 { 983 compatible = "qcom,i2c-qup-v2.2.1"; 984 reg = <0x0c1b6000 0x600>; 985 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 986 987 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 988 <&gcc GCC_BLSP2_AHB_CLK>; 989 clock-names = "core", "iface"; 990 clock-frequency = <400000>; 991 992 status = "disabled"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 }; 996 997 blsp2_i2c2: i2c@c1b7000 { 998 compatible = "qcom,i2c-qup-v2.2.1"; 999 reg = <0x0c1b7000 0x600>; 1000 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1001 1002 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1003 <&gcc GCC_BLSP2_AHB_CLK>; 1004 clock-names = "core", "iface"; 1005 clock-frequency = <400000>; 1006 1007 status = "disabled"; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 }; 1011 1012 blsp2_i2c3: i2c@c1b8000 { 1013 compatible = "qcom,i2c-qup-v2.2.1"; 1014 reg = <0x0c1b8000 0x600>; 1015 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1016 1017 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1018 <&gcc GCC_BLSP2_AHB_CLK>; 1019 clock-names = "core", "iface"; 1020 clock-frequency = <400000>; 1021 1022 status = "disabled"; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 }; 1026 1027 blsp2_i2c4: i2c@c1b9000 { 1028 compatible = "qcom,i2c-qup-v2.2.1"; 1029 reg = <0x0c1b9000 0x600>; 1030 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1031 1032 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 1033 <&gcc GCC_BLSP2_AHB_CLK>; 1034 clock-names = "core", "iface"; 1035 clock-frequency = <400000>; 1036 1037 status = "disabled"; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 }; 1041 1042 blsp2_i2c5: i2c@c1ba000 { 1043 compatible = "qcom,i2c-qup-v2.2.1"; 1044 reg = <0x0c1ba000 0x600>; 1045 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1046 1047 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 1048 <&gcc GCC_BLSP2_AHB_CLK>; 1049 clock-names = "core", "iface"; 1050 clock-frequency = <400000>; 1051 1052 status = "disabled"; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 }; 1056 1057 blsp2_uart1: serial@c1b0000 { 1058 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1059 reg = <0xc1b0000 0x1000>; 1060 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1062 <&gcc GCC_BLSP2_AHB_CLK>; 1063 clock-names = "core", "iface"; 1064 status = "disabled"; 1065 }; 1066 1067 timer@17920000 { 1068 #address-cells = <1>; 1069 #size-cells = <1>; 1070 ranges; 1071 compatible = "arm,armv7-timer-mem"; 1072 reg = <0x17920000 0x1000>; 1073 1074 frame@17921000 { 1075 frame-number = <0>; 1076 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1078 reg = <0x17921000 0x1000>, 1079 <0x17922000 0x1000>; 1080 }; 1081 1082 frame@17923000 { 1083 frame-number = <1>; 1084 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1085 reg = <0x17923000 0x1000>; 1086 status = "disabled"; 1087 }; 1088 1089 frame@17924000 { 1090 frame-number = <2>; 1091 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1092 reg = <0x17924000 0x1000>; 1093 status = "disabled"; 1094 }; 1095 1096 frame@17925000 { 1097 frame-number = <3>; 1098 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1099 reg = <0x17925000 0x1000>; 1100 status = "disabled"; 1101 }; 1102 1103 frame@17926000 { 1104 frame-number = <4>; 1105 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1106 reg = <0x17926000 0x1000>; 1107 status = "disabled"; 1108 }; 1109 1110 frame@17927000 { 1111 frame-number = <5>; 1112 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1113 reg = <0x17927000 0x1000>; 1114 status = "disabled"; 1115 }; 1116 1117 frame@17928000 { 1118 frame-number = <6>; 1119 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1120 reg = <0x17928000 0x1000>; 1121 status = "disabled"; 1122 }; 1123 }; 1124 1125 intc: interrupt-controller@17a00000 { 1126 compatible = "arm,gic-v3"; 1127 reg = <0x17a00000 0x10000>, /* GICD */ 1128 <0x17b00000 0x100000>; /* GICR * 8 */ 1129 #interrupt-cells = <3>; 1130 #address-cells = <1>; 1131 #size-cells = <1>; 1132 ranges; 1133 interrupt-controller; 1134 #redistributor-regions = <1>; 1135 redistributor-stride = <0x0 0x20000>; 1136 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1137 }; 1138 1139 ufshc: ufshc@1da4000 { 1140 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1141 reg = <0x01da4000 0x2500>; 1142 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1143 phys = <&ufsphy_lanes>; 1144 phy-names = "ufsphy"; 1145 lanes-per-direction = <2>; 1146 power-domains = <&gcc UFS_GDSC>; 1147 #reset-cells = <1>; 1148 1149 clock-names = 1150 "core_clk", 1151 "bus_aggr_clk", 1152 "iface_clk", 1153 "core_clk_unipro", 1154 "ref_clk", 1155 "tx_lane0_sync_clk", 1156 "rx_lane0_sync_clk", 1157 "rx_lane1_sync_clk"; 1158 clocks = 1159 <&gcc GCC_UFS_AXI_CLK>, 1160 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1161 <&gcc GCC_UFS_AHB_CLK>, 1162 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1163 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1164 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1165 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1166 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1167 freq-table-hz = 1168 <50000000 200000000>, 1169 <0 0>, 1170 <0 0>, 1171 <37500000 150000000>, 1172 <0 0>, 1173 <0 0>, 1174 <0 0>, 1175 <0 0>; 1176 1177 resets = <&gcc GCC_UFS_BCR>; 1178 reset-names = "rst"; 1179 }; 1180 1181 ufsphy: phy@1da7000 { 1182 compatible = "qcom,msm8998-qmp-ufs-phy"; 1183 reg = <0x01da7000 0x18c>; 1184 #address-cells = <1>; 1185 #size-cells = <1>; 1186 ranges; 1187 1188 clock-names = 1189 "ref", 1190 "ref_aux"; 1191 clocks = 1192 <&gcc GCC_UFS_CLKREF_CLK>, 1193 <&gcc GCC_UFS_PHY_AUX_CLK>; 1194 1195 reset-names = "ufsphy"; 1196 resets = <&ufshc 0>; 1197 1198 ufsphy_lanes: lanes@1da7400 { 1199 reg = <0x01da7400 0x128>, 1200 <0x01da7600 0x1fc>, 1201 <0x01da7c00 0x1dc>, 1202 <0x01da7800 0x128>, 1203 <0x01da7a00 0x1fc>; 1204 #phy-cells = <0>; 1205 }; 1206 }; 1207 }; 1208}; 1209 1210#include "msm8998-pins.dtsi" 1211