1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/gpio/gpio.h> 7 8/ { 9 interrupt-parent = <&intc>; 10 11 qcom,msm-id = <292 0x0>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 chosen { }; 17 18 memory { 19 device_type = "memory"; 20 /* We expect the bootloader to fill in the reg */ 21 reg = <0 0 0 0>; 22 }; 23 24 reserved-memory { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 29 memory@85800000 { 30 reg = <0x0 0x85800000 0x0 0x800000>; 31 no-map; 32 }; 33 34 smem_mem: smem-mem@86000000 { 35 reg = <0x0 0x86000000 0x0 0x200000>; 36 no-map; 37 }; 38 39 memory@86200000 { 40 reg = <0x0 0x86200000 0x0 0x2600000>; 41 no-map; 42 }; 43 44 rmtfs { 45 compatible = "qcom,rmtfs-mem"; 46 47 size = <0x0 0x200000>; 48 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 49 no-map; 50 51 qcom,client-id = <1>; 52 qcom,vmid = <15>; 53 }; 54 }; 55 56 clocks { 57 xo: xo { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <19200000>; 61 }; 62 63 sleep_clk { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <32764>; 67 }; 68 }; 69 70 cpus { 71 #address-cells = <2>; 72 #size-cells = <0>; 73 74 CPU0: cpu@0 { 75 device_type = "cpu"; 76 compatible = "arm,armv8"; 77 reg = <0x0 0x0>; 78 enable-method = "psci"; 79 efficiency = <1024>; 80 next-level-cache = <&L2_0>; 81 L2_0: l2-cache { 82 compatible = "arm,arch-cache"; 83 cache-level = <2>; 84 }; 85 L1_I_0: l1-icache { 86 compatible = "arm,arch-cache"; 87 }; 88 L1_D_0: l1-dcache { 89 compatible = "arm,arch-cache"; 90 }; 91 }; 92 93 CPU1: cpu@1 { 94 device_type = "cpu"; 95 compatible = "arm,armv8"; 96 reg = <0x0 0x1>; 97 enable-method = "psci"; 98 efficiency = <1024>; 99 next-level-cache = <&L2_0>; 100 L1_I_1: l1-icache { 101 compatible = "arm,arch-cache"; 102 }; 103 L1_D_1: l1-dcache { 104 compatible = "arm,arch-cache"; 105 }; 106 }; 107 108 CPU2: cpu@2 { 109 device_type = "cpu"; 110 compatible = "arm,armv8"; 111 reg = <0x0 0x2>; 112 enable-method = "psci"; 113 efficiency = <1024>; 114 next-level-cache = <&L2_0>; 115 L1_I_2: l1-icache { 116 compatible = "arm,arch-cache"; 117 }; 118 L1_D_2: l1-dcache { 119 compatible = "arm,arch-cache"; 120 }; 121 }; 122 123 CPU3: cpu@3 { 124 device_type = "cpu"; 125 compatible = "arm,armv8"; 126 reg = <0x0 0x3>; 127 enable-method = "psci"; 128 efficiency = <1024>; 129 next-level-cache = <&L2_0>; 130 L1_I_3: l1-icache { 131 compatible = "arm,arch-cache"; 132 }; 133 L1_D_3: l1-dcache { 134 compatible = "arm,arch-cache"; 135 }; 136 }; 137 138 CPU4: cpu@100 { 139 device_type = "cpu"; 140 compatible = "arm,armv8"; 141 reg = <0x0 0x100>; 142 enable-method = "psci"; 143 efficiency = <1536>; 144 next-level-cache = <&L2_1>; 145 L2_1: l2-cache { 146 compatible = "arm,arch-cache"; 147 cache-level = <2>; 148 }; 149 L1_I_100: l1-icache { 150 compatible = "arm,arch-cache"; 151 }; 152 L1_D_100: l1-dcache { 153 compatible = "arm,arch-cache"; 154 }; 155 }; 156 157 CPU5: cpu@101 { 158 device_type = "cpu"; 159 compatible = "arm,armv8"; 160 reg = <0x0 0x101>; 161 enable-method = "psci"; 162 efficiency = <1536>; 163 next-level-cache = <&L2_1>; 164 L1_I_101: l1-icache { 165 compatible = "arm,arch-cache"; 166 }; 167 L1_D_101: l1-dcache { 168 compatible = "arm,arch-cache"; 169 }; 170 }; 171 172 CPU6: cpu@102 { 173 device_type = "cpu"; 174 compatible = "arm,armv8"; 175 reg = <0x0 0x102>; 176 enable-method = "psci"; 177 efficiency = <1536>; 178 next-level-cache = <&L2_1>; 179 L1_I_102: l1-icache { 180 compatible = "arm,arch-cache"; 181 }; 182 L1_D_102: l1-dcache { 183 compatible = "arm,arch-cache"; 184 }; 185 }; 186 187 CPU7: cpu@103 { 188 device_type = "cpu"; 189 compatible = "arm,armv8"; 190 reg = <0x0 0x103>; 191 enable-method = "psci"; 192 efficiency = <1536>; 193 next-level-cache = <&L2_1>; 194 L1_I_103: l1-icache { 195 compatible = "arm,arch-cache"; 196 }; 197 L1_D_103: l1-dcache { 198 compatible = "arm,arch-cache"; 199 }; 200 }; 201 202 cpu-map { 203 cluster0 { 204 core0 { 205 cpu = <&CPU0>; 206 }; 207 208 core1 { 209 cpu = <&CPU1>; 210 }; 211 212 core2 { 213 cpu = <&CPU2>; 214 }; 215 216 core3 { 217 cpu = <&CPU3>; 218 }; 219 }; 220 221 cluster1 { 222 core0 { 223 cpu = <&CPU4>; 224 }; 225 226 core1 { 227 cpu = <&CPU5>; 228 }; 229 230 core2 { 231 cpu = <&CPU6>; 232 }; 233 234 core3 { 235 cpu = <&CPU7>; 236 }; 237 }; 238 }; 239 }; 240 241 firmware { 242 scm { 243 compatible = "qcom,scm-msm8998", "qcom,scm"; 244 }; 245 }; 246 247 tcsr_mutex: hwlock { 248 compatible = "qcom,tcsr-mutex"; 249 syscon = <&tcsr_mutex_regs 0 0x1000>; 250 #hwlock-cells = <1>; 251 }; 252 253 psci { 254 compatible = "arm,psci-1.0"; 255 method = "smc"; 256 }; 257 258 rpm-glink { 259 compatible = "qcom,glink-rpm"; 260 261 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 262 qcom,rpm-msg-ram = <&rpm_msg_ram>; 263 mboxes = <&apcs_glb 0>; 264 265 rpm_requests: rpm-requests { 266 compatible = "qcom,rpm-msm8998"; 267 qcom,glink-channels = "rpm_requests"; 268 }; 269 }; 270 271 smem { 272 compatible = "qcom,smem"; 273 memory-region = <&smem_mem>; 274 hwlocks = <&tcsr_mutex 3>; 275 }; 276 277 smp2p-lpass { 278 compatible = "qcom,smp2p"; 279 qcom,smem = <443>, <429>; 280 281 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 282 283 mboxes = <&apcs_glb 10>; 284 285 qcom,local-pid = <0>; 286 qcom,remote-pid = <2>; 287 288 adsp_smp2p_out: master-kernel { 289 qcom,entry-name = "master-kernel"; 290 #qcom,smem-state-cells = <1>; 291 }; 292 293 adsp_smp2p_in: slave-kernel { 294 qcom,entry-name = "slave-kernel"; 295 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 }; 299 }; 300 301 smp2p-mpss { 302 compatible = "qcom,smp2p"; 303 qcom,smem = <435>, <428>; 304 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 305 mboxes = <&apcs_glb 14>; 306 qcom,local-pid = <0>; 307 qcom,remote-pid = <1>; 308 309 modem_smp2p_out: master-kernel { 310 qcom,entry-name = "master-kernel"; 311 #qcom,smem-state-cells = <1>; 312 }; 313 314 modem_smp2p_in: slave-kernel { 315 qcom,entry-name = "slave-kernel"; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 }; 319 }; 320 321 smp2p-slpi { 322 compatible = "qcom,smp2p"; 323 qcom,smem = <481>, <430>; 324 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 325 mboxes = <&apcs_glb 26>; 326 qcom,local-pid = <0>; 327 qcom,remote-pid = <3>; 328 329 slpi_smp2p_out: master-kernel { 330 qcom,entry-name = "master-kernel"; 331 #qcom,smem-state-cells = <1>; 332 }; 333 334 slpi_smp2p_in: slave-kernel { 335 qcom,entry-name = "slave-kernel"; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 }; 339 }; 340 341 thermal-zones { 342 cpu-thermal0 { 343 polling-delay-passive = <250>; 344 polling-delay = <1000>; 345 346 thermal-sensors = <&tsens0 6>; 347 348 trips { 349 cpu_alert0: trip0 { 350 temperature = <75000>; 351 hysteresis = <2000>; 352 type = "passive"; 353 }; 354 355 cpu_crit0: trip1 { 356 temperature = <110000>; 357 hysteresis = <2000>; 358 type = "critical"; 359 }; 360 }; 361 }; 362 363 cpu-thermal1 { 364 polling-delay-passive = <250>; 365 polling-delay = <1000>; 366 367 thermal-sensors = <&tsens0 7>; 368 369 trips { 370 cpu_alert1: trip0 { 371 temperature = <75000>; 372 hysteresis = <2000>; 373 type = "passive"; 374 }; 375 376 cpu_crit1: trip1 { 377 temperature = <110000>; 378 hysteresis = <2000>; 379 type = "critical"; 380 }; 381 }; 382 }; 383 384 cpu-thermal2 { 385 polling-delay-passive = <250>; 386 polling-delay = <1000>; 387 388 thermal-sensors = <&tsens0 8>; 389 390 trips { 391 cpu_alert2: trip0 { 392 temperature = <75000>; 393 hysteresis = <2000>; 394 type = "passive"; 395 }; 396 397 cpu_crit2: trip1 { 398 temperature = <110000>; 399 hysteresis = <2000>; 400 type = "critical"; 401 }; 402 }; 403 }; 404 405 cpu-thermal3 { 406 polling-delay-passive = <250>; 407 polling-delay = <1000>; 408 409 thermal-sensors = <&tsens0 9>; 410 411 trips { 412 cpu_alert3: trip0 { 413 temperature = <75000>; 414 hysteresis = <2000>; 415 type = "passive"; 416 }; 417 418 cpu_crit3: trip1 { 419 temperature = <110000>; 420 hysteresis = <2000>; 421 type = "critical"; 422 }; 423 }; 424 }; 425 426 cpu-thermal4 { 427 polling-delay-passive = <250>; 428 polling-delay = <1000>; 429 430 thermal-sensors = <&tsens0 10>; 431 432 trips { 433 cpu_alert4: trip0 { 434 temperature = <75000>; 435 hysteresis = <2000>; 436 type = "passive"; 437 }; 438 439 cpu_crit4: trip1 { 440 temperature = <110000>; 441 hysteresis = <2000>; 442 type = "critical"; 443 }; 444 }; 445 }; 446 447 cpu-thermal5 { 448 polling-delay-passive = <250>; 449 polling-delay = <1000>; 450 451 thermal-sensors = <&tsens0 11>; 452 453 trips { 454 cpu_alert5: trip0 { 455 temperature = <75000>; 456 hysteresis = <2000>; 457 type = "passive"; 458 }; 459 460 cpu_crit5: trip1 { 461 temperature = <110000>; 462 hysteresis = <2000>; 463 type = "critical"; 464 }; 465 }; 466 }; 467 468 cpu-thermal6 { 469 polling-delay-passive = <250>; 470 polling-delay = <1000>; 471 472 thermal-sensors = <&tsens1 0>; 473 474 trips { 475 cpu_alert6: trip0 { 476 temperature = <75000>; 477 hysteresis = <2000>; 478 type = "passive"; 479 }; 480 481 cpu_crit6: trip1 { 482 temperature = <110000>; 483 hysteresis = <2000>; 484 type = "critical"; 485 }; 486 }; 487 }; 488 489 cpu-thermal7 { 490 polling-delay-passive = <250>; 491 polling-delay = <1000>; 492 493 thermal-sensors = <&tsens1 1>; 494 495 trips { 496 cpu_alert7: trip0 { 497 temperature = <75000>; 498 hysteresis = <2000>; 499 type = "passive"; 500 }; 501 502 cpu_crit7: trip1 { 503 temperature = <110000>; 504 hysteresis = <2000>; 505 type = "critical"; 506 }; 507 }; 508 }; 509 510 gpu-thermal { 511 polling-delay-passive = <250>; 512 polling-delay = <1000>; 513 514 thermal-sensors = <&tsens1 3>; 515 }; 516 }; 517 518 timer { 519 compatible = "arm,armv8-timer"; 520 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 521 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 522 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 523 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 524 }; 525 526 soc: soc { 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges = <0 0 0 0xffffffff>; 530 compatible = "simple-bus"; 531 532 rpm_msg_ram: memory@68000 { 533 compatible = "qcom,rpm-msg-ram"; 534 reg = <0x778000 0x7000>; 535 }; 536 537 qfprom: qfprom@780000 { 538 compatible = "qcom,qfprom"; 539 reg = <0x780000 0x621c>; 540 #address-cells = <1>; 541 #size-cells = <1>; 542 }; 543 544 gcc: clock-controller@100000 { 545 compatible = "qcom,gcc-msm8998"; 546 #clock-cells = <1>; 547 #reset-cells = <1>; 548 #power-domain-cells = <1>; 549 reg = <0x100000 0xb0000>; 550 }; 551 552 tlmm: pinctrl@3400000 { 553 compatible = "qcom,msm8998-pinctrl"; 554 reg = <0x3400000 0xc00000>; 555 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 556 gpio-controller; 557 #gpio-cells = <0x2>; 558 interrupt-controller; 559 #interrupt-cells = <0x2>; 560 }; 561 562 spmi_bus: spmi@800f000 { 563 compatible = "qcom,spmi-pmic-arb"; 564 reg = <0x800f000 0x1000>, 565 <0x8400000 0x1000000>, 566 <0x9400000 0x1000000>, 567 <0xa400000 0x220000>, 568 <0x800a000 0x3000>; 569 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 570 interrupt-names = "periph_irq"; 571 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 572 qcom,ee = <0>; 573 qcom,channel = <0>; 574 #address-cells = <2>; 575 #size-cells = <0>; 576 interrupt-controller; 577 #interrupt-cells = <4>; 578 cell-index = <0>; 579 }; 580 581 tsens0: thermal@10aa000 { 582 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 583 reg = <0x10aa000 0x2000>; 584 585 #qcom,sensors = <12>; 586 #thermal-sensor-cells = <1>; 587 }; 588 589 tsens1: thermal@10ad000 { 590 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 591 reg = <0x10ad000 0x2000>; 592 593 #qcom,sensors = <8>; 594 #thermal-sensor-cells = <1>; 595 }; 596 597 tcsr_mutex_regs: syscon@1f40000 { 598 compatible = "syscon"; 599 reg = <0x1f40000 0x20000>; 600 }; 601 602 apcs_glb: mailbox@9820000 { 603 compatible = "qcom,msm8998-apcs-hmss-global"; 604 reg = <0x17911000 0x1000>; 605 606 #mbox-cells = <1>; 607 }; 608 609 sdhc2: sdhci@c0a4900 { 610 compatible = "qcom,sdhci-msm-v4"; 611 reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; 612 reg-names = "hc_mem", "core_mem"; 613 614 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 616 interrupt-names = "hc_irq", "pwr_irq"; 617 618 clock-names = "iface", "core", "xo"; 619 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 620 <&gcc GCC_SDCC2_APPS_CLK>, 621 <&xo>; 622 bus-width = <4>; 623 status = "disabled"; 624 }; 625 626 blsp2_uart1: serial@c1b0000 { 627 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 628 reg = <0xc1b0000 0x1000>; 629 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 631 <&gcc GCC_BLSP2_AHB_CLK>; 632 clock-names = "core", "iface"; 633 status = "disabled"; 634 }; 635 636 timer@17920000 { 637 #address-cells = <1>; 638 #size-cells = <1>; 639 ranges; 640 compatible = "arm,armv7-timer-mem"; 641 reg = <0x17920000 0x1000>; 642 643 frame@17921000 { 644 frame-number = <0>; 645 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 647 reg = <0x17921000 0x1000>, 648 <0x17922000 0x1000>; 649 }; 650 651 frame@17923000 { 652 frame-number = <1>; 653 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 654 reg = <0x17923000 0x1000>; 655 status = "disabled"; 656 }; 657 658 frame@17924000 { 659 frame-number = <2>; 660 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 661 reg = <0x17924000 0x1000>; 662 status = "disabled"; 663 }; 664 665 frame@17925000 { 666 frame-number = <3>; 667 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 668 reg = <0x17925000 0x1000>; 669 status = "disabled"; 670 }; 671 672 frame@17926000 { 673 frame-number = <4>; 674 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 675 reg = <0x17926000 0x1000>; 676 status = "disabled"; 677 }; 678 679 frame@17927000 { 680 frame-number = <5>; 681 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 682 reg = <0x17927000 0x1000>; 683 status = "disabled"; 684 }; 685 686 frame@17928000 { 687 frame-number = <6>; 688 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 689 reg = <0x17928000 0x1000>; 690 status = "disabled"; 691 }; 692 }; 693 694 intc: interrupt-controller@17a00000 { 695 compatible = "arm,gic-v3"; 696 reg = <0x17a00000 0x10000>, /* GICD */ 697 <0x17b00000 0x100000>; /* GICR * 8 */ 698 #interrupt-cells = <3>; 699 #address-cells = <1>; 700 #size-cells = <1>; 701 ranges; 702 interrupt-controller; 703 #redistributor-regions = <1>; 704 redistributor-stride = <0x0 0x20000>; 705 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 706 }; 707 }; 708}; 709 710#include "msm8998-pins.dtsi" 711