1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 qcom,msm-id = <292 0x0>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 memory@80000000 { 23 device_type = "memory"; 24 /* We expect the bootloader to fill in the reg */ 25 reg = <0x0 0x80000000 0x0 0x0>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 hyp_mem: memory@85800000 { 34 reg = <0x0 0x85800000 0x0 0x600000>; 35 no-map; 36 }; 37 38 xbl_mem: memory@85e00000 { 39 reg = <0x0 0x85e00000 0x0 0x100000>; 40 no-map; 41 }; 42 43 smem_mem: smem-mem@86000000 { 44 reg = <0x0 0x86000000 0x0 0x200000>; 45 no-map; 46 }; 47 48 tz_mem: memory@86200000 { 49 reg = <0x0 0x86200000 0x0 0x2d00000>; 50 no-map; 51 }; 52 53 rmtfs_mem: memory@88f00000 { 54 compatible = "qcom,rmtfs-mem"; 55 reg = <0x0 0x88f00000 0x0 0x200000>; 56 no-map; 57 58 qcom,client-id = <1>; 59 qcom,vmid = <15>; 60 }; 61 62 spss_mem: memory@8ab00000 { 63 reg = <0x0 0x8ab00000 0x0 0x700000>; 64 no-map; 65 }; 66 67 adsp_mem: memory@8b200000 { 68 reg = <0x0 0x8b200000 0x0 0x1a00000>; 69 no-map; 70 }; 71 72 mpss_mem: memory@8cc00000 { 73 reg = <0x0 0x8cc00000 0x0 0x7000000>; 74 no-map; 75 }; 76 77 venus_mem: memory@93c00000 { 78 reg = <0x0 0x93c00000 0x0 0x500000>; 79 no-map; 80 }; 81 82 mba_mem: memory@94100000 { 83 reg = <0x0 0x94100000 0x0 0x200000>; 84 no-map; 85 }; 86 87 slpi_mem: memory@94300000 { 88 reg = <0x0 0x94300000 0x0 0xf00000>; 89 no-map; 90 }; 91 92 ipa_fw_mem: memory@95200000 { 93 reg = <0x0 0x95200000 0x0 0x10000>; 94 no-map; 95 }; 96 97 ipa_gsi_mem: memory@95210000 { 98 reg = <0x0 0x95210000 0x0 0x5000>; 99 no-map; 100 }; 101 102 gpu_mem: memory@95600000 { 103 reg = <0x0 0x95600000 0x0 0x100000>; 104 no-map; 105 }; 106 107 wlan_msa_mem: memory@95700000 { 108 reg = <0x0 0x95700000 0x0 0x100000>; 109 no-map; 110 }; 111 112 mdata_mem: mpss-metadata { 113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 114 size = <0x0 0x4000>; 115 no-map; 116 }; 117 }; 118 119 clocks { 120 xo: xo-board { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <19200000>; 124 clock-output-names = "xo_board"; 125 }; 126 127 sleep_clk: sleep-clk { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <32764>; 131 }; 132 }; 133 134 cpus { 135 #address-cells = <2>; 136 #size-cells = <0>; 137 138 CPU0: cpu@0 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo280"; 141 reg = <0x0 0x0>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 145 next-level-cache = <&L2_0>; 146 L2_0: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 }; 150 }; 151 152 CPU1: cpu@1 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo280"; 155 reg = <0x0 0x1>; 156 enable-method = "psci"; 157 capacity-dmips-mhz = <1024>; 158 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 159 next-level-cache = <&L2_0>; 160 }; 161 162 CPU2: cpu@2 { 163 device_type = "cpu"; 164 compatible = "qcom,kryo280"; 165 reg = <0x0 0x2>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <1024>; 168 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 169 next-level-cache = <&L2_0>; 170 }; 171 172 CPU3: cpu@3 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo280"; 175 reg = <0x0 0x3>; 176 enable-method = "psci"; 177 capacity-dmips-mhz = <1024>; 178 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 179 next-level-cache = <&L2_0>; 180 }; 181 182 CPU4: cpu@100 { 183 device_type = "cpu"; 184 compatible = "qcom,kryo280"; 185 reg = <0x0 0x100>; 186 enable-method = "psci"; 187 capacity-dmips-mhz = <1536>; 188 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 189 next-level-cache = <&L2_1>; 190 L2_1: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 }; 194 }; 195 196 CPU5: cpu@101 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo280"; 199 reg = <0x0 0x101>; 200 enable-method = "psci"; 201 capacity-dmips-mhz = <1536>; 202 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 203 next-level-cache = <&L2_1>; 204 }; 205 206 CPU6: cpu@102 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo280"; 209 reg = <0x0 0x102>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1536>; 212 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 213 next-level-cache = <&L2_1>; 214 }; 215 216 CPU7: cpu@103 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo280"; 219 reg = <0x0 0x103>; 220 enable-method = "psci"; 221 capacity-dmips-mhz = <1536>; 222 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 223 next-level-cache = <&L2_1>; 224 }; 225 226 cpu-map { 227 cluster0 { 228 core0 { 229 cpu = <&CPU0>; 230 }; 231 232 core1 { 233 cpu = <&CPU1>; 234 }; 235 236 core2 { 237 cpu = <&CPU2>; 238 }; 239 240 core3 { 241 cpu = <&CPU3>; 242 }; 243 }; 244 245 cluster1 { 246 core0 { 247 cpu = <&CPU4>; 248 }; 249 250 core1 { 251 cpu = <&CPU5>; 252 }; 253 254 core2 { 255 cpu = <&CPU6>; 256 }; 257 258 core3 { 259 cpu = <&CPU7>; 260 }; 261 }; 262 }; 263 264 idle-states { 265 entry-method = "psci"; 266 267 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "little-retention"; 270 /* CPU Retention (C2D), L2 Active */ 271 arm,psci-suspend-param = <0x00000002>; 272 entry-latency-us = <81>; 273 exit-latency-us = <86>; 274 min-residency-us = <504>; 275 }; 276 277 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "little-power-collapse"; 280 /* CPU + L2 Power Collapse (C3, D4) */ 281 arm,psci-suspend-param = <0x40000003>; 282 entry-latency-us = <814>; 283 exit-latency-us = <4562>; 284 min-residency-us = <9183>; 285 local-timer-stop; 286 }; 287 288 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 289 compatible = "arm,idle-state"; 290 idle-state-name = "big-retention"; 291 /* CPU Retention (C2D), L2 Active */ 292 arm,psci-suspend-param = <0x00000002>; 293 entry-latency-us = <79>; 294 exit-latency-us = <82>; 295 min-residency-us = <1302>; 296 }; 297 298 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 299 compatible = "arm,idle-state"; 300 idle-state-name = "big-power-collapse"; 301 /* CPU + L2 Power Collapse (C3, D4) */ 302 arm,psci-suspend-param = <0x40000003>; 303 entry-latency-us = <724>; 304 exit-latency-us = <2027>; 305 min-residency-us = <9419>; 306 local-timer-stop; 307 }; 308 }; 309 }; 310 311 firmware { 312 scm { 313 compatible = "qcom,scm-msm8998", "qcom,scm"; 314 }; 315 }; 316 317 psci { 318 compatible = "arm,psci-1.0"; 319 method = "smc"; 320 }; 321 322 rpm-glink { 323 compatible = "qcom,glink-rpm"; 324 325 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 326 qcom,rpm-msg-ram = <&rpm_msg_ram>; 327 mboxes = <&apcs_glb 0>; 328 329 rpm_requests: rpm-requests { 330 compatible = "qcom,rpm-msm8998"; 331 qcom,glink-channels = "rpm_requests"; 332 333 rpmcc: clock-controller { 334 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 335 #clock-cells = <1>; 336 }; 337 338 rpmpd: power-controller { 339 compatible = "qcom,msm8998-rpmpd"; 340 #power-domain-cells = <1>; 341 operating-points-v2 = <&rpmpd_opp_table>; 342 343 rpmpd_opp_table: opp-table { 344 compatible = "operating-points-v2"; 345 346 rpmpd_opp_ret: opp1 { 347 opp-level = <RPM_SMD_LEVEL_RETENTION>; 348 }; 349 350 rpmpd_opp_ret_plus: opp2 { 351 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 352 }; 353 354 rpmpd_opp_min_svs: opp3 { 355 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 356 }; 357 358 rpmpd_opp_low_svs: opp4 { 359 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 360 }; 361 362 rpmpd_opp_svs: opp5 { 363 opp-level = <RPM_SMD_LEVEL_SVS>; 364 }; 365 366 rpmpd_opp_svs_plus: opp6 { 367 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 368 }; 369 370 rpmpd_opp_nom: opp7 { 371 opp-level = <RPM_SMD_LEVEL_NOM>; 372 }; 373 374 rpmpd_opp_nom_plus: opp8 { 375 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 376 }; 377 378 rpmpd_opp_turbo: opp9 { 379 opp-level = <RPM_SMD_LEVEL_TURBO>; 380 }; 381 382 rpmpd_opp_turbo_plus: opp10 { 383 opp-level = <RPM_SMD_LEVEL_BINNING>; 384 }; 385 }; 386 }; 387 }; 388 }; 389 390 smem { 391 compatible = "qcom,smem"; 392 memory-region = <&smem_mem>; 393 hwlocks = <&tcsr_mutex 3>; 394 }; 395 396 smp2p-lpass { 397 compatible = "qcom,smp2p"; 398 qcom,smem = <443>, <429>; 399 400 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 401 402 mboxes = <&apcs_glb 10>; 403 404 qcom,local-pid = <0>; 405 qcom,remote-pid = <2>; 406 407 adsp_smp2p_out: master-kernel { 408 qcom,entry-name = "master-kernel"; 409 #qcom,smem-state-cells = <1>; 410 }; 411 412 adsp_smp2p_in: slave-kernel { 413 qcom,entry-name = "slave-kernel"; 414 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 smp2p-mpss { 421 compatible = "qcom,smp2p"; 422 qcom,smem = <435>, <428>; 423 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 424 mboxes = <&apcs_glb 14>; 425 qcom,local-pid = <0>; 426 qcom,remote-pid = <1>; 427 428 modem_smp2p_out: master-kernel { 429 qcom,entry-name = "master-kernel"; 430 #qcom,smem-state-cells = <1>; 431 }; 432 433 modem_smp2p_in: slave-kernel { 434 qcom,entry-name = "slave-kernel"; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 }; 438 }; 439 440 smp2p-slpi { 441 compatible = "qcom,smp2p"; 442 qcom,smem = <481>, <430>; 443 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 444 mboxes = <&apcs_glb 26>; 445 qcom,local-pid = <0>; 446 qcom,remote-pid = <3>; 447 448 slpi_smp2p_out: master-kernel { 449 qcom,entry-name = "master-kernel"; 450 #qcom,smem-state-cells = <1>; 451 }; 452 453 slpi_smp2p_in: slave-kernel { 454 qcom,entry-name = "slave-kernel"; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 }; 458 }; 459 460 thermal-zones { 461 cpu0-thermal { 462 polling-delay-passive = <250>; 463 polling-delay = <1000>; 464 465 thermal-sensors = <&tsens0 1>; 466 467 trips { 468 cpu0_alert0: trip-point0 { 469 temperature = <75000>; 470 hysteresis = <2000>; 471 type = "passive"; 472 }; 473 474 cpu0_crit: cpu-crit { 475 temperature = <110000>; 476 hysteresis = <2000>; 477 type = "critical"; 478 }; 479 }; 480 }; 481 482 cpu1-thermal { 483 polling-delay-passive = <250>; 484 polling-delay = <1000>; 485 486 thermal-sensors = <&tsens0 2>; 487 488 trips { 489 cpu1_alert0: trip-point0 { 490 temperature = <75000>; 491 hysteresis = <2000>; 492 type = "passive"; 493 }; 494 495 cpu1_crit: cpu-crit { 496 temperature = <110000>; 497 hysteresis = <2000>; 498 type = "critical"; 499 }; 500 }; 501 }; 502 503 cpu2-thermal { 504 polling-delay-passive = <250>; 505 polling-delay = <1000>; 506 507 thermal-sensors = <&tsens0 3>; 508 509 trips { 510 cpu2_alert0: trip-point0 { 511 temperature = <75000>; 512 hysteresis = <2000>; 513 type = "passive"; 514 }; 515 516 cpu2_crit: cpu-crit { 517 temperature = <110000>; 518 hysteresis = <2000>; 519 type = "critical"; 520 }; 521 }; 522 }; 523 524 cpu3-thermal { 525 polling-delay-passive = <250>; 526 polling-delay = <1000>; 527 528 thermal-sensors = <&tsens0 4>; 529 530 trips { 531 cpu3_alert0: trip-point0 { 532 temperature = <75000>; 533 hysteresis = <2000>; 534 type = "passive"; 535 }; 536 537 cpu3_crit: cpu-crit { 538 temperature = <110000>; 539 hysteresis = <2000>; 540 type = "critical"; 541 }; 542 }; 543 }; 544 545 cpu4-thermal { 546 polling-delay-passive = <250>; 547 polling-delay = <1000>; 548 549 thermal-sensors = <&tsens0 7>; 550 551 trips { 552 cpu4_alert0: trip-point0 { 553 temperature = <75000>; 554 hysteresis = <2000>; 555 type = "passive"; 556 }; 557 558 cpu4_crit: cpu-crit { 559 temperature = <110000>; 560 hysteresis = <2000>; 561 type = "critical"; 562 }; 563 }; 564 }; 565 566 cpu5-thermal { 567 polling-delay-passive = <250>; 568 polling-delay = <1000>; 569 570 thermal-sensors = <&tsens0 8>; 571 572 trips { 573 cpu5_alert0: trip-point0 { 574 temperature = <75000>; 575 hysteresis = <2000>; 576 type = "passive"; 577 }; 578 579 cpu5_crit: cpu-crit { 580 temperature = <110000>; 581 hysteresis = <2000>; 582 type = "critical"; 583 }; 584 }; 585 }; 586 587 cpu6-thermal { 588 polling-delay-passive = <250>; 589 polling-delay = <1000>; 590 591 thermal-sensors = <&tsens0 9>; 592 593 trips { 594 cpu6_alert0: trip-point0 { 595 temperature = <75000>; 596 hysteresis = <2000>; 597 type = "passive"; 598 }; 599 600 cpu6_crit: cpu-crit { 601 temperature = <110000>; 602 hysteresis = <2000>; 603 type = "critical"; 604 }; 605 }; 606 }; 607 608 cpu7-thermal { 609 polling-delay-passive = <250>; 610 polling-delay = <1000>; 611 612 thermal-sensors = <&tsens0 10>; 613 614 trips { 615 cpu7_alert0: trip-point0 { 616 temperature = <75000>; 617 hysteresis = <2000>; 618 type = "passive"; 619 }; 620 621 cpu7_crit: cpu-crit { 622 temperature = <110000>; 623 hysteresis = <2000>; 624 type = "critical"; 625 }; 626 }; 627 }; 628 629 gpu-bottom-thermal { 630 polling-delay-passive = <250>; 631 polling-delay = <1000>; 632 633 thermal-sensors = <&tsens0 12>; 634 635 trips { 636 gpu1_alert0: trip-point0 { 637 temperature = <90000>; 638 hysteresis = <2000>; 639 type = "hot"; 640 }; 641 }; 642 }; 643 644 gpu-top-thermal { 645 polling-delay-passive = <250>; 646 polling-delay = <1000>; 647 648 thermal-sensors = <&tsens0 13>; 649 650 trips { 651 gpu2_alert0: trip-point0 { 652 temperature = <90000>; 653 hysteresis = <2000>; 654 type = "hot"; 655 }; 656 }; 657 }; 658 659 clust0-mhm-thermal { 660 polling-delay-passive = <250>; 661 polling-delay = <1000>; 662 663 thermal-sensors = <&tsens0 5>; 664 665 trips { 666 cluster0_mhm_alert0: trip-point0 { 667 temperature = <90000>; 668 hysteresis = <2000>; 669 type = "hot"; 670 }; 671 }; 672 }; 673 674 clust1-mhm-thermal { 675 polling-delay-passive = <250>; 676 polling-delay = <1000>; 677 678 thermal-sensors = <&tsens0 6>; 679 680 trips { 681 cluster1_mhm_alert0: trip-point0 { 682 temperature = <90000>; 683 hysteresis = <2000>; 684 type = "hot"; 685 }; 686 }; 687 }; 688 689 cluster1-l2-thermal { 690 polling-delay-passive = <250>; 691 polling-delay = <1000>; 692 693 thermal-sensors = <&tsens0 11>; 694 695 trips { 696 cluster1_l2_alert0: trip-point0 { 697 temperature = <90000>; 698 hysteresis = <2000>; 699 type = "hot"; 700 }; 701 }; 702 }; 703 704 modem-thermal { 705 polling-delay-passive = <250>; 706 polling-delay = <1000>; 707 708 thermal-sensors = <&tsens1 1>; 709 710 trips { 711 modem_alert0: trip-point0 { 712 temperature = <90000>; 713 hysteresis = <2000>; 714 type = "hot"; 715 }; 716 }; 717 }; 718 719 mem-thermal { 720 polling-delay-passive = <250>; 721 polling-delay = <1000>; 722 723 thermal-sensors = <&tsens1 2>; 724 725 trips { 726 mem_alert0: trip-point0 { 727 temperature = <90000>; 728 hysteresis = <2000>; 729 type = "hot"; 730 }; 731 }; 732 }; 733 734 wlan-thermal { 735 polling-delay-passive = <250>; 736 polling-delay = <1000>; 737 738 thermal-sensors = <&tsens1 3>; 739 740 trips { 741 wlan_alert0: trip-point0 { 742 temperature = <90000>; 743 hysteresis = <2000>; 744 type = "hot"; 745 }; 746 }; 747 }; 748 749 q6-dsp-thermal { 750 polling-delay-passive = <250>; 751 polling-delay = <1000>; 752 753 thermal-sensors = <&tsens1 4>; 754 755 trips { 756 q6_dsp_alert0: trip-point0 { 757 temperature = <90000>; 758 hysteresis = <2000>; 759 type = "hot"; 760 }; 761 }; 762 }; 763 764 camera-thermal { 765 polling-delay-passive = <250>; 766 polling-delay = <1000>; 767 768 thermal-sensors = <&tsens1 5>; 769 770 trips { 771 camera_alert0: trip-point0 { 772 temperature = <90000>; 773 hysteresis = <2000>; 774 type = "hot"; 775 }; 776 }; 777 }; 778 779 multimedia-thermal { 780 polling-delay-passive = <250>; 781 polling-delay = <1000>; 782 783 thermal-sensors = <&tsens1 6>; 784 785 trips { 786 multimedia_alert0: trip-point0 { 787 temperature = <90000>; 788 hysteresis = <2000>; 789 type = "hot"; 790 }; 791 }; 792 }; 793 }; 794 795 timer { 796 compatible = "arm,armv8-timer"; 797 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 798 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 799 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 800 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 801 }; 802 803 soc: soc@0 { 804 #address-cells = <1>; 805 #size-cells = <1>; 806 ranges = <0 0 0 0xffffffff>; 807 compatible = "simple-bus"; 808 809 gcc: clock-controller@100000 { 810 compatible = "qcom,gcc-msm8998"; 811 #clock-cells = <1>; 812 #reset-cells = <1>; 813 #power-domain-cells = <1>; 814 reg = <0x00100000 0xb0000>; 815 816 clock-names = "xo", "sleep_clk"; 817 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 818 819 /* 820 * The hypervisor typically configures the memory region where these clocks 821 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 822 * these clocks on a device with such configuration (e.g. because they are 823 * enabled but unused during boot-up), the device will most likely decide 824 * to reboot. 825 * In light of that, we are conservative here and we list all such clocks 826 * as protected. The board dts (or a user-supplied dts) can override the 827 * list of protected clocks if it differs from the norm, and it is in fact 828 * desired for the HLOS to manage these clocks 829 */ 830 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 831 <SSC_XO>, 832 <SSC_CNOC_AHBS_CLK>; 833 }; 834 835 rpm_msg_ram: sram@778000 { 836 compatible = "qcom,rpm-msg-ram"; 837 reg = <0x00778000 0x7000>; 838 }; 839 840 qfprom: qfprom@784000 { 841 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 842 reg = <0x00784000 0x621c>; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 846 qusb2_hstx_trim: hstx-trim@23a { 847 reg = <0x23a 0x1>; 848 bits = <0 4>; 849 }; 850 }; 851 852 tsens0: thermal@10ab000 { 853 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 854 reg = <0x010ab000 0x1000>, /* TM */ 855 <0x010aa000 0x1000>; /* SROT */ 856 #qcom,sensors = <14>; 857 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-names = "uplow", "critical"; 860 #thermal-sensor-cells = <1>; 861 }; 862 863 tsens1: thermal@10ae000 { 864 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 865 reg = <0x010ae000 0x1000>, /* TM */ 866 <0x010ad000 0x1000>; /* SROT */ 867 #qcom,sensors = <8>; 868 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "uplow", "critical"; 871 #thermal-sensor-cells = <1>; 872 }; 873 874 anoc1_smmu: iommu@1680000 { 875 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 876 reg = <0x01680000 0x10000>; 877 #iommu-cells = <1>; 878 879 #global-interrupts = <0>; 880 interrupts = 881 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 882 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 883 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 884 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 885 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 886 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 887 }; 888 889 anoc2_smmu: iommu@16c0000 { 890 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 891 reg = <0x016c0000 0x40000>; 892 #iommu-cells = <1>; 893 894 #global-interrupts = <0>; 895 interrupts = 896 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 897 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 898 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 899 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 900 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 902 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 903 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 904 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 905 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 906 }; 907 908 pcie0: pci@1c00000 { 909 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 910 reg = <0x01c00000 0x2000>, 911 <0x1b000000 0xf1d>, 912 <0x1b000f20 0xa8>, 913 <0x1b100000 0x100000>; 914 reg-names = "parf", "dbi", "elbi", "config"; 915 device_type = "pci"; 916 linux,pci-domain = <0>; 917 bus-range = <0x00 0xff>; 918 #address-cells = <3>; 919 #size-cells = <2>; 920 num-lanes = <1>; 921 phys = <&pciephy>; 922 phy-names = "pciephy"; 923 status = "disabled"; 924 925 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 926 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 927 928 #interrupt-cells = <1>; 929 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 930 interrupt-names = "msi"; 931 interrupt-map-mask = <0 0 0 0x7>; 932 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 933 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 934 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 935 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 936 937 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 938 <&gcc GCC_PCIE_0_AUX_CLK>, 939 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 940 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 941 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 942 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 943 944 power-domains = <&gcc PCIE_0_GDSC>; 945 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 946 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 947 }; 948 949 pcie_phy: phy@1c06000 { 950 compatible = "qcom,msm8998-qmp-pcie-phy"; 951 reg = <0x01c06000 0x18c>; 952 #address-cells = <1>; 953 #size-cells = <1>; 954 status = "disabled"; 955 ranges; 956 957 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 958 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 959 <&gcc GCC_PCIE_CLKREF_CLK>; 960 clock-names = "aux", "cfg_ahb", "ref"; 961 962 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 963 reset-names = "phy", "common"; 964 965 vdda-phy-supply = <&vreg_l1a_0p875>; 966 vdda-pll-supply = <&vreg_l2a_1p2>; 967 968 pciephy: phy@1c06800 { 969 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 970 #phy-cells = <0>; 971 972 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 973 clock-names = "pipe0"; 974 clock-output-names = "pcie_0_pipe_clk_src"; 975 #clock-cells = <0>; 976 }; 977 }; 978 979 ufshc: ufshc@1da4000 { 980 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 981 reg = <0x01da4000 0x2500>; 982 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 983 phys = <&ufsphy_lanes>; 984 phy-names = "ufsphy"; 985 lanes-per-direction = <2>; 986 power-domains = <&gcc UFS_GDSC>; 987 status = "disabled"; 988 #reset-cells = <1>; 989 990 clock-names = 991 "core_clk", 992 "bus_aggr_clk", 993 "iface_clk", 994 "core_clk_unipro", 995 "ref_clk", 996 "tx_lane0_sync_clk", 997 "rx_lane0_sync_clk", 998 "rx_lane1_sync_clk"; 999 clocks = 1000 <&gcc GCC_UFS_AXI_CLK>, 1001 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1002 <&gcc GCC_UFS_AHB_CLK>, 1003 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1004 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1005 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1006 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1007 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1008 freq-table-hz = 1009 <50000000 200000000>, 1010 <0 0>, 1011 <0 0>, 1012 <37500000 150000000>, 1013 <0 0>, 1014 <0 0>, 1015 <0 0>, 1016 <0 0>; 1017 1018 resets = <&gcc GCC_UFS_BCR>; 1019 reset-names = "rst"; 1020 }; 1021 1022 ufsphy: phy@1da7000 { 1023 compatible = "qcom,msm8998-qmp-ufs-phy"; 1024 reg = <0x01da7000 0x18c>; 1025 #address-cells = <1>; 1026 #size-cells = <1>; 1027 status = "disabled"; 1028 ranges; 1029 1030 clock-names = 1031 "ref", 1032 "ref_aux"; 1033 clocks = 1034 <&gcc GCC_UFS_CLKREF_CLK>, 1035 <&gcc GCC_UFS_PHY_AUX_CLK>; 1036 1037 reset-names = "ufsphy"; 1038 resets = <&ufshc 0>; 1039 1040 ufsphy_lanes: phy@1da7400 { 1041 reg = <0x01da7400 0x128>, 1042 <0x01da7600 0x1fc>, 1043 <0x01da7c00 0x1dc>, 1044 <0x01da7800 0x128>, 1045 <0x01da7a00 0x1fc>; 1046 #phy-cells = <0>; 1047 }; 1048 }; 1049 1050 tcsr_mutex: hwlock@1f40000 { 1051 compatible = "qcom,tcsr-mutex"; 1052 reg = <0x01f40000 0x20000>; 1053 #hwlock-cells = <1>; 1054 }; 1055 1056 tcsr_regs_1: syscon@1f60000 { 1057 compatible = "qcom,msm8998-tcsr", "syscon"; 1058 reg = <0x01f60000 0x20000>; 1059 }; 1060 1061 tlmm: pinctrl@3400000 { 1062 compatible = "qcom,msm8998-pinctrl"; 1063 reg = <0x03400000 0xc00000>; 1064 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1065 gpio-ranges = <&tlmm 0 0 150>; 1066 gpio-controller; 1067 #gpio-cells = <2>; 1068 interrupt-controller; 1069 #interrupt-cells = <2>; 1070 1071 sdc2_on: sdc2-on-state { 1072 clk-pins { 1073 pins = "sdc2_clk"; 1074 drive-strength = <16>; 1075 bias-disable; 1076 }; 1077 1078 cmd-pins { 1079 pins = "sdc2_cmd"; 1080 drive-strength = <10>; 1081 bias-pull-up; 1082 }; 1083 1084 data-pins { 1085 pins = "sdc2_data"; 1086 drive-strength = <10>; 1087 bias-pull-up; 1088 }; 1089 }; 1090 1091 sdc2_off: sdc2-off-state { 1092 clk-pins { 1093 pins = "sdc2_clk"; 1094 drive-strength = <2>; 1095 bias-disable; 1096 }; 1097 1098 cmd-pins { 1099 pins = "sdc2_cmd"; 1100 drive-strength = <2>; 1101 bias-pull-up; 1102 }; 1103 1104 data-pins { 1105 pins = "sdc2_data"; 1106 drive-strength = <2>; 1107 bias-pull-up; 1108 }; 1109 }; 1110 1111 sdc2_cd: sdc2-cd-state { 1112 pins = "gpio95"; 1113 function = "gpio"; 1114 bias-pull-up; 1115 drive-strength = <2>; 1116 }; 1117 1118 blsp1_uart3_on: blsp1-uart3-on-state { 1119 tx-pins { 1120 pins = "gpio45"; 1121 function = "blsp_uart3_a"; 1122 drive-strength = <2>; 1123 bias-disable; 1124 }; 1125 1126 rx-pins { 1127 pins = "gpio46"; 1128 function = "blsp_uart3_a"; 1129 drive-strength = <2>; 1130 bias-disable; 1131 }; 1132 1133 cts-pins { 1134 pins = "gpio47"; 1135 function = "blsp_uart3_a"; 1136 drive-strength = <2>; 1137 bias-disable; 1138 }; 1139 1140 rfr-pins { 1141 pins = "gpio48"; 1142 function = "blsp_uart3_a"; 1143 drive-strength = <2>; 1144 bias-disable; 1145 }; 1146 }; 1147 1148 blsp1_i2c1_default: blsp1-i2c1-default-state { 1149 pins = "gpio2", "gpio3"; 1150 function = "blsp_i2c1"; 1151 drive-strength = <2>; 1152 bias-disable; 1153 }; 1154 1155 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1156 pins = "gpio2", "gpio3"; 1157 function = "blsp_i2c1"; 1158 drive-strength = <2>; 1159 bias-pull-up; 1160 }; 1161 1162 blsp1_i2c2_default: blsp1-i2c2-default-state { 1163 pins = "gpio32", "gpio33"; 1164 function = "blsp_i2c2"; 1165 drive-strength = <2>; 1166 bias-disable; 1167 }; 1168 1169 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1170 pins = "gpio32", "gpio33"; 1171 function = "blsp_i2c2"; 1172 drive-strength = <2>; 1173 bias-pull-up; 1174 }; 1175 1176 blsp1_i2c3_default: blsp1-i2c3-default-state { 1177 pins = "gpio47", "gpio48"; 1178 function = "blsp_i2c3"; 1179 drive-strength = <2>; 1180 bias-disable; 1181 }; 1182 1183 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1184 pins = "gpio47", "gpio48"; 1185 function = "blsp_i2c3"; 1186 drive-strength = <2>; 1187 bias-pull-up; 1188 }; 1189 1190 blsp1_i2c4_default: blsp1-i2c4-default-state { 1191 pins = "gpio10", "gpio11"; 1192 function = "blsp_i2c4"; 1193 drive-strength = <2>; 1194 bias-disable; 1195 }; 1196 1197 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1198 pins = "gpio10", "gpio11"; 1199 function = "blsp_i2c4"; 1200 drive-strength = <2>; 1201 bias-pull-up; 1202 }; 1203 1204 blsp1_i2c5_default: blsp1-i2c5-default-state { 1205 pins = "gpio87", "gpio88"; 1206 function = "blsp_i2c5"; 1207 drive-strength = <2>; 1208 bias-disable; 1209 }; 1210 1211 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1212 pins = "gpio87", "gpio88"; 1213 function = "blsp_i2c5"; 1214 drive-strength = <2>; 1215 bias-pull-up; 1216 }; 1217 1218 blsp1_i2c6_default: blsp1-i2c6-default-state { 1219 pins = "gpio43", "gpio44"; 1220 function = "blsp_i2c6"; 1221 drive-strength = <2>; 1222 bias-disable; 1223 }; 1224 1225 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1226 pins = "gpio43", "gpio44"; 1227 function = "blsp_i2c6"; 1228 drive-strength = <2>; 1229 bias-pull-up; 1230 }; 1231 1232 blsp1_spi_b_default: blsp1-spi-b-default-state { 1233 pins = "gpio23", "gpio28"; 1234 function = "blsp1_spi_b"; 1235 drive-strength = <6>; 1236 bias-disable; 1237 }; 1238 1239 blsp1_spi1_default: blsp1-spi1-default-state { 1240 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1241 function = "blsp_spi1"; 1242 drive-strength = <6>; 1243 bias-disable; 1244 }; 1245 1246 blsp1_spi2_default: blsp1-spi2-default-state { 1247 pins = "gpio31", "gpio34", "gpio32", "gpio33"; 1248 function = "blsp_spi2"; 1249 drive-strength = <6>; 1250 bias-disable; 1251 }; 1252 1253 blsp1_spi3_default: blsp1-spi3-default-state { 1254 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 1255 function = "blsp_spi2"; 1256 drive-strength = <6>; 1257 bias-disable; 1258 }; 1259 1260 blsp1_spi4_default: blsp1-spi4-default-state { 1261 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1262 function = "blsp_spi4"; 1263 drive-strength = <6>; 1264 bias-disable; 1265 }; 1266 1267 blsp1_spi5_default: blsp1-spi5-default-state { 1268 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1269 function = "blsp_spi5"; 1270 drive-strength = <6>; 1271 bias-disable; 1272 }; 1273 1274 blsp1_spi6_default: blsp1-spi6-default-state { 1275 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1276 function = "blsp_spi6"; 1277 drive-strength = <6>; 1278 bias-disable; 1279 }; 1280 1281 1282 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1283 blsp2_i2c1_default: blsp2-i2c1-default-state { 1284 pins = "gpio55", "gpio56"; 1285 function = "blsp_i2c7"; 1286 drive-strength = <2>; 1287 bias-disable; 1288 }; 1289 1290 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1291 pins = "gpio55", "gpio56"; 1292 function = "blsp_i2c7"; 1293 drive-strength = <2>; 1294 bias-pull-up; 1295 }; 1296 1297 blsp2_i2c2_default: blsp2-i2c2-default-state { 1298 pins = "gpio6", "gpio7"; 1299 function = "blsp_i2c8"; 1300 drive-strength = <2>; 1301 bias-disable; 1302 }; 1303 1304 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1305 pins = "gpio6", "gpio7"; 1306 function = "blsp_i2c8"; 1307 drive-strength = <2>; 1308 bias-pull-up; 1309 }; 1310 1311 blsp2_i2c3_default: blsp2-i2c3-default-state { 1312 pins = "gpio51", "gpio52"; 1313 function = "blsp_i2c9"; 1314 drive-strength = <2>; 1315 bias-disable; 1316 }; 1317 1318 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1319 pins = "gpio51", "gpio52"; 1320 function = "blsp_i2c9"; 1321 drive-strength = <2>; 1322 bias-pull-up; 1323 }; 1324 1325 blsp2_i2c4_default: blsp2-i2c4-default-state { 1326 pins = "gpio67", "gpio68"; 1327 function = "blsp_i2c10"; 1328 drive-strength = <2>; 1329 bias-disable; 1330 }; 1331 1332 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1333 pins = "gpio67", "gpio68"; 1334 function = "blsp_i2c10"; 1335 drive-strength = <2>; 1336 bias-pull-up; 1337 }; 1338 1339 blsp2_i2c5_default: blsp2-i2c5-default-state { 1340 pins = "gpio60", "gpio61"; 1341 function = "blsp_i2c11"; 1342 drive-strength = <2>; 1343 bias-disable; 1344 }; 1345 1346 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1347 pins = "gpio60", "gpio61"; 1348 function = "blsp_i2c11"; 1349 drive-strength = <2>; 1350 bias-pull-up; 1351 }; 1352 1353 blsp2_i2c6_default: blsp2-i2c6-default-state { 1354 pins = "gpio83", "gpio84"; 1355 function = "blsp_i2c12"; 1356 drive-strength = <2>; 1357 bias-disable; 1358 }; 1359 1360 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1361 pins = "gpio83", "gpio84"; 1362 function = "blsp_i2c12"; 1363 drive-strength = <2>; 1364 bias-pull-up; 1365 }; 1366 1367 blsp2_spi1_default: blsp2-spi1-default-state { 1368 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1369 function = "blsp_spi7"; 1370 drive-strength = <6>; 1371 bias-disable; 1372 }; 1373 1374 blsp2_spi2_default: blsp2-spi2-default-state { 1375 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1376 function = "blsp_spi8"; 1377 drive-strength = <6>; 1378 bias-disable; 1379 }; 1380 1381 blsp2_spi3_default: blsp2-spi3-default-state { 1382 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1383 function = "blsp_spi9"; 1384 drive-strength = <6>; 1385 bias-disable; 1386 }; 1387 1388 blsp2_spi4_default: blsp2-spi4-default-state { 1389 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 1390 function = "blsp_spi10"; 1391 drive-strength = <6>; 1392 bias-disable; 1393 }; 1394 1395 blsp2_spi5_default: blsp2-spi5-default-state { 1396 pins = "gpio58", "gpio59", "gpio60", "gpio61"; 1397 function = "blsp_spi11"; 1398 drive-strength = <6>; 1399 bias-disable; 1400 }; 1401 1402 blsp2_spi6_default: blsp2-spi6-default-state { 1403 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 1404 function = "blsp_spi12"; 1405 drive-strength = <6>; 1406 bias-disable; 1407 }; 1408 }; 1409 1410 remoteproc_mss: remoteproc@4080000 { 1411 compatible = "qcom,msm8998-mss-pil"; 1412 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1413 reg-names = "qdsp6", "rmb"; 1414 1415 interrupts-extended = 1416 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1417 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1418 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1419 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1420 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1421 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1422 interrupt-names = "wdog", "fatal", "ready", 1423 "handover", "stop-ack", 1424 "shutdown-ack"; 1425 1426 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1427 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1428 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1429 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1430 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1431 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1432 <&rpmcc RPM_SMD_QDSS_CLK>, 1433 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1434 clock-names = "iface", "bus", "mem", "gpll0_mss", 1435 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1436 1437 qcom,smem-states = <&modem_smp2p_out 0>; 1438 qcom,smem-state-names = "stop"; 1439 1440 resets = <&gcc GCC_MSS_RESTART>; 1441 reset-names = "mss_restart"; 1442 1443 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1444 1445 power-domains = <&rpmpd MSM8998_VDDCX>, 1446 <&rpmpd MSM8998_VDDMX>; 1447 power-domain-names = "cx", "mx"; 1448 1449 status = "disabled"; 1450 1451 mba { 1452 memory-region = <&mba_mem>; 1453 }; 1454 1455 mpss { 1456 memory-region = <&mpss_mem>; 1457 }; 1458 1459 metadata { 1460 memory-region = <&mdata_mem>; 1461 }; 1462 1463 glink-edge { 1464 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1465 label = "modem"; 1466 qcom,remote-pid = <1>; 1467 mboxes = <&apcs_glb 15>; 1468 }; 1469 }; 1470 1471 adreno_gpu: gpu@5000000 { 1472 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1473 reg = <0x05000000 0x40000>; 1474 reg-names = "kgsl_3d0_reg_memory"; 1475 1476 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1477 <&gpucc RBBMTIMER_CLK>, 1478 <&gcc GCC_BIMC_GFX_CLK>, 1479 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1480 <&gpucc RBCPR_CLK>, 1481 <&gpucc GFX3D_CLK>; 1482 clock-names = "iface", 1483 "rbbmtimer", 1484 "mem", 1485 "mem_iface", 1486 "rbcpr", 1487 "core"; 1488 1489 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1490 iommus = <&adreno_smmu 0>; 1491 operating-points-v2 = <&gpu_opp_table>; 1492 power-domains = <&rpmpd MSM8998_VDDMX>; 1493 status = "disabled"; 1494 1495 gpu_opp_table: opp-table { 1496 compatible = "operating-points-v2"; 1497 opp-710000097 { 1498 opp-hz = /bits/ 64 <710000097>; 1499 opp-level = <RPM_SMD_LEVEL_TURBO>; 1500 opp-supported-hw = <0xff>; 1501 }; 1502 1503 opp-670000048 { 1504 opp-hz = /bits/ 64 <670000048>; 1505 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1506 opp-supported-hw = <0xff>; 1507 }; 1508 1509 opp-596000097 { 1510 opp-hz = /bits/ 64 <596000097>; 1511 opp-level = <RPM_SMD_LEVEL_NOM>; 1512 opp-supported-hw = <0xff>; 1513 }; 1514 1515 opp-515000097 { 1516 opp-hz = /bits/ 64 <515000097>; 1517 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1518 opp-supported-hw = <0xff>; 1519 }; 1520 1521 opp-414000000 { 1522 opp-hz = /bits/ 64 <414000000>; 1523 opp-level = <RPM_SMD_LEVEL_SVS>; 1524 opp-supported-hw = <0xff>; 1525 }; 1526 1527 opp-342000000 { 1528 opp-hz = /bits/ 64 <342000000>; 1529 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1530 opp-supported-hw = <0xff>; 1531 }; 1532 1533 opp-257000000 { 1534 opp-hz = /bits/ 64 <257000000>; 1535 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1536 opp-supported-hw = <0xff>; 1537 }; 1538 }; 1539 }; 1540 1541 adreno_smmu: iommu@5040000 { 1542 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1543 reg = <0x05040000 0x10000>; 1544 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1545 <&gcc GCC_BIMC_GFX_CLK>, 1546 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1547 clock-names = "iface", "mem", "mem_iface"; 1548 1549 #global-interrupts = <0>; 1550 #iommu-cells = <1>; 1551 interrupts = 1552 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1553 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1555 /* 1556 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1557 * GPU-CX for SMMU but we need both of them up for Adreno. 1558 * Contemporarily, we also need to manage the VDDMX rpmpd 1559 * domain in the Adreno driver. 1560 * Enable GPU CX/GX GDSCs here so that we can manage the 1561 * SoC VDDMX RPM Power Domain in the Adreno driver. 1562 */ 1563 power-domains = <&gpucc GPU_GX_GDSC>; 1564 status = "disabled"; 1565 }; 1566 1567 gpucc: clock-controller@5065000 { 1568 compatible = "qcom,msm8998-gpucc"; 1569 #clock-cells = <1>; 1570 #reset-cells = <1>; 1571 #power-domain-cells = <1>; 1572 reg = <0x05065000 0x9000>; 1573 1574 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1575 <&gcc GPLL0_OUT_MAIN>; 1576 clock-names = "xo", 1577 "gpll0"; 1578 }; 1579 1580 remoteproc_slpi: remoteproc@5800000 { 1581 compatible = "qcom,msm8998-slpi-pas"; 1582 reg = <0x05800000 0x4040>; 1583 1584 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1585 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1586 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1587 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1588 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1589 interrupt-names = "wdog", "fatal", "ready", 1590 "handover", "stop-ack"; 1591 1592 px-supply = <&vreg_lvs2a_1p8>; 1593 1594 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1595 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1596 clock-names = "xo", "aggre2"; 1597 1598 memory-region = <&slpi_mem>; 1599 1600 qcom,smem-states = <&slpi_smp2p_out 0>; 1601 qcom,smem-state-names = "stop"; 1602 1603 power-domains = <&rpmpd MSM8998_SSCCX>; 1604 power-domain-names = "ssc_cx"; 1605 1606 status = "disabled"; 1607 1608 glink-edge { 1609 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1610 label = "dsps"; 1611 qcom,remote-pid = <3>; 1612 mboxes = <&apcs_glb 27>; 1613 }; 1614 }; 1615 1616 stm: stm@6002000 { 1617 compatible = "arm,coresight-stm", "arm,primecell"; 1618 reg = <0x06002000 0x1000>, 1619 <0x16280000 0x180000>; 1620 reg-names = "stm-base", "stm-stimulus-base"; 1621 status = "disabled"; 1622 1623 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1624 clock-names = "apb_pclk", "atclk"; 1625 1626 out-ports { 1627 port { 1628 stm_out: endpoint { 1629 remote-endpoint = <&funnel0_in7>; 1630 }; 1631 }; 1632 }; 1633 }; 1634 1635 funnel1: funnel@6041000 { 1636 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1637 reg = <0x06041000 0x1000>; 1638 status = "disabled"; 1639 1640 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1641 clock-names = "apb_pclk", "atclk"; 1642 1643 out-ports { 1644 port { 1645 funnel0_out: endpoint { 1646 remote-endpoint = 1647 <&merge_funnel_in0>; 1648 }; 1649 }; 1650 }; 1651 1652 in-ports { 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 1656 port@7 { 1657 reg = <7>; 1658 funnel0_in7: endpoint { 1659 remote-endpoint = <&stm_out>; 1660 }; 1661 }; 1662 }; 1663 }; 1664 1665 funnel2: funnel@6042000 { 1666 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1667 reg = <0x06042000 0x1000>; 1668 status = "disabled"; 1669 1670 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1671 clock-names = "apb_pclk", "atclk"; 1672 1673 out-ports { 1674 port { 1675 funnel1_out: endpoint { 1676 remote-endpoint = 1677 <&merge_funnel_in1>; 1678 }; 1679 }; 1680 }; 1681 1682 in-ports { 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 1686 port@6 { 1687 reg = <6>; 1688 funnel1_in6: endpoint { 1689 remote-endpoint = 1690 <&apss_merge_funnel_out>; 1691 }; 1692 }; 1693 }; 1694 }; 1695 1696 funnel3: funnel@6045000 { 1697 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1698 reg = <0x06045000 0x1000>; 1699 status = "disabled"; 1700 1701 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1702 clock-names = "apb_pclk", "atclk"; 1703 1704 out-ports { 1705 port { 1706 merge_funnel_out: endpoint { 1707 remote-endpoint = 1708 <&etf_in>; 1709 }; 1710 }; 1711 }; 1712 1713 in-ports { 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 1717 port@0 { 1718 reg = <0>; 1719 merge_funnel_in0: endpoint { 1720 remote-endpoint = 1721 <&funnel0_out>; 1722 }; 1723 }; 1724 1725 port@1 { 1726 reg = <1>; 1727 merge_funnel_in1: endpoint { 1728 remote-endpoint = 1729 <&funnel1_out>; 1730 }; 1731 }; 1732 }; 1733 }; 1734 1735 replicator1: replicator@6046000 { 1736 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1737 reg = <0x06046000 0x1000>; 1738 status = "disabled"; 1739 1740 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1741 clock-names = "apb_pclk", "atclk"; 1742 1743 out-ports { 1744 port { 1745 replicator_out: endpoint { 1746 remote-endpoint = <&etr_in>; 1747 }; 1748 }; 1749 }; 1750 1751 in-ports { 1752 port { 1753 replicator_in: endpoint { 1754 remote-endpoint = <&etf_out>; 1755 }; 1756 }; 1757 }; 1758 }; 1759 1760 etf: etf@6047000 { 1761 compatible = "arm,coresight-tmc", "arm,primecell"; 1762 reg = <0x06047000 0x1000>; 1763 status = "disabled"; 1764 1765 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1766 clock-names = "apb_pclk", "atclk"; 1767 1768 out-ports { 1769 port { 1770 etf_out: endpoint { 1771 remote-endpoint = 1772 <&replicator_in>; 1773 }; 1774 }; 1775 }; 1776 1777 in-ports { 1778 port { 1779 etf_in: endpoint { 1780 remote-endpoint = 1781 <&merge_funnel_out>; 1782 }; 1783 }; 1784 }; 1785 }; 1786 1787 etr: etr@6048000 { 1788 compatible = "arm,coresight-tmc", "arm,primecell"; 1789 reg = <0x06048000 0x1000>; 1790 status = "disabled"; 1791 1792 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1793 clock-names = "apb_pclk", "atclk"; 1794 arm,scatter-gather; 1795 1796 in-ports { 1797 port { 1798 etr_in: endpoint { 1799 remote-endpoint = 1800 <&replicator_out>; 1801 }; 1802 }; 1803 }; 1804 }; 1805 1806 etm1: etm@7840000 { 1807 compatible = "arm,coresight-etm4x", "arm,primecell"; 1808 reg = <0x07840000 0x1000>; 1809 status = "disabled"; 1810 1811 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1812 clock-names = "apb_pclk", "atclk"; 1813 1814 cpu = <&CPU0>; 1815 1816 out-ports { 1817 port { 1818 etm0_out: endpoint { 1819 remote-endpoint = 1820 <&apss_funnel_in0>; 1821 }; 1822 }; 1823 }; 1824 }; 1825 1826 etm2: etm@7940000 { 1827 compatible = "arm,coresight-etm4x", "arm,primecell"; 1828 reg = <0x07940000 0x1000>; 1829 status = "disabled"; 1830 1831 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1832 clock-names = "apb_pclk", "atclk"; 1833 1834 cpu = <&CPU1>; 1835 1836 out-ports { 1837 port { 1838 etm1_out: endpoint { 1839 remote-endpoint = 1840 <&apss_funnel_in1>; 1841 }; 1842 }; 1843 }; 1844 }; 1845 1846 etm3: etm@7a40000 { 1847 compatible = "arm,coresight-etm4x", "arm,primecell"; 1848 reg = <0x07a40000 0x1000>; 1849 status = "disabled"; 1850 1851 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1852 clock-names = "apb_pclk", "atclk"; 1853 1854 cpu = <&CPU2>; 1855 1856 out-ports { 1857 port { 1858 etm2_out: endpoint { 1859 remote-endpoint = 1860 <&apss_funnel_in2>; 1861 }; 1862 }; 1863 }; 1864 }; 1865 1866 etm4: etm@7b40000 { 1867 compatible = "arm,coresight-etm4x", "arm,primecell"; 1868 reg = <0x07b40000 0x1000>; 1869 status = "disabled"; 1870 1871 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1872 clock-names = "apb_pclk", "atclk"; 1873 1874 cpu = <&CPU3>; 1875 1876 out-ports { 1877 port { 1878 etm3_out: endpoint { 1879 remote-endpoint = 1880 <&apss_funnel_in3>; 1881 }; 1882 }; 1883 }; 1884 }; 1885 1886 funnel4: funnel@7b60000 { /* APSS Funnel */ 1887 compatible = "arm,coresight-etm4x", "arm,primecell"; 1888 reg = <0x07b60000 0x1000>; 1889 status = "disabled"; 1890 1891 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1892 clock-names = "apb_pclk", "atclk"; 1893 1894 out-ports { 1895 port { 1896 apss_funnel_out: endpoint { 1897 remote-endpoint = 1898 <&apss_merge_funnel_in>; 1899 }; 1900 }; 1901 }; 1902 1903 in-ports { 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 1907 port@0 { 1908 reg = <0>; 1909 apss_funnel_in0: endpoint { 1910 remote-endpoint = 1911 <&etm0_out>; 1912 }; 1913 }; 1914 1915 port@1 { 1916 reg = <1>; 1917 apss_funnel_in1: endpoint { 1918 remote-endpoint = 1919 <&etm1_out>; 1920 }; 1921 }; 1922 1923 port@2 { 1924 reg = <2>; 1925 apss_funnel_in2: endpoint { 1926 remote-endpoint = 1927 <&etm2_out>; 1928 }; 1929 }; 1930 1931 port@3 { 1932 reg = <3>; 1933 apss_funnel_in3: endpoint { 1934 remote-endpoint = 1935 <&etm3_out>; 1936 }; 1937 }; 1938 1939 port@4 { 1940 reg = <4>; 1941 apss_funnel_in4: endpoint { 1942 remote-endpoint = 1943 <&etm4_out>; 1944 }; 1945 }; 1946 1947 port@5 { 1948 reg = <5>; 1949 apss_funnel_in5: endpoint { 1950 remote-endpoint = 1951 <&etm5_out>; 1952 }; 1953 }; 1954 1955 port@6 { 1956 reg = <6>; 1957 apss_funnel_in6: endpoint { 1958 remote-endpoint = 1959 <&etm6_out>; 1960 }; 1961 }; 1962 1963 port@7 { 1964 reg = <7>; 1965 apss_funnel_in7: endpoint { 1966 remote-endpoint = 1967 <&etm7_out>; 1968 }; 1969 }; 1970 }; 1971 }; 1972 1973 funnel5: funnel@7b70000 { 1974 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1975 reg = <0x07b70000 0x1000>; 1976 status = "disabled"; 1977 1978 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1979 clock-names = "apb_pclk", "atclk"; 1980 1981 out-ports { 1982 port { 1983 apss_merge_funnel_out: endpoint { 1984 remote-endpoint = 1985 <&funnel1_in6>; 1986 }; 1987 }; 1988 }; 1989 1990 in-ports { 1991 port { 1992 apss_merge_funnel_in: endpoint { 1993 remote-endpoint = 1994 <&apss_funnel_out>; 1995 }; 1996 }; 1997 }; 1998 }; 1999 2000 etm5: etm@7c40000 { 2001 compatible = "arm,coresight-etm4x", "arm,primecell"; 2002 reg = <0x07c40000 0x1000>; 2003 status = "disabled"; 2004 2005 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2006 clock-names = "apb_pclk", "atclk"; 2007 2008 cpu = <&CPU4>; 2009 2010 port { 2011 etm4_out: endpoint { 2012 remote-endpoint = <&apss_funnel_in4>; 2013 }; 2014 }; 2015 }; 2016 2017 etm6: etm@7d40000 { 2018 compatible = "arm,coresight-etm4x", "arm,primecell"; 2019 reg = <0x07d40000 0x1000>; 2020 status = "disabled"; 2021 2022 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2023 clock-names = "apb_pclk", "atclk"; 2024 2025 cpu = <&CPU5>; 2026 2027 port { 2028 etm5_out: endpoint { 2029 remote-endpoint = <&apss_funnel_in5>; 2030 }; 2031 }; 2032 }; 2033 2034 etm7: etm@7e40000 { 2035 compatible = "arm,coresight-etm4x", "arm,primecell"; 2036 reg = <0x07e40000 0x1000>; 2037 status = "disabled"; 2038 2039 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2040 clock-names = "apb_pclk", "atclk"; 2041 2042 cpu = <&CPU6>; 2043 2044 port { 2045 etm6_out: endpoint { 2046 remote-endpoint = <&apss_funnel_in6>; 2047 }; 2048 }; 2049 }; 2050 2051 etm8: etm@7f40000 { 2052 compatible = "arm,coresight-etm4x", "arm,primecell"; 2053 reg = <0x07f40000 0x1000>; 2054 status = "disabled"; 2055 2056 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2057 clock-names = "apb_pclk", "atclk"; 2058 2059 cpu = <&CPU7>; 2060 2061 port { 2062 etm7_out: endpoint { 2063 remote-endpoint = <&apss_funnel_in7>; 2064 }; 2065 }; 2066 }; 2067 2068 sram@290000 { 2069 compatible = "qcom,rpm-stats"; 2070 reg = <0x00290000 0x10000>; 2071 }; 2072 2073 spmi_bus: spmi@800f000 { 2074 compatible = "qcom,spmi-pmic-arb"; 2075 reg = <0x0800f000 0x1000>, 2076 <0x08400000 0x1000000>, 2077 <0x09400000 0x1000000>, 2078 <0x0a400000 0x220000>, 2079 <0x0800a000 0x3000>; 2080 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2081 interrupt-names = "periph_irq"; 2082 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2083 qcom,ee = <0>; 2084 qcom,channel = <0>; 2085 #address-cells = <2>; 2086 #size-cells = <0>; 2087 interrupt-controller; 2088 #interrupt-cells = <4>; 2089 }; 2090 2091 usb3: usb@a8f8800 { 2092 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2093 reg = <0x0a8f8800 0x400>; 2094 status = "disabled"; 2095 #address-cells = <1>; 2096 #size-cells = <1>; 2097 ranges; 2098 2099 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2100 <&gcc GCC_USB30_MASTER_CLK>, 2101 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2102 <&gcc GCC_USB30_SLEEP_CLK>, 2103 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2104 clock-names = "cfg_noc", 2105 "core", 2106 "iface", 2107 "sleep", 2108 "mock_utmi"; 2109 2110 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2111 <&gcc GCC_USB30_MASTER_CLK>; 2112 assigned-clock-rates = <19200000>, <120000000>; 2113 2114 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2116 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2117 2118 power-domains = <&gcc USB_30_GDSC>; 2119 2120 resets = <&gcc GCC_USB_30_BCR>; 2121 2122 usb3_dwc3: usb@a800000 { 2123 compatible = "snps,dwc3"; 2124 reg = <0x0a800000 0xcd00>; 2125 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2126 snps,dis_u2_susphy_quirk; 2127 snps,dis_enblslpm_quirk; 2128 phys = <&qusb2phy>, <&usb1_ssphy>; 2129 phy-names = "usb2-phy", "usb3-phy"; 2130 snps,has-lpm-erratum; 2131 snps,hird-threshold = /bits/ 8 <0x10>; 2132 }; 2133 }; 2134 2135 usb3phy: phy@c010000 { 2136 compatible = "qcom,msm8998-qmp-usb3-phy"; 2137 reg = <0x0c010000 0x18c>; 2138 status = "disabled"; 2139 #address-cells = <1>; 2140 #size-cells = <1>; 2141 ranges; 2142 2143 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2144 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2145 <&gcc GCC_USB3_CLKREF_CLK>; 2146 clock-names = "aux", "cfg_ahb", "ref"; 2147 2148 resets = <&gcc GCC_USB3_PHY_BCR>, 2149 <&gcc GCC_USB3PHY_PHY_BCR>; 2150 reset-names = "phy", "common"; 2151 2152 usb1_ssphy: phy@c010200 { 2153 reg = <0xc010200 0x128>, 2154 <0xc010400 0x200>, 2155 <0xc010c00 0x20c>, 2156 <0xc010600 0x128>, 2157 <0xc010800 0x200>; 2158 #phy-cells = <0>; 2159 #clock-cells = <0>; 2160 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2161 clock-names = "pipe0"; 2162 clock-output-names = "usb3_phy_pipe_clk_src"; 2163 }; 2164 }; 2165 2166 qusb2phy: phy@c012000 { 2167 compatible = "qcom,msm8998-qusb2-phy"; 2168 reg = <0x0c012000 0x2a8>; 2169 status = "disabled"; 2170 #phy-cells = <0>; 2171 2172 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2173 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2174 clock-names = "cfg_ahb", "ref"; 2175 2176 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2177 2178 nvmem-cells = <&qusb2_hstx_trim>; 2179 }; 2180 2181 sdhc2: mmc@c0a4900 { 2182 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2183 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2184 reg-names = "hc", "core"; 2185 2186 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2188 interrupt-names = "hc_irq", "pwr_irq"; 2189 2190 clock-names = "iface", "core", "xo"; 2191 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2192 <&gcc GCC_SDCC2_APPS_CLK>, 2193 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2194 bus-width = <4>; 2195 status = "disabled"; 2196 }; 2197 2198 blsp1_dma: dma-controller@c144000 { 2199 compatible = "qcom,bam-v1.7.0"; 2200 reg = <0x0c144000 0x25000>; 2201 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2202 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2203 clock-names = "bam_clk"; 2204 #dma-cells = <1>; 2205 qcom,ee = <0>; 2206 qcom,controlled-remotely; 2207 num-channels = <18>; 2208 qcom,num-ees = <4>; 2209 }; 2210 2211 blsp1_uart3: serial@c171000 { 2212 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2213 reg = <0x0c171000 0x1000>; 2214 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2215 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2216 <&gcc GCC_BLSP1_AHB_CLK>; 2217 clock-names = "core", "iface"; 2218 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2219 dma-names = "tx", "rx"; 2220 pinctrl-names = "default"; 2221 pinctrl-0 = <&blsp1_uart3_on>; 2222 status = "disabled"; 2223 }; 2224 2225 blsp1_i2c1: i2c@c175000 { 2226 compatible = "qcom,i2c-qup-v2.2.1"; 2227 reg = <0x0c175000 0x600>; 2228 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2229 2230 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2231 <&gcc GCC_BLSP1_AHB_CLK>; 2232 clock-names = "core", "iface"; 2233 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2234 dma-names = "tx", "rx"; 2235 pinctrl-names = "default", "sleep"; 2236 pinctrl-0 = <&blsp1_i2c1_default>; 2237 pinctrl-1 = <&blsp1_i2c1_sleep>; 2238 clock-frequency = <400000>; 2239 2240 status = "disabled"; 2241 #address-cells = <1>; 2242 #size-cells = <0>; 2243 }; 2244 2245 blsp1_i2c2: i2c@c176000 { 2246 compatible = "qcom,i2c-qup-v2.2.1"; 2247 reg = <0x0c176000 0x600>; 2248 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2249 2250 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2251 <&gcc GCC_BLSP1_AHB_CLK>; 2252 clock-names = "core", "iface"; 2253 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2254 dma-names = "tx", "rx"; 2255 pinctrl-names = "default", "sleep"; 2256 pinctrl-0 = <&blsp1_i2c2_default>; 2257 pinctrl-1 = <&blsp1_i2c2_sleep>; 2258 clock-frequency = <400000>; 2259 2260 status = "disabled"; 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 }; 2264 2265 blsp1_i2c3: i2c@c177000 { 2266 compatible = "qcom,i2c-qup-v2.2.1"; 2267 reg = <0x0c177000 0x600>; 2268 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2269 2270 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2271 <&gcc GCC_BLSP1_AHB_CLK>; 2272 clock-names = "core", "iface"; 2273 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2274 dma-names = "tx", "rx"; 2275 pinctrl-names = "default", "sleep"; 2276 pinctrl-0 = <&blsp1_i2c3_default>; 2277 pinctrl-1 = <&blsp1_i2c3_sleep>; 2278 clock-frequency = <400000>; 2279 2280 status = "disabled"; 2281 #address-cells = <1>; 2282 #size-cells = <0>; 2283 }; 2284 2285 blsp1_i2c4: i2c@c178000 { 2286 compatible = "qcom,i2c-qup-v2.2.1"; 2287 reg = <0x0c178000 0x600>; 2288 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2289 2290 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2291 <&gcc GCC_BLSP1_AHB_CLK>; 2292 clock-names = "core", "iface"; 2293 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2294 dma-names = "tx", "rx"; 2295 pinctrl-names = "default", "sleep"; 2296 pinctrl-0 = <&blsp1_i2c4_default>; 2297 pinctrl-1 = <&blsp1_i2c4_sleep>; 2298 clock-frequency = <400000>; 2299 2300 status = "disabled"; 2301 #address-cells = <1>; 2302 #size-cells = <0>; 2303 }; 2304 2305 blsp1_i2c5: i2c@c179000 { 2306 compatible = "qcom,i2c-qup-v2.2.1"; 2307 reg = <0x0c179000 0x600>; 2308 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2309 2310 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2311 <&gcc GCC_BLSP1_AHB_CLK>; 2312 clock-names = "core", "iface"; 2313 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2314 dma-names = "tx", "rx"; 2315 pinctrl-names = "default", "sleep"; 2316 pinctrl-0 = <&blsp1_i2c5_default>; 2317 pinctrl-1 = <&blsp1_i2c5_sleep>; 2318 clock-frequency = <400000>; 2319 2320 status = "disabled"; 2321 #address-cells = <1>; 2322 #size-cells = <0>; 2323 }; 2324 2325 blsp1_i2c6: i2c@c17a000 { 2326 compatible = "qcom,i2c-qup-v2.2.1"; 2327 reg = <0x0c17a000 0x600>; 2328 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2329 2330 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2331 <&gcc GCC_BLSP1_AHB_CLK>; 2332 clock-names = "core", "iface"; 2333 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2334 dma-names = "tx", "rx"; 2335 pinctrl-names = "default", "sleep"; 2336 pinctrl-0 = <&blsp1_i2c6_default>; 2337 pinctrl-1 = <&blsp1_i2c6_sleep>; 2338 clock-frequency = <400000>; 2339 2340 status = "disabled"; 2341 #address-cells = <1>; 2342 #size-cells = <0>; 2343 }; 2344 2345 blsp1_spi1: spi@c175000 { 2346 compatible = "qcom,spi-qup-v2.2.1"; 2347 reg = <0x0c175000 0x600>; 2348 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2349 2350 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2351 <&gcc GCC_BLSP1_AHB_CLK>; 2352 clock-names = "core", "iface"; 2353 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2354 dma-names = "tx", "rx"; 2355 pinctrl-names = "default"; 2356 pinctrl-0 = <&blsp1_spi1_default>; 2357 2358 status = "disabled"; 2359 #address-cells = <1>; 2360 #size-cells = <0>; 2361 }; 2362 2363 blsp1_spi2: spi@c176000 { 2364 compatible = "qcom,spi-qup-v2.2.1"; 2365 reg = <0x0c176000 0x600>; 2366 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2367 2368 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2369 <&gcc GCC_BLSP1_AHB_CLK>; 2370 clock-names = "core", "iface"; 2371 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2372 dma-names = "tx", "rx"; 2373 pinctrl-names = "default"; 2374 pinctrl-0 = <&blsp1_spi2_default>; 2375 2376 status = "disabled"; 2377 #address-cells = <1>; 2378 #size-cells = <0>; 2379 }; 2380 2381 blsp1_spi3: spi@c177000 { 2382 compatible = "qcom,spi-qup-v2.2.1"; 2383 reg = <0x0c177000 0x600>; 2384 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2385 2386 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2387 <&gcc GCC_BLSP1_AHB_CLK>; 2388 clock-names = "core", "iface"; 2389 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2390 dma-names = "tx", "rx"; 2391 pinctrl-names = "default"; 2392 pinctrl-0 = <&blsp1_spi3_default>; 2393 2394 status = "disabled"; 2395 #address-cells = <1>; 2396 #size-cells = <0>; 2397 }; 2398 2399 blsp1_spi4: spi@c178000 { 2400 compatible = "qcom,spi-qup-v2.2.1"; 2401 reg = <0x0c178000 0x600>; 2402 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2403 2404 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2405 <&gcc GCC_BLSP1_AHB_CLK>; 2406 clock-names = "core", "iface"; 2407 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2408 dma-names = "tx", "rx"; 2409 pinctrl-names = "default"; 2410 pinctrl-0 = <&blsp1_spi4_default>; 2411 2412 status = "disabled"; 2413 #address-cells = <1>; 2414 #size-cells = <0>; 2415 }; 2416 2417 blsp1_spi5: spi@c179000 { 2418 compatible = "qcom,spi-qup-v2.2.1"; 2419 reg = <0x0c179000 0x600>; 2420 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2421 2422 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2423 <&gcc GCC_BLSP1_AHB_CLK>; 2424 clock-names = "core", "iface"; 2425 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2426 dma-names = "tx", "rx"; 2427 pinctrl-names = "default"; 2428 pinctrl-0 = <&blsp1_spi5_default>; 2429 2430 status = "disabled"; 2431 #address-cells = <1>; 2432 #size-cells = <0>; 2433 }; 2434 2435 blsp1_spi6: spi@c17a000 { 2436 compatible = "qcom,spi-qup-v2.2.1"; 2437 reg = <0x0c17a000 0x600>; 2438 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2439 2440 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2441 <&gcc GCC_BLSP1_AHB_CLK>; 2442 clock-names = "core", "iface"; 2443 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2444 dma-names = "tx", "rx"; 2445 pinctrl-names = "default"; 2446 pinctrl-0 = <&blsp1_spi6_default>; 2447 2448 status = "disabled"; 2449 #address-cells = <1>; 2450 #size-cells = <0>; 2451 }; 2452 2453 blsp2_dma: dma-controller@c184000 { 2454 compatible = "qcom,bam-v1.7.0"; 2455 reg = <0x0c184000 0x25000>; 2456 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2457 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2458 clock-names = "bam_clk"; 2459 #dma-cells = <1>; 2460 qcom,ee = <0>; 2461 qcom,controlled-remotely; 2462 num-channels = <18>; 2463 qcom,num-ees = <4>; 2464 }; 2465 2466 blsp2_uart1: serial@c1b0000 { 2467 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2468 reg = <0x0c1b0000 0x1000>; 2469 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2470 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2471 <&gcc GCC_BLSP2_AHB_CLK>; 2472 clock-names = "core", "iface"; 2473 status = "disabled"; 2474 }; 2475 2476 blsp2_i2c1: i2c@c1b5000 { 2477 compatible = "qcom,i2c-qup-v2.2.1"; 2478 reg = <0x0c1b5000 0x600>; 2479 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2480 2481 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2482 <&gcc GCC_BLSP2_AHB_CLK>; 2483 clock-names = "core", "iface"; 2484 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2485 dma-names = "tx", "rx"; 2486 pinctrl-names = "default", "sleep"; 2487 pinctrl-0 = <&blsp2_i2c1_default>; 2488 pinctrl-1 = <&blsp2_i2c1_sleep>; 2489 clock-frequency = <400000>; 2490 2491 status = "disabled"; 2492 #address-cells = <1>; 2493 #size-cells = <0>; 2494 }; 2495 2496 blsp2_i2c2: i2c@c1b6000 { 2497 compatible = "qcom,i2c-qup-v2.2.1"; 2498 reg = <0x0c1b6000 0x600>; 2499 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2500 2501 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2502 <&gcc GCC_BLSP2_AHB_CLK>; 2503 clock-names = "core", "iface"; 2504 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2505 dma-names = "tx", "rx"; 2506 pinctrl-names = "default", "sleep"; 2507 pinctrl-0 = <&blsp2_i2c2_default>; 2508 pinctrl-1 = <&blsp2_i2c2_sleep>; 2509 clock-frequency = <400000>; 2510 2511 status = "disabled"; 2512 #address-cells = <1>; 2513 #size-cells = <0>; 2514 }; 2515 2516 blsp2_i2c3: i2c@c1b7000 { 2517 compatible = "qcom,i2c-qup-v2.2.1"; 2518 reg = <0x0c1b7000 0x600>; 2519 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2520 2521 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2522 <&gcc GCC_BLSP2_AHB_CLK>; 2523 clock-names = "core", "iface"; 2524 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2525 dma-names = "tx", "rx"; 2526 pinctrl-names = "default", "sleep"; 2527 pinctrl-0 = <&blsp2_i2c3_default>; 2528 pinctrl-1 = <&blsp2_i2c3_sleep>; 2529 clock-frequency = <400000>; 2530 2531 status = "disabled"; 2532 #address-cells = <1>; 2533 #size-cells = <0>; 2534 }; 2535 2536 blsp2_i2c4: i2c@c1b8000 { 2537 compatible = "qcom,i2c-qup-v2.2.1"; 2538 reg = <0x0c1b8000 0x600>; 2539 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2540 2541 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2542 <&gcc GCC_BLSP2_AHB_CLK>; 2543 clock-names = "core", "iface"; 2544 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2545 dma-names = "tx", "rx"; 2546 pinctrl-names = "default", "sleep"; 2547 pinctrl-0 = <&blsp2_i2c4_default>; 2548 pinctrl-1 = <&blsp2_i2c4_sleep>; 2549 clock-frequency = <400000>; 2550 2551 status = "disabled"; 2552 #address-cells = <1>; 2553 #size-cells = <0>; 2554 }; 2555 2556 blsp2_i2c5: i2c@c1b9000 { 2557 compatible = "qcom,i2c-qup-v2.2.1"; 2558 reg = <0x0c1b9000 0x600>; 2559 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2560 2561 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2562 <&gcc GCC_BLSP2_AHB_CLK>; 2563 clock-names = "core", "iface"; 2564 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2565 dma-names = "tx", "rx"; 2566 pinctrl-names = "default", "sleep"; 2567 pinctrl-0 = <&blsp2_i2c5_default>; 2568 pinctrl-1 = <&blsp2_i2c5_sleep>; 2569 clock-frequency = <400000>; 2570 2571 status = "disabled"; 2572 #address-cells = <1>; 2573 #size-cells = <0>; 2574 }; 2575 2576 blsp2_i2c6: i2c@c1ba000 { 2577 compatible = "qcom,i2c-qup-v2.2.1"; 2578 reg = <0x0c1ba000 0x600>; 2579 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2580 2581 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2582 <&gcc GCC_BLSP2_AHB_CLK>; 2583 clock-names = "core", "iface"; 2584 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2585 dma-names = "tx", "rx"; 2586 pinctrl-names = "default", "sleep"; 2587 pinctrl-0 = <&blsp2_i2c6_default>; 2588 pinctrl-1 = <&blsp2_i2c6_sleep>; 2589 clock-frequency = <400000>; 2590 2591 status = "disabled"; 2592 #address-cells = <1>; 2593 #size-cells = <0>; 2594 }; 2595 2596 blsp2_spi1: spi@c1b5000 { 2597 compatible = "qcom,spi-qup-v2.2.1"; 2598 reg = <0x0c1b5000 0x600>; 2599 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2600 2601 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 2602 <&gcc GCC_BLSP2_AHB_CLK>; 2603 clock-names = "core", "iface"; 2604 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2605 dma-names = "tx", "rx"; 2606 pinctrl-names = "default"; 2607 pinctrl-0 = <&blsp2_spi1_default>; 2608 2609 status = "disabled"; 2610 #address-cells = <1>; 2611 #size-cells = <0>; 2612 }; 2613 2614 blsp2_spi2: spi@c1b6000 { 2615 compatible = "qcom,spi-qup-v2.2.1"; 2616 reg = <0x0c1b6000 0x600>; 2617 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2618 2619 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 2620 <&gcc GCC_BLSP2_AHB_CLK>; 2621 clock-names = "core", "iface"; 2622 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2623 dma-names = "tx", "rx"; 2624 pinctrl-names = "default"; 2625 pinctrl-0 = <&blsp2_spi2_default>; 2626 2627 status = "disabled"; 2628 #address-cells = <1>; 2629 #size-cells = <0>; 2630 }; 2631 2632 blsp2_spi3: spi@c1b7000 { 2633 compatible = "qcom,spi-qup-v2.2.1"; 2634 reg = <0x0c1b7000 0x600>; 2635 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2636 2637 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 2638 <&gcc GCC_BLSP2_AHB_CLK>; 2639 clock-names = "core", "iface"; 2640 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2641 dma-names = "tx", "rx"; 2642 pinctrl-names = "default"; 2643 pinctrl-0 = <&blsp2_spi3_default>; 2644 2645 status = "disabled"; 2646 #address-cells = <1>; 2647 #size-cells = <0>; 2648 }; 2649 2650 blsp2_spi4: spi@c1b8000 { 2651 compatible = "qcom,spi-qup-v2.2.1"; 2652 reg = <0x0c1b8000 0x600>; 2653 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2654 2655 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 2656 <&gcc GCC_BLSP2_AHB_CLK>; 2657 clock-names = "core", "iface"; 2658 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2659 dma-names = "tx", "rx"; 2660 pinctrl-names = "default"; 2661 pinctrl-0 = <&blsp2_spi4_default>; 2662 2663 status = "disabled"; 2664 #address-cells = <1>; 2665 #size-cells = <0>; 2666 }; 2667 2668 blsp2_spi5: spi@c1b9000 { 2669 compatible = "qcom,spi-qup-v2.2.1"; 2670 reg = <0x0c1b9000 0x600>; 2671 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2672 2673 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 2674 <&gcc GCC_BLSP2_AHB_CLK>; 2675 clock-names = "core", "iface"; 2676 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2677 dma-names = "tx", "rx"; 2678 pinctrl-names = "default"; 2679 pinctrl-0 = <&blsp2_spi5_default>; 2680 2681 status = "disabled"; 2682 #address-cells = <1>; 2683 #size-cells = <0>; 2684 }; 2685 2686 blsp2_spi6: spi@c1ba000 { 2687 compatible = "qcom,spi-qup-v2.2.1"; 2688 reg = <0x0c1ba000 0x600>; 2689 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2690 2691 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 2692 <&gcc GCC_BLSP2_AHB_CLK>; 2693 clock-names = "core", "iface"; 2694 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2695 dma-names = "tx", "rx"; 2696 pinctrl-names = "default"; 2697 pinctrl-0 = <&blsp2_spi6_default>; 2698 2699 status = "disabled"; 2700 #address-cells = <1>; 2701 #size-cells = <0>; 2702 }; 2703 2704 mmcc: clock-controller@c8c0000 { 2705 compatible = "qcom,mmcc-msm8998"; 2706 #clock-cells = <1>; 2707 #reset-cells = <1>; 2708 #power-domain-cells = <1>; 2709 reg = <0xc8c0000 0x40000>; 2710 2711 clock-names = "xo", 2712 "gpll0", 2713 "dsi0dsi", 2714 "dsi0byte", 2715 "dsi1dsi", 2716 "dsi1byte", 2717 "hdmipll", 2718 "dplink", 2719 "dpvco"; 2720 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2721 <&gcc GCC_MMSS_GPLL0_CLK>, 2722 <0>, 2723 <0>, 2724 <0>, 2725 <0>, 2726 <0>, 2727 <0>, 2728 <0>; 2729 }; 2730 2731 mmss_smmu: iommu@cd00000 { 2732 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 2733 reg = <0x0cd00000 0x40000>; 2734 #iommu-cells = <1>; 2735 2736 clocks = <&mmcc MNOC_AHB_CLK>, 2737 <&mmcc BIMC_SMMU_AHB_CLK>, 2738 <&rpmcc RPM_SMD_MMAXI_CLK>, 2739 <&mmcc BIMC_SMMU_AXI_CLK>; 2740 clock-names = "iface-mm", "iface-smmu", 2741 "bus-mm", "bus-smmu"; 2742 2743 #global-interrupts = <0>; 2744 interrupts = 2745 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2746 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2747 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2748 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2749 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2752 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2753 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2754 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2755 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2765 }; 2766 2767 remoteproc_adsp: remoteproc@17300000 { 2768 compatible = "qcom,msm8998-adsp-pas"; 2769 reg = <0x17300000 0x4040>; 2770 2771 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2772 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2773 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2774 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2775 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2776 interrupt-names = "wdog", "fatal", "ready", 2777 "handover", "stop-ack"; 2778 2779 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2780 clock-names = "xo"; 2781 2782 memory-region = <&adsp_mem>; 2783 2784 qcom,smem-states = <&adsp_smp2p_out 0>; 2785 qcom,smem-state-names = "stop"; 2786 2787 power-domains = <&rpmpd MSM8998_VDDCX>; 2788 power-domain-names = "cx"; 2789 2790 status = "disabled"; 2791 2792 glink-edge { 2793 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2794 label = "lpass"; 2795 qcom,remote-pid = <2>; 2796 mboxes = <&apcs_glb 9>; 2797 }; 2798 }; 2799 2800 apcs_glb: mailbox@17911000 { 2801 compatible = "qcom,msm8998-apcs-hmss-global", 2802 "qcom,msm8994-apcs-kpss-global"; 2803 reg = <0x17911000 0x1000>; 2804 2805 #mbox-cells = <1>; 2806 }; 2807 2808 timer@17920000 { 2809 #address-cells = <1>; 2810 #size-cells = <1>; 2811 ranges; 2812 compatible = "arm,armv7-timer-mem"; 2813 reg = <0x17920000 0x1000>; 2814 2815 frame@17921000 { 2816 frame-number = <0>; 2817 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2818 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2819 reg = <0x17921000 0x1000>, 2820 <0x17922000 0x1000>; 2821 }; 2822 2823 frame@17923000 { 2824 frame-number = <1>; 2825 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2826 reg = <0x17923000 0x1000>; 2827 status = "disabled"; 2828 }; 2829 2830 frame@17924000 { 2831 frame-number = <2>; 2832 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2833 reg = <0x17924000 0x1000>; 2834 status = "disabled"; 2835 }; 2836 2837 frame@17925000 { 2838 frame-number = <3>; 2839 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2840 reg = <0x17925000 0x1000>; 2841 status = "disabled"; 2842 }; 2843 2844 frame@17926000 { 2845 frame-number = <4>; 2846 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2847 reg = <0x17926000 0x1000>; 2848 status = "disabled"; 2849 }; 2850 2851 frame@17927000 { 2852 frame-number = <5>; 2853 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2854 reg = <0x17927000 0x1000>; 2855 status = "disabled"; 2856 }; 2857 2858 frame@17928000 { 2859 frame-number = <6>; 2860 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2861 reg = <0x17928000 0x1000>; 2862 status = "disabled"; 2863 }; 2864 }; 2865 2866 intc: interrupt-controller@17a00000 { 2867 compatible = "arm,gic-v3"; 2868 reg = <0x17a00000 0x10000>, /* GICD */ 2869 <0x17b00000 0x100000>; /* GICR * 8 */ 2870 #interrupt-cells = <3>; 2871 #address-cells = <1>; 2872 #size-cells = <1>; 2873 ranges; 2874 interrupt-controller; 2875 #redistributor-regions = <1>; 2876 redistributor-stride = <0x0 0x20000>; 2877 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2878 }; 2879 2880 wifi: wifi@18800000 { 2881 compatible = "qcom,wcn3990-wifi"; 2882 status = "disabled"; 2883 reg = <0x18800000 0x800000>; 2884 reg-names = "membase"; 2885 memory-region = <&wlan_msa_mem>; 2886 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2887 clock-names = "cxo_ref_clk_pin"; 2888 interrupts = 2889 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2890 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2891 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2892 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2893 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2894 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2896 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2897 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2898 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2899 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2900 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2901 iommus = <&anoc2_smmu 0x1900>, 2902 <&anoc2_smmu 0x1901>; 2903 qcom,snoc-host-cap-8bit-quirk; 2904 }; 2905 }; 2906}; 2907