1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,apr.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 cpu-idle-states = <&CPU_SLEEP_0>; 50 capacity-dmips-mhz = <1024>; 51 clocks = <&kryocc 0>; 52 operating-points-v2 = <&cluster0_opp>; 53 #cooling-cells = <2>; 54 next-level-cache = <&L2_0>; 55 L2_0: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 }; 59 }; 60 61 CPU1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "qcom,kryo"; 64 reg = <0x0 0x1>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 capacity-dmips-mhz = <1024>; 68 clocks = <&kryocc 0>; 69 operating-points-v2 = <&cluster0_opp>; 70 #cooling-cells = <2>; 71 next-level-cache = <&L2_0>; 72 }; 73 74 CPU2: cpu@100 { 75 device_type = "cpu"; 76 compatible = "qcom,kryo"; 77 reg = <0x0 0x100>; 78 enable-method = "psci"; 79 cpu-idle-states = <&CPU_SLEEP_0>; 80 capacity-dmips-mhz = <1024>; 81 clocks = <&kryocc 1>; 82 operating-points-v2 = <&cluster1_opp>; 83 #cooling-cells = <2>; 84 next-level-cache = <&L2_1>; 85 L2_1: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 }; 89 }; 90 91 CPU3: cpu@101 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo"; 94 reg = <0x0 0x101>; 95 enable-method = "psci"; 96 cpu-idle-states = <&CPU_SLEEP_0>; 97 capacity-dmips-mhz = <1024>; 98 clocks = <&kryocc 1>; 99 operating-points-v2 = <&cluster1_opp>; 100 #cooling-cells = <2>; 101 next-level-cache = <&L2_1>; 102 }; 103 104 cpu-map { 105 cluster0 { 106 core0 { 107 cpu = <&CPU0>; 108 }; 109 110 core1 { 111 cpu = <&CPU1>; 112 }; 113 }; 114 115 cluster1 { 116 core0 { 117 cpu = <&CPU2>; 118 }; 119 120 core1 { 121 cpu = <&CPU3>; 122 }; 123 }; 124 }; 125 126 idle-states { 127 entry-method = "psci"; 128 129 CPU_SLEEP_0: cpu-sleep-0 { 130 compatible = "arm,idle-state"; 131 idle-state-name = "standalone-power-collapse"; 132 arm,psci-suspend-param = <0x00000004>; 133 entry-latency-us = <130>; 134 exit-latency-us = <80>; 135 min-residency-us = <300>; 136 }; 137 }; 138 }; 139 140 cluster0_opp: opp-table-cluster0 { 141 compatible = "operating-points-v2-kryo-cpu"; 142 nvmem-cells = <&speedbin_efuse>; 143 opp-shared; 144 145 /* Nominal fmax for now */ 146 opp-307200000 { 147 opp-hz = /bits/ 64 <307200000>; 148 opp-supported-hw = <0xf>; 149 clock-latency-ns = <200000>; 150 }; 151 opp-422400000 { 152 opp-hz = /bits/ 64 <422400000>; 153 opp-supported-hw = <0xf>; 154 clock-latency-ns = <200000>; 155 }; 156 opp-480000000 { 157 opp-hz = /bits/ 64 <480000000>; 158 opp-supported-hw = <0xf>; 159 clock-latency-ns = <200000>; 160 }; 161 opp-556800000 { 162 opp-hz = /bits/ 64 <556800000>; 163 opp-supported-hw = <0xf>; 164 clock-latency-ns = <200000>; 165 }; 166 opp-652800000 { 167 opp-hz = /bits/ 64 <652800000>; 168 opp-supported-hw = <0xf>; 169 clock-latency-ns = <200000>; 170 }; 171 opp-729600000 { 172 opp-hz = /bits/ 64 <729600000>; 173 opp-supported-hw = <0xf>; 174 clock-latency-ns = <200000>; 175 }; 176 opp-844800000 { 177 opp-hz = /bits/ 64 <844800000>; 178 opp-supported-hw = <0xf>; 179 clock-latency-ns = <200000>; 180 }; 181 opp-960000000 { 182 opp-hz = /bits/ 64 <960000000>; 183 opp-supported-hw = <0xf>; 184 clock-latency-ns = <200000>; 185 }; 186 opp-1036800000 { 187 opp-hz = /bits/ 64 <1036800000>; 188 opp-supported-hw = <0xf>; 189 clock-latency-ns = <200000>; 190 }; 191 opp-1113600000 { 192 opp-hz = /bits/ 64 <1113600000>; 193 opp-supported-hw = <0xf>; 194 clock-latency-ns = <200000>; 195 }; 196 opp-1190400000 { 197 opp-hz = /bits/ 64 <1190400000>; 198 opp-supported-hw = <0xf>; 199 clock-latency-ns = <200000>; 200 }; 201 opp-1228800000 { 202 opp-hz = /bits/ 64 <1228800000>; 203 opp-supported-hw = <0xf>; 204 clock-latency-ns = <200000>; 205 }; 206 opp-1324800000 { 207 opp-hz = /bits/ 64 <1324800000>; 208 opp-supported-hw = <0xd>; 209 clock-latency-ns = <200000>; 210 }; 211 opp-1363200000 { 212 opp-hz = /bits/ 64 <1363200000>; 213 opp-supported-hw = <0x2>; 214 clock-latency-ns = <200000>; 215 }; 216 opp-1401600000 { 217 opp-hz = /bits/ 64 <1401600000>; 218 opp-supported-hw = <0xd>; 219 clock-latency-ns = <200000>; 220 }; 221 opp-1478400000 { 222 opp-hz = /bits/ 64 <1478400000>; 223 opp-supported-hw = <0x9>; 224 clock-latency-ns = <200000>; 225 }; 226 opp-1497600000 { 227 opp-hz = /bits/ 64 <1497600000>; 228 opp-supported-hw = <0x04>; 229 clock-latency-ns = <200000>; 230 }; 231 opp-1593600000 { 232 opp-hz = /bits/ 64 <1593600000>; 233 opp-supported-hw = <0x9>; 234 clock-latency-ns = <200000>; 235 }; 236 }; 237 238 cluster1_opp: opp-table-cluster1 { 239 compatible = "operating-points-v2-kryo-cpu"; 240 nvmem-cells = <&speedbin_efuse>; 241 opp-shared; 242 243 /* Nominal fmax for now */ 244 opp-307200000 { 245 opp-hz = /bits/ 64 <307200000>; 246 opp-supported-hw = <0xf>; 247 clock-latency-ns = <200000>; 248 }; 249 opp-403200000 { 250 opp-hz = /bits/ 64 <403200000>; 251 opp-supported-hw = <0xf>; 252 clock-latency-ns = <200000>; 253 }; 254 opp-480000000 { 255 opp-hz = /bits/ 64 <480000000>; 256 opp-supported-hw = <0xf>; 257 clock-latency-ns = <200000>; 258 }; 259 opp-556800000 { 260 opp-hz = /bits/ 64 <556800000>; 261 opp-supported-hw = <0xf>; 262 clock-latency-ns = <200000>; 263 }; 264 opp-652800000 { 265 opp-hz = /bits/ 64 <652800000>; 266 opp-supported-hw = <0xf>; 267 clock-latency-ns = <200000>; 268 }; 269 opp-729600000 { 270 opp-hz = /bits/ 64 <729600000>; 271 opp-supported-hw = <0xf>; 272 clock-latency-ns = <200000>; 273 }; 274 opp-806400000 { 275 opp-hz = /bits/ 64 <806400000>; 276 opp-supported-hw = <0xf>; 277 clock-latency-ns = <200000>; 278 }; 279 opp-883200000 { 280 opp-hz = /bits/ 64 <883200000>; 281 opp-supported-hw = <0xf>; 282 clock-latency-ns = <200000>; 283 }; 284 opp-940800000 { 285 opp-hz = /bits/ 64 <940800000>; 286 opp-supported-hw = <0xf>; 287 clock-latency-ns = <200000>; 288 }; 289 opp-1036800000 { 290 opp-hz = /bits/ 64 <1036800000>; 291 opp-supported-hw = <0xf>; 292 clock-latency-ns = <200000>; 293 }; 294 opp-1113600000 { 295 opp-hz = /bits/ 64 <1113600000>; 296 opp-supported-hw = <0xf>; 297 clock-latency-ns = <200000>; 298 }; 299 opp-1190400000 { 300 opp-hz = /bits/ 64 <1190400000>; 301 opp-supported-hw = <0xf>; 302 clock-latency-ns = <200000>; 303 }; 304 opp-1248000000 { 305 opp-hz = /bits/ 64 <1248000000>; 306 opp-supported-hw = <0xf>; 307 clock-latency-ns = <200000>; 308 }; 309 opp-1324800000 { 310 opp-hz = /bits/ 64 <1324800000>; 311 opp-supported-hw = <0xf>; 312 clock-latency-ns = <200000>; 313 }; 314 opp-1401600000 { 315 opp-hz = /bits/ 64 <1401600000>; 316 opp-supported-hw = <0xf>; 317 clock-latency-ns = <200000>; 318 }; 319 opp-1478400000 { 320 opp-hz = /bits/ 64 <1478400000>; 321 opp-supported-hw = <0xf>; 322 clock-latency-ns = <200000>; 323 }; 324 opp-1555200000 { 325 opp-hz = /bits/ 64 <1555200000>; 326 opp-supported-hw = <0xf>; 327 clock-latency-ns = <200000>; 328 }; 329 opp-1632000000 { 330 opp-hz = /bits/ 64 <1632000000>; 331 opp-supported-hw = <0xf>; 332 clock-latency-ns = <200000>; 333 }; 334 opp-1708800000 { 335 opp-hz = /bits/ 64 <1708800000>; 336 opp-supported-hw = <0xf>; 337 clock-latency-ns = <200000>; 338 }; 339 opp-1785600000 { 340 opp-hz = /bits/ 64 <1785600000>; 341 opp-supported-hw = <0xf>; 342 clock-latency-ns = <200000>; 343 }; 344 opp-1804800000 { 345 opp-hz = /bits/ 64 <1804800000>; 346 opp-supported-hw = <0xe>; 347 clock-latency-ns = <200000>; 348 }; 349 opp-1824000000 { 350 opp-hz = /bits/ 64 <1824000000>; 351 opp-supported-hw = <0x1>; 352 clock-latency-ns = <200000>; 353 }; 354 opp-1900800000 { 355 opp-hz = /bits/ 64 <1900800000>; 356 opp-supported-hw = <0x4>; 357 clock-latency-ns = <200000>; 358 }; 359 opp-1920000000 { 360 opp-hz = /bits/ 64 <1920000000>; 361 opp-supported-hw = <0x1>; 362 clock-latency-ns = <200000>; 363 }; 364 opp-1996800000 { 365 opp-hz = /bits/ 64 <1996800000>; 366 opp-supported-hw = <0x1>; 367 clock-latency-ns = <200000>; 368 }; 369 opp-2073600000 { 370 opp-hz = /bits/ 64 <2073600000>; 371 opp-supported-hw = <0x1>; 372 clock-latency-ns = <200000>; 373 }; 374 opp-2150400000 { 375 opp-hz = /bits/ 64 <2150400000>; 376 opp-supported-hw = <0x1>; 377 clock-latency-ns = <200000>; 378 }; 379 }; 380 381 firmware { 382 scm { 383 compatible = "qcom,scm-msm8996", "qcom,scm"; 384 qcom,dload-mode = <&tcsr_2 0x13000>; 385 }; 386 }; 387 388 memory@80000000 { 389 device_type = "memory"; 390 /* We expect the bootloader to fill in the reg */ 391 reg = <0x0 0x80000000 0x0 0x0>; 392 }; 393 394 psci { 395 compatible = "arm,psci-1.0"; 396 method = "smc"; 397 }; 398 399 reserved-memory { 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 404 hyp_mem: memory@85800000 { 405 reg = <0x0 0x85800000 0x0 0x600000>; 406 no-map; 407 }; 408 409 xbl_mem: memory@85e00000 { 410 reg = <0x0 0x85e00000 0x0 0x200000>; 411 no-map; 412 }; 413 414 smem_mem: smem-mem@86000000 { 415 reg = <0x0 0x86000000 0x0 0x200000>; 416 no-map; 417 }; 418 419 tz_mem: memory@86200000 { 420 reg = <0x0 0x86200000 0x0 0x2600000>; 421 no-map; 422 }; 423 424 rmtfs_mem: rmtfs { 425 compatible = "qcom,rmtfs-mem"; 426 427 size = <0x0 0x200000>; 428 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 429 no-map; 430 431 qcom,client-id = <1>; 432 qcom,vmid = <15>; 433 }; 434 435 mpss_mem: mpss@88800000 { 436 reg = <0x0 0x88800000 0x0 0x6200000>; 437 no-map; 438 }; 439 440 adsp_mem: adsp@8ea00000 { 441 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 442 no-map; 443 }; 444 445 slpi_mem: slpi@90500000 { 446 reg = <0x0 0x90500000 0x0 0xa00000>; 447 no-map; 448 }; 449 450 gpu_mem: gpu@90f00000 { 451 compatible = "shared-dma-pool"; 452 reg = <0x0 0x90f00000 0x0 0x100000>; 453 no-map; 454 }; 455 456 venus_mem: venus@91000000 { 457 reg = <0x0 0x91000000 0x0 0x500000>; 458 no-map; 459 }; 460 461 mba_mem: mba@91500000 { 462 reg = <0x0 0x91500000 0x0 0x200000>; 463 no-map; 464 }; 465 466 mdata_mem: mpss-metadata { 467 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 468 size = <0x0 0x4000>; 469 no-map; 470 }; 471 }; 472 473 rpm-glink { 474 compatible = "qcom,glink-rpm"; 475 476 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 477 478 qcom,rpm-msg-ram = <&rpm_msg_ram>; 479 480 mboxes = <&apcs_glb 0>; 481 482 rpm_requests: rpm-requests { 483 compatible = "qcom,rpm-msm8996"; 484 qcom,glink-channels = "rpm_requests"; 485 486 rpmcc: clock-controller { 487 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 488 #clock-cells = <1>; 489 clocks = <&xo_board>; 490 clock-names = "xo"; 491 }; 492 493 rpmpd: power-controller { 494 compatible = "qcom,msm8996-rpmpd"; 495 #power-domain-cells = <1>; 496 operating-points-v2 = <&rpmpd_opp_table>; 497 498 rpmpd_opp_table: opp-table { 499 compatible = "operating-points-v2"; 500 501 rpmpd_opp1: opp1 { 502 opp-level = <1>; 503 }; 504 505 rpmpd_opp2: opp2 { 506 opp-level = <2>; 507 }; 508 509 rpmpd_opp3: opp3 { 510 opp-level = <3>; 511 }; 512 513 rpmpd_opp4: opp4 { 514 opp-level = <4>; 515 }; 516 517 rpmpd_opp5: opp5 { 518 opp-level = <5>; 519 }; 520 521 rpmpd_opp6: opp6 { 522 opp-level = <6>; 523 }; 524 }; 525 }; 526 }; 527 }; 528 529 smem { 530 compatible = "qcom,smem"; 531 memory-region = <&smem_mem>; 532 hwlocks = <&tcsr_mutex 3>; 533 }; 534 535 smp2p-adsp { 536 compatible = "qcom,smp2p"; 537 qcom,smem = <443>, <429>; 538 539 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 540 541 mboxes = <&apcs_glb 10>; 542 543 qcom,local-pid = <0>; 544 qcom,remote-pid = <2>; 545 546 adsp_smp2p_out: master-kernel { 547 qcom,entry-name = "master-kernel"; 548 #qcom,smem-state-cells = <1>; 549 }; 550 551 adsp_smp2p_in: slave-kernel { 552 qcom,entry-name = "slave-kernel"; 553 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 }; 557 }; 558 559 smp2p-mpss { 560 compatible = "qcom,smp2p"; 561 qcom,smem = <435>, <428>; 562 563 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 564 565 mboxes = <&apcs_glb 14>; 566 567 qcom,local-pid = <0>; 568 qcom,remote-pid = <1>; 569 570 mpss_smp2p_out: master-kernel { 571 qcom,entry-name = "master-kernel"; 572 #qcom,smem-state-cells = <1>; 573 }; 574 575 mpss_smp2p_in: slave-kernel { 576 qcom,entry-name = "slave-kernel"; 577 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 }; 581 }; 582 583 smp2p-slpi { 584 compatible = "qcom,smp2p"; 585 qcom,smem = <481>, <430>; 586 587 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 588 589 mboxes = <&apcs_glb 26>; 590 591 qcom,local-pid = <0>; 592 qcom,remote-pid = <3>; 593 594 slpi_smp2p_out: master-kernel { 595 qcom,entry-name = "master-kernel"; 596 #qcom,smem-state-cells = <1>; 597 }; 598 599 slpi_smp2p_in: slave-kernel { 600 qcom,entry-name = "slave-kernel"; 601 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 }; 606 607 soc: soc { 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0 0 0 0xffffffff>; 611 compatible = "simple-bus"; 612 613 pcie_phy: phy-wrapper@34000 { 614 compatible = "qcom,msm8996-qmp-pcie-phy"; 615 reg = <0x00034000 0x488>; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0x0 0x00034000 0x4000>; 619 620 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 621 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 622 <&gcc GCC_PCIE_CLKREF_CLK>; 623 clock-names = "aux", "cfg_ahb", "ref"; 624 625 resets = <&gcc GCC_PCIE_PHY_BCR>, 626 <&gcc GCC_PCIE_PHY_COM_BCR>, 627 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 628 reset-names = "phy", "common", "cfg"; 629 630 status = "disabled"; 631 632 pciephy_0: phy@1000 { 633 reg = <0x1000 0x130>, 634 <0x1200 0x200>, 635 <0x1400 0x1dc>; 636 637 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 638 clock-names = "pipe0"; 639 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 640 reset-names = "lane0"; 641 642 #clock-cells = <0>; 643 clock-output-names = "pcie_0_pipe_clk_src"; 644 645 #phy-cells = <0>; 646 }; 647 648 pciephy_1: phy@2000 { 649 reg = <0x2000 0x130>, 650 <0x2200 0x200>, 651 <0x2400 0x1dc>; 652 653 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 654 clock-names = "pipe1"; 655 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 656 reset-names = "lane1"; 657 658 #clock-cells = <0>; 659 clock-output-names = "pcie_1_pipe_clk_src"; 660 661 #phy-cells = <0>; 662 }; 663 664 pciephy_2: phy@3000 { 665 reg = <0x3000 0x130>, 666 <0x3200 0x200>, 667 <0x3400 0x1dc>; 668 669 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 670 clock-names = "pipe2"; 671 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 672 reset-names = "lane2"; 673 674 #clock-cells = <0>; 675 clock-output-names = "pcie_2_pipe_clk_src"; 676 677 #phy-cells = <0>; 678 }; 679 }; 680 681 rpm_msg_ram: sram@68000 { 682 compatible = "qcom,rpm-msg-ram"; 683 reg = <0x00068000 0x6000>; 684 }; 685 686 qfprom@74000 { 687 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 688 reg = <0x00074000 0x8ff>; 689 #address-cells = <1>; 690 #size-cells = <1>; 691 692 qusb2p_hstx_trim: hstx_trim@24e { 693 reg = <0x24e 0x2>; 694 bits = <5 4>; 695 }; 696 697 qusb2s_hstx_trim: hstx_trim@24f { 698 reg = <0x24f 0x1>; 699 bits = <1 4>; 700 }; 701 702 speedbin_efuse: speedbin@133 { 703 reg = <0x133 0x1>; 704 bits = <5 3>; 705 }; 706 }; 707 708 rng: rng@83000 { 709 compatible = "qcom,prng-ee"; 710 reg = <0x00083000 0x1000>; 711 clocks = <&gcc GCC_PRNG_AHB_CLK>; 712 clock-names = "core"; 713 }; 714 715 gcc: clock-controller@300000 { 716 compatible = "qcom,gcc-msm8996"; 717 #clock-cells = <1>; 718 #reset-cells = <1>; 719 #power-domain-cells = <1>; 720 reg = <0x00300000 0x90000>; 721 722 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 723 <&rpmcc RPM_SMD_LN_BB_CLK>, 724 <&sleep_clk>, 725 <&pciephy_0>, 726 <&pciephy_1>, 727 <&pciephy_2>, 728 <&ssusb_phy_0>, 729 <&ufsphy_lane 0>, 730 <&ufsphy_lane 1>, 731 <&ufsphy_lane 2>; 732 clock-names = "cxo", 733 "cxo2", 734 "sleep_clk", 735 "pcie_0_pipe_clk_src", 736 "pcie_1_pipe_clk_src", 737 "pcie_2_pipe_clk_src", 738 "usb3_phy_pipe_clk_src", 739 "ufs_rx_symbol_0_clk_src", 740 "ufs_rx_symbol_1_clk_src", 741 "ufs_tx_symbol_0_clk_src"; 742 }; 743 744 bimc: interconnect@408000 { 745 compatible = "qcom,msm8996-bimc"; 746 reg = <0x00408000 0x5a000>; 747 #interconnect-cells = <1>; 748 clock-names = "bus", "bus_a"; 749 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 750 <&rpmcc RPM_SMD_BIMC_A_CLK>; 751 }; 752 753 tsens0: thermal-sensor@4a9000 { 754 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 755 reg = <0x004a9000 0x1000>, /* TM */ 756 <0x004a8000 0x1000>; /* SROT */ 757 #qcom,sensors = <13>; 758 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 760 interrupt-names = "uplow", "critical"; 761 #thermal-sensor-cells = <1>; 762 }; 763 764 tsens1: thermal-sensor@4ad000 { 765 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 766 reg = <0x004ad000 0x1000>, /* TM */ 767 <0x004ac000 0x1000>; /* SROT */ 768 #qcom,sensors = <8>; 769 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 771 interrupt-names = "uplow", "critical"; 772 #thermal-sensor-cells = <1>; 773 }; 774 775 cryptobam: dma-controller@644000 { 776 compatible = "qcom,bam-v1.7.0"; 777 reg = <0x00644000 0x24000>; 778 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&gcc GCC_CE1_CLK>; 780 clock-names = "bam_clk"; 781 #dma-cells = <1>; 782 qcom,ee = <0>; 783 qcom,controlled-remotely; 784 }; 785 786 crypto: crypto@67a000 { 787 compatible = "qcom,crypto-v5.4"; 788 reg = <0x0067a000 0x6000>; 789 clocks = <&gcc GCC_CE1_AHB_CLK>, 790 <&gcc GCC_CE1_AXI_CLK>, 791 <&gcc GCC_CE1_CLK>; 792 clock-names = "iface", "bus", "core"; 793 dmas = <&cryptobam 6>, <&cryptobam 7>; 794 dma-names = "rx", "tx"; 795 }; 796 797 cnoc: interconnect@500000 { 798 compatible = "qcom,msm8996-cnoc"; 799 reg = <0x00500000 0x1000>; 800 #interconnect-cells = <1>; 801 clock-names = "bus", "bus_a"; 802 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 803 <&rpmcc RPM_SMD_CNOC_A_CLK>; 804 }; 805 806 snoc: interconnect@524000 { 807 compatible = "qcom,msm8996-snoc"; 808 reg = <0x00524000 0x1c000>; 809 #interconnect-cells = <1>; 810 clock-names = "bus", "bus_a"; 811 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 812 <&rpmcc RPM_SMD_SNOC_A_CLK>; 813 }; 814 815 a0noc: interconnect@543000 { 816 compatible = "qcom,msm8996-a0noc"; 817 reg = <0x00543000 0x6000>; 818 #interconnect-cells = <1>; 819 clock-names = "aggre0_snoc_axi", 820 "aggre0_cnoc_ahb", 821 "aggre0_noc_mpu_cfg"; 822 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 823 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 824 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 825 power-domains = <&gcc AGGRE0_NOC_GDSC>; 826 }; 827 828 a1noc: interconnect@562000 { 829 compatible = "qcom,msm8996-a1noc"; 830 reg = <0x00562000 0x5000>; 831 #interconnect-cells = <1>; 832 clock-names = "bus", "bus_a"; 833 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 834 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 835 }; 836 837 a2noc: interconnect@583000 { 838 compatible = "qcom,msm8996-a2noc"; 839 reg = <0x00583000 0x7000>; 840 #interconnect-cells = <1>; 841 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; 842 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 843 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 844 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 845 <&gcc GCC_UFS_AXI_CLK>; 846 }; 847 848 mnoc: interconnect@5a4000 { 849 compatible = "qcom,msm8996-mnoc"; 850 reg = <0x005a4000 0x1c000>; 851 #interconnect-cells = <1>; 852 clock-names = "bus", "bus_a", "iface"; 853 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 854 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 855 <&mmcc AHB_CLK_SRC>; 856 }; 857 858 pnoc: interconnect@5c0000 { 859 compatible = "qcom,msm8996-pnoc"; 860 reg = <0x005c0000 0x3000>; 861 #interconnect-cells = <1>; 862 clock-names = "bus", "bus_a"; 863 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 864 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 865 }; 866 867 tcsr_mutex: hwlock@740000 { 868 compatible = "qcom,tcsr-mutex"; 869 reg = <0x00740000 0x20000>; 870 #hwlock-cells = <1>; 871 }; 872 873 tcsr_1: syscon@760000 { 874 compatible = "qcom,tcsr-msm8996", "syscon"; 875 reg = <0x00760000 0x20000>; 876 }; 877 878 tcsr_2: syscon@7a0000 { 879 compatible = "qcom,tcsr-msm8996", "syscon"; 880 reg = <0x007a0000 0x18000>; 881 }; 882 883 mmcc: clock-controller@8c0000 { 884 compatible = "qcom,mmcc-msm8996"; 885 #clock-cells = <1>; 886 #reset-cells = <1>; 887 #power-domain-cells = <1>; 888 reg = <0x008c0000 0x40000>; 889 clocks = <&xo_board>, 890 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 891 <&gcc GPLL0>, 892 <&dsi0_phy 1>, 893 <&dsi0_phy 0>, 894 <&dsi1_phy 1>, 895 <&dsi1_phy 0>, 896 <&hdmi_phy>; 897 clock-names = "xo", 898 "gcc_mmss_noc_cfg_ahb_clk", 899 "gpll0", 900 "dsi0pll", 901 "dsi0pllbyte", 902 "dsi1pll", 903 "dsi1pllbyte", 904 "hdmipll"; 905 assigned-clocks = <&mmcc MMPLL9_PLL>, 906 <&mmcc MMPLL1_PLL>, 907 <&mmcc MMPLL3_PLL>, 908 <&mmcc MMPLL4_PLL>, 909 <&mmcc MMPLL5_PLL>; 910 assigned-clock-rates = <624000000>, 911 <810000000>, 912 <980000000>, 913 <960000000>, 914 <825000000>; 915 }; 916 917 mdss: display-subsystem@900000 { 918 compatible = "qcom,mdss"; 919 920 reg = <0x00900000 0x1000>, 921 <0x009b0000 0x1040>, 922 <0x009b8000 0x1040>; 923 reg-names = "mdss_phys", 924 "vbif_phys", 925 "vbif_nrt_phys"; 926 927 power-domains = <&mmcc MDSS_GDSC>; 928 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 929 930 interrupt-controller; 931 #interrupt-cells = <1>; 932 933 clocks = <&mmcc MDSS_AHB_CLK>, 934 <&mmcc MDSS_MDP_CLK>; 935 clock-names = "iface", "core"; 936 937 #address-cells = <1>; 938 #size-cells = <1>; 939 ranges; 940 941 status = "disabled"; 942 943 mdp: display-controller@901000 { 944 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 945 reg = <0x00901000 0x90000>; 946 reg-names = "mdp_phys"; 947 948 interrupt-parent = <&mdss>; 949 interrupts = <0>; 950 951 clocks = <&mmcc MDSS_AHB_CLK>, 952 <&mmcc MDSS_AXI_CLK>, 953 <&mmcc MDSS_MDP_CLK>, 954 <&mmcc SMMU_MDP_AXI_CLK>, 955 <&mmcc MDSS_VSYNC_CLK>; 956 clock-names = "iface", 957 "bus", 958 "core", 959 "iommu", 960 "vsync"; 961 962 iommus = <&mdp_smmu 0>; 963 964 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 965 <&mmcc MDSS_VSYNC_CLK>; 966 assigned-clock-rates = <300000000>, 967 <19200000>; 968 969 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 970 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 971 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 972 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 973 974 ports { 975 #address-cells = <1>; 976 #size-cells = <0>; 977 978 port@0 { 979 reg = <0>; 980 mdp5_intf3_out: endpoint { 981 remote-endpoint = <&hdmi_in>; 982 }; 983 }; 984 985 port@1 { 986 reg = <1>; 987 mdp5_intf1_out: endpoint { 988 remote-endpoint = <&dsi0_in>; 989 }; 990 }; 991 992 port@2 { 993 reg = <2>; 994 mdp5_intf2_out: endpoint { 995 remote-endpoint = <&dsi1_in>; 996 }; 997 }; 998 }; 999 }; 1000 1001 dsi0: dsi@994000 { 1002 compatible = "qcom,msm8996-dsi-ctrl", 1003 "qcom,mdss-dsi-ctrl"; 1004 reg = <0x00994000 0x400>; 1005 reg-names = "dsi_ctrl"; 1006 1007 interrupt-parent = <&mdss>; 1008 interrupts = <4>; 1009 1010 clocks = <&mmcc MDSS_MDP_CLK>, 1011 <&mmcc MDSS_BYTE0_CLK>, 1012 <&mmcc MDSS_AHB_CLK>, 1013 <&mmcc MDSS_AXI_CLK>, 1014 <&mmcc MMSS_MISC_AHB_CLK>, 1015 <&mmcc MDSS_PCLK0_CLK>, 1016 <&mmcc MDSS_ESC0_CLK>; 1017 clock-names = "mdp_core", 1018 "byte", 1019 "iface", 1020 "bus", 1021 "core_mmss", 1022 "pixel", 1023 "core"; 1024 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1025 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1026 1027 phys = <&dsi0_phy>; 1028 status = "disabled"; 1029 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 1033 ports { 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 port@0 { 1038 reg = <0>; 1039 dsi0_in: endpoint { 1040 remote-endpoint = <&mdp5_intf1_out>; 1041 }; 1042 }; 1043 1044 port@1 { 1045 reg = <1>; 1046 dsi0_out: endpoint { 1047 }; 1048 }; 1049 }; 1050 }; 1051 1052 dsi0_phy: phy@994400 { 1053 compatible = "qcom,dsi-phy-14nm"; 1054 reg = <0x00994400 0x100>, 1055 <0x00994500 0x300>, 1056 <0x00994800 0x188>; 1057 reg-names = "dsi_phy", 1058 "dsi_phy_lane", 1059 "dsi_pll"; 1060 1061 #clock-cells = <1>; 1062 #phy-cells = <0>; 1063 1064 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1065 clock-names = "iface", "ref"; 1066 status = "disabled"; 1067 }; 1068 1069 dsi1: dsi@996000 { 1070 compatible = "qcom,msm8996-dsi-ctrl", 1071 "qcom,mdss-dsi-ctrl"; 1072 reg = <0x00996000 0x400>; 1073 reg-names = "dsi_ctrl"; 1074 1075 interrupt-parent = <&mdss>; 1076 interrupts = <4>; 1077 1078 clocks = <&mmcc MDSS_MDP_CLK>, 1079 <&mmcc MDSS_BYTE1_CLK>, 1080 <&mmcc MDSS_AHB_CLK>, 1081 <&mmcc MDSS_AXI_CLK>, 1082 <&mmcc MMSS_MISC_AHB_CLK>, 1083 <&mmcc MDSS_PCLK1_CLK>, 1084 <&mmcc MDSS_ESC1_CLK>; 1085 clock-names = "mdp_core", 1086 "byte", 1087 "iface", 1088 "bus", 1089 "core_mmss", 1090 "pixel", 1091 "core"; 1092 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1093 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 1094 1095 phys = <&dsi1_phy>; 1096 status = "disabled"; 1097 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 1101 ports { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 1105 port@0 { 1106 reg = <0>; 1107 dsi1_in: endpoint { 1108 remote-endpoint = <&mdp5_intf2_out>; 1109 }; 1110 }; 1111 1112 port@1 { 1113 reg = <1>; 1114 dsi1_out: endpoint { 1115 }; 1116 }; 1117 }; 1118 }; 1119 1120 dsi1_phy: phy@996400 { 1121 compatible = "qcom,dsi-phy-14nm"; 1122 reg = <0x00996400 0x100>, 1123 <0x00996500 0x300>, 1124 <0x00996800 0x188>; 1125 reg-names = "dsi_phy", 1126 "dsi_phy_lane", 1127 "dsi_pll"; 1128 1129 #clock-cells = <1>; 1130 #phy-cells = <0>; 1131 1132 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1133 clock-names = "iface", "ref"; 1134 status = "disabled"; 1135 }; 1136 1137 hdmi: hdmi-tx@9a0000 { 1138 compatible = "qcom,hdmi-tx-8996"; 1139 reg = <0x009a0000 0x50c>, 1140 <0x00070000 0x6158>, 1141 <0x009e0000 0xfff>; 1142 reg-names = "core_physical", 1143 "qfprom_physical", 1144 "hdcp_physical"; 1145 1146 interrupt-parent = <&mdss>; 1147 interrupts = <8>; 1148 1149 clocks = <&mmcc MDSS_MDP_CLK>, 1150 <&mmcc MDSS_AHB_CLK>, 1151 <&mmcc MDSS_HDMI_CLK>, 1152 <&mmcc MDSS_HDMI_AHB_CLK>, 1153 <&mmcc MDSS_EXTPCLK_CLK>; 1154 clock-names = 1155 "mdp_core", 1156 "iface", 1157 "core", 1158 "alt_iface", 1159 "extp"; 1160 1161 phys = <&hdmi_phy>; 1162 #sound-dai-cells = <1>; 1163 1164 status = "disabled"; 1165 1166 ports { 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 1170 port@0 { 1171 reg = <0>; 1172 hdmi_in: endpoint { 1173 remote-endpoint = <&mdp5_intf3_out>; 1174 }; 1175 }; 1176 }; 1177 }; 1178 1179 hdmi_phy: phy@9a0600 { 1180 #phy-cells = <0>; 1181 compatible = "qcom,hdmi-phy-8996"; 1182 reg = <0x009a0600 0x1c4>, 1183 <0x009a0a00 0x124>, 1184 <0x009a0c00 0x124>, 1185 <0x009a0e00 0x124>, 1186 <0x009a1000 0x124>, 1187 <0x009a1200 0x0c8>; 1188 reg-names = "hdmi_pll", 1189 "hdmi_tx_l0", 1190 "hdmi_tx_l1", 1191 "hdmi_tx_l2", 1192 "hdmi_tx_l3", 1193 "hdmi_phy"; 1194 1195 clocks = <&mmcc MDSS_AHB_CLK>, 1196 <&gcc GCC_HDMI_CLKREF_CLK>, 1197 <&xo_board>; 1198 clock-names = "iface", 1199 "ref", 1200 "xo"; 1201 1202 #clock-cells = <0>; 1203 1204 status = "disabled"; 1205 }; 1206 }; 1207 1208 gpu: gpu@b00000 { 1209 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1210 1211 reg = <0x00b00000 0x3f000>; 1212 reg-names = "kgsl_3d0_reg_memory"; 1213 1214 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1215 1216 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1217 <&mmcc GPU_AHB_CLK>, 1218 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1219 <&gcc GCC_BIMC_GFX_CLK>, 1220 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1221 1222 clock-names = "core", 1223 "iface", 1224 "rbbmtimer", 1225 "mem", 1226 "mem_iface"; 1227 1228 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1229 interconnect-names = "gfx-mem"; 1230 1231 power-domains = <&mmcc GPU_GX_GDSC>; 1232 iommus = <&adreno_smmu 0>; 1233 1234 nvmem-cells = <&speedbin_efuse>; 1235 nvmem-cell-names = "speed_bin"; 1236 1237 operating-points-v2 = <&gpu_opp_table>; 1238 1239 status = "disabled"; 1240 1241 #cooling-cells = <2>; 1242 1243 gpu_opp_table: opp-table { 1244 compatible = "operating-points-v2"; 1245 1246 /* 1247 * 624Mhz is only available on speed bins 0 and 3. 1248 * 560Mhz is only available on speed bins 0, 2 and 3. 1249 * All the rest are available on all bins of the hardware. 1250 */ 1251 opp-624000000 { 1252 opp-hz = /bits/ 64 <624000000>; 1253 opp-supported-hw = <0x09>; 1254 }; 1255 opp-560000000 { 1256 opp-hz = /bits/ 64 <560000000>; 1257 opp-supported-hw = <0x0d>; 1258 }; 1259 opp-510000000 { 1260 opp-hz = /bits/ 64 <510000000>; 1261 opp-supported-hw = <0xff>; 1262 }; 1263 opp-401800000 { 1264 opp-hz = /bits/ 64 <401800000>; 1265 opp-supported-hw = <0xff>; 1266 }; 1267 opp-315000000 { 1268 opp-hz = /bits/ 64 <315000000>; 1269 opp-supported-hw = <0xff>; 1270 }; 1271 opp-214000000 { 1272 opp-hz = /bits/ 64 <214000000>; 1273 opp-supported-hw = <0xff>; 1274 }; 1275 opp-133000000 { 1276 opp-hz = /bits/ 64 <133000000>; 1277 opp-supported-hw = <0xff>; 1278 }; 1279 }; 1280 1281 zap-shader { 1282 memory-region = <&gpu_mem>; 1283 }; 1284 }; 1285 1286 tlmm: pinctrl@1010000 { 1287 compatible = "qcom,msm8996-pinctrl"; 1288 reg = <0x01010000 0x300000>; 1289 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1290 gpio-controller; 1291 gpio-ranges = <&tlmm 0 0 150>; 1292 #gpio-cells = <2>; 1293 interrupt-controller; 1294 #interrupt-cells = <2>; 1295 1296 blsp1_spi1_default: blsp1-spi1-default-state { 1297 spi-pins { 1298 pins = "gpio0", "gpio1", "gpio3"; 1299 function = "blsp_spi1"; 1300 drive-strength = <12>; 1301 bias-disable; 1302 }; 1303 1304 cs-pins { 1305 pins = "gpio2"; 1306 function = "gpio"; 1307 drive-strength = <16>; 1308 bias-disable; 1309 output-high; 1310 }; 1311 }; 1312 1313 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1314 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1315 function = "gpio"; 1316 drive-strength = <2>; 1317 bias-pull-down; 1318 }; 1319 1320 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1321 pins = "gpio4", "gpio5"; 1322 function = "blsp_uart8"; 1323 drive-strength = <16>; 1324 bias-disable; 1325 }; 1326 1327 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1328 pins = "gpio4", "gpio5"; 1329 function = "gpio"; 1330 drive-strength = <2>; 1331 bias-disable; 1332 }; 1333 1334 blsp2_i2c2_default: blsp2-i2c2-state { 1335 pins = "gpio6", "gpio7"; 1336 function = "blsp_i2c8"; 1337 drive-strength = <16>; 1338 bias-disable; 1339 }; 1340 1341 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1342 pins = "gpio6", "gpio7"; 1343 function = "gpio"; 1344 drive-strength = <2>; 1345 bias-disable; 1346 }; 1347 1348 blsp1_i2c6_default: blsp1-i2c6-state { 1349 pins = "gpio27", "gpio28"; 1350 function = "blsp_i2c6"; 1351 drive-strength = <16>; 1352 bias-disable; 1353 }; 1354 1355 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1356 pins = "gpio27", "gpio28"; 1357 function = "gpio"; 1358 drive-strength = <2>; 1359 bias-pull-up; 1360 }; 1361 1362 cci0_default: cci0-default-state { 1363 pins = "gpio17", "gpio18"; 1364 function = "cci_i2c"; 1365 drive-strength = <16>; 1366 bias-disable; 1367 }; 1368 1369 camera0_state_on: 1370 camera_rear_default: camera-rear-default-state { 1371 camera0_mclk: mclk0-pins { 1372 pins = "gpio13"; 1373 function = "cam_mclk"; 1374 drive-strength = <16>; 1375 bias-disable; 1376 }; 1377 1378 camera0_rst: rst-pins { 1379 pins = "gpio25"; 1380 function = "gpio"; 1381 drive-strength = <16>; 1382 bias-disable; 1383 }; 1384 1385 camera0_pwdn: pwdn-pins { 1386 pins = "gpio26"; 1387 function = "gpio"; 1388 drive-strength = <16>; 1389 bias-disable; 1390 }; 1391 }; 1392 1393 cci1_default: cci1-default-state { 1394 pins = "gpio19", "gpio20"; 1395 function = "cci_i2c"; 1396 drive-strength = <16>; 1397 bias-disable; 1398 }; 1399 1400 camera1_state_on: 1401 camera_board_default: camera-board-default-state { 1402 mclk1-pins { 1403 pins = "gpio14"; 1404 function = "cam_mclk"; 1405 drive-strength = <16>; 1406 bias-disable; 1407 }; 1408 1409 pwdn-pins { 1410 pins = "gpio98"; 1411 function = "gpio"; 1412 drive-strength = <16>; 1413 bias-disable; 1414 }; 1415 1416 rst-pins { 1417 pins = "gpio104"; 1418 function = "gpio"; 1419 drive-strength = <16>; 1420 bias-disable; 1421 }; 1422 }; 1423 1424 camera2_state_on: 1425 camera_front_default: camera-front-default-state { 1426 camera2_mclk: mclk2-pins { 1427 pins = "gpio15"; 1428 function = "cam_mclk"; 1429 drive-strength = <16>; 1430 bias-disable; 1431 }; 1432 1433 camera2_rst: rst-pins { 1434 pins = "gpio23"; 1435 function = "gpio"; 1436 drive-strength = <16>; 1437 bias-disable; 1438 }; 1439 1440 pwdn-pins { 1441 pins = "gpio133"; 1442 function = "gpio"; 1443 drive-strength = <16>; 1444 bias-disable; 1445 }; 1446 }; 1447 1448 pcie0_state_on: pcie0-state-on-state { 1449 perst-pins { 1450 pins = "gpio35"; 1451 function = "gpio"; 1452 drive-strength = <2>; 1453 bias-pull-down; 1454 }; 1455 1456 clkreq-pins { 1457 pins = "gpio36"; 1458 function = "pci_e0"; 1459 drive-strength = <2>; 1460 bias-pull-up; 1461 }; 1462 1463 wake-pins { 1464 pins = "gpio37"; 1465 function = "gpio"; 1466 drive-strength = <2>; 1467 bias-pull-up; 1468 }; 1469 }; 1470 1471 pcie0_state_off: pcie0-state-off-state { 1472 perst-pins { 1473 pins = "gpio35"; 1474 function = "gpio"; 1475 drive-strength = <2>; 1476 bias-pull-down; 1477 }; 1478 1479 clkreq-pins { 1480 pins = "gpio36"; 1481 function = "gpio"; 1482 drive-strength = <2>; 1483 bias-disable; 1484 }; 1485 1486 wake-pins { 1487 pins = "gpio37"; 1488 function = "gpio"; 1489 drive-strength = <2>; 1490 bias-disable; 1491 }; 1492 }; 1493 1494 blsp1_uart2_default: blsp1-uart2-default-state { 1495 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1496 function = "blsp_uart2"; 1497 drive-strength = <16>; 1498 bias-disable; 1499 }; 1500 1501 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1502 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1503 function = "gpio"; 1504 drive-strength = <2>; 1505 bias-disable; 1506 }; 1507 1508 blsp1_i2c3_default: blsp1-i2c3-default-state { 1509 pins = "gpio47", "gpio48"; 1510 function = "blsp_i2c3"; 1511 drive-strength = <16>; 1512 bias-disable; 1513 }; 1514 1515 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1516 pins = "gpio47", "gpio48"; 1517 function = "gpio"; 1518 drive-strength = <2>; 1519 bias-disable; 1520 }; 1521 1522 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1523 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1524 function = "blsp_uart9"; 1525 drive-strength = <16>; 1526 bias-disable; 1527 }; 1528 1529 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1530 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1531 function = "blsp_uart9"; 1532 drive-strength = <2>; 1533 bias-disable; 1534 }; 1535 1536 blsp2_i2c3_default: blsp2-i2c3-state-state { 1537 pins = "gpio51", "gpio52"; 1538 function = "blsp_i2c9"; 1539 drive-strength = <16>; 1540 bias-disable; 1541 }; 1542 1543 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1544 pins = "gpio51", "gpio52"; 1545 function = "gpio"; 1546 drive-strength = <2>; 1547 bias-disable; 1548 }; 1549 1550 wcd_intr_default: wcd-intr-default-state { 1551 pins = "gpio54"; 1552 function = "gpio"; 1553 drive-strength = <2>; 1554 bias-pull-down; 1555 }; 1556 1557 blsp2_i2c1_default: blsp2-i2c1-state { 1558 pins = "gpio55", "gpio56"; 1559 function = "blsp_i2c7"; 1560 drive-strength = <16>; 1561 bias-disable; 1562 }; 1563 1564 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1565 pins = "gpio55", "gpio56"; 1566 function = "gpio"; 1567 drive-strength = <2>; 1568 bias-disable; 1569 }; 1570 1571 blsp2_i2c5_default: blsp2-i2c5-state { 1572 pins = "gpio60", "gpio61"; 1573 function = "blsp_i2c11"; 1574 drive-strength = <2>; 1575 bias-disable; 1576 }; 1577 1578 /* Sleep state for BLSP2_I2C5 is missing.. */ 1579 1580 cdc_reset_active: cdc-reset-active-state { 1581 pins = "gpio64"; 1582 function = "gpio"; 1583 drive-strength = <16>; 1584 bias-pull-down; 1585 output-high; 1586 }; 1587 1588 cdc_reset_sleep: cdc-reset-sleep-state { 1589 pins = "gpio64"; 1590 function = "gpio"; 1591 drive-strength = <16>; 1592 bias-disable; 1593 output-low; 1594 }; 1595 1596 blsp2_spi6_default: blsp2-spi6-default-state { 1597 spi-pins { 1598 pins = "gpio85", "gpio86", "gpio88"; 1599 function = "blsp_spi12"; 1600 drive-strength = <12>; 1601 bias-disable; 1602 }; 1603 1604 cs-pins { 1605 pins = "gpio87"; 1606 function = "gpio"; 1607 drive-strength = <16>; 1608 bias-disable; 1609 output-high; 1610 }; 1611 }; 1612 1613 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1614 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1615 function = "gpio"; 1616 drive-strength = <2>; 1617 bias-pull-down; 1618 }; 1619 1620 blsp2_i2c6_default: blsp2-i2c6-state { 1621 pins = "gpio87", "gpio88"; 1622 function = "blsp_i2c12"; 1623 drive-strength = <16>; 1624 bias-disable; 1625 }; 1626 1627 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1628 pins = "gpio87", "gpio88"; 1629 function = "gpio"; 1630 drive-strength = <2>; 1631 bias-disable; 1632 }; 1633 1634 pcie1_state_on: pcie1-on-state { 1635 perst-pins { 1636 pins = "gpio130"; 1637 function = "gpio"; 1638 drive-strength = <2>; 1639 bias-pull-down; 1640 }; 1641 1642 clkreq-pins { 1643 pins = "gpio131"; 1644 function = "pci_e1"; 1645 drive-strength = <2>; 1646 bias-pull-up; 1647 }; 1648 1649 wake-pins { 1650 pins = "gpio132"; 1651 function = "gpio"; 1652 drive-strength = <2>; 1653 bias-pull-down; 1654 }; 1655 }; 1656 1657 pcie1_state_off: pcie1-off-state { 1658 /* Perst is missing? */ 1659 clkreq-pins { 1660 pins = "gpio131"; 1661 function = "gpio"; 1662 drive-strength = <2>; 1663 bias-disable; 1664 }; 1665 1666 wake-pins { 1667 pins = "gpio132"; 1668 function = "gpio"; 1669 drive-strength = <2>; 1670 bias-disable; 1671 }; 1672 }; 1673 1674 pcie2_state_on: pcie2-on-state { 1675 perst-pins { 1676 pins = "gpio114"; 1677 function = "gpio"; 1678 drive-strength = <2>; 1679 bias-pull-down; 1680 }; 1681 1682 clkreq-pins { 1683 pins = "gpio115"; 1684 function = "pci_e2"; 1685 drive-strength = <2>; 1686 bias-pull-up; 1687 }; 1688 1689 wake-pins { 1690 pins = "gpio116"; 1691 function = "gpio"; 1692 drive-strength = <2>; 1693 bias-pull-down; 1694 }; 1695 }; 1696 1697 pcie2_state_off: pcie2-off-state { 1698 /* Perst is missing? */ 1699 clkreq-pins { 1700 pins = "gpio115"; 1701 function = "gpio"; 1702 drive-strength = <2>; 1703 bias-disable; 1704 }; 1705 1706 wake-pins { 1707 pins = "gpio116"; 1708 function = "gpio"; 1709 drive-strength = <2>; 1710 bias-disable; 1711 }; 1712 }; 1713 1714 sdc1_state_on: sdc1-on-state { 1715 clk-pins { 1716 pins = "sdc1_clk"; 1717 bias-disable; 1718 drive-strength = <16>; 1719 }; 1720 1721 cmd-pins { 1722 pins = "sdc1_cmd"; 1723 bias-pull-up; 1724 drive-strength = <10>; 1725 }; 1726 1727 data-pins { 1728 pins = "sdc1_data"; 1729 bias-pull-up; 1730 drive-strength = <10>; 1731 }; 1732 1733 rclk-pins { 1734 pins = "sdc1_rclk"; 1735 bias-pull-down; 1736 }; 1737 }; 1738 1739 sdc1_state_off: sdc1-off-state { 1740 clk-pins { 1741 pins = "sdc1_clk"; 1742 bias-disable; 1743 drive-strength = <2>; 1744 }; 1745 1746 cmd-pins { 1747 pins = "sdc1_cmd"; 1748 bias-pull-up; 1749 drive-strength = <2>; 1750 }; 1751 1752 data-pins { 1753 pins = "sdc1_data"; 1754 bias-pull-up; 1755 drive-strength = <2>; 1756 }; 1757 1758 rclk-pins { 1759 pins = "sdc1_rclk"; 1760 bias-pull-down; 1761 }; 1762 }; 1763 1764 sdc2_state_on: sdc2-on-state { 1765 clk-pins { 1766 pins = "sdc2_clk"; 1767 bias-disable; 1768 drive-strength = <16>; 1769 }; 1770 1771 cmd-pins { 1772 pins = "sdc2_cmd"; 1773 bias-pull-up; 1774 drive-strength = <10>; 1775 }; 1776 1777 data-pins { 1778 pins = "sdc2_data"; 1779 bias-pull-up; 1780 drive-strength = <10>; 1781 }; 1782 }; 1783 1784 sdc2_state_off: sdc2-off-state { 1785 clk-pins { 1786 pins = "sdc2_clk"; 1787 bias-disable; 1788 drive-strength = <2>; 1789 }; 1790 1791 cmd-pins { 1792 pins = "sdc2_cmd"; 1793 bias-pull-up; 1794 drive-strength = <2>; 1795 }; 1796 1797 data-pins { 1798 pins = "sdc2_data"; 1799 bias-pull-up; 1800 drive-strength = <2>; 1801 }; 1802 }; 1803 }; 1804 1805 sram@290000 { 1806 compatible = "qcom,rpm-stats"; 1807 reg = <0x00290000 0x10000>; 1808 }; 1809 1810 spmi_bus: spmi@400f000 { 1811 compatible = "qcom,spmi-pmic-arb"; 1812 reg = <0x0400f000 0x1000>, 1813 <0x04400000 0x800000>, 1814 <0x04c00000 0x800000>, 1815 <0x05800000 0x200000>, 1816 <0x0400a000 0x002100>; 1817 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1818 interrupt-names = "periph_irq"; 1819 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1820 qcom,ee = <0>; 1821 qcom,channel = <0>; 1822 #address-cells = <2>; 1823 #size-cells = <0>; 1824 interrupt-controller; 1825 #interrupt-cells = <4>; 1826 }; 1827 1828 bus@0 { 1829 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1830 compatible = "simple-pm-bus"; 1831 #address-cells = <1>; 1832 #size-cells = <1>; 1833 ranges; 1834 1835 pcie0: pcie@600000 { 1836 compatible = "qcom,pcie-msm8996"; 1837 status = "disabled"; 1838 power-domains = <&gcc PCIE0_GDSC>; 1839 bus-range = <0x00 0xff>; 1840 num-lanes = <1>; 1841 1842 reg = <0x00600000 0x2000>, 1843 <0x0c000000 0xf1d>, 1844 <0x0c000f20 0xa8>, 1845 <0x0c100000 0x100000>; 1846 reg-names = "parf", "dbi", "elbi","config"; 1847 1848 phys = <&pciephy_0>; 1849 phy-names = "pciephy"; 1850 1851 #address-cells = <3>; 1852 #size-cells = <2>; 1853 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1854 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1855 1856 device_type = "pci"; 1857 1858 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1859 interrupt-names = "msi"; 1860 #interrupt-cells = <1>; 1861 interrupt-map-mask = <0 0 0 0x7>; 1862 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1863 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1864 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1865 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1866 1867 pinctrl-names = "default", "sleep"; 1868 pinctrl-0 = <&pcie0_state_on>; 1869 pinctrl-1 = <&pcie0_state_off>; 1870 1871 linux,pci-domain = <0>; 1872 1873 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1874 <&gcc GCC_PCIE_0_AUX_CLK>, 1875 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1876 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1877 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1878 1879 clock-names = "pipe", 1880 "aux", 1881 "cfg", 1882 "bus_master", 1883 "bus_slave"; 1884 }; 1885 1886 pcie1: pcie@608000 { 1887 compatible = "qcom,pcie-msm8996"; 1888 power-domains = <&gcc PCIE1_GDSC>; 1889 bus-range = <0x00 0xff>; 1890 num-lanes = <1>; 1891 1892 status = "disabled"; 1893 1894 reg = <0x00608000 0x2000>, 1895 <0x0d000000 0xf1d>, 1896 <0x0d000f20 0xa8>, 1897 <0x0d100000 0x100000>; 1898 1899 reg-names = "parf", "dbi", "elbi","config"; 1900 1901 phys = <&pciephy_1>; 1902 phy-names = "pciephy"; 1903 1904 #address-cells = <3>; 1905 #size-cells = <2>; 1906 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 1907 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1908 1909 device_type = "pci"; 1910 1911 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1912 interrupt-names = "msi"; 1913 #interrupt-cells = <1>; 1914 interrupt-map-mask = <0 0 0 0x7>; 1915 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1916 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1917 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1918 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1919 1920 pinctrl-names = "default", "sleep"; 1921 pinctrl-0 = <&pcie1_state_on>; 1922 pinctrl-1 = <&pcie1_state_off>; 1923 1924 linux,pci-domain = <1>; 1925 1926 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1927 <&gcc GCC_PCIE_1_AUX_CLK>, 1928 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1929 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1930 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1931 1932 clock-names = "pipe", 1933 "aux", 1934 "cfg", 1935 "bus_master", 1936 "bus_slave"; 1937 }; 1938 1939 pcie2: pcie@610000 { 1940 compatible = "qcom,pcie-msm8996"; 1941 power-domains = <&gcc PCIE2_GDSC>; 1942 bus-range = <0x00 0xff>; 1943 num-lanes = <1>; 1944 status = "disabled"; 1945 reg = <0x00610000 0x2000>, 1946 <0x0e000000 0xf1d>, 1947 <0x0e000f20 0xa8>, 1948 <0x0e100000 0x100000>; 1949 1950 reg-names = "parf", "dbi", "elbi","config"; 1951 1952 phys = <&pciephy_2>; 1953 phy-names = "pciephy"; 1954 1955 #address-cells = <3>; 1956 #size-cells = <2>; 1957 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 1958 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1959 1960 device_type = "pci"; 1961 1962 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1963 interrupt-names = "msi"; 1964 #interrupt-cells = <1>; 1965 interrupt-map-mask = <0 0 0 0x7>; 1966 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1967 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1968 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1969 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1970 1971 pinctrl-names = "default", "sleep"; 1972 pinctrl-0 = <&pcie2_state_on>; 1973 pinctrl-1 = <&pcie2_state_off>; 1974 1975 linux,pci-domain = <2>; 1976 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1977 <&gcc GCC_PCIE_2_AUX_CLK>, 1978 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1979 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1980 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1981 1982 clock-names = "pipe", 1983 "aux", 1984 "cfg", 1985 "bus_master", 1986 "bus_slave"; 1987 }; 1988 }; 1989 1990 ufshc: ufshc@624000 { 1991 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1992 "jedec,ufs-2.0"; 1993 reg = <0x00624000 0x2500>; 1994 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1995 1996 phys = <&ufsphy_lane>; 1997 phy-names = "ufsphy"; 1998 1999 power-domains = <&gcc UFS_GDSC>; 2000 2001 clock-names = 2002 "core_clk_src", 2003 "core_clk", 2004 "bus_clk", 2005 "bus_aggr_clk", 2006 "iface_clk", 2007 "core_clk_unipro_src", 2008 "core_clk_unipro", 2009 "core_clk_ice", 2010 "ref_clk", 2011 "tx_lane0_sync_clk", 2012 "rx_lane0_sync_clk"; 2013 clocks = 2014 <&gcc UFS_AXI_CLK_SRC>, 2015 <&gcc GCC_UFS_AXI_CLK>, 2016 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2017 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2018 <&gcc GCC_UFS_AHB_CLK>, 2019 <&gcc UFS_ICE_CORE_CLK_SRC>, 2020 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2021 <&gcc GCC_UFS_ICE_CORE_CLK>, 2022 <&rpmcc RPM_SMD_LN_BB_CLK>, 2023 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2024 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2025 freq-table-hz = 2026 <100000000 200000000>, 2027 <0 0>, 2028 <0 0>, 2029 <0 0>, 2030 <0 0>, 2031 <150000000 300000000>, 2032 <0 0>, 2033 <0 0>, 2034 <0 0>, 2035 <0 0>, 2036 <0 0>; 2037 2038 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2039 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2040 interconnect-names = "ufs-ddr", "cpu-ufs"; 2041 2042 lanes-per-direction = <1>; 2043 #reset-cells = <1>; 2044 status = "disabled"; 2045 }; 2046 2047 ufsphy: phy@627000 { 2048 compatible = "qcom,msm8996-qmp-ufs-phy"; 2049 reg = <0x00627000 0x1c4>; 2050 #address-cells = <1>; 2051 #size-cells = <1>; 2052 ranges; 2053 2054 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2055 clock-names = "ref"; 2056 2057 resets = <&ufshc 0>; 2058 reset-names = "ufsphy"; 2059 status = "disabled"; 2060 2061 ufsphy_lane: phy@627400 { 2062 reg = <0x627400 0x12c>, 2063 <0x627600 0x200>, 2064 <0x627c00 0x1b4>; 2065 #clock-cells = <1>; 2066 #phy-cells = <0>; 2067 }; 2068 }; 2069 2070 camss: camss@a00000 { 2071 compatible = "qcom,msm8996-camss"; 2072 reg = <0x00a34000 0x1000>, 2073 <0x00a00030 0x4>, 2074 <0x00a35000 0x1000>, 2075 <0x00a00038 0x4>, 2076 <0x00a36000 0x1000>, 2077 <0x00a00040 0x4>, 2078 <0x00a30000 0x100>, 2079 <0x00a30400 0x100>, 2080 <0x00a30800 0x100>, 2081 <0x00a30c00 0x100>, 2082 <0x00a31000 0x500>, 2083 <0x00a00020 0x10>, 2084 <0x00a10000 0x1000>, 2085 <0x00a14000 0x1000>; 2086 reg-names = "csiphy0", 2087 "csiphy0_clk_mux", 2088 "csiphy1", 2089 "csiphy1_clk_mux", 2090 "csiphy2", 2091 "csiphy2_clk_mux", 2092 "csid0", 2093 "csid1", 2094 "csid2", 2095 "csid3", 2096 "ispif", 2097 "csi_clk_mux", 2098 "vfe0", 2099 "vfe1"; 2100 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2101 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2102 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2103 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2104 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2105 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2106 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2107 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2108 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2109 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2110 interrupt-names = "csiphy0", 2111 "csiphy1", 2112 "csiphy2", 2113 "csid0", 2114 "csid1", 2115 "csid2", 2116 "csid3", 2117 "ispif", 2118 "vfe0", 2119 "vfe1"; 2120 power-domains = <&mmcc VFE0_GDSC>, 2121 <&mmcc VFE1_GDSC>; 2122 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2123 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2124 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2125 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2126 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2127 <&mmcc CAMSS_CSI0_AHB_CLK>, 2128 <&mmcc CAMSS_CSI0_CLK>, 2129 <&mmcc CAMSS_CSI0PHY_CLK>, 2130 <&mmcc CAMSS_CSI0PIX_CLK>, 2131 <&mmcc CAMSS_CSI0RDI_CLK>, 2132 <&mmcc CAMSS_CSI1_AHB_CLK>, 2133 <&mmcc CAMSS_CSI1_CLK>, 2134 <&mmcc CAMSS_CSI1PHY_CLK>, 2135 <&mmcc CAMSS_CSI1PIX_CLK>, 2136 <&mmcc CAMSS_CSI1RDI_CLK>, 2137 <&mmcc CAMSS_CSI2_AHB_CLK>, 2138 <&mmcc CAMSS_CSI2_CLK>, 2139 <&mmcc CAMSS_CSI2PHY_CLK>, 2140 <&mmcc CAMSS_CSI2PIX_CLK>, 2141 <&mmcc CAMSS_CSI2RDI_CLK>, 2142 <&mmcc CAMSS_CSI3_AHB_CLK>, 2143 <&mmcc CAMSS_CSI3_CLK>, 2144 <&mmcc CAMSS_CSI3PHY_CLK>, 2145 <&mmcc CAMSS_CSI3PIX_CLK>, 2146 <&mmcc CAMSS_CSI3RDI_CLK>, 2147 <&mmcc CAMSS_AHB_CLK>, 2148 <&mmcc CAMSS_VFE0_CLK>, 2149 <&mmcc CAMSS_CSI_VFE0_CLK>, 2150 <&mmcc CAMSS_VFE0_AHB_CLK>, 2151 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2152 <&mmcc CAMSS_VFE1_CLK>, 2153 <&mmcc CAMSS_CSI_VFE1_CLK>, 2154 <&mmcc CAMSS_VFE1_AHB_CLK>, 2155 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2156 <&mmcc CAMSS_VFE_AHB_CLK>, 2157 <&mmcc CAMSS_VFE_AXI_CLK>; 2158 clock-names = "top_ahb", 2159 "ispif_ahb", 2160 "csiphy0_timer", 2161 "csiphy1_timer", 2162 "csiphy2_timer", 2163 "csi0_ahb", 2164 "csi0", 2165 "csi0_phy", 2166 "csi0_pix", 2167 "csi0_rdi", 2168 "csi1_ahb", 2169 "csi1", 2170 "csi1_phy", 2171 "csi1_pix", 2172 "csi1_rdi", 2173 "csi2_ahb", 2174 "csi2", 2175 "csi2_phy", 2176 "csi2_pix", 2177 "csi2_rdi", 2178 "csi3_ahb", 2179 "csi3", 2180 "csi3_phy", 2181 "csi3_pix", 2182 "csi3_rdi", 2183 "ahb", 2184 "vfe0", 2185 "csi_vfe0", 2186 "vfe0_ahb", 2187 "vfe0_stream", 2188 "vfe1", 2189 "csi_vfe1", 2190 "vfe1_ahb", 2191 "vfe1_stream", 2192 "vfe_ahb", 2193 "vfe_axi"; 2194 iommus = <&vfe_smmu 0>, 2195 <&vfe_smmu 1>, 2196 <&vfe_smmu 2>, 2197 <&vfe_smmu 3>; 2198 status = "disabled"; 2199 ports { 2200 #address-cells = <1>; 2201 #size-cells = <0>; 2202 }; 2203 }; 2204 2205 cci: cci@a0c000 { 2206 compatible = "qcom,msm8996-cci"; 2207 #address-cells = <1>; 2208 #size-cells = <0>; 2209 reg = <0xa0c000 0x1000>; 2210 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2211 power-domains = <&mmcc CAMSS_GDSC>; 2212 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2213 <&mmcc CAMSS_CCI_AHB_CLK>, 2214 <&mmcc CAMSS_CCI_CLK>, 2215 <&mmcc CAMSS_AHB_CLK>; 2216 clock-names = "camss_top_ahb", 2217 "cci_ahb", 2218 "cci", 2219 "camss_ahb"; 2220 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2221 <&mmcc CAMSS_CCI_CLK>; 2222 assigned-clock-rates = <80000000>, <37500000>; 2223 pinctrl-names = "default"; 2224 pinctrl-0 = <&cci0_default &cci1_default>; 2225 status = "disabled"; 2226 2227 cci_i2c0: i2c-bus@0 { 2228 reg = <0>; 2229 clock-frequency = <400000>; 2230 #address-cells = <1>; 2231 #size-cells = <0>; 2232 }; 2233 2234 cci_i2c1: i2c-bus@1 { 2235 reg = <1>; 2236 clock-frequency = <400000>; 2237 #address-cells = <1>; 2238 #size-cells = <0>; 2239 }; 2240 }; 2241 2242 adreno_smmu: iommu@b40000 { 2243 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2244 reg = <0x00b40000 0x10000>; 2245 2246 #global-interrupts = <1>; 2247 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2250 #iommu-cells = <1>; 2251 2252 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2253 <&mmcc GPU_AHB_CLK>; 2254 clock-names = "bus", "iface"; 2255 2256 power-domains = <&mmcc GPU_GDSC>; 2257 }; 2258 2259 venus: video-codec@c00000 { 2260 compatible = "qcom,msm8996-venus"; 2261 reg = <0x00c00000 0xff000>; 2262 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2263 power-domains = <&mmcc VENUS_GDSC>; 2264 clocks = <&mmcc VIDEO_CORE_CLK>, 2265 <&mmcc VIDEO_AHB_CLK>, 2266 <&mmcc VIDEO_AXI_CLK>, 2267 <&mmcc VIDEO_MAXI_CLK>; 2268 clock-names = "core", "iface", "bus", "mbus"; 2269 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2270 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2271 interconnect-names = "video-mem", "cpu-cfg"; 2272 iommus = <&venus_smmu 0x00>, 2273 <&venus_smmu 0x01>, 2274 <&venus_smmu 0x0a>, 2275 <&venus_smmu 0x07>, 2276 <&venus_smmu 0x0e>, 2277 <&venus_smmu 0x0f>, 2278 <&venus_smmu 0x08>, 2279 <&venus_smmu 0x09>, 2280 <&venus_smmu 0x0b>, 2281 <&venus_smmu 0x0c>, 2282 <&venus_smmu 0x0d>, 2283 <&venus_smmu 0x10>, 2284 <&venus_smmu 0x11>, 2285 <&venus_smmu 0x21>, 2286 <&venus_smmu 0x28>, 2287 <&venus_smmu 0x29>, 2288 <&venus_smmu 0x2b>, 2289 <&venus_smmu 0x2c>, 2290 <&venus_smmu 0x2d>, 2291 <&venus_smmu 0x31>; 2292 memory-region = <&venus_mem>; 2293 status = "disabled"; 2294 2295 video-decoder { 2296 compatible = "venus-decoder"; 2297 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2298 clock-names = "core"; 2299 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2300 }; 2301 2302 video-encoder { 2303 compatible = "venus-encoder"; 2304 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2305 clock-names = "core"; 2306 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2307 }; 2308 }; 2309 2310 mdp_smmu: iommu@d00000 { 2311 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2312 reg = <0x00d00000 0x10000>; 2313 2314 #global-interrupts = <1>; 2315 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2316 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2317 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2318 #iommu-cells = <1>; 2319 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2320 <&mmcc SMMU_MDP_AHB_CLK>; 2321 clock-names = "bus", "iface"; 2322 2323 power-domains = <&mmcc MDSS_GDSC>; 2324 }; 2325 2326 venus_smmu: iommu@d40000 { 2327 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2328 reg = <0x00d40000 0x20000>; 2329 #global-interrupts = <1>; 2330 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2331 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2332 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2333 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2338 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2339 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2340 <&mmcc SMMU_VIDEO_AHB_CLK>; 2341 clock-names = "bus", "iface"; 2342 #iommu-cells = <1>; 2343 status = "okay"; 2344 }; 2345 2346 vfe_smmu: iommu@da0000 { 2347 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2348 reg = <0x00da0000 0x10000>; 2349 2350 #global-interrupts = <1>; 2351 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2352 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2353 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2354 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2355 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2356 <&mmcc SMMU_VFE_AHB_CLK>; 2357 clock-names = "bus", "iface"; 2358 #iommu-cells = <1>; 2359 }; 2360 2361 lpass_q6_smmu: iommu@1600000 { 2362 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2363 reg = <0x01600000 0x20000>; 2364 #iommu-cells = <1>; 2365 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2366 2367 #global-interrupts = <1>; 2368 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2381 2382 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2383 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2384 clock-names = "bus", "iface"; 2385 }; 2386 2387 slpi_pil: remoteproc@1c00000 { 2388 compatible = "qcom,msm8996-slpi-pil"; 2389 reg = <0x01c00000 0x4000>; 2390 2391 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2392 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2393 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2394 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2395 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2396 interrupt-names = "wdog", 2397 "fatal", 2398 "ready", 2399 "handover", 2400 "stop-ack"; 2401 2402 clocks = <&xo_board>, 2403 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2404 clock-names = "xo", "aggre2"; 2405 2406 memory-region = <&slpi_mem>; 2407 2408 qcom,smem-states = <&slpi_smp2p_out 0>; 2409 qcom,smem-state-names = "stop"; 2410 2411 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2412 power-domain-names = "ssc_cx"; 2413 2414 status = "disabled"; 2415 2416 smd-edge { 2417 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2418 2419 label = "dsps"; 2420 mboxes = <&apcs_glb 25>; 2421 qcom,smd-edge = <3>; 2422 qcom,remote-pid = <3>; 2423 }; 2424 }; 2425 2426 mss_pil: remoteproc@2080000 { 2427 compatible = "qcom,msm8996-mss-pil"; 2428 reg = <0x2080000 0x100>, 2429 <0x2180000 0x020>; 2430 reg-names = "qdsp6", "rmb"; 2431 2432 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2433 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2434 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2435 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2436 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2437 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2438 interrupt-names = "wdog", "fatal", "ready", 2439 "handover", "stop-ack", 2440 "shutdown-ack"; 2441 2442 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2443 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2444 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2445 <&xo_board>, 2446 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2447 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2448 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2449 <&rpmcc RPM_SMD_PCNOC_CLK>, 2450 <&rpmcc RPM_SMD_QDSS_CLK>; 2451 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2452 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2453 2454 resets = <&gcc GCC_MSS_RESTART>; 2455 reset-names = "mss_restart"; 2456 2457 power-domains = <&rpmpd MSM8996_VDDCX>, 2458 <&rpmpd MSM8996_VDDMX>; 2459 power-domain-names = "cx", "mx"; 2460 2461 qcom,smem-states = <&mpss_smp2p_out 0>; 2462 qcom,smem-state-names = "stop"; 2463 2464 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2465 2466 status = "disabled"; 2467 2468 mba { 2469 memory-region = <&mba_mem>; 2470 }; 2471 2472 mpss { 2473 memory-region = <&mpss_mem>; 2474 }; 2475 2476 metadata { 2477 memory-region = <&mdata_mem>; 2478 }; 2479 2480 smd-edge { 2481 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2482 2483 label = "mpss"; 2484 mboxes = <&apcs_glb 12>; 2485 qcom,smd-edge = <0>; 2486 qcom,remote-pid = <1>; 2487 }; 2488 }; 2489 2490 stm@3002000 { 2491 compatible = "arm,coresight-stm", "arm,primecell"; 2492 reg = <0x3002000 0x1000>, 2493 <0x8280000 0x180000>; 2494 reg-names = "stm-base", "stm-stimulus-base"; 2495 2496 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2497 clock-names = "apb_pclk", "atclk"; 2498 2499 out-ports { 2500 port { 2501 stm_out: endpoint { 2502 remote-endpoint = 2503 <&funnel0_in>; 2504 }; 2505 }; 2506 }; 2507 }; 2508 2509 tpiu@3020000 { 2510 compatible = "arm,coresight-tpiu", "arm,primecell"; 2511 reg = <0x3020000 0x1000>; 2512 2513 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2514 clock-names = "apb_pclk", "atclk"; 2515 2516 in-ports { 2517 port { 2518 tpiu_in: endpoint { 2519 remote-endpoint = 2520 <&replicator_out1>; 2521 }; 2522 }; 2523 }; 2524 }; 2525 2526 funnel@3021000 { 2527 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2528 reg = <0x3021000 0x1000>; 2529 2530 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2531 clock-names = "apb_pclk", "atclk"; 2532 2533 in-ports { 2534 #address-cells = <1>; 2535 #size-cells = <0>; 2536 2537 port@7 { 2538 reg = <7>; 2539 funnel0_in: endpoint { 2540 remote-endpoint = 2541 <&stm_out>; 2542 }; 2543 }; 2544 }; 2545 2546 out-ports { 2547 port { 2548 funnel0_out: endpoint { 2549 remote-endpoint = 2550 <&merge_funnel_in0>; 2551 }; 2552 }; 2553 }; 2554 }; 2555 2556 funnel@3022000 { 2557 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2558 reg = <0x3022000 0x1000>; 2559 2560 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2561 clock-names = "apb_pclk", "atclk"; 2562 2563 in-ports { 2564 #address-cells = <1>; 2565 #size-cells = <0>; 2566 2567 port@6 { 2568 reg = <6>; 2569 funnel1_in: endpoint { 2570 remote-endpoint = 2571 <&apss_merge_funnel_out>; 2572 }; 2573 }; 2574 }; 2575 2576 out-ports { 2577 port { 2578 funnel1_out: endpoint { 2579 remote-endpoint = 2580 <&merge_funnel_in1>; 2581 }; 2582 }; 2583 }; 2584 }; 2585 2586 funnel@3023000 { 2587 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2588 reg = <0x3023000 0x1000>; 2589 2590 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2591 clock-names = "apb_pclk", "atclk"; 2592 2593 2594 out-ports { 2595 port { 2596 funnel2_out: endpoint { 2597 remote-endpoint = 2598 <&merge_funnel_in2>; 2599 }; 2600 }; 2601 }; 2602 }; 2603 2604 funnel@3025000 { 2605 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2606 reg = <0x3025000 0x1000>; 2607 2608 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2609 clock-names = "apb_pclk", "atclk"; 2610 2611 in-ports { 2612 #address-cells = <1>; 2613 #size-cells = <0>; 2614 2615 port@0 { 2616 reg = <0>; 2617 merge_funnel_in0: endpoint { 2618 remote-endpoint = 2619 <&funnel0_out>; 2620 }; 2621 }; 2622 2623 port@1 { 2624 reg = <1>; 2625 merge_funnel_in1: endpoint { 2626 remote-endpoint = 2627 <&funnel1_out>; 2628 }; 2629 }; 2630 2631 port@2 { 2632 reg = <2>; 2633 merge_funnel_in2: endpoint { 2634 remote-endpoint = 2635 <&funnel2_out>; 2636 }; 2637 }; 2638 }; 2639 2640 out-ports { 2641 port { 2642 merge_funnel_out: endpoint { 2643 remote-endpoint = 2644 <&etf_in>; 2645 }; 2646 }; 2647 }; 2648 }; 2649 2650 replicator@3026000 { 2651 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2652 reg = <0x3026000 0x1000>; 2653 2654 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2655 clock-names = "apb_pclk", "atclk"; 2656 2657 in-ports { 2658 port { 2659 replicator_in: endpoint { 2660 remote-endpoint = 2661 <&etf_out>; 2662 }; 2663 }; 2664 }; 2665 2666 out-ports { 2667 #address-cells = <1>; 2668 #size-cells = <0>; 2669 2670 port@0 { 2671 reg = <0>; 2672 replicator_out0: endpoint { 2673 remote-endpoint = 2674 <&etr_in>; 2675 }; 2676 }; 2677 2678 port@1 { 2679 reg = <1>; 2680 replicator_out1: endpoint { 2681 remote-endpoint = 2682 <&tpiu_in>; 2683 }; 2684 }; 2685 }; 2686 }; 2687 2688 etf@3027000 { 2689 compatible = "arm,coresight-tmc", "arm,primecell"; 2690 reg = <0x3027000 0x1000>; 2691 2692 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2693 clock-names = "apb_pclk", "atclk"; 2694 2695 in-ports { 2696 port { 2697 etf_in: endpoint { 2698 remote-endpoint = 2699 <&merge_funnel_out>; 2700 }; 2701 }; 2702 }; 2703 2704 out-ports { 2705 port { 2706 etf_out: endpoint { 2707 remote-endpoint = 2708 <&replicator_in>; 2709 }; 2710 }; 2711 }; 2712 }; 2713 2714 etr@3028000 { 2715 compatible = "arm,coresight-tmc", "arm,primecell"; 2716 reg = <0x3028000 0x1000>; 2717 2718 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2719 clock-names = "apb_pclk", "atclk"; 2720 arm,scatter-gather; 2721 2722 in-ports { 2723 port { 2724 etr_in: endpoint { 2725 remote-endpoint = 2726 <&replicator_out0>; 2727 }; 2728 }; 2729 }; 2730 }; 2731 2732 debug@3810000 { 2733 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2734 reg = <0x3810000 0x1000>; 2735 2736 clocks = <&rpmcc RPM_QDSS_CLK>; 2737 clock-names = "apb_pclk"; 2738 2739 cpu = <&CPU0>; 2740 }; 2741 2742 etm@3840000 { 2743 compatible = "arm,coresight-etm4x", "arm,primecell"; 2744 reg = <0x3840000 0x1000>; 2745 2746 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2747 clock-names = "apb_pclk", "atclk"; 2748 2749 cpu = <&CPU0>; 2750 2751 out-ports { 2752 port { 2753 etm0_out: endpoint { 2754 remote-endpoint = 2755 <&apss_funnel0_in0>; 2756 }; 2757 }; 2758 }; 2759 }; 2760 2761 debug@3910000 { 2762 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2763 reg = <0x3910000 0x1000>; 2764 2765 clocks = <&rpmcc RPM_QDSS_CLK>; 2766 clock-names = "apb_pclk"; 2767 2768 cpu = <&CPU1>; 2769 }; 2770 2771 etm@3940000 { 2772 compatible = "arm,coresight-etm4x", "arm,primecell"; 2773 reg = <0x3940000 0x1000>; 2774 2775 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2776 clock-names = "apb_pclk", "atclk"; 2777 2778 cpu = <&CPU1>; 2779 2780 out-ports { 2781 port { 2782 etm1_out: endpoint { 2783 remote-endpoint = 2784 <&apss_funnel0_in1>; 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 funnel@39b0000 { /* APSS Funnel 0 */ 2791 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2792 reg = <0x39b0000 0x1000>; 2793 2794 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2795 clock-names = "apb_pclk", "atclk"; 2796 2797 in-ports { 2798 #address-cells = <1>; 2799 #size-cells = <0>; 2800 2801 port@0 { 2802 reg = <0>; 2803 apss_funnel0_in0: endpoint { 2804 remote-endpoint = <&etm0_out>; 2805 }; 2806 }; 2807 2808 port@1 { 2809 reg = <1>; 2810 apss_funnel0_in1: endpoint { 2811 remote-endpoint = <&etm1_out>; 2812 }; 2813 }; 2814 }; 2815 2816 out-ports { 2817 port { 2818 apss_funnel0_out: endpoint { 2819 remote-endpoint = 2820 <&apss_merge_funnel_in0>; 2821 }; 2822 }; 2823 }; 2824 }; 2825 2826 debug@3a10000 { 2827 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2828 reg = <0x3a10000 0x1000>; 2829 2830 clocks = <&rpmcc RPM_QDSS_CLK>; 2831 clock-names = "apb_pclk"; 2832 2833 cpu = <&CPU2>; 2834 }; 2835 2836 etm@3a40000 { 2837 compatible = "arm,coresight-etm4x", "arm,primecell"; 2838 reg = <0x3a40000 0x1000>; 2839 2840 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2841 clock-names = "apb_pclk", "atclk"; 2842 2843 cpu = <&CPU2>; 2844 2845 out-ports { 2846 port { 2847 etm2_out: endpoint { 2848 remote-endpoint = 2849 <&apss_funnel1_in0>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 debug@3b10000 { 2856 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2857 reg = <0x3b10000 0x1000>; 2858 2859 clocks = <&rpmcc RPM_QDSS_CLK>; 2860 clock-names = "apb_pclk"; 2861 2862 cpu = <&CPU3>; 2863 }; 2864 2865 etm@3b40000 { 2866 compatible = "arm,coresight-etm4x", "arm,primecell"; 2867 reg = <0x3b40000 0x1000>; 2868 2869 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2870 clock-names = "apb_pclk", "atclk"; 2871 2872 cpu = <&CPU3>; 2873 2874 out-ports { 2875 port { 2876 etm3_out: endpoint { 2877 remote-endpoint = 2878 <&apss_funnel1_in1>; 2879 }; 2880 }; 2881 }; 2882 }; 2883 2884 funnel@3bb0000 { /* APSS Funnel 1 */ 2885 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2886 reg = <0x3bb0000 0x1000>; 2887 2888 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2889 clock-names = "apb_pclk", "atclk"; 2890 2891 in-ports { 2892 #address-cells = <1>; 2893 #size-cells = <0>; 2894 2895 port@0 { 2896 reg = <0>; 2897 apss_funnel1_in0: endpoint { 2898 remote-endpoint = <&etm2_out>; 2899 }; 2900 }; 2901 2902 port@1 { 2903 reg = <1>; 2904 apss_funnel1_in1: endpoint { 2905 remote-endpoint = <&etm3_out>; 2906 }; 2907 }; 2908 }; 2909 2910 out-ports { 2911 port { 2912 apss_funnel1_out: endpoint { 2913 remote-endpoint = 2914 <&apss_merge_funnel_in1>; 2915 }; 2916 }; 2917 }; 2918 }; 2919 2920 funnel@3bc0000 { 2921 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2922 reg = <0x3bc0000 0x1000>; 2923 2924 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2925 clock-names = "apb_pclk", "atclk"; 2926 2927 in-ports { 2928 #address-cells = <1>; 2929 #size-cells = <0>; 2930 2931 port@0 { 2932 reg = <0>; 2933 apss_merge_funnel_in0: endpoint { 2934 remote-endpoint = 2935 <&apss_funnel0_out>; 2936 }; 2937 }; 2938 2939 port@1 { 2940 reg = <1>; 2941 apss_merge_funnel_in1: endpoint { 2942 remote-endpoint = 2943 <&apss_funnel1_out>; 2944 }; 2945 }; 2946 }; 2947 2948 out-ports { 2949 port { 2950 apss_merge_funnel_out: endpoint { 2951 remote-endpoint = 2952 <&funnel1_in>; 2953 }; 2954 }; 2955 }; 2956 }; 2957 2958 kryocc: clock-controller@6400000 { 2959 compatible = "qcom,msm8996-apcc"; 2960 reg = <0x06400000 0x90000>; 2961 2962 clock-names = "xo", "sys_apcs_aux"; 2963 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 2964 2965 #clock-cells = <1>; 2966 }; 2967 2968 usb3: usb@6af8800 { 2969 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2970 reg = <0x06af8800 0x400>; 2971 #address-cells = <1>; 2972 #size-cells = <1>; 2973 ranges; 2974 2975 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2977 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2978 2979 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2980 <&gcc GCC_USB30_MASTER_CLK>, 2981 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2982 <&gcc GCC_USB30_SLEEP_CLK>, 2983 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2984 clock-names = "cfg_noc", 2985 "core", 2986 "iface", 2987 "sleep", 2988 "mock_utmi"; 2989 2990 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2991 <&gcc GCC_USB30_MASTER_CLK>; 2992 assigned-clock-rates = <19200000>, <120000000>; 2993 2994 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2995 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2996 interconnect-names = "usb-ddr", "apps-usb"; 2997 2998 power-domains = <&gcc USB30_GDSC>; 2999 status = "disabled"; 3000 3001 usb3_dwc3: usb@6a00000 { 3002 compatible = "snps,dwc3"; 3003 reg = <0x06a00000 0xcc00>; 3004 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 3005 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 3006 phy-names = "usb2-phy", "usb3-phy"; 3007 snps,hird-threshold = /bits/ 8 <0>; 3008 snps,dis_u2_susphy_quirk; 3009 snps,dis_enblslpm_quirk; 3010 snps,is-utmi-l1-suspend; 3011 tx-fifo-resize; 3012 }; 3013 }; 3014 3015 usb3phy: phy@7410000 { 3016 compatible = "qcom,msm8996-qmp-usb3-phy"; 3017 reg = <0x07410000 0x1c4>; 3018 #address-cells = <1>; 3019 #size-cells = <1>; 3020 ranges; 3021 3022 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3023 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3024 <&gcc GCC_USB3_CLKREF_CLK>; 3025 clock-names = "aux", "cfg_ahb", "ref"; 3026 3027 resets = <&gcc GCC_USB3_PHY_BCR>, 3028 <&gcc GCC_USB3PHY_PHY_BCR>; 3029 reset-names = "phy", "common"; 3030 status = "disabled"; 3031 3032 ssusb_phy_0: phy@7410200 { 3033 reg = <0x07410200 0x200>, 3034 <0x07410400 0x130>, 3035 <0x07410600 0x1a8>; 3036 #phy-cells = <0>; 3037 3038 #clock-cells = <0>; 3039 clock-output-names = "usb3_phy_pipe_clk_src"; 3040 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3041 clock-names = "pipe0"; 3042 }; 3043 }; 3044 3045 hsusb_phy1: phy@7411000 { 3046 compatible = "qcom,msm8996-qusb2-phy"; 3047 reg = <0x07411000 0x180>; 3048 #phy-cells = <0>; 3049 3050 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3051 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3052 clock-names = "cfg_ahb", "ref"; 3053 3054 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3055 nvmem-cells = <&qusb2p_hstx_trim>; 3056 status = "disabled"; 3057 }; 3058 3059 hsusb_phy2: phy@7412000 { 3060 compatible = "qcom,msm8996-qusb2-phy"; 3061 reg = <0x07412000 0x180>; 3062 #phy-cells = <0>; 3063 3064 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3065 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3066 clock-names = "cfg_ahb", "ref"; 3067 3068 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3069 nvmem-cells = <&qusb2s_hstx_trim>; 3070 status = "disabled"; 3071 }; 3072 3073 sdhc1: mmc@7464900 { 3074 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3075 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3076 reg-names = "hc", "core"; 3077 3078 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3080 interrupt-names = "hc_irq", "pwr_irq"; 3081 3082 clock-names = "iface", "core", "xo"; 3083 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3084 <&gcc GCC_SDCC1_APPS_CLK>, 3085 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3086 resets = <&gcc GCC_SDCC1_BCR>; 3087 3088 pinctrl-names = "default", "sleep"; 3089 pinctrl-0 = <&sdc1_state_on>; 3090 pinctrl-1 = <&sdc1_state_off>; 3091 3092 bus-width = <8>; 3093 non-removable; 3094 status = "disabled"; 3095 }; 3096 3097 sdhc2: mmc@74a4900 { 3098 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3099 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3100 reg-names = "hc", "core"; 3101 3102 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3104 interrupt-names = "hc_irq", "pwr_irq"; 3105 3106 clock-names = "iface", "core", "xo"; 3107 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3108 <&gcc GCC_SDCC2_APPS_CLK>, 3109 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3110 resets = <&gcc GCC_SDCC2_BCR>; 3111 3112 pinctrl-names = "default", "sleep"; 3113 pinctrl-0 = <&sdc2_state_on>; 3114 pinctrl-1 = <&sdc2_state_off>; 3115 3116 bus-width = <4>; 3117 status = "disabled"; 3118 }; 3119 3120 blsp1_dma: dma-controller@7544000 { 3121 compatible = "qcom,bam-v1.7.0"; 3122 reg = <0x07544000 0x2b000>; 3123 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3124 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3125 clock-names = "bam_clk"; 3126 qcom,controlled-remotely; 3127 #dma-cells = <1>; 3128 qcom,ee = <0>; 3129 }; 3130 3131 blsp1_uart2: serial@7570000 { 3132 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3133 reg = <0x07570000 0x1000>; 3134 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3135 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3136 <&gcc GCC_BLSP1_AHB_CLK>; 3137 clock-names = "core", "iface"; 3138 pinctrl-names = "default", "sleep"; 3139 pinctrl-0 = <&blsp1_uart2_default>; 3140 pinctrl-1 = <&blsp1_uart2_sleep>; 3141 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3142 dma-names = "tx", "rx"; 3143 status = "disabled"; 3144 }; 3145 3146 blsp1_spi1: spi@7575000 { 3147 compatible = "qcom,spi-qup-v2.2.1"; 3148 reg = <0x07575000 0x600>; 3149 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3150 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3151 <&gcc GCC_BLSP1_AHB_CLK>; 3152 clock-names = "core", "iface"; 3153 pinctrl-names = "default", "sleep"; 3154 pinctrl-0 = <&blsp1_spi1_default>; 3155 pinctrl-1 = <&blsp1_spi1_sleep>; 3156 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3157 dma-names = "tx", "rx"; 3158 #address-cells = <1>; 3159 #size-cells = <0>; 3160 status = "disabled"; 3161 }; 3162 3163 blsp1_i2c3: i2c@7577000 { 3164 compatible = "qcom,i2c-qup-v2.2.1"; 3165 reg = <0x07577000 0x1000>; 3166 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3167 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3168 <&gcc GCC_BLSP1_AHB_CLK>; 3169 clock-names = "core", "iface"; 3170 pinctrl-names = "default", "sleep"; 3171 pinctrl-0 = <&blsp1_i2c3_default>; 3172 pinctrl-1 = <&blsp1_i2c3_sleep>; 3173 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3174 dma-names = "tx", "rx"; 3175 #address-cells = <1>; 3176 #size-cells = <0>; 3177 status = "disabled"; 3178 }; 3179 3180 blsp1_i2c6: i2c@757a000 { 3181 compatible = "qcom,i2c-qup-v2.2.1"; 3182 reg = <0x757a000 0x1000>; 3183 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3184 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3185 <&gcc GCC_BLSP1_AHB_CLK>; 3186 clock-names = "core", "iface"; 3187 pinctrl-names = "default", "sleep"; 3188 pinctrl-0 = <&blsp1_i2c6_default>; 3189 pinctrl-1 = <&blsp1_i2c6_sleep>; 3190 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3191 dma-names = "tx", "rx"; 3192 #address-cells = <1>; 3193 #size-cells = <0>; 3194 status = "disabled"; 3195 }; 3196 3197 blsp2_dma: dma-controller@7584000 { 3198 compatible = "qcom,bam-v1.7.0"; 3199 reg = <0x07584000 0x2b000>; 3200 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3201 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3202 clock-names = "bam_clk"; 3203 qcom,controlled-remotely; 3204 #dma-cells = <1>; 3205 qcom,ee = <0>; 3206 }; 3207 3208 blsp2_uart2: serial@75b0000 { 3209 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3210 reg = <0x075b0000 0x1000>; 3211 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3212 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3213 <&gcc GCC_BLSP2_AHB_CLK>; 3214 clock-names = "core", "iface"; 3215 status = "disabled"; 3216 }; 3217 3218 blsp2_uart3: serial@75b1000 { 3219 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3220 reg = <0x075b1000 0x1000>; 3221 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3222 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3223 <&gcc GCC_BLSP2_AHB_CLK>; 3224 clock-names = "core", "iface"; 3225 status = "disabled"; 3226 }; 3227 3228 blsp2_i2c1: i2c@75b5000 { 3229 compatible = "qcom,i2c-qup-v2.2.1"; 3230 reg = <0x075b5000 0x1000>; 3231 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3232 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3233 <&gcc GCC_BLSP2_AHB_CLK>; 3234 clock-names = "core", "iface"; 3235 pinctrl-names = "default", "sleep"; 3236 pinctrl-0 = <&blsp2_i2c1_default>; 3237 pinctrl-1 = <&blsp2_i2c1_sleep>; 3238 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3239 dma-names = "tx", "rx"; 3240 #address-cells = <1>; 3241 #size-cells = <0>; 3242 status = "disabled"; 3243 }; 3244 3245 blsp2_i2c2: i2c@75b6000 { 3246 compatible = "qcom,i2c-qup-v2.2.1"; 3247 reg = <0x075b6000 0x1000>; 3248 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3249 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3250 <&gcc GCC_BLSP2_AHB_CLK>; 3251 clock-names = "core", "iface"; 3252 pinctrl-names = "default", "sleep"; 3253 pinctrl-0 = <&blsp2_i2c2_default>; 3254 pinctrl-1 = <&blsp2_i2c2_sleep>; 3255 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3256 dma-names = "tx", "rx"; 3257 #address-cells = <1>; 3258 #size-cells = <0>; 3259 status = "disabled"; 3260 }; 3261 3262 blsp2_i2c3: i2c@75b7000 { 3263 compatible = "qcom,i2c-qup-v2.2.1"; 3264 reg = <0x075b7000 0x1000>; 3265 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3266 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3267 <&gcc GCC_BLSP2_AHB_CLK>; 3268 clock-names = "core", "iface"; 3269 clock-frequency = <400000>; 3270 pinctrl-names = "default", "sleep"; 3271 pinctrl-0 = <&blsp2_i2c3_default>; 3272 pinctrl-1 = <&blsp2_i2c3_sleep>; 3273 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3274 dma-names = "tx", "rx"; 3275 #address-cells = <1>; 3276 #size-cells = <0>; 3277 status = "disabled"; 3278 }; 3279 3280 blsp2_i2c5: i2c@75b9000 { 3281 compatible = "qcom,i2c-qup-v2.2.1"; 3282 reg = <0x75b9000 0x1000>; 3283 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3284 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3285 <&gcc GCC_BLSP2_AHB_CLK>; 3286 clock-names = "core", "iface"; 3287 pinctrl-names = "default"; 3288 pinctrl-0 = <&blsp2_i2c5_default>; 3289 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3290 dma-names = "tx", "rx"; 3291 #address-cells = <1>; 3292 #size-cells = <0>; 3293 status = "disabled"; 3294 }; 3295 3296 blsp2_i2c6: i2c@75ba000 { 3297 compatible = "qcom,i2c-qup-v2.2.1"; 3298 reg = <0x75ba000 0x1000>; 3299 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3300 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3301 <&gcc GCC_BLSP2_AHB_CLK>; 3302 clock-names = "core", "iface"; 3303 pinctrl-names = "default", "sleep"; 3304 pinctrl-0 = <&blsp2_i2c6_default>; 3305 pinctrl-1 = <&blsp2_i2c6_sleep>; 3306 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3307 dma-names = "tx", "rx"; 3308 #address-cells = <1>; 3309 #size-cells = <0>; 3310 status = "disabled"; 3311 }; 3312 3313 blsp2_spi6: spi@75ba000 { 3314 compatible = "qcom,spi-qup-v2.2.1"; 3315 reg = <0x075ba000 0x600>; 3316 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3317 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3318 <&gcc GCC_BLSP2_AHB_CLK>; 3319 clock-names = "core", "iface"; 3320 pinctrl-names = "default", "sleep"; 3321 pinctrl-0 = <&blsp2_spi6_default>; 3322 pinctrl-1 = <&blsp2_spi6_sleep>; 3323 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3324 dma-names = "tx", "rx"; 3325 #address-cells = <1>; 3326 #size-cells = <0>; 3327 status = "disabled"; 3328 }; 3329 3330 usb2: usb@76f8800 { 3331 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3332 reg = <0x076f8800 0x400>; 3333 #address-cells = <1>; 3334 #size-cells = <1>; 3335 ranges; 3336 3337 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3338 <&gcc GCC_USB20_MASTER_CLK>, 3339 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3340 <&gcc GCC_USB20_SLEEP_CLK>, 3341 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3342 clock-names = "cfg_noc", 3343 "core", 3344 "iface", 3345 "sleep", 3346 "mock_utmi"; 3347 3348 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3349 <&gcc GCC_USB20_MASTER_CLK>; 3350 assigned-clock-rates = <19200000>, <60000000>; 3351 3352 power-domains = <&gcc USB30_GDSC>; 3353 qcom,select-utmi-as-pipe-clk; 3354 status = "disabled"; 3355 3356 usb2_dwc3: usb@7600000 { 3357 compatible = "snps,dwc3"; 3358 reg = <0x07600000 0xcc00>; 3359 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3360 phys = <&hsusb_phy2>; 3361 phy-names = "usb2-phy"; 3362 maximum-speed = "high-speed"; 3363 snps,dis_u2_susphy_quirk; 3364 snps,dis_enblslpm_quirk; 3365 }; 3366 }; 3367 3368 slimbam: dma-controller@9184000 { 3369 compatible = "qcom,bam-v1.7.0"; 3370 qcom,controlled-remotely; 3371 reg = <0x09184000 0x32000>; 3372 num-channels = <31>; 3373 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3374 #dma-cells = <1>; 3375 qcom,ee = <1>; 3376 qcom,num-ees = <2>; 3377 }; 3378 3379 slim_msm: slim-ngd@91c0000 { 3380 compatible = "qcom,slim-ngd-v1.5.0"; 3381 reg = <0x091c0000 0x2c000>; 3382 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3383 dmas = <&slimbam 3>, <&slimbam 4>; 3384 dma-names = "rx", "tx"; 3385 #address-cells = <1>; 3386 #size-cells = <0>; 3387 3388 status = "disabled"; 3389 }; 3390 3391 adsp_pil: remoteproc@9300000 { 3392 compatible = "qcom,msm8996-adsp-pil"; 3393 reg = <0x09300000 0x80000>; 3394 3395 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3396 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3397 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3398 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3399 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3400 interrupt-names = "wdog", "fatal", "ready", 3401 "handover", "stop-ack"; 3402 3403 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3404 clock-names = "xo"; 3405 3406 memory-region = <&adsp_mem>; 3407 3408 qcom,smem-states = <&adsp_smp2p_out 0>; 3409 qcom,smem-state-names = "stop"; 3410 3411 power-domains = <&rpmpd MSM8996_VDDCX>; 3412 power-domain-names = "cx"; 3413 3414 status = "disabled"; 3415 3416 smd-edge { 3417 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3418 3419 label = "lpass"; 3420 mboxes = <&apcs_glb 8>; 3421 qcom,smd-edge = <1>; 3422 qcom,remote-pid = <2>; 3423 3424 apr { 3425 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3426 compatible = "qcom,apr-v2"; 3427 qcom,smd-channels = "apr_audio_svc"; 3428 qcom,domain = <APR_DOMAIN_ADSP>; 3429 #address-cells = <1>; 3430 #size-cells = <0>; 3431 3432 service@3 { 3433 reg = <APR_SVC_ADSP_CORE>; 3434 compatible = "qcom,q6core"; 3435 }; 3436 3437 q6afe: service@4 { 3438 compatible = "qcom,q6afe"; 3439 reg = <APR_SVC_AFE>; 3440 q6afedai: dais { 3441 compatible = "qcom,q6afe-dais"; 3442 #address-cells = <1>; 3443 #size-cells = <0>; 3444 #sound-dai-cells = <1>; 3445 dai@1 { 3446 reg = <1>; 3447 }; 3448 }; 3449 }; 3450 3451 q6asm: service@7 { 3452 compatible = "qcom,q6asm"; 3453 reg = <APR_SVC_ASM>; 3454 q6asmdai: dais { 3455 compatible = "qcom,q6asm-dais"; 3456 #address-cells = <1>; 3457 #size-cells = <0>; 3458 #sound-dai-cells = <1>; 3459 iommus = <&lpass_q6_smmu 1>; 3460 }; 3461 }; 3462 3463 q6adm: service@8 { 3464 compatible = "qcom,q6adm"; 3465 reg = <APR_SVC_ADM>; 3466 q6routing: routing { 3467 compatible = "qcom,q6adm-routing"; 3468 #sound-dai-cells = <0>; 3469 }; 3470 }; 3471 }; 3472 }; 3473 }; 3474 3475 apcs_glb: mailbox@9820000 { 3476 compatible = "qcom,msm8996-apcs-hmss-global"; 3477 reg = <0x09820000 0x1000>; 3478 3479 #mbox-cells = <1>; 3480 #clock-cells = <0>; 3481 }; 3482 3483 timer@9840000 { 3484 #address-cells = <1>; 3485 #size-cells = <1>; 3486 ranges; 3487 compatible = "arm,armv7-timer-mem"; 3488 reg = <0x09840000 0x1000>; 3489 clock-frequency = <19200000>; 3490 3491 frame@9850000 { 3492 frame-number = <0>; 3493 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3495 reg = <0x09850000 0x1000>, 3496 <0x09860000 0x1000>; 3497 }; 3498 3499 frame@9870000 { 3500 frame-number = <1>; 3501 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3502 reg = <0x09870000 0x1000>; 3503 status = "disabled"; 3504 }; 3505 3506 frame@9880000 { 3507 frame-number = <2>; 3508 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3509 reg = <0x09880000 0x1000>; 3510 status = "disabled"; 3511 }; 3512 3513 frame@9890000 { 3514 frame-number = <3>; 3515 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3516 reg = <0x09890000 0x1000>; 3517 status = "disabled"; 3518 }; 3519 3520 frame@98a0000 { 3521 frame-number = <4>; 3522 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3523 reg = <0x098a0000 0x1000>; 3524 status = "disabled"; 3525 }; 3526 3527 frame@98b0000 { 3528 frame-number = <5>; 3529 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3530 reg = <0x098b0000 0x1000>; 3531 status = "disabled"; 3532 }; 3533 3534 frame@98c0000 { 3535 frame-number = <6>; 3536 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3537 reg = <0x098c0000 0x1000>; 3538 status = "disabled"; 3539 }; 3540 }; 3541 3542 saw3: syscon@9a10000 { 3543 compatible = "syscon"; 3544 reg = <0x09a10000 0x1000>; 3545 }; 3546 3547 cbf: clock-controller@9a11000 { 3548 compatible = "qcom,msm8996-cbf"; 3549 reg = <0x09a11000 0x10000>; 3550 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3551 #clock-cells = <0>; 3552 }; 3553 3554 intc: interrupt-controller@9bc0000 { 3555 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3556 #interrupt-cells = <3>; 3557 interrupt-controller; 3558 #redistributor-regions = <1>; 3559 redistributor-stride = <0x0 0x40000>; 3560 reg = <0x09bc0000 0x10000>, 3561 <0x09c00000 0x100000>; 3562 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3563 }; 3564 }; 3565 3566 sound: sound { 3567 }; 3568 3569 thermal-zones { 3570 cpu0-thermal { 3571 polling-delay-passive = <250>; 3572 polling-delay = <1000>; 3573 3574 thermal-sensors = <&tsens0 3>; 3575 3576 trips { 3577 cpu0_alert0: trip-point0 { 3578 temperature = <75000>; 3579 hysteresis = <2000>; 3580 type = "passive"; 3581 }; 3582 3583 cpu0_crit: cpu-crit { 3584 temperature = <110000>; 3585 hysteresis = <2000>; 3586 type = "critical"; 3587 }; 3588 }; 3589 }; 3590 3591 cpu1-thermal { 3592 polling-delay-passive = <250>; 3593 polling-delay = <1000>; 3594 3595 thermal-sensors = <&tsens0 5>; 3596 3597 trips { 3598 cpu1_alert0: trip-point0 { 3599 temperature = <75000>; 3600 hysteresis = <2000>; 3601 type = "passive"; 3602 }; 3603 3604 cpu1_crit: cpu-crit { 3605 temperature = <110000>; 3606 hysteresis = <2000>; 3607 type = "critical"; 3608 }; 3609 }; 3610 }; 3611 3612 cpu2-thermal { 3613 polling-delay-passive = <250>; 3614 polling-delay = <1000>; 3615 3616 thermal-sensors = <&tsens0 8>; 3617 3618 trips { 3619 cpu2_alert0: trip-point0 { 3620 temperature = <75000>; 3621 hysteresis = <2000>; 3622 type = "passive"; 3623 }; 3624 3625 cpu2_crit: cpu-crit { 3626 temperature = <110000>; 3627 hysteresis = <2000>; 3628 type = "critical"; 3629 }; 3630 }; 3631 }; 3632 3633 cpu3-thermal { 3634 polling-delay-passive = <250>; 3635 polling-delay = <1000>; 3636 3637 thermal-sensors = <&tsens0 10>; 3638 3639 trips { 3640 cpu3_alert0: trip-point0 { 3641 temperature = <75000>; 3642 hysteresis = <2000>; 3643 type = "passive"; 3644 }; 3645 3646 cpu3_crit: cpu-crit { 3647 temperature = <110000>; 3648 hysteresis = <2000>; 3649 type = "critical"; 3650 }; 3651 }; 3652 }; 3653 3654 gpu-top-thermal { 3655 polling-delay-passive = <250>; 3656 polling-delay = <1000>; 3657 3658 thermal-sensors = <&tsens1 6>; 3659 3660 trips { 3661 gpu1_alert0: trip-point0 { 3662 temperature = <90000>; 3663 hysteresis = <2000>; 3664 type = "passive"; 3665 }; 3666 }; 3667 3668 cooling-maps { 3669 map0 { 3670 trip = <&gpu1_alert0>; 3671 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3672 }; 3673 }; 3674 }; 3675 3676 gpu-bottom-thermal { 3677 polling-delay-passive = <250>; 3678 polling-delay = <1000>; 3679 3680 thermal-sensors = <&tsens1 7>; 3681 3682 trips { 3683 gpu2_alert0: trip-point0 { 3684 temperature = <90000>; 3685 hysteresis = <2000>; 3686 type = "passive"; 3687 }; 3688 }; 3689 3690 cooling-maps { 3691 map0 { 3692 trip = <&gpu2_alert0>; 3693 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3694 }; 3695 }; 3696 }; 3697 3698 m4m-thermal { 3699 polling-delay-passive = <250>; 3700 polling-delay = <1000>; 3701 3702 thermal-sensors = <&tsens0 1>; 3703 3704 trips { 3705 m4m_alert0: trip-point0 { 3706 temperature = <90000>; 3707 hysteresis = <2000>; 3708 type = "hot"; 3709 }; 3710 }; 3711 }; 3712 3713 l3-or-venus-thermal { 3714 polling-delay-passive = <250>; 3715 polling-delay = <1000>; 3716 3717 thermal-sensors = <&tsens0 2>; 3718 3719 trips { 3720 l3_or_venus_alert0: trip-point0 { 3721 temperature = <90000>; 3722 hysteresis = <2000>; 3723 type = "hot"; 3724 }; 3725 }; 3726 }; 3727 3728 cluster0-l2-thermal { 3729 polling-delay-passive = <250>; 3730 polling-delay = <1000>; 3731 3732 thermal-sensors = <&tsens0 7>; 3733 3734 trips { 3735 cluster0_l2_alert0: trip-point0 { 3736 temperature = <90000>; 3737 hysteresis = <2000>; 3738 type = "hot"; 3739 }; 3740 }; 3741 }; 3742 3743 cluster1-l2-thermal { 3744 polling-delay-passive = <250>; 3745 polling-delay = <1000>; 3746 3747 thermal-sensors = <&tsens0 12>; 3748 3749 trips { 3750 cluster1_l2_alert0: trip-point0 { 3751 temperature = <90000>; 3752 hysteresis = <2000>; 3753 type = "hot"; 3754 }; 3755 }; 3756 }; 3757 3758 camera-thermal { 3759 polling-delay-passive = <250>; 3760 polling-delay = <1000>; 3761 3762 thermal-sensors = <&tsens1 1>; 3763 3764 trips { 3765 camera_alert0: trip-point0 { 3766 temperature = <90000>; 3767 hysteresis = <2000>; 3768 type = "hot"; 3769 }; 3770 }; 3771 }; 3772 3773 q6-dsp-thermal { 3774 polling-delay-passive = <250>; 3775 polling-delay = <1000>; 3776 3777 thermal-sensors = <&tsens1 2>; 3778 3779 trips { 3780 q6_dsp_alert0: trip-point0 { 3781 temperature = <90000>; 3782 hysteresis = <2000>; 3783 type = "hot"; 3784 }; 3785 }; 3786 }; 3787 3788 mem-thermal { 3789 polling-delay-passive = <250>; 3790 polling-delay = <1000>; 3791 3792 thermal-sensors = <&tsens1 3>; 3793 3794 trips { 3795 mem_alert0: trip-point0 { 3796 temperature = <90000>; 3797 hysteresis = <2000>; 3798 type = "hot"; 3799 }; 3800 }; 3801 }; 3802 3803 modemtx-thermal { 3804 polling-delay-passive = <250>; 3805 polling-delay = <1000>; 3806 3807 thermal-sensors = <&tsens1 4>; 3808 3809 trips { 3810 modemtx_alert0: trip-point0 { 3811 temperature = <90000>; 3812 hysteresis = <2000>; 3813 type = "hot"; 3814 }; 3815 }; 3816 }; 3817 }; 3818 3819 timer { 3820 compatible = "arm,armv8-timer"; 3821 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3822 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3823 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3824 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3825 }; 3826}; 3827