1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,apr.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo_board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep_clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32764>; 31 clock-output-names = "sleep_clk"; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 capacity-dmips-mhz = <1024>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 CPU2: cpu@100 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo"; 66 reg = <0x0 0x100>; 67 enable-method = "psci"; 68 cpu-idle-states = <&CPU_SLEEP_0>; 69 capacity-dmips-mhz = <1024>; 70 next-level-cache = <&L2_1>; 71 L2_1: l2-cache { 72 compatible = "cache"; 73 cache-level = <2>; 74 }; 75 }; 76 77 CPU3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo"; 80 reg = <0x0 0x101>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 capacity-dmips-mhz = <1024>; 84 next-level-cache = <&L2_1>; 85 }; 86 87 cpu-map { 88 cluster0 { 89 core0 { 90 cpu = <&CPU0>; 91 }; 92 93 core1 { 94 cpu = <&CPU1>; 95 }; 96 }; 97 98 cluster1 { 99 core0 { 100 cpu = <&CPU2>; 101 }; 102 103 core1 { 104 cpu = <&CPU3>; 105 }; 106 }; 107 }; 108 109 idle-states { 110 entry-method = "psci"; 111 112 CPU_SLEEP_0: cpu-sleep-0 { 113 compatible = "arm,idle-state"; 114 idle-state-name = "standalone-power-collapse"; 115 arm,psci-suspend-param = <0x00000004>; 116 entry-latency-us = <130>; 117 exit-latency-us = <80>; 118 min-residency-us = <300>; 119 }; 120 }; 121 }; 122 123 firmware { 124 scm { 125 compatible = "qcom,scm-msm8996"; 126 qcom,dload-mode = <&tcsr 0x13000>; 127 }; 128 }; 129 130 tcsr_mutex: hwlock { 131 compatible = "qcom,tcsr-mutex"; 132 syscon = <&tcsr_mutex_regs 0 0x1000>; 133 #hwlock-cells = <1>; 134 }; 135 136 memory { 137 device_type = "memory"; 138 /* We expect the bootloader to fill in the reg */ 139 reg = <0 0 0 0>; 140 }; 141 142 psci { 143 compatible = "arm,psci-1.0"; 144 method = "smc"; 145 }; 146 147 reserved-memory { 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 mba_region: mba@91500000 { 153 reg = <0x0 0x91500000 0x0 0x200000>; 154 no-map; 155 }; 156 157 slpi_region: slpi@90b00000 { 158 reg = <0x0 0x90b00000 0x0 0xa00000>; 159 no-map; 160 }; 161 162 venus_region: venus@90400000 { 163 reg = <0x0 0x90400000 0x0 0x700000>; 164 no-map; 165 }; 166 167 adsp_region: adsp@8ea00000 { 168 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 169 no-map; 170 }; 171 172 mpss_region: mpss@88800000 { 173 reg = <0x0 0x88800000 0x0 0x6200000>; 174 no-map; 175 }; 176 177 smem_mem: smem-mem@86000000 { 178 reg = <0x0 0x86000000 0x0 0x200000>; 179 no-map; 180 }; 181 182 memory@85800000 { 183 reg = <0x0 0x85800000 0x0 0x800000>; 184 no-map; 185 }; 186 187 memory@86200000 { 188 reg = <0x0 0x86200000 0x0 0x2600000>; 189 no-map; 190 }; 191 192 rmtfs@86700000 { 193 compatible = "qcom,rmtfs-mem"; 194 195 size = <0x0 0x200000>; 196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 197 no-map; 198 199 qcom,client-id = <1>; 200 qcom,vmid = <15>; 201 }; 202 203 zap_shader_region: gpu@8f200000 { 204 compatible = "shared-dma-pool"; 205 reg = <0x0 0x90b00000 0x0 0xa00000>; 206 no-map; 207 }; 208 }; 209 210 rpm-glink { 211 compatible = "qcom,glink-rpm"; 212 213 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 214 215 qcom,rpm-msg-ram = <&rpm_msg_ram>; 216 217 mboxes = <&apcs_glb 0>; 218 219 rpm_requests: rpm-requests { 220 compatible = "qcom,rpm-msm8996"; 221 qcom,glink-channels = "rpm_requests"; 222 223 rpmcc: qcom,rpmcc { 224 compatible = "qcom,rpmcc-msm8996"; 225 #clock-cells = <1>; 226 }; 227 228 rpmpd: power-controller { 229 compatible = "qcom,msm8996-rpmpd"; 230 #power-domain-cells = <1>; 231 operating-points-v2 = <&rpmpd_opp_table>; 232 233 rpmpd_opp_table: opp-table { 234 compatible = "operating-points-v2"; 235 236 rpmpd_opp1: opp1 { 237 opp-level = <1>; 238 }; 239 240 rpmpd_opp2: opp2 { 241 opp-level = <2>; 242 }; 243 244 rpmpd_opp3: opp3 { 245 opp-level = <3>; 246 }; 247 248 rpmpd_opp4: opp4 { 249 opp-level = <4>; 250 }; 251 252 rpmpd_opp5: opp5 { 253 opp-level = <5>; 254 }; 255 256 rpmpd_opp6: opp6 { 257 opp-level = <6>; 258 }; 259 }; 260 }; 261 }; 262 }; 263 264 smem { 265 compatible = "qcom,smem"; 266 memory-region = <&smem_mem>; 267 hwlocks = <&tcsr_mutex 3>; 268 }; 269 270 smp2p-adsp { 271 compatible = "qcom,smp2p"; 272 qcom,smem = <443>, <429>; 273 274 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 275 276 mboxes = <&apcs_glb 10>; 277 278 qcom,local-pid = <0>; 279 qcom,remote-pid = <2>; 280 281 smp2p_adsp_out: master-kernel { 282 qcom,entry-name = "master-kernel"; 283 #qcom,smem-state-cells = <1>; 284 }; 285 286 smp2p_adsp_in: slave-kernel { 287 qcom,entry-name = "slave-kernel"; 288 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 }; 293 294 smp2p-modem { 295 compatible = "qcom,smp2p"; 296 qcom,smem = <435>, <428>; 297 298 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 299 300 mboxes = <&apcs_glb 14>; 301 302 qcom,local-pid = <0>; 303 qcom,remote-pid = <1>; 304 305 modem_smp2p_out: master-kernel { 306 qcom,entry-name = "master-kernel"; 307 #qcom,smem-state-cells = <1>; 308 }; 309 310 modem_smp2p_in: slave-kernel { 311 qcom,entry-name = "slave-kernel"; 312 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 }; 316 }; 317 318 smp2p-slpi { 319 compatible = "qcom,smp2p"; 320 qcom,smem = <481>, <430>; 321 322 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 323 324 mboxes = <&apcs_glb 26>; 325 326 qcom,local-pid = <0>; 327 qcom,remote-pid = <3>; 328 329 smp2p_slpi_in: slave-kernel { 330 qcom,entry-name = "slave-kernel"; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 }; 334 335 smp2p_slpi_out: master-kernel { 336 qcom,entry-name = "master-kernel"; 337 #qcom,smem-state-cells = <1>; 338 }; 339 }; 340 341 soc: soc { 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges = <0 0 0 0xffffffff>; 345 compatible = "simple-bus"; 346 347 pcie_phy: phy@34000 { 348 compatible = "qcom,msm8996-qmp-pcie-phy"; 349 reg = <0x00034000 0x488>; 350 #clock-cells = <1>; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges; 354 355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 356 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 357 <&gcc GCC_PCIE_CLKREF_CLK>; 358 clock-names = "aux", "cfg_ahb", "ref"; 359 360 resets = <&gcc GCC_PCIE_PHY_BCR>, 361 <&gcc GCC_PCIE_PHY_COM_BCR>, 362 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 363 reset-names = "phy", "common", "cfg"; 364 status = "disabled"; 365 366 pciephy_0: lane@35000 { 367 reg = <0x00035000 0x130>, 368 <0x00035200 0x200>, 369 <0x00035400 0x1dc>; 370 #phy-cells = <0>; 371 372 clock-output-names = "pcie_0_pipe_clk_src"; 373 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 374 clock-names = "pipe0"; 375 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 376 reset-names = "lane0"; 377 }; 378 379 pciephy_1: lane@36000 { 380 reg = <0x00036000 0x130>, 381 <0x00036200 0x200>, 382 <0x00036400 0x1dc>; 383 #phy-cells = <0>; 384 385 clock-output-names = "pcie_1_pipe_clk_src"; 386 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 387 clock-names = "pipe1"; 388 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 389 reset-names = "lane1"; 390 }; 391 392 pciephy_2: lane@37000 { 393 reg = <0x00037000 0x130>, 394 <0x00037200 0x200>, 395 <0x00037400 0x1dc>; 396 #phy-cells = <0>; 397 398 clock-output-names = "pcie_2_pipe_clk_src"; 399 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 400 clock-names = "pipe2"; 401 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 402 reset-names = "lane2"; 403 }; 404 }; 405 406 rpm_msg_ram: memory@68000 { 407 compatible = "qcom,rpm-msg-ram"; 408 reg = <0x00068000 0x6000>; 409 }; 410 411 qfprom@74000 { 412 compatible = "qcom,qfprom"; 413 reg = <0x00074000 0x8ff>; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 417 qusb2p_hstx_trim: hstx_trim@24e { 418 reg = <0x24e 0x2>; 419 bits = <5 4>; 420 }; 421 422 qusb2s_hstx_trim: hstx_trim@24f { 423 reg = <0x24f 0x1>; 424 bits = <1 4>; 425 }; 426 427 gpu_speed_bin: gpu_speed_bin@133 { 428 reg = <0x133 0x1>; 429 bits = <5 3>; 430 }; 431 }; 432 433 rng: rng@83000 { 434 compatible = "qcom,prng-ee"; 435 reg = <0x00083000 0x1000>; 436 clocks = <&gcc GCC_PRNG_AHB_CLK>; 437 clock-names = "core"; 438 }; 439 440 gcc: clock-controller@300000 { 441 compatible = "qcom,gcc-msm8996"; 442 #clock-cells = <1>; 443 #reset-cells = <1>; 444 #power-domain-cells = <1>; 445 reg = <0x00300000 0x90000>; 446 447 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; 448 clock-names = "cxo2"; 449 }; 450 451 tsens0: thermal-sensor@4a9000 { 452 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 453 reg = <0x004a9000 0x1000>, /* TM */ 454 <0x004a8000 0x1000>; /* SROT */ 455 #qcom,sensors = <13>; 456 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "uplow", "critical"; 459 #thermal-sensor-cells = <1>; 460 }; 461 462 tsens1: thermal-sensor@4ad000 { 463 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 464 reg = <0x004ad000 0x1000>, /* TM */ 465 <0x004ac000 0x1000>; /* SROT */ 466 #qcom,sensors = <8>; 467 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-names = "uplow", "critical"; 470 #thermal-sensor-cells = <1>; 471 }; 472 473 tcsr_mutex_regs: syscon@740000 { 474 compatible = "syscon"; 475 reg = <0x00740000 0x20000>; 476 }; 477 478 tcsr: syscon@7a0000 { 479 compatible = "qcom,tcsr-msm8996", "syscon"; 480 reg = <0x007a0000 0x18000>; 481 }; 482 483 mmcc: clock-controller@8c0000 { 484 compatible = "qcom,mmcc-msm8996"; 485 #clock-cells = <1>; 486 #reset-cells = <1>; 487 #power-domain-cells = <1>; 488 reg = <0x008c0000 0x40000>; 489 assigned-clocks = <&mmcc MMPLL9_PLL>, 490 <&mmcc MMPLL1_PLL>, 491 <&mmcc MMPLL3_PLL>, 492 <&mmcc MMPLL4_PLL>, 493 <&mmcc MMPLL5_PLL>; 494 assigned-clock-rates = <624000000>, 495 <810000000>, 496 <980000000>, 497 <960000000>, 498 <825000000>; 499 }; 500 501 mdss: mdss@900000 { 502 compatible = "qcom,mdss"; 503 504 reg = <0x00900000 0x1000>, 505 <0x009b0000 0x1040>, 506 <0x009b8000 0x1040>; 507 reg-names = "mdss_phys", 508 "vbif_phys", 509 "vbif_nrt_phys"; 510 511 power-domains = <&mmcc MDSS_GDSC>; 512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 513 514 interrupt-controller; 515 #interrupt-cells = <1>; 516 517 clocks = <&mmcc MDSS_AHB_CLK>; 518 clock-names = "iface"; 519 520 #address-cells = <1>; 521 #size-cells = <1>; 522 ranges; 523 524 mdp: mdp@901000 { 525 compatible = "qcom,mdp5"; 526 reg = <0x00901000 0x90000>; 527 reg-names = "mdp_phys"; 528 529 interrupt-parent = <&mdss>; 530 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 531 532 clocks = <&mmcc MDSS_AHB_CLK>, 533 <&mmcc MDSS_AXI_CLK>, 534 <&mmcc MDSS_MDP_CLK>, 535 <&mmcc SMMU_MDP_AXI_CLK>, 536 <&mmcc MDSS_VSYNC_CLK>; 537 clock-names = "iface", 538 "bus", 539 "core", 540 "iommu", 541 "vsync"; 542 543 iommus = <&mdp_smmu 0>; 544 545 ports { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 port@0 { 550 reg = <0>; 551 mdp5_intf3_out: endpoint { 552 remote-endpoint = <&hdmi_in>; 553 }; 554 }; 555 }; 556 }; 557 558 hdmi: hdmi-tx@9a0000 { 559 compatible = "qcom,hdmi-tx-8996"; 560 reg = <0x009a0000 0x50c>, 561 <0x00070000 0x6158>, 562 <0x009e0000 0xfff>; 563 reg-names = "core_physical", 564 "qfprom_physical", 565 "hdcp_physical"; 566 567 interrupt-parent = <&mdss>; 568 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 569 570 clocks = <&mmcc MDSS_MDP_CLK>, 571 <&mmcc MDSS_AHB_CLK>, 572 <&mmcc MDSS_HDMI_CLK>, 573 <&mmcc MDSS_HDMI_AHB_CLK>, 574 <&mmcc MDSS_EXTPCLK_CLK>; 575 clock-names = 576 "mdp_core", 577 "iface", 578 "core", 579 "alt_iface", 580 "extp"; 581 582 phys = <&hdmi_phy>; 583 phy-names = "hdmi_phy"; 584 #sound-dai-cells = <1>; 585 586 ports { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 590 port@0 { 591 reg = <0>; 592 hdmi_in: endpoint { 593 remote-endpoint = <&mdp5_intf3_out>; 594 }; 595 }; 596 }; 597 }; 598 599 hdmi_phy: hdmi-phy@9a0600 { 600 #phy-cells = <0>; 601 compatible = "qcom,hdmi-phy-8996"; 602 reg = <0x009a0600 0x1c4>, 603 <0x009a0a00 0x124>, 604 <0x009a0c00 0x124>, 605 <0x009a0e00 0x124>, 606 <0x009a1000 0x124>, 607 <0x009a1200 0x0c8>; 608 reg-names = "hdmi_pll", 609 "hdmi_tx_l0", 610 "hdmi_tx_l1", 611 "hdmi_tx_l2", 612 "hdmi_tx_l3", 613 "hdmi_phy"; 614 615 clocks = <&mmcc MDSS_AHB_CLK>, 616 <&gcc GCC_HDMI_CLKREF_CLK>; 617 clock-names = "iface", 618 "ref"; 619 }; 620 }; 621 gpu@b00000 { 622 compatible = "qcom,adreno-530.2", "qcom,adreno"; 623 #stream-id-cells = <16>; 624 625 reg = <0x00b00000 0x3f000>; 626 reg-names = "kgsl_3d0_reg_memory"; 627 628 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 629 630 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 631 <&mmcc GPU_AHB_CLK>, 632 <&mmcc GPU_GX_RBBMTIMER_CLK>, 633 <&gcc GCC_BIMC_GFX_CLK>, 634 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 635 636 clock-names = "core", 637 "iface", 638 "rbbmtimer", 639 "mem", 640 "mem_iface"; 641 642 power-domains = <&mmcc GPU_GX_GDSC>; 643 iommus = <&adreno_smmu 0>; 644 645 nvmem-cells = <&gpu_speed_bin>; 646 nvmem-cell-names = "speed_bin"; 647 648 qcom,gpu-quirk-two-pass-use-wfi; 649 qcom,gpu-quirk-fault-detect-mask; 650 651 operating-points-v2 = <&gpu_opp_table>; 652 653 gpu_opp_table: opp-table { 654 compatible ="operating-points-v2"; 655 656 /* 657 * 624Mhz and 560Mhz are only available on speed 658 * bin (1 << 0). All the rest are available on 659 * all bins of the hardware 660 */ 661 opp-624000000 { 662 opp-hz = /bits/ 64 <624000000>; 663 opp-supported-hw = <0x01>; 664 }; 665 opp-560000000 { 666 opp-hz = /bits/ 64 <560000000>; 667 opp-supported-hw = <0x01>; 668 }; 669 opp-510000000 { 670 opp-hz = /bits/ 64 <510000000>; 671 opp-supported-hw = <0xFF>; 672 }; 673 opp-401800000 { 674 opp-hz = /bits/ 64 <401800000>; 675 opp-supported-hw = <0xFF>; 676 }; 677 opp-315000000 { 678 opp-hz = /bits/ 64 <315000000>; 679 opp-supported-hw = <0xFF>; 680 }; 681 opp-214000000 { 682 opp-hz = /bits/ 64 <214000000>; 683 opp-supported-hw = <0xFF>; 684 }; 685 opp-133000000 { 686 opp-hz = /bits/ 64 <133000000>; 687 opp-supported-hw = <0xFF>; 688 }; 689 }; 690 691 zap-shader { 692 memory-region = <&zap_shader_region>; 693 }; 694 }; 695 696 msmgpio: pinctrl@1010000 { 697 compatible = "qcom,msm8996-pinctrl"; 698 reg = <0x01010000 0x300000>; 699 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 700 gpio-controller; 701 gpio-ranges = <&msmgpio 0 0 150>; 702 #gpio-cells = <2>; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 }; 706 707 spmi_bus: qcom,spmi@400f000 { 708 compatible = "qcom,spmi-pmic-arb"; 709 reg = <0x0400f000 0x1000>, 710 <0x04400000 0x800000>, 711 <0x04c00000 0x800000>, 712 <0x05800000 0x200000>, 713 <0x0400a000 0x002100>; 714 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 715 interrupt-names = "periph_irq"; 716 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 717 qcom,ee = <0>; 718 qcom,channel = <0>; 719 #address-cells = <2>; 720 #size-cells = <0>; 721 interrupt-controller; 722 #interrupt-cells = <4>; 723 }; 724 725 agnoc@0 { 726 power-domains = <&gcc AGGRE0_NOC_GDSC>; 727 compatible = "simple-pm-bus"; 728 #address-cells = <1>; 729 #size-cells = <1>; 730 ranges; 731 732 pcie0: pcie@600000 { 733 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 734 status = "disabled"; 735 power-domains = <&gcc PCIE0_GDSC>; 736 bus-range = <0x00 0xff>; 737 num-lanes = <1>; 738 739 reg = <0x00600000 0x2000>, 740 <0x0c000000 0xf1d>, 741 <0x0c000f20 0xa8>, 742 <0x0c100000 0x100000>; 743 reg-names = "parf", "dbi", "elbi","config"; 744 745 phys = <&pciephy_0>; 746 phy-names = "pciephy"; 747 748 #address-cells = <3>; 749 #size-cells = <2>; 750 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 751 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 752 753 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "msi"; 755 #interrupt-cells = <1>; 756 interrupt-map-mask = <0 0 0 0x7>; 757 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 758 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 759 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 760 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 761 762 pinctrl-names = "default", "sleep"; 763 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 764 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 765 766 linux,pci-domain = <0>; 767 768 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 769 <&gcc GCC_PCIE_0_AUX_CLK>, 770 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 771 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 772 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 773 774 clock-names = "pipe", 775 "aux", 776 "cfg", 777 "bus_master", 778 "bus_slave"; 779 780 }; 781 782 pcie1: pcie@608000 { 783 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 784 power-domains = <&gcc PCIE1_GDSC>; 785 bus-range = <0x00 0xff>; 786 num-lanes = <1>; 787 788 status = "disabled"; 789 790 reg = <0x00608000 0x2000>, 791 <0x0d000000 0xf1d>, 792 <0x0d000f20 0xa8>, 793 <0x0d100000 0x100000>; 794 795 reg-names = "parf", "dbi", "elbi","config"; 796 797 phys = <&pciephy_1>; 798 phy-names = "pciephy"; 799 800 #address-cells = <3>; 801 #size-cells = <2>; 802 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 803 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 804 805 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 806 interrupt-names = "msi"; 807 #interrupt-cells = <1>; 808 interrupt-map-mask = <0 0 0 0x7>; 809 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 810 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 811 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 812 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 813 814 pinctrl-names = "default", "sleep"; 815 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 816 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 817 818 linux,pci-domain = <1>; 819 820 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 821 <&gcc GCC_PCIE_1_AUX_CLK>, 822 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 823 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 824 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 825 826 clock-names = "pipe", 827 "aux", 828 "cfg", 829 "bus_master", 830 "bus_slave"; 831 }; 832 833 pcie2: pcie@610000 { 834 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 835 power-domains = <&gcc PCIE2_GDSC>; 836 bus-range = <0x00 0xff>; 837 num-lanes = <1>; 838 status = "disabled"; 839 reg = <0x00610000 0x2000>, 840 <0x0e000000 0xf1d>, 841 <0x0e000f20 0xa8>, 842 <0x0e100000 0x100000>; 843 844 reg-names = "parf", "dbi", "elbi","config"; 845 846 phys = <&pciephy_2>; 847 phy-names = "pciephy"; 848 849 #address-cells = <3>; 850 #size-cells = <2>; 851 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 852 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 853 854 device_type = "pci"; 855 856 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 857 interrupt-names = "msi"; 858 #interrupt-cells = <1>; 859 interrupt-map-mask = <0 0 0 0x7>; 860 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 861 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 862 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 863 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 864 865 pinctrl-names = "default", "sleep"; 866 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 867 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 868 869 linux,pci-domain = <2>; 870 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 871 <&gcc GCC_PCIE_2_AUX_CLK>, 872 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 873 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 874 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 875 876 clock-names = "pipe", 877 "aux", 878 "cfg", 879 "bus_master", 880 "bus_slave"; 881 }; 882 }; 883 884 ufshc: ufshc@624000 { 885 compatible = "qcom,ufshc"; 886 reg = <0x00624000 0x2500>; 887 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 888 889 phys = <&ufsphy_lane>; 890 phy-names = "ufsphy"; 891 892 power-domains = <&gcc UFS_GDSC>; 893 894 clock-names = 895 "core_clk_src", 896 "core_clk", 897 "bus_clk", 898 "bus_aggr_clk", 899 "iface_clk", 900 "core_clk_unipro_src", 901 "core_clk_unipro", 902 "core_clk_ice", 903 "ref_clk", 904 "tx_lane0_sync_clk", 905 "rx_lane0_sync_clk"; 906 clocks = 907 <&gcc UFS_AXI_CLK_SRC>, 908 <&gcc GCC_UFS_AXI_CLK>, 909 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 910 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 911 <&gcc GCC_UFS_AHB_CLK>, 912 <&gcc UFS_ICE_CORE_CLK_SRC>, 913 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 914 <&gcc GCC_UFS_ICE_CORE_CLK>, 915 <&rpmcc RPM_SMD_LN_BB_CLK>, 916 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 917 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 918 freq-table-hz = 919 <100000000 200000000>, 920 <0 0>, 921 <0 0>, 922 <0 0>, 923 <0 0>, 924 <150000000 300000000>, 925 <0 0>, 926 <0 0>, 927 <0 0>, 928 <0 0>, 929 <0 0>; 930 931 lanes-per-direction = <1>; 932 #reset-cells = <1>; 933 status = "disabled"; 934 935 ufs_variant { 936 compatible = "qcom,ufs_variant"; 937 }; 938 }; 939 940 ufsphy: phy@627000 { 941 compatible = "qcom,msm8996-qmp-ufs-phy"; 942 reg = <0x00627000 0x1c4>; 943 #address-cells = <1>; 944 #size-cells = <1>; 945 ranges; 946 947 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 948 clock-names = "ref"; 949 950 resets = <&ufshc 0>; 951 reset-names = "ufsphy"; 952 status = "disabled"; 953 954 ufsphy_lane: lanes@627400 { 955 reg = <0x627400 0x12c>, 956 <0x627600 0x200>, 957 <0x627c00 0x1b4>; 958 #phy-cells = <0>; 959 }; 960 }; 961 962 camss: camss@a00000 { 963 compatible = "qcom,msm8996-camss"; 964 reg = <0x00a34000 0x1000>, 965 <0x00a00030 0x4>, 966 <0x00a35000 0x1000>, 967 <0x00a00038 0x4>, 968 <0x00a36000 0x1000>, 969 <0x00a00040 0x4>, 970 <0x00a30000 0x100>, 971 <0x00a30400 0x100>, 972 <0x00a30800 0x100>, 973 <0x00a30c00 0x100>, 974 <0x00a31000 0x500>, 975 <0x00a00020 0x10>, 976 <0x00a10000 0x1000>, 977 <0x00a14000 0x1000>; 978 reg-names = "csiphy0", 979 "csiphy0_clk_mux", 980 "csiphy1", 981 "csiphy1_clk_mux", 982 "csiphy2", 983 "csiphy2_clk_mux", 984 "csid0", 985 "csid1", 986 "csid2", 987 "csid3", 988 "ispif", 989 "csi_clk_mux", 990 "vfe0", 991 "vfe1"; 992 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 993 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 994 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 995 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 996 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 997 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 998 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 999 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1000 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1001 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1002 interrupt-names = "csiphy0", 1003 "csiphy1", 1004 "csiphy2", 1005 "csid0", 1006 "csid1", 1007 "csid2", 1008 "csid3", 1009 "ispif", 1010 "vfe0", 1011 "vfe1"; 1012 power-domains = <&mmcc VFE0_GDSC>; 1013 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1014 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1015 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1016 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1017 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1018 <&mmcc CAMSS_CSI0_AHB_CLK>, 1019 <&mmcc CAMSS_CSI0_CLK>, 1020 <&mmcc CAMSS_CSI0PHY_CLK>, 1021 <&mmcc CAMSS_CSI0PIX_CLK>, 1022 <&mmcc CAMSS_CSI0RDI_CLK>, 1023 <&mmcc CAMSS_CSI1_AHB_CLK>, 1024 <&mmcc CAMSS_CSI1_CLK>, 1025 <&mmcc CAMSS_CSI1PHY_CLK>, 1026 <&mmcc CAMSS_CSI1PIX_CLK>, 1027 <&mmcc CAMSS_CSI1RDI_CLK>, 1028 <&mmcc CAMSS_CSI2_AHB_CLK>, 1029 <&mmcc CAMSS_CSI2_CLK>, 1030 <&mmcc CAMSS_CSI2PHY_CLK>, 1031 <&mmcc CAMSS_CSI2PIX_CLK>, 1032 <&mmcc CAMSS_CSI2RDI_CLK>, 1033 <&mmcc CAMSS_CSI3_AHB_CLK>, 1034 <&mmcc CAMSS_CSI3_CLK>, 1035 <&mmcc CAMSS_CSI3PHY_CLK>, 1036 <&mmcc CAMSS_CSI3PIX_CLK>, 1037 <&mmcc CAMSS_CSI3RDI_CLK>, 1038 <&mmcc CAMSS_AHB_CLK>, 1039 <&mmcc CAMSS_VFE0_CLK>, 1040 <&mmcc CAMSS_CSI_VFE0_CLK>, 1041 <&mmcc CAMSS_VFE0_AHB_CLK>, 1042 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1043 <&mmcc CAMSS_VFE1_CLK>, 1044 <&mmcc CAMSS_CSI_VFE1_CLK>, 1045 <&mmcc CAMSS_VFE1_AHB_CLK>, 1046 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1047 <&mmcc CAMSS_VFE_AHB_CLK>, 1048 <&mmcc CAMSS_VFE_AXI_CLK>; 1049 clock-names = "top_ahb", 1050 "ispif_ahb", 1051 "csiphy0_timer", 1052 "csiphy1_timer", 1053 "csiphy2_timer", 1054 "csi0_ahb", 1055 "csi0", 1056 "csi0_phy", 1057 "csi0_pix", 1058 "csi0_rdi", 1059 "csi1_ahb", 1060 "csi1", 1061 "csi1_phy", 1062 "csi1_pix", 1063 "csi1_rdi", 1064 "csi2_ahb", 1065 "csi2", 1066 "csi2_phy", 1067 "csi2_pix", 1068 "csi2_rdi", 1069 "csi3_ahb", 1070 "csi3", 1071 "csi3_phy", 1072 "csi3_pix", 1073 "csi3_rdi", 1074 "ahb", 1075 "vfe0", 1076 "csi_vfe0", 1077 "vfe0_ahb", 1078 "vfe0_stream", 1079 "vfe1", 1080 "csi_vfe1", 1081 "vfe1_ahb", 1082 "vfe1_stream", 1083 "vfe_ahb", 1084 "vfe_axi"; 1085 iommus = <&vfe_smmu 0>, 1086 <&vfe_smmu 1>, 1087 <&vfe_smmu 2>, 1088 <&vfe_smmu 3>; 1089 status = "disabled"; 1090 ports { 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 }; 1094 }; 1095 1096 cci: cci@a0c000 { 1097 compatible = "qcom,msm8996-cci"; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 reg = <0xa0c000 0x1000>; 1101 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1102 power-domains = <&mmcc CAMSS_GDSC>; 1103 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1104 <&mmcc CAMSS_CCI_AHB_CLK>, 1105 <&mmcc CAMSS_CCI_CLK>, 1106 <&mmcc CAMSS_AHB_CLK>; 1107 clock-names = "camss_top_ahb", 1108 "cci_ahb", 1109 "cci", 1110 "camss_ahb"; 1111 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1112 <&mmcc CAMSS_CCI_CLK>; 1113 assigned-clock-rates = <80000000>, <37500000>; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&cci0_default &cci1_default>; 1116 status = "disabled"; 1117 1118 cci_i2c0: i2c-bus@0 { 1119 reg = <0>; 1120 clock-frequency = <400000>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 }; 1124 1125 cci_i2c1: i2c-bus@1 { 1126 reg = <1>; 1127 clock-frequency = <400000>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 }; 1131 }; 1132 1133 adreno_smmu: iommu@b40000 { 1134 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1135 reg = <0x00b40000 0x10000>; 1136 1137 #global-interrupts = <1>; 1138 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1141 #iommu-cells = <1>; 1142 1143 clocks = <&mmcc GPU_AHB_CLK>, 1144 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1145 clock-names = "iface", "bus"; 1146 1147 power-domains = <&mmcc GPU_GDSC>; 1148 }; 1149 1150 video-codec@c00000 { 1151 compatible = "qcom,msm8996-venus"; 1152 reg = <0x00c00000 0xff000>; 1153 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 1154 power-domains = <&mmcc VENUS_GDSC>; 1155 clocks = <&mmcc VIDEO_CORE_CLK>, 1156 <&mmcc VIDEO_AHB_CLK>, 1157 <&mmcc VIDEO_AXI_CLK>, 1158 <&mmcc VIDEO_MAXI_CLK>; 1159 clock-names = "core", "iface", "bus", "mbus"; 1160 iommus = <&venus_smmu 0x00>, 1161 <&venus_smmu 0x01>, 1162 <&venus_smmu 0x0a>, 1163 <&venus_smmu 0x07>, 1164 <&venus_smmu 0x0e>, 1165 <&venus_smmu 0x0f>, 1166 <&venus_smmu 0x08>, 1167 <&venus_smmu 0x09>, 1168 <&venus_smmu 0x0b>, 1169 <&venus_smmu 0x0c>, 1170 <&venus_smmu 0x0d>, 1171 <&venus_smmu 0x10>, 1172 <&venus_smmu 0x11>, 1173 <&venus_smmu 0x21>, 1174 <&venus_smmu 0x28>, 1175 <&venus_smmu 0x29>, 1176 <&venus_smmu 0x2b>, 1177 <&venus_smmu 0x2c>, 1178 <&venus_smmu 0x2d>, 1179 <&venus_smmu 0x31>; 1180 memory-region = <&venus_region>; 1181 status = "okay"; 1182 1183 video-decoder { 1184 compatible = "venus-decoder"; 1185 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 1186 clock-names = "core"; 1187 power-domains = <&mmcc VENUS_CORE0_GDSC>; 1188 }; 1189 1190 video-encoder { 1191 compatible = "venus-encoder"; 1192 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 1193 clock-names = "core"; 1194 power-domains = <&mmcc VENUS_CORE1_GDSC>; 1195 }; 1196 }; 1197 1198 mdp_smmu: iommu@d00000 { 1199 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1200 reg = <0x00d00000 0x10000>; 1201 1202 #global-interrupts = <1>; 1203 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1206 #iommu-cells = <1>; 1207 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 1208 <&mmcc SMMU_MDP_AXI_CLK>; 1209 clock-names = "iface", "bus"; 1210 1211 power-domains = <&mmcc MDSS_GDSC>; 1212 }; 1213 1214 venus_smmu: iommu@d40000 { 1215 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1216 reg = <0x00d40000 0x20000>; 1217 #global-interrupts = <1>; 1218 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1226 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 1227 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 1228 <&mmcc SMMU_VIDEO_AXI_CLK>; 1229 clock-names = "iface", "bus"; 1230 #iommu-cells = <1>; 1231 status = "okay"; 1232 }; 1233 1234 vfe_smmu: iommu@da0000 { 1235 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1236 reg = <0x00da0000 0x10000>; 1237 1238 #global-interrupts = <1>; 1239 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1242 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 1243 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 1244 <&mmcc SMMU_VFE_AXI_CLK>; 1245 clock-names = "iface", 1246 "bus"; 1247 #iommu-cells = <1>; 1248 }; 1249 1250 lpass_q6_smmu: iommu@1600000 { 1251 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1252 reg = <0x01600000 0x20000>; 1253 #iommu-cells = <1>; 1254 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 1255 1256 #global-interrupts = <1>; 1257 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 1270 1271 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 1272 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1273 clock-names = "iface", "bus"; 1274 }; 1275 1276 stm@3002000 { 1277 compatible = "arm,coresight-stm", "arm,primecell"; 1278 reg = <0x3002000 0x1000>, 1279 <0x8280000 0x180000>; 1280 reg-names = "stm-base", "stm-stimulus-base"; 1281 1282 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1283 clock-names = "apb_pclk", "atclk"; 1284 1285 out-ports { 1286 port { 1287 stm_out: endpoint { 1288 remote-endpoint = 1289 <&funnel0_in>; 1290 }; 1291 }; 1292 }; 1293 }; 1294 1295 tpiu@3020000 { 1296 compatible = "arm,coresight-tpiu", "arm,primecell"; 1297 reg = <0x3020000 0x1000>; 1298 1299 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1300 clock-names = "apb_pclk", "atclk"; 1301 1302 in-ports { 1303 port { 1304 tpiu_in: endpoint { 1305 remote-endpoint = 1306 <&replicator_out1>; 1307 }; 1308 }; 1309 }; 1310 }; 1311 1312 funnel@3021000 { 1313 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1314 reg = <0x3021000 0x1000>; 1315 1316 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1317 clock-names = "apb_pclk", "atclk"; 1318 1319 in-ports { 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 1323 port@7 { 1324 reg = <7>; 1325 funnel0_in: endpoint { 1326 remote-endpoint = 1327 <&stm_out>; 1328 }; 1329 }; 1330 }; 1331 1332 out-ports { 1333 port { 1334 funnel0_out: endpoint { 1335 remote-endpoint = 1336 <&merge_funnel_in0>; 1337 }; 1338 }; 1339 }; 1340 }; 1341 1342 funnel@3022000 { 1343 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1344 reg = <0x3022000 0x1000>; 1345 1346 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1347 clock-names = "apb_pclk", "atclk"; 1348 1349 in-ports { 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 1353 port@6 { 1354 reg = <6>; 1355 funnel1_in: endpoint { 1356 remote-endpoint = 1357 <&apss_merge_funnel_out>; 1358 }; 1359 }; 1360 }; 1361 1362 out-ports { 1363 port { 1364 funnel1_out: endpoint { 1365 remote-endpoint = 1366 <&merge_funnel_in1>; 1367 }; 1368 }; 1369 }; 1370 }; 1371 1372 funnel@3023000 { 1373 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1374 reg = <0x3023000 0x1000>; 1375 1376 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1377 clock-names = "apb_pclk", "atclk"; 1378 1379 1380 out-ports { 1381 port { 1382 funnel2_out: endpoint { 1383 remote-endpoint = 1384 <&merge_funnel_in2>; 1385 }; 1386 }; 1387 }; 1388 }; 1389 1390 funnel@3025000 { 1391 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1392 reg = <0x3025000 0x1000>; 1393 1394 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1395 clock-names = "apb_pclk", "atclk"; 1396 1397 in-ports { 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 1401 port@0 { 1402 reg = <0>; 1403 merge_funnel_in0: endpoint { 1404 remote-endpoint = 1405 <&funnel0_out>; 1406 }; 1407 }; 1408 1409 port@1 { 1410 reg = <1>; 1411 merge_funnel_in1: endpoint { 1412 remote-endpoint = 1413 <&funnel1_out>; 1414 }; 1415 }; 1416 1417 port@2 { 1418 reg = <2>; 1419 merge_funnel_in2: endpoint { 1420 remote-endpoint = 1421 <&funnel2_out>; 1422 }; 1423 }; 1424 }; 1425 1426 out-ports { 1427 port { 1428 merge_funnel_out: endpoint { 1429 remote-endpoint = 1430 <&etf_in>; 1431 }; 1432 }; 1433 }; 1434 }; 1435 1436 replicator@3026000 { 1437 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1438 reg = <0x3026000 0x1000>; 1439 1440 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1441 clock-names = "apb_pclk", "atclk"; 1442 1443 in-ports { 1444 port { 1445 replicator_in: endpoint { 1446 remote-endpoint = 1447 <&etf_out>; 1448 }; 1449 }; 1450 }; 1451 1452 out-ports { 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 1456 port@0 { 1457 reg = <0>; 1458 replicator_out0: endpoint { 1459 remote-endpoint = 1460 <&etr_in>; 1461 }; 1462 }; 1463 1464 port@1 { 1465 reg = <1>; 1466 replicator_out1: endpoint { 1467 remote-endpoint = 1468 <&tpiu_in>; 1469 }; 1470 }; 1471 }; 1472 }; 1473 1474 etf@3027000 { 1475 compatible = "arm,coresight-tmc", "arm,primecell"; 1476 reg = <0x3027000 0x1000>; 1477 1478 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1479 clock-names = "apb_pclk", "atclk"; 1480 1481 in-ports { 1482 port { 1483 etf_in: endpoint { 1484 remote-endpoint = 1485 <&merge_funnel_out>; 1486 }; 1487 }; 1488 }; 1489 1490 out-ports { 1491 port { 1492 etf_out: endpoint { 1493 remote-endpoint = 1494 <&replicator_in>; 1495 }; 1496 }; 1497 }; 1498 }; 1499 1500 etr@3028000 { 1501 compatible = "arm,coresight-tmc", "arm,primecell"; 1502 reg = <0x3028000 0x1000>; 1503 1504 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1505 clock-names = "apb_pclk", "atclk"; 1506 arm,scatter-gather; 1507 1508 in-ports { 1509 port { 1510 etr_in: endpoint { 1511 remote-endpoint = 1512 <&replicator_out0>; 1513 }; 1514 }; 1515 }; 1516 }; 1517 1518 debug@3810000 { 1519 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1520 reg = <0x3810000 0x1000>; 1521 1522 clocks = <&rpmcc RPM_QDSS_CLK>; 1523 clock-names = "apb_pclk"; 1524 1525 cpu = <&CPU0>; 1526 }; 1527 1528 etm@3840000 { 1529 compatible = "arm,coresight-etm4x", "arm,primecell"; 1530 reg = <0x3840000 0x1000>; 1531 1532 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1533 clock-names = "apb_pclk", "atclk"; 1534 1535 cpu = <&CPU0>; 1536 1537 out-ports { 1538 port { 1539 etm0_out: endpoint { 1540 remote-endpoint = 1541 <&apss_funnel0_in0>; 1542 }; 1543 }; 1544 }; 1545 }; 1546 1547 debug@3910000 { 1548 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1549 reg = <0x3910000 0x1000>; 1550 1551 clocks = <&rpmcc RPM_QDSS_CLK>; 1552 clock-names = "apb_pclk"; 1553 1554 cpu = <&CPU1>; 1555 }; 1556 1557 etm@3940000 { 1558 compatible = "arm,coresight-etm4x", "arm,primecell"; 1559 reg = <0x3940000 0x1000>; 1560 1561 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1562 clock-names = "apb_pclk", "atclk"; 1563 1564 cpu = <&CPU1>; 1565 1566 out-ports { 1567 port { 1568 etm1_out: endpoint { 1569 remote-endpoint = 1570 <&apss_funnel0_in1>; 1571 }; 1572 }; 1573 }; 1574 }; 1575 1576 funnel@39b0000 { /* APSS Funnel 0 */ 1577 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1578 reg = <0x39b0000 0x1000>; 1579 1580 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1581 clock-names = "apb_pclk", "atclk"; 1582 1583 in-ports { 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 1587 port@0 { 1588 reg = <0>; 1589 apss_funnel0_in0: endpoint { 1590 remote-endpoint = <&etm0_out>; 1591 }; 1592 }; 1593 1594 port@1 { 1595 reg = <1>; 1596 apss_funnel0_in1: endpoint { 1597 remote-endpoint = <&etm1_out>; 1598 }; 1599 }; 1600 }; 1601 1602 out-ports { 1603 port { 1604 apss_funnel0_out: endpoint { 1605 remote-endpoint = 1606 <&apss_merge_funnel_in0>; 1607 }; 1608 }; 1609 }; 1610 }; 1611 1612 debug@3a10000 { 1613 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1614 reg = <0x3a10000 0x1000>; 1615 1616 clocks = <&rpmcc RPM_QDSS_CLK>; 1617 clock-names = "apb_pclk"; 1618 1619 cpu = <&CPU2>; 1620 }; 1621 1622 etm@3a40000 { 1623 compatible = "arm,coresight-etm4x", "arm,primecell"; 1624 reg = <0x3a40000 0x1000>; 1625 1626 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1627 clock-names = "apb_pclk", "atclk"; 1628 1629 cpu = <&CPU2>; 1630 1631 out-ports { 1632 port { 1633 etm2_out: endpoint { 1634 remote-endpoint = 1635 <&apss_funnel1_in0>; 1636 }; 1637 }; 1638 }; 1639 }; 1640 1641 debug@3b10000 { 1642 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1643 reg = <0x3b10000 0x1000>; 1644 1645 clocks = <&rpmcc RPM_QDSS_CLK>; 1646 clock-names = "apb_pclk"; 1647 1648 cpu = <&CPU3>; 1649 }; 1650 1651 etm@3b40000 { 1652 compatible = "arm,coresight-etm4x", "arm,primecell"; 1653 reg = <0x3b40000 0x1000>; 1654 1655 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1656 clock-names = "apb_pclk", "atclk"; 1657 1658 cpu = <&CPU3>; 1659 1660 out-ports { 1661 port { 1662 etm3_out: endpoint { 1663 remote-endpoint = 1664 <&apss_funnel1_in1>; 1665 }; 1666 }; 1667 }; 1668 }; 1669 1670 funnel@3bb0000 { /* APSS Funnel 1 */ 1671 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1672 reg = <0x3bb0000 0x1000>; 1673 1674 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1675 clock-names = "apb_pclk", "atclk"; 1676 1677 in-ports { 1678 #address-cells = <1>; 1679 #size-cells = <0>; 1680 1681 port@0 { 1682 reg = <0>; 1683 apss_funnel1_in0: endpoint { 1684 remote-endpoint = <&etm2_out>; 1685 }; 1686 }; 1687 1688 port@1 { 1689 reg = <1>; 1690 apss_funnel1_in1: endpoint { 1691 remote-endpoint = <&etm3_out>; 1692 }; 1693 }; 1694 }; 1695 1696 out-ports { 1697 port { 1698 apss_funnel1_out: endpoint { 1699 remote-endpoint = 1700 <&apss_merge_funnel_in1>; 1701 }; 1702 }; 1703 }; 1704 }; 1705 1706 funnel@3bc0000 { 1707 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1708 reg = <0x3bc0000 0x1000>; 1709 1710 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1711 clock-names = "apb_pclk", "atclk"; 1712 1713 in-ports { 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 1717 port@0 { 1718 reg = <0>; 1719 apss_merge_funnel_in0: endpoint { 1720 remote-endpoint = 1721 <&apss_funnel0_out>; 1722 }; 1723 }; 1724 1725 port@1 { 1726 reg = <1>; 1727 apss_merge_funnel_in1: endpoint { 1728 remote-endpoint = 1729 <&apss_funnel1_out>; 1730 }; 1731 }; 1732 }; 1733 1734 out-ports { 1735 port { 1736 apss_merge_funnel_out: endpoint { 1737 remote-endpoint = 1738 <&funnel1_in>; 1739 }; 1740 }; 1741 }; 1742 }; 1743 kryocc: clock-controller@6400000 { 1744 compatible = "qcom,apcc-msm8996"; 1745 reg = <0x06400000 0x90000>; 1746 #clock-cells = <1>; 1747 }; 1748 1749 usb3: usb@6af8800 { 1750 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1751 reg = <0x06af8800 0x400>; 1752 #address-cells = <1>; 1753 #size-cells = <1>; 1754 ranges; 1755 1756 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 1757 <&gcc GCC_USB30_MASTER_CLK>, 1758 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1759 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1760 <&gcc GCC_USB30_SLEEP_CLK>, 1761 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1762 1763 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1764 <&gcc GCC_USB30_MASTER_CLK>; 1765 assigned-clock-rates = <19200000>, <120000000>; 1766 1767 power-domains = <&gcc USB30_GDSC>; 1768 status = "disabled"; 1769 1770 dwc3@6a00000 { 1771 compatible = "snps,dwc3"; 1772 reg = <0x06a00000 0xcc00>; 1773 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 1774 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 1775 phy-names = "usb2-phy", "usb3-phy"; 1776 snps,dis_u2_susphy_quirk; 1777 snps,dis_enblslpm_quirk; 1778 }; 1779 }; 1780 1781 usb3phy: phy@7410000 { 1782 compatible = "qcom,msm8996-qmp-usb3-phy"; 1783 reg = <0x07410000 0x1c4>; 1784 #clock-cells = <1>; 1785 #address-cells = <1>; 1786 #size-cells = <1>; 1787 ranges; 1788 1789 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1790 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1791 <&gcc GCC_USB3_CLKREF_CLK>; 1792 clock-names = "aux", "cfg_ahb", "ref"; 1793 1794 resets = <&gcc GCC_USB3_PHY_BCR>, 1795 <&gcc GCC_USB3PHY_PHY_BCR>; 1796 reset-names = "phy", "common"; 1797 status = "disabled"; 1798 1799 ssusb_phy_0: lane@7410200 { 1800 reg = <0x07410200 0x200>, 1801 <0x07410400 0x130>, 1802 <0x07410600 0x1a8>; 1803 #phy-cells = <0>; 1804 1805 clock-output-names = "usb3_phy_pipe_clk_src"; 1806 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1807 clock-names = "pipe0"; 1808 }; 1809 }; 1810 1811 hsusb_phy1: phy@7411000 { 1812 compatible = "qcom,msm8996-qusb2-phy"; 1813 reg = <0x07411000 0x180>; 1814 #phy-cells = <0>; 1815 1816 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1817 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1818 clock-names = "cfg_ahb", "ref"; 1819 1820 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1821 nvmem-cells = <&qusb2p_hstx_trim>; 1822 status = "disabled"; 1823 }; 1824 1825 hsusb_phy2: phy@7412000 { 1826 compatible = "qcom,msm8996-qusb2-phy"; 1827 reg = <0x07412000 0x180>; 1828 #phy-cells = <0>; 1829 1830 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1831 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 1832 clock-names = "cfg_ahb", "ref"; 1833 1834 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1835 nvmem-cells = <&qusb2s_hstx_trim>; 1836 status = "disabled"; 1837 }; 1838 1839 sdhc2: sdhci@74a4900 { 1840 status = "disabled"; 1841 compatible = "qcom,sdhci-msm-v4"; 1842 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 1843 reg-names = "hc_mem", "core_mem"; 1844 1845 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, 1846 <0 221 IRQ_TYPE_LEVEL_HIGH>; 1847 interrupt-names = "hc_irq", "pwr_irq"; 1848 1849 clock-names = "iface", "core", "xo"; 1850 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1851 <&gcc GCC_SDCC2_APPS_CLK>, 1852 <&xo_board>; 1853 bus-width = <4>; 1854 }; 1855 1856 blsp1_uart1: serial@7570000 { 1857 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1858 reg = <0x07570000 0x1000>; 1859 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1860 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1861 <&gcc GCC_BLSP1_AHB_CLK>; 1862 clock-names = "core", "iface"; 1863 status = "disabled"; 1864 }; 1865 1866 blsp1_spi0: spi@7575000 { 1867 compatible = "qcom,spi-qup-v2.2.1"; 1868 reg = <0x07575000 0x600>; 1869 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1870 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1871 <&gcc GCC_BLSP1_AHB_CLK>; 1872 clock-names = "core", "iface"; 1873 pinctrl-names = "default", "sleep"; 1874 pinctrl-0 = <&blsp1_spi0_default>; 1875 pinctrl-1 = <&blsp1_spi0_sleep>; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 status = "disabled"; 1879 }; 1880 1881 blsp1_i2c2: i2c@7577000 { 1882 compatible = "qcom,i2c-qup-v2.2.1"; 1883 reg = <0x07577000 0x1000>; 1884 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1885 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1886 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 1887 clock-names = "iface", "core"; 1888 pinctrl-names = "default", "sleep"; 1889 pinctrl-0 = <&blsp1_i2c2_default>; 1890 pinctrl-1 = <&blsp1_i2c2_sleep>; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 status = "disabled"; 1894 }; 1895 1896 blsp2_uart1: serial@75b0000 { 1897 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1898 reg = <0x075b0000 0x1000>; 1899 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1900 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1901 <&gcc GCC_BLSP2_AHB_CLK>; 1902 clock-names = "core", "iface"; 1903 status = "disabled"; 1904 }; 1905 1906 blsp2_uart2: serial@75b1000 { 1907 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1908 reg = <0x075b1000 0x1000>; 1909 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1910 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 1911 <&gcc GCC_BLSP2_AHB_CLK>; 1912 clock-names = "core", "iface"; 1913 status = "disabled"; 1914 }; 1915 1916 blsp2_i2c0: i2c@75b5000 { 1917 compatible = "qcom,i2c-qup-v2.2.1"; 1918 reg = <0x075b5000 0x1000>; 1919 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1920 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1921 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 1922 clock-names = "iface", "core"; 1923 pinctrl-names = "default", "sleep"; 1924 pinctrl-0 = <&blsp2_i2c0_default>; 1925 pinctrl-1 = <&blsp2_i2c0_sleep>; 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 status = "disabled"; 1929 }; 1930 1931 blsp2_i2c1: i2c@75b6000 { 1932 compatible = "qcom,i2c-qup-v2.2.1"; 1933 reg = <0x075b6000 0x1000>; 1934 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1935 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1936 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 1937 clock-names = "iface", "core"; 1938 pinctrl-names = "default", "sleep"; 1939 pinctrl-0 = <&blsp2_i2c1_default>; 1940 pinctrl-1 = <&blsp2_i2c1_sleep>; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 status = "disabled"; 1944 }; 1945 1946 blsp2_spi5: spi@75ba000{ 1947 compatible = "qcom,spi-qup-v2.2.1"; 1948 reg = <0x075ba000 0x600>; 1949 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1950 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 1951 <&gcc GCC_BLSP2_AHB_CLK>; 1952 clock-names = "core", "iface"; 1953 pinctrl-names = "default", "sleep"; 1954 pinctrl-0 = <&blsp2_spi5_default>; 1955 pinctrl-1 = <&blsp2_spi5_sleep>; 1956 #address-cells = <1>; 1957 #size-cells = <0>; 1958 status = "disabled"; 1959 }; 1960 1961 usb2: usb@76f8800 { 1962 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1963 reg = <0x076f8800 0x400>; 1964 #address-cells = <1>; 1965 #size-cells = <1>; 1966 ranges; 1967 1968 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 1969 <&gcc GCC_USB20_MASTER_CLK>, 1970 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1971 <&gcc GCC_USB20_SLEEP_CLK>, 1972 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1973 1974 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1975 <&gcc GCC_USB20_MASTER_CLK>; 1976 assigned-clock-rates = <19200000>, <60000000>; 1977 1978 power-domains = <&gcc USB30_GDSC>; 1979 status = "disabled"; 1980 1981 dwc3@7600000 { 1982 compatible = "snps,dwc3"; 1983 reg = <0x07600000 0xcc00>; 1984 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 1985 phys = <&hsusb_phy2>; 1986 phy-names = "usb2-phy"; 1987 snps,dis_u2_susphy_quirk; 1988 snps,dis_enblslpm_quirk; 1989 }; 1990 }; 1991 1992 slimbam: dma@9184000 { 1993 compatible = "qcom,bam-v1.7.0"; 1994 qcom,controlled-remotely; 1995 reg = <0x09184000 0x32000>; 1996 num-channels = <31>; 1997 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 1998 #dma-cells = <1>; 1999 qcom,ee = <1>; 2000 qcom,num-ees = <2>; 2001 }; 2002 2003 slim_msm: slim@91c0000 { 2004 compatible = "qcom,slim-ngd-v1.5.0"; 2005 reg = <0x091c0000 0x2C000>; 2006 reg-names = "ctrl"; 2007 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 2008 dmas = <&slimbam 3>, <&slimbam 4>, 2009 <&slimbam 5>, <&slimbam 6>; 2010 dma-names = "rx", "tx", "tx2", "rx2"; 2011 #address-cells = <1>; 2012 #size-cells = <0>; 2013 ngd@1 { 2014 reg = <1>; 2015 #address-cells = <1>; 2016 #size-cells = <1>; 2017 2018 tasha_ifd: tas-ifd { 2019 compatible = "slim217,1a0"; 2020 reg = <0 0>; 2021 }; 2022 2023 wcd9335: codec@1{ 2024 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 2025 pinctrl-names = "default"; 2026 2027 compatible = "slim217,1a0"; 2028 reg = <1 0>; 2029 2030 interrupt-parent = <&msmgpio>; 2031 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 2032 <53 IRQ_TYPE_LEVEL_HIGH>; 2033 interrupt-names = "intr1", "intr2"; 2034 interrupt-controller; 2035 #interrupt-cells = <1>; 2036 reset-gpios = <&msmgpio 64 0>; 2037 2038 slim-ifc-dev = <&tasha_ifd>; 2039 2040 #sound-dai-cells = <1>; 2041 }; 2042 }; 2043 }; 2044 2045 adsp_pil: remoteproc@9300000 { 2046 compatible = "qcom,msm8996-adsp-pil"; 2047 reg = <0x09300000 0x80000>; 2048 2049 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 2050 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2051 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2052 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2053 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2054 interrupt-names = "wdog", "fatal", "ready", 2055 "handover", "stop-ack"; 2056 2057 clocks = <&xo_board>; 2058 clock-names = "xo"; 2059 2060 memory-region = <&adsp_region>; 2061 2062 qcom,smem-states = <&smp2p_adsp_out 0>; 2063 qcom,smem-state-names = "stop"; 2064 2065 smd-edge { 2066 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2067 2068 label = "lpass"; 2069 mboxes = <&apcs_glb 8>; 2070 qcom,smd-edge = <1>; 2071 qcom,remote-pid = <2>; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 apr { 2075 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 2076 compatible = "qcom,apr-v2"; 2077 qcom,smd-channels = "apr_audio_svc"; 2078 qcom,apr-domain = <APR_DOMAIN_ADSP>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 2082 q6core { 2083 reg = <APR_SVC_ADSP_CORE>; 2084 compatible = "qcom,q6core"; 2085 }; 2086 2087 q6afe: q6afe { 2088 compatible = "qcom,q6afe"; 2089 reg = <APR_SVC_AFE>; 2090 q6afedai: dais { 2091 compatible = "qcom,q6afe-dais"; 2092 #address-cells = <1>; 2093 #size-cells = <0>; 2094 #sound-dai-cells = <1>; 2095 hdmi@1 { 2096 reg = <1>; 2097 }; 2098 }; 2099 }; 2100 2101 q6asm: q6asm { 2102 compatible = "qcom,q6asm"; 2103 reg = <APR_SVC_ASM>; 2104 q6asmdai: dais { 2105 compatible = "qcom,q6asm-dais"; 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 #sound-dai-cells = <1>; 2109 iommus = <&lpass_q6_smmu 1>; 2110 }; 2111 }; 2112 2113 q6adm: q6adm { 2114 compatible = "qcom,q6adm"; 2115 reg = <APR_SVC_ADM>; 2116 q6routing: routing { 2117 compatible = "qcom,q6adm-routing"; 2118 #sound-dai-cells = <0>; 2119 }; 2120 }; 2121 }; 2122 2123 }; 2124 }; 2125 2126 apcs_glb: mailbox@9820000 { 2127 compatible = "qcom,msm8996-apcs-hmss-global"; 2128 reg = <0x09820000 0x1000>; 2129 2130 #mbox-cells = <1>; 2131 }; 2132 2133 timer@9840000 { 2134 #address-cells = <1>; 2135 #size-cells = <1>; 2136 ranges; 2137 compatible = "arm,armv7-timer-mem"; 2138 reg = <0x09840000 0x1000>; 2139 clock-frequency = <19200000>; 2140 2141 frame@9850000 { 2142 frame-number = <0>; 2143 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2145 reg = <0x09850000 0x1000>, 2146 <0x09860000 0x1000>; 2147 }; 2148 2149 frame@9870000 { 2150 frame-number = <1>; 2151 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2152 reg = <0x09870000 0x1000>; 2153 status = "disabled"; 2154 }; 2155 2156 frame@9880000 { 2157 frame-number = <2>; 2158 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2159 reg = <0x09880000 0x1000>; 2160 status = "disabled"; 2161 }; 2162 2163 frame@9890000 { 2164 frame-number = <3>; 2165 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2166 reg = <0x09890000 0x1000>; 2167 status = "disabled"; 2168 }; 2169 2170 frame@98a0000 { 2171 frame-number = <4>; 2172 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2173 reg = <0x098a0000 0x1000>; 2174 status = "disabled"; 2175 }; 2176 2177 frame@98b0000 { 2178 frame-number = <5>; 2179 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2180 reg = <0x098b0000 0x1000>; 2181 status = "disabled"; 2182 }; 2183 2184 frame@98c0000 { 2185 frame-number = <6>; 2186 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2187 reg = <0x098c0000 0x1000>; 2188 status = "disabled"; 2189 }; 2190 }; 2191 2192 saw3: syscon@9a10000 { 2193 compatible = "syscon"; 2194 reg = <0x09a10000 0x1000>; 2195 }; 2196 2197 intc: interrupt-controller@9bc0000 { 2198 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 2199 #interrupt-cells = <3>; 2200 interrupt-controller; 2201 #redistributor-regions = <1>; 2202 redistributor-stride = <0x0 0x40000>; 2203 reg = <0x09bc0000 0x10000>, 2204 <0x09c00000 0x100000>; 2205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2206 }; 2207 }; 2208 2209 sound: sound { 2210 }; 2211 2212 thermal-zones { 2213 cpu0-thermal { 2214 polling-delay-passive = <250>; 2215 polling-delay = <1000>; 2216 2217 thermal-sensors = <&tsens0 3>; 2218 2219 trips { 2220 cpu0_alert0: trip-point0 { 2221 temperature = <75000>; 2222 hysteresis = <2000>; 2223 type = "passive"; 2224 }; 2225 2226 cpu0_crit: cpu_crit { 2227 temperature = <110000>; 2228 hysteresis = <2000>; 2229 type = "critical"; 2230 }; 2231 }; 2232 }; 2233 2234 cpu1-thermal { 2235 polling-delay-passive = <250>; 2236 polling-delay = <1000>; 2237 2238 thermal-sensors = <&tsens0 5>; 2239 2240 trips { 2241 cpu1_alert0: trip-point0 { 2242 temperature = <75000>; 2243 hysteresis = <2000>; 2244 type = "passive"; 2245 }; 2246 2247 cpu1_crit: cpu_crit { 2248 temperature = <110000>; 2249 hysteresis = <2000>; 2250 type = "critical"; 2251 }; 2252 }; 2253 }; 2254 2255 cpu2-thermal { 2256 polling-delay-passive = <250>; 2257 polling-delay = <1000>; 2258 2259 thermal-sensors = <&tsens0 8>; 2260 2261 trips { 2262 cpu2_alert0: trip-point0 { 2263 temperature = <75000>; 2264 hysteresis = <2000>; 2265 type = "passive"; 2266 }; 2267 2268 cpu2_crit: cpu_crit { 2269 temperature = <110000>; 2270 hysteresis = <2000>; 2271 type = "critical"; 2272 }; 2273 }; 2274 }; 2275 2276 cpu3-thermal { 2277 polling-delay-passive = <250>; 2278 polling-delay = <1000>; 2279 2280 thermal-sensors = <&tsens0 10>; 2281 2282 trips { 2283 cpu3_alert0: trip-point0 { 2284 temperature = <75000>; 2285 hysteresis = <2000>; 2286 type = "passive"; 2287 }; 2288 2289 cpu3_crit: cpu_crit { 2290 temperature = <110000>; 2291 hysteresis = <2000>; 2292 type = "critical"; 2293 }; 2294 }; 2295 }; 2296 2297 gpu-thermal-top { 2298 polling-delay-passive = <250>; 2299 polling-delay = <1000>; 2300 2301 thermal-sensors = <&tsens1 6>; 2302 2303 trips { 2304 gpu1_alert0: trip-point0 { 2305 temperature = <90000>; 2306 hysteresis = <2000>; 2307 type = "hot"; 2308 }; 2309 }; 2310 }; 2311 2312 gpu-thermal-bottom { 2313 polling-delay-passive = <250>; 2314 polling-delay = <1000>; 2315 2316 thermal-sensors = <&tsens1 7>; 2317 2318 trips { 2319 gpu2_alert0: trip-point0 { 2320 temperature = <90000>; 2321 hysteresis = <2000>; 2322 type = "hot"; 2323 }; 2324 }; 2325 }; 2326 2327 m4m-thermal { 2328 polling-delay-passive = <250>; 2329 polling-delay = <1000>; 2330 2331 thermal-sensors = <&tsens0 1>; 2332 2333 trips { 2334 m4m_alert0: trip-point0 { 2335 temperature = <90000>; 2336 hysteresis = <2000>; 2337 type = "hot"; 2338 }; 2339 }; 2340 }; 2341 2342 l3-or-venus-thermal { 2343 polling-delay-passive = <250>; 2344 polling-delay = <1000>; 2345 2346 thermal-sensors = <&tsens0 2>; 2347 2348 trips { 2349 l3_or_venus_alert0: trip-point0 { 2350 temperature = <90000>; 2351 hysteresis = <2000>; 2352 type = "hot"; 2353 }; 2354 }; 2355 }; 2356 2357 cluster0-l2-thermal { 2358 polling-delay-passive = <250>; 2359 polling-delay = <1000>; 2360 2361 thermal-sensors = <&tsens0 7>; 2362 2363 trips { 2364 cluster0_l2_alert0: trip-point0 { 2365 temperature = <90000>; 2366 hysteresis = <2000>; 2367 type = "hot"; 2368 }; 2369 }; 2370 }; 2371 2372 cluster1-l2-thermal { 2373 polling-delay-passive = <250>; 2374 polling-delay = <1000>; 2375 2376 thermal-sensors = <&tsens0 12>; 2377 2378 trips { 2379 cluster1_l2_alert0: trip-point0 { 2380 temperature = <90000>; 2381 hysteresis = <2000>; 2382 type = "hot"; 2383 }; 2384 }; 2385 }; 2386 2387 camera-thermal { 2388 polling-delay-passive = <250>; 2389 polling-delay = <1000>; 2390 2391 thermal-sensors = <&tsens1 1>; 2392 2393 trips { 2394 camera_alert0: trip-point0 { 2395 temperature = <90000>; 2396 hysteresis = <2000>; 2397 type = "hot"; 2398 }; 2399 }; 2400 }; 2401 2402 q6-dsp-thermal { 2403 polling-delay-passive = <250>; 2404 polling-delay = <1000>; 2405 2406 thermal-sensors = <&tsens1 2>; 2407 2408 trips { 2409 q6_dsp_alert0: trip-point0 { 2410 temperature = <90000>; 2411 hysteresis = <2000>; 2412 type = "hot"; 2413 }; 2414 }; 2415 }; 2416 2417 mem-thermal { 2418 polling-delay-passive = <250>; 2419 polling-delay = <1000>; 2420 2421 thermal-sensors = <&tsens1 3>; 2422 2423 trips { 2424 mem_alert0: trip-point0 { 2425 temperature = <90000>; 2426 hysteresis = <2000>; 2427 type = "hot"; 2428 }; 2429 }; 2430 }; 2431 2432 modemtx-thermal { 2433 polling-delay-passive = <250>; 2434 polling-delay = <1000>; 2435 2436 thermal-sensors = <&tsens1 4>; 2437 2438 trips { 2439 modemtx_alert0: trip-point0 { 2440 temperature = <90000>; 2441 hysteresis = <2000>; 2442 type = "hot"; 2443 }; 2444 }; 2445 }; 2446 }; 2447 2448 timer { 2449 compatible = "arm,armv8-timer"; 2450 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2451 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2452 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2453 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2454 }; 2455}; 2456#include "msm8996-pins.dtsi" 2457