1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,apr.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <19200000>; 30 clock-output-names = "xo_board"; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 clock-output-names = "sleep_clk"; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 cpu-idle-states = <&CPU_SLEEP_0>; 51 capacity-dmips-mhz = <1024>; 52 clocks = <&kryocc 0>; 53 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 54 operating-points-v2 = <&cluster0_opp>; 55 #cooling-cells = <2>; 56 next-level-cache = <&L2_0>; 57 L2_0: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 }; 62 }; 63 64 CPU1: cpu@1 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo"; 67 reg = <0x0 0x1>; 68 enable-method = "psci"; 69 cpu-idle-states = <&CPU_SLEEP_0>; 70 capacity-dmips-mhz = <1024>; 71 clocks = <&kryocc 0>; 72 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 73 operating-points-v2 = <&cluster0_opp>; 74 #cooling-cells = <2>; 75 next-level-cache = <&L2_0>; 76 }; 77 78 CPU2: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 cpu-idle-states = <&CPU_SLEEP_0>; 84 capacity-dmips-mhz = <1024>; 85 clocks = <&kryocc 1>; 86 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 87 operating-points-v2 = <&cluster1_opp>; 88 #cooling-cells = <2>; 89 next-level-cache = <&L2_1>; 90 L2_1: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 }; 95 }; 96 97 CPU3: cpu@101 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo"; 100 reg = <0x0 0x101>; 101 enable-method = "psci"; 102 cpu-idle-states = <&CPU_SLEEP_0>; 103 capacity-dmips-mhz = <1024>; 104 clocks = <&kryocc 1>; 105 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 106 operating-points-v2 = <&cluster1_opp>; 107 #cooling-cells = <2>; 108 next-level-cache = <&L2_1>; 109 }; 110 111 cpu-map { 112 cluster0 { 113 core0 { 114 cpu = <&CPU0>; 115 }; 116 117 core1 { 118 cpu = <&CPU1>; 119 }; 120 }; 121 122 cluster1 { 123 core0 { 124 cpu = <&CPU2>; 125 }; 126 127 core1 { 128 cpu = <&CPU3>; 129 }; 130 }; 131 }; 132 133 idle-states { 134 entry-method = "psci"; 135 136 CPU_SLEEP_0: cpu-sleep-0 { 137 compatible = "arm,idle-state"; 138 idle-state-name = "standalone-power-collapse"; 139 arm,psci-suspend-param = <0x00000004>; 140 entry-latency-us = <130>; 141 exit-latency-us = <80>; 142 min-residency-us = <300>; 143 }; 144 }; 145 }; 146 147 cluster0_opp: opp-table-cluster0 { 148 compatible = "operating-points-v2-kryo-cpu"; 149 nvmem-cells = <&speedbin_efuse>; 150 opp-shared; 151 152 /* Nominal fmax for now */ 153 opp-307200000 { 154 opp-hz = /bits/ 64 <307200000>; 155 opp-supported-hw = <0xf>; 156 clock-latency-ns = <200000>; 157 opp-peak-kBps = <307200>; 158 }; 159 opp-422400000 { 160 opp-hz = /bits/ 64 <422400000>; 161 opp-supported-hw = <0xf>; 162 clock-latency-ns = <200000>; 163 opp-peak-kBps = <307200>; 164 }; 165 opp-480000000 { 166 opp-hz = /bits/ 64 <480000000>; 167 opp-supported-hw = <0xf>; 168 clock-latency-ns = <200000>; 169 opp-peak-kBps = <307200>; 170 }; 171 opp-556800000 { 172 opp-hz = /bits/ 64 <556800000>; 173 opp-supported-hw = <0xf>; 174 clock-latency-ns = <200000>; 175 opp-peak-kBps = <307200>; 176 }; 177 opp-652800000 { 178 opp-hz = /bits/ 64 <652800000>; 179 opp-supported-hw = <0xf>; 180 clock-latency-ns = <200000>; 181 opp-peak-kBps = <384000>; 182 }; 183 opp-729600000 { 184 opp-hz = /bits/ 64 <729600000>; 185 opp-supported-hw = <0xf>; 186 clock-latency-ns = <200000>; 187 opp-peak-kBps = <460800>; 188 }; 189 opp-844800000 { 190 opp-hz = /bits/ 64 <844800000>; 191 opp-supported-hw = <0xf>; 192 clock-latency-ns = <200000>; 193 opp-peak-kBps = <537600>; 194 }; 195 opp-960000000 { 196 opp-hz = /bits/ 64 <960000000>; 197 opp-supported-hw = <0xf>; 198 clock-latency-ns = <200000>; 199 opp-peak-kBps = <672000>; 200 }; 201 opp-1036800000 { 202 opp-hz = /bits/ 64 <1036800000>; 203 opp-supported-hw = <0xf>; 204 clock-latency-ns = <200000>; 205 opp-peak-kBps = <672000>; 206 }; 207 opp-1113600000 { 208 opp-hz = /bits/ 64 <1113600000>; 209 opp-supported-hw = <0xf>; 210 clock-latency-ns = <200000>; 211 opp-peak-kBps = <825600>; 212 }; 213 opp-1190400000 { 214 opp-hz = /bits/ 64 <1190400000>; 215 opp-supported-hw = <0xf>; 216 clock-latency-ns = <200000>; 217 opp-peak-kBps = <825600>; 218 }; 219 opp-1228800000 { 220 opp-hz = /bits/ 64 <1228800000>; 221 opp-supported-hw = <0xf>; 222 clock-latency-ns = <200000>; 223 opp-peak-kBps = <902400>; 224 }; 225 opp-1324800000 { 226 opp-hz = /bits/ 64 <1324800000>; 227 opp-supported-hw = <0xd>; 228 clock-latency-ns = <200000>; 229 opp-peak-kBps = <1056000>; 230 }; 231 opp-1363200000 { 232 opp-hz = /bits/ 64 <1363200000>; 233 opp-supported-hw = <0x2>; 234 clock-latency-ns = <200000>; 235 opp-peak-kBps = <1132800>; 236 }; 237 opp-1401600000 { 238 opp-hz = /bits/ 64 <1401600000>; 239 opp-supported-hw = <0xd>; 240 clock-latency-ns = <200000>; 241 opp-peak-kBps = <1132800>; 242 }; 243 opp-1478400000 { 244 opp-hz = /bits/ 64 <1478400000>; 245 opp-supported-hw = <0x9>; 246 clock-latency-ns = <200000>; 247 opp-peak-kBps = <1190400>; 248 }; 249 opp-1497600000 { 250 opp-hz = /bits/ 64 <1497600000>; 251 opp-supported-hw = <0x04>; 252 clock-latency-ns = <200000>; 253 opp-peak-kBps = <1305600>; 254 }; 255 opp-1593600000 { 256 opp-hz = /bits/ 64 <1593600000>; 257 opp-supported-hw = <0x9>; 258 clock-latency-ns = <200000>; 259 opp-peak-kBps = <1382400>; 260 }; 261 }; 262 263 cluster1_opp: opp-table-cluster1 { 264 compatible = "operating-points-v2-kryo-cpu"; 265 nvmem-cells = <&speedbin_efuse>; 266 opp-shared; 267 268 /* Nominal fmax for now */ 269 opp-307200000 { 270 opp-hz = /bits/ 64 <307200000>; 271 opp-supported-hw = <0xf>; 272 clock-latency-ns = <200000>; 273 opp-peak-kBps = <307200>; 274 }; 275 opp-403200000 { 276 opp-hz = /bits/ 64 <403200000>; 277 opp-supported-hw = <0xf>; 278 clock-latency-ns = <200000>; 279 opp-peak-kBps = <307200>; 280 }; 281 opp-480000000 { 282 opp-hz = /bits/ 64 <480000000>; 283 opp-supported-hw = <0xf>; 284 clock-latency-ns = <200000>; 285 opp-peak-kBps = <307200>; 286 }; 287 opp-556800000 { 288 opp-hz = /bits/ 64 <556800000>; 289 opp-supported-hw = <0xf>; 290 clock-latency-ns = <200000>; 291 opp-peak-kBps = <307200>; 292 }; 293 opp-652800000 { 294 opp-hz = /bits/ 64 <652800000>; 295 opp-supported-hw = <0xf>; 296 clock-latency-ns = <200000>; 297 opp-peak-kBps = <307200>; 298 }; 299 opp-729600000 { 300 opp-hz = /bits/ 64 <729600000>; 301 opp-supported-hw = <0xf>; 302 clock-latency-ns = <200000>; 303 opp-peak-kBps = <307200>; 304 }; 305 opp-806400000 { 306 opp-hz = /bits/ 64 <806400000>; 307 opp-supported-hw = <0xf>; 308 clock-latency-ns = <200000>; 309 opp-peak-kBps = <384000>; 310 }; 311 opp-883200000 { 312 opp-hz = /bits/ 64 <883200000>; 313 opp-supported-hw = <0xf>; 314 clock-latency-ns = <200000>; 315 opp-peak-kBps = <460800>; 316 }; 317 opp-940800000 { 318 opp-hz = /bits/ 64 <940800000>; 319 opp-supported-hw = <0xf>; 320 clock-latency-ns = <200000>; 321 opp-peak-kBps = <537600>; 322 }; 323 opp-1036800000 { 324 opp-hz = /bits/ 64 <1036800000>; 325 opp-supported-hw = <0xf>; 326 clock-latency-ns = <200000>; 327 opp-peak-kBps = <595200>; 328 }; 329 opp-1113600000 { 330 opp-hz = /bits/ 64 <1113600000>; 331 opp-supported-hw = <0xf>; 332 clock-latency-ns = <200000>; 333 opp-peak-kBps = <672000>; 334 }; 335 opp-1190400000 { 336 opp-hz = /bits/ 64 <1190400000>; 337 opp-supported-hw = <0xf>; 338 clock-latency-ns = <200000>; 339 opp-peak-kBps = <672000>; 340 }; 341 opp-1248000000 { 342 opp-hz = /bits/ 64 <1248000000>; 343 opp-supported-hw = <0xf>; 344 clock-latency-ns = <200000>; 345 opp-peak-kBps = <748800>; 346 }; 347 opp-1324800000 { 348 opp-hz = /bits/ 64 <1324800000>; 349 opp-supported-hw = <0xf>; 350 clock-latency-ns = <200000>; 351 opp-peak-kBps = <825600>; 352 }; 353 opp-1401600000 { 354 opp-hz = /bits/ 64 <1401600000>; 355 opp-supported-hw = <0xf>; 356 clock-latency-ns = <200000>; 357 opp-peak-kBps = <902400>; 358 }; 359 opp-1478400000 { 360 opp-hz = /bits/ 64 <1478400000>; 361 opp-supported-hw = <0xf>; 362 clock-latency-ns = <200000>; 363 opp-peak-kBps = <979200>; 364 }; 365 opp-1555200000 { 366 opp-hz = /bits/ 64 <1555200000>; 367 opp-supported-hw = <0xf>; 368 clock-latency-ns = <200000>; 369 opp-peak-kBps = <1056000>; 370 }; 371 opp-1632000000 { 372 opp-hz = /bits/ 64 <1632000000>; 373 opp-supported-hw = <0xf>; 374 clock-latency-ns = <200000>; 375 opp-peak-kBps = <1190400>; 376 }; 377 opp-1708800000 { 378 opp-hz = /bits/ 64 <1708800000>; 379 opp-supported-hw = <0xf>; 380 clock-latency-ns = <200000>; 381 opp-peak-kBps = <1228800>; 382 }; 383 opp-1785600000 { 384 opp-hz = /bits/ 64 <1785600000>; 385 opp-supported-hw = <0xf>; 386 clock-latency-ns = <200000>; 387 opp-peak-kBps = <1305600>; 388 }; 389 opp-1804800000 { 390 opp-hz = /bits/ 64 <1804800000>; 391 opp-supported-hw = <0xe>; 392 clock-latency-ns = <200000>; 393 opp-peak-kBps = <1305600>; 394 }; 395 opp-1824000000 { 396 opp-hz = /bits/ 64 <1824000000>; 397 opp-supported-hw = <0x1>; 398 clock-latency-ns = <200000>; 399 opp-peak-kBps = <1382400>; 400 }; 401 opp-1900800000 { 402 opp-hz = /bits/ 64 <1900800000>; 403 opp-supported-hw = <0x4>; 404 clock-latency-ns = <200000>; 405 opp-peak-kBps = <1305600>; 406 }; 407 opp-1920000000 { 408 opp-hz = /bits/ 64 <1920000000>; 409 opp-supported-hw = <0x1>; 410 clock-latency-ns = <200000>; 411 opp-peak-kBps = <1459200>; 412 }; 413 opp-1996800000 { 414 opp-hz = /bits/ 64 <1996800000>; 415 opp-supported-hw = <0x1>; 416 clock-latency-ns = <200000>; 417 opp-peak-kBps = <1593600>; 418 }; 419 opp-2073600000 { 420 opp-hz = /bits/ 64 <2073600000>; 421 opp-supported-hw = <0x1>; 422 clock-latency-ns = <200000>; 423 opp-peak-kBps = <1593600>; 424 }; 425 opp-2150400000 { 426 opp-hz = /bits/ 64 <2150400000>; 427 opp-supported-hw = <0x1>; 428 clock-latency-ns = <200000>; 429 opp-peak-kBps = <1593600>; 430 }; 431 }; 432 433 firmware { 434 scm { 435 compatible = "qcom,scm-msm8996", "qcom,scm"; 436 qcom,dload-mode = <&tcsr_2 0x13000>; 437 }; 438 }; 439 440 memory@80000000 { 441 device_type = "memory"; 442 /* We expect the bootloader to fill in the reg */ 443 reg = <0x0 0x80000000 0x0 0x0>; 444 }; 445 446 etm { 447 compatible = "qcom,coresight-remote-etm"; 448 449 out-ports { 450 port { 451 modem_etm_out_funnel_in2: endpoint { 452 remote-endpoint = 453 <&funnel_in2_in_modem_etm>; 454 }; 455 }; 456 }; 457 }; 458 459 psci { 460 compatible = "arm,psci-1.0"; 461 method = "smc"; 462 }; 463 464 rpm: remoteproc { 465 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; 466 467 glink-edge { 468 compatible = "qcom,glink-rpm"; 469 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 470 qcom,rpm-msg-ram = <&rpm_msg_ram>; 471 mboxes = <&apcs_glb 0>; 472 473 rpm_requests: rpm-requests { 474 compatible = "qcom,rpm-msm8996"; 475 qcom,glink-channels = "rpm_requests"; 476 477 rpmcc: clock-controller { 478 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 479 #clock-cells = <1>; 480 clocks = <&xo_board>; 481 clock-names = "xo"; 482 }; 483 484 rpmpd: power-controller { 485 compatible = "qcom,msm8996-rpmpd"; 486 #power-domain-cells = <1>; 487 operating-points-v2 = <&rpmpd_opp_table>; 488 489 rpmpd_opp_table: opp-table { 490 compatible = "operating-points-v2"; 491 492 rpmpd_opp1: opp1 { 493 opp-level = <1>; 494 }; 495 496 rpmpd_opp2: opp2 { 497 opp-level = <2>; 498 }; 499 500 rpmpd_opp3: opp3 { 501 opp-level = <3>; 502 }; 503 504 rpmpd_opp4: opp4 { 505 opp-level = <4>; 506 }; 507 508 rpmpd_opp5: opp5 { 509 opp-level = <5>; 510 }; 511 512 rpmpd_opp6: opp6 { 513 opp-level = <6>; 514 }; 515 }; 516 }; 517 }; 518 }; 519 }; 520 521 reserved-memory { 522 #address-cells = <2>; 523 #size-cells = <2>; 524 ranges; 525 526 hyp_mem: memory@85800000 { 527 reg = <0x0 0x85800000 0x0 0x600000>; 528 no-map; 529 }; 530 531 xbl_mem: memory@85e00000 { 532 reg = <0x0 0x85e00000 0x0 0x200000>; 533 no-map; 534 }; 535 536 smem_mem: smem-mem@86000000 { 537 reg = <0x0 0x86000000 0x0 0x200000>; 538 no-map; 539 }; 540 541 tz_mem: memory@86200000 { 542 reg = <0x0 0x86200000 0x0 0x2600000>; 543 no-map; 544 }; 545 546 rmtfs_mem: rmtfs { 547 compatible = "qcom,rmtfs-mem"; 548 549 size = <0x0 0x200000>; 550 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 551 no-map; 552 553 qcom,client-id = <1>; 554 qcom,vmid = <15>; 555 }; 556 557 mpss_mem: mpss@88800000 { 558 reg = <0x0 0x88800000 0x0 0x6200000>; 559 no-map; 560 }; 561 562 adsp_mem: adsp@8ea00000 { 563 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 564 no-map; 565 }; 566 567 slpi_mem: slpi@90500000 { 568 reg = <0x0 0x90500000 0x0 0xa00000>; 569 no-map; 570 }; 571 572 gpu_mem: gpu@90f00000 { 573 compatible = "shared-dma-pool"; 574 reg = <0x0 0x90f00000 0x0 0x100000>; 575 no-map; 576 }; 577 578 venus_mem: venus@91000000 { 579 reg = <0x0 0x91000000 0x0 0x500000>; 580 no-map; 581 }; 582 583 mba_mem: mba@91500000 { 584 reg = <0x0 0x91500000 0x0 0x200000>; 585 no-map; 586 }; 587 588 mdata_mem: mpss-metadata { 589 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 590 size = <0x0 0x4000>; 591 no-map; 592 }; 593 }; 594 595 smem { 596 compatible = "qcom,smem"; 597 memory-region = <&smem_mem>; 598 hwlocks = <&tcsr_mutex 3>; 599 }; 600 601 smp2p-adsp { 602 compatible = "qcom,smp2p"; 603 qcom,smem = <443>, <429>; 604 605 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 606 607 mboxes = <&apcs_glb 10>; 608 609 qcom,local-pid = <0>; 610 qcom,remote-pid = <2>; 611 612 adsp_smp2p_out: master-kernel { 613 qcom,entry-name = "master-kernel"; 614 #qcom,smem-state-cells = <1>; 615 }; 616 617 adsp_smp2p_in: slave-kernel { 618 qcom,entry-name = "slave-kernel"; 619 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 }; 624 625 smp2p-mpss { 626 compatible = "qcom,smp2p"; 627 qcom,smem = <435>, <428>; 628 629 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 630 631 mboxes = <&apcs_glb 14>; 632 633 qcom,local-pid = <0>; 634 qcom,remote-pid = <1>; 635 636 mpss_smp2p_out: master-kernel { 637 qcom,entry-name = "master-kernel"; 638 #qcom,smem-state-cells = <1>; 639 }; 640 641 mpss_smp2p_in: slave-kernel { 642 qcom,entry-name = "slave-kernel"; 643 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 }; 648 649 smp2p-slpi { 650 compatible = "qcom,smp2p"; 651 qcom,smem = <481>, <430>; 652 653 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 654 655 mboxes = <&apcs_glb 26>; 656 657 qcom,local-pid = <0>; 658 qcom,remote-pid = <3>; 659 660 slpi_smp2p_out: master-kernel { 661 qcom,entry-name = "master-kernel"; 662 #qcom,smem-state-cells = <1>; 663 }; 664 665 slpi_smp2p_in: slave-kernel { 666 qcom,entry-name = "slave-kernel"; 667 668 interrupt-controller; 669 #interrupt-cells = <2>; 670 }; 671 }; 672 673 soc: soc@0 { 674 #address-cells = <1>; 675 #size-cells = <1>; 676 ranges = <0 0 0 0xffffffff>; 677 compatible = "simple-bus"; 678 679 pcie_phy: phy-wrapper@34000 { 680 compatible = "qcom,msm8996-qmp-pcie-phy"; 681 reg = <0x00034000 0x488>; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 ranges = <0x0 0x00034000 0x4000>; 685 686 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 687 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 688 <&gcc GCC_PCIE_CLKREF_CLK>; 689 clock-names = "aux", "cfg_ahb", "ref"; 690 691 resets = <&gcc GCC_PCIE_PHY_BCR>, 692 <&gcc GCC_PCIE_PHY_COM_BCR>, 693 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 694 reset-names = "phy", "common", "cfg"; 695 696 status = "disabled"; 697 698 pciephy_0: phy@1000 { 699 reg = <0x1000 0x130>, 700 <0x1200 0x200>, 701 <0x1400 0x1dc>; 702 703 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 704 clock-names = "pipe0"; 705 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 706 reset-names = "lane0"; 707 708 #clock-cells = <0>; 709 clock-output-names = "pcie_0_pipe_clk_src"; 710 711 #phy-cells = <0>; 712 }; 713 714 pciephy_1: phy@2000 { 715 reg = <0x2000 0x130>, 716 <0x2200 0x200>, 717 <0x2400 0x1dc>; 718 719 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 720 clock-names = "pipe1"; 721 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 722 reset-names = "lane1"; 723 724 #clock-cells = <0>; 725 clock-output-names = "pcie_1_pipe_clk_src"; 726 727 #phy-cells = <0>; 728 }; 729 730 pciephy_2: phy@3000 { 731 reg = <0x3000 0x130>, 732 <0x3200 0x200>, 733 <0x3400 0x1dc>; 734 735 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 736 clock-names = "pipe2"; 737 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 738 reset-names = "lane2"; 739 740 #clock-cells = <0>; 741 clock-output-names = "pcie_2_pipe_clk_src"; 742 743 #phy-cells = <0>; 744 }; 745 }; 746 747 rpm_msg_ram: sram@68000 { 748 compatible = "qcom,rpm-msg-ram"; 749 reg = <0x00068000 0x6000>; 750 }; 751 752 qfprom@74000 { 753 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 754 reg = <0x00074000 0x8ff>; 755 #address-cells = <1>; 756 #size-cells = <1>; 757 758 qusb2p_hstx_trim: hstx_trim@24e { 759 reg = <0x24e 0x2>; 760 bits = <5 4>; 761 }; 762 763 qusb2s_hstx_trim: hstx_trim@24f { 764 reg = <0x24f 0x1>; 765 bits = <1 4>; 766 }; 767 768 speedbin_efuse: speedbin@133 { 769 reg = <0x133 0x1>; 770 bits = <5 3>; 771 }; 772 }; 773 774 rng: rng@83000 { 775 compatible = "qcom,prng-ee"; 776 reg = <0x00083000 0x1000>; 777 clocks = <&gcc GCC_PRNG_AHB_CLK>; 778 clock-names = "core"; 779 }; 780 781 gcc: clock-controller@300000 { 782 compatible = "qcom,gcc-msm8996"; 783 #clock-cells = <1>; 784 #reset-cells = <1>; 785 #power-domain-cells = <1>; 786 reg = <0x00300000 0x90000>; 787 788 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 789 <&rpmcc RPM_SMD_LN_BB_CLK>, 790 <&sleep_clk>, 791 <&pciephy_0>, 792 <&pciephy_1>, 793 <&pciephy_2>, 794 <&ssusb_phy_0>, 795 <&ufsphy_lane 0>, 796 <&ufsphy_lane 1>, 797 <&ufsphy_lane 2>; 798 clock-names = "cxo", 799 "cxo2", 800 "sleep_clk", 801 "pcie_0_pipe_clk_src", 802 "pcie_1_pipe_clk_src", 803 "pcie_2_pipe_clk_src", 804 "usb3_phy_pipe_clk_src", 805 "ufs_rx_symbol_0_clk_src", 806 "ufs_rx_symbol_1_clk_src", 807 "ufs_tx_symbol_0_clk_src"; 808 }; 809 810 bimc: interconnect@408000 { 811 compatible = "qcom,msm8996-bimc"; 812 reg = <0x00408000 0x5a000>; 813 #interconnect-cells = <1>; 814 clock-names = "bus", "bus_a"; 815 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 816 <&rpmcc RPM_SMD_BIMC_A_CLK>; 817 }; 818 819 tsens0: thermal-sensor@4a9000 { 820 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 821 reg = <0x004a9000 0x1000>, /* TM */ 822 <0x004a8000 0x1000>; /* SROT */ 823 #qcom,sensors = <13>; 824 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 826 interrupt-names = "uplow", "critical"; 827 #thermal-sensor-cells = <1>; 828 }; 829 830 tsens1: thermal-sensor@4ad000 { 831 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 832 reg = <0x004ad000 0x1000>, /* TM */ 833 <0x004ac000 0x1000>; /* SROT */ 834 #qcom,sensors = <8>; 835 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 837 interrupt-names = "uplow", "critical"; 838 #thermal-sensor-cells = <1>; 839 }; 840 841 cryptobam: dma-controller@644000 { 842 compatible = "qcom,bam-v1.7.0"; 843 reg = <0x00644000 0x24000>; 844 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&gcc GCC_CE1_CLK>; 846 clock-names = "bam_clk"; 847 #dma-cells = <1>; 848 qcom,ee = <0>; 849 qcom,controlled-remotely; 850 }; 851 852 crypto: crypto@67a000 { 853 compatible = "qcom,crypto-v5.4"; 854 reg = <0x0067a000 0x6000>; 855 clocks = <&gcc GCC_CE1_AHB_CLK>, 856 <&gcc GCC_CE1_AXI_CLK>, 857 <&gcc GCC_CE1_CLK>; 858 clock-names = "iface", "bus", "core"; 859 dmas = <&cryptobam 6>, <&cryptobam 7>; 860 dma-names = "rx", "tx"; 861 }; 862 863 cnoc: interconnect@500000 { 864 compatible = "qcom,msm8996-cnoc"; 865 reg = <0x00500000 0x1000>; 866 #interconnect-cells = <1>; 867 clock-names = "bus", "bus_a"; 868 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 869 <&rpmcc RPM_SMD_CNOC_A_CLK>; 870 }; 871 872 snoc: interconnect@524000 { 873 compatible = "qcom,msm8996-snoc"; 874 reg = <0x00524000 0x1c000>; 875 #interconnect-cells = <1>; 876 clock-names = "bus", "bus_a"; 877 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 878 <&rpmcc RPM_SMD_SNOC_A_CLK>; 879 }; 880 881 a0noc: interconnect@543000 { 882 compatible = "qcom,msm8996-a0noc"; 883 reg = <0x00543000 0x6000>; 884 #interconnect-cells = <1>; 885 clock-names = "aggre0_snoc_axi", 886 "aggre0_cnoc_ahb", 887 "aggre0_noc_mpu_cfg"; 888 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 889 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 890 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 891 power-domains = <&gcc AGGRE0_NOC_GDSC>; 892 }; 893 894 a1noc: interconnect@562000 { 895 compatible = "qcom,msm8996-a1noc"; 896 reg = <0x00562000 0x5000>; 897 #interconnect-cells = <1>; 898 clock-names = "bus", "bus_a"; 899 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 900 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 901 }; 902 903 a2noc: interconnect@583000 { 904 compatible = "qcom,msm8996-a2noc"; 905 reg = <0x00583000 0x7000>; 906 #interconnect-cells = <1>; 907 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; 908 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 909 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 910 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 911 <&gcc GCC_UFS_AXI_CLK>; 912 }; 913 914 mnoc: interconnect@5a4000 { 915 compatible = "qcom,msm8996-mnoc"; 916 reg = <0x005a4000 0x1c000>; 917 #interconnect-cells = <1>; 918 clock-names = "bus", "bus_a", "iface"; 919 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 920 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 921 <&mmcc AHB_CLK_SRC>; 922 }; 923 924 pnoc: interconnect@5c0000 { 925 compatible = "qcom,msm8996-pnoc"; 926 reg = <0x005c0000 0x3000>; 927 #interconnect-cells = <1>; 928 clock-names = "bus", "bus_a"; 929 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 930 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 931 }; 932 933 tcsr_mutex: hwlock@740000 { 934 compatible = "qcom,tcsr-mutex"; 935 reg = <0x00740000 0x20000>; 936 #hwlock-cells = <1>; 937 }; 938 939 tcsr_1: syscon@760000 { 940 compatible = "qcom,tcsr-msm8996", "syscon"; 941 reg = <0x00760000 0x20000>; 942 }; 943 944 tcsr_2: syscon@7a0000 { 945 compatible = "qcom,tcsr-msm8996", "syscon"; 946 reg = <0x007a0000 0x18000>; 947 }; 948 949 mmcc: clock-controller@8c0000 { 950 compatible = "qcom,mmcc-msm8996"; 951 #clock-cells = <1>; 952 #reset-cells = <1>; 953 #power-domain-cells = <1>; 954 reg = <0x008c0000 0x40000>; 955 clocks = <&xo_board>, 956 <&gcc GPLL0>, 957 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 958 <&mdss_dsi0_phy 1>, 959 <&mdss_dsi0_phy 0>, 960 <&mdss_dsi1_phy 1>, 961 <&mdss_dsi1_phy 0>, 962 <&mdss_hdmi_phy>; 963 clock-names = "xo", 964 "gpll0", 965 "gcc_mmss_noc_cfg_ahb_clk", 966 "dsi0pll", 967 "dsi0pllbyte", 968 "dsi1pll", 969 "dsi1pllbyte", 970 "hdmipll"; 971 assigned-clocks = <&mmcc MMPLL9_PLL>, 972 <&mmcc MMPLL1_PLL>, 973 <&mmcc MMPLL3_PLL>, 974 <&mmcc MMPLL4_PLL>, 975 <&mmcc MMPLL5_PLL>; 976 assigned-clock-rates = <624000000>, 977 <810000000>, 978 <980000000>, 979 <960000000>, 980 <825000000>; 981 }; 982 983 mdss: display-subsystem@900000 { 984 compatible = "qcom,mdss"; 985 986 reg = <0x00900000 0x1000>, 987 <0x009b0000 0x1040>, 988 <0x009b8000 0x1040>; 989 reg-names = "mdss_phys", 990 "vbif_phys", 991 "vbif_nrt_phys"; 992 993 power-domains = <&mmcc MDSS_GDSC>; 994 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 995 996 interrupt-controller; 997 #interrupt-cells = <1>; 998 999 clocks = <&mmcc MDSS_AHB_CLK>, 1000 <&mmcc MDSS_MDP_CLK>; 1001 clock-names = "iface", "core"; 1002 1003 #address-cells = <1>; 1004 #size-cells = <1>; 1005 ranges; 1006 1007 status = "disabled"; 1008 1009 mdp: display-controller@901000 { 1010 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 1011 reg = <0x00901000 0x90000>; 1012 reg-names = "mdp_phys"; 1013 1014 interrupt-parent = <&mdss>; 1015 interrupts = <0>; 1016 1017 clocks = <&mmcc MDSS_AHB_CLK>, 1018 <&mmcc MDSS_AXI_CLK>, 1019 <&mmcc MDSS_MDP_CLK>, 1020 <&mmcc SMMU_MDP_AXI_CLK>, 1021 <&mmcc MDSS_VSYNC_CLK>; 1022 clock-names = "iface", 1023 "bus", 1024 "core", 1025 "iommu", 1026 "vsync"; 1027 1028 iommus = <&mdp_smmu 0>; 1029 1030 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1031 <&mmcc MDSS_VSYNC_CLK>; 1032 assigned-clock-rates = <300000000>, 1033 <19200000>; 1034 1035 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1036 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 1037 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 1038 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 1039 1040 ports { 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 1044 port@0 { 1045 reg = <0>; 1046 mdp5_intf3_out: endpoint { 1047 remote-endpoint = <&mdss_hdmi_in>; 1048 }; 1049 }; 1050 1051 port@1 { 1052 reg = <1>; 1053 mdp5_intf1_out: endpoint { 1054 remote-endpoint = <&mdss_dsi0_in>; 1055 }; 1056 }; 1057 1058 port@2 { 1059 reg = <2>; 1060 mdp5_intf2_out: endpoint { 1061 remote-endpoint = <&mdss_dsi1_in>; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 mdss_dsi0: dsi@994000 { 1068 compatible = "qcom,msm8996-dsi-ctrl", 1069 "qcom,mdss-dsi-ctrl"; 1070 reg = <0x00994000 0x400>; 1071 reg-names = "dsi_ctrl"; 1072 1073 interrupt-parent = <&mdss>; 1074 interrupts = <4>; 1075 1076 clocks = <&mmcc MDSS_MDP_CLK>, 1077 <&mmcc MDSS_BYTE0_CLK>, 1078 <&mmcc MDSS_AHB_CLK>, 1079 <&mmcc MDSS_AXI_CLK>, 1080 <&mmcc MMSS_MISC_AHB_CLK>, 1081 <&mmcc MDSS_PCLK0_CLK>, 1082 <&mmcc MDSS_ESC0_CLK>; 1083 clock-names = "mdp_core", 1084 "byte", 1085 "iface", 1086 "bus", 1087 "core_mmss", 1088 "pixel", 1089 "core"; 1090 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1091 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1092 1093 phys = <&mdss_dsi0_phy>; 1094 status = "disabled"; 1095 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 1099 ports { 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 1103 port@0 { 1104 reg = <0>; 1105 mdss_dsi0_in: endpoint { 1106 remote-endpoint = <&mdp5_intf1_out>; 1107 }; 1108 }; 1109 1110 port@1 { 1111 reg = <1>; 1112 mdss_dsi0_out: endpoint { 1113 }; 1114 }; 1115 }; 1116 }; 1117 1118 mdss_dsi0_phy: phy@994400 { 1119 compatible = "qcom,dsi-phy-14nm"; 1120 reg = <0x00994400 0x100>, 1121 <0x00994500 0x300>, 1122 <0x00994800 0x188>; 1123 reg-names = "dsi_phy", 1124 "dsi_phy_lane", 1125 "dsi_pll"; 1126 1127 #clock-cells = <1>; 1128 #phy-cells = <0>; 1129 1130 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1131 clock-names = "iface", "ref"; 1132 status = "disabled"; 1133 }; 1134 1135 mdss_dsi1: dsi@996000 { 1136 compatible = "qcom,msm8996-dsi-ctrl", 1137 "qcom,mdss-dsi-ctrl"; 1138 reg = <0x00996000 0x400>; 1139 reg-names = "dsi_ctrl"; 1140 1141 interrupt-parent = <&mdss>; 1142 interrupts = <5>; 1143 1144 clocks = <&mmcc MDSS_MDP_CLK>, 1145 <&mmcc MDSS_BYTE1_CLK>, 1146 <&mmcc MDSS_AHB_CLK>, 1147 <&mmcc MDSS_AXI_CLK>, 1148 <&mmcc MMSS_MISC_AHB_CLK>, 1149 <&mmcc MDSS_PCLK1_CLK>, 1150 <&mmcc MDSS_ESC1_CLK>; 1151 clock-names = "mdp_core", 1152 "byte", 1153 "iface", 1154 "bus", 1155 "core_mmss", 1156 "pixel", 1157 "core"; 1158 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1159 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 1160 1161 phys = <&mdss_dsi1_phy>; 1162 status = "disabled"; 1163 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 1167 ports { 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 1171 port@0 { 1172 reg = <0>; 1173 mdss_dsi1_in: endpoint { 1174 remote-endpoint = <&mdp5_intf2_out>; 1175 }; 1176 }; 1177 1178 port@1 { 1179 reg = <1>; 1180 mdss_dsi1_out: endpoint { 1181 }; 1182 }; 1183 }; 1184 }; 1185 1186 mdss_dsi1_phy: phy@996400 { 1187 compatible = "qcom,dsi-phy-14nm"; 1188 reg = <0x00996400 0x100>, 1189 <0x00996500 0x300>, 1190 <0x00996800 0x188>; 1191 reg-names = "dsi_phy", 1192 "dsi_phy_lane", 1193 "dsi_pll"; 1194 1195 #clock-cells = <1>; 1196 #phy-cells = <0>; 1197 1198 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1199 clock-names = "iface", "ref"; 1200 status = "disabled"; 1201 }; 1202 1203 mdss_hdmi: hdmi-tx@9a0000 { 1204 compatible = "qcom,hdmi-tx-8996"; 1205 reg = <0x009a0000 0x50c>, 1206 <0x00070000 0x6158>, 1207 <0x009e0000 0xfff>; 1208 reg-names = "core_physical", 1209 "qfprom_physical", 1210 "hdcp_physical"; 1211 1212 interrupt-parent = <&mdss>; 1213 interrupts = <8>; 1214 1215 clocks = <&mmcc MDSS_MDP_CLK>, 1216 <&mmcc MDSS_AHB_CLK>, 1217 <&mmcc MDSS_HDMI_CLK>, 1218 <&mmcc MDSS_HDMI_AHB_CLK>, 1219 <&mmcc MDSS_EXTPCLK_CLK>; 1220 clock-names = 1221 "mdp_core", 1222 "iface", 1223 "core", 1224 "alt_iface", 1225 "extp"; 1226 1227 phys = <&mdss_hdmi_phy>; 1228 #sound-dai-cells = <1>; 1229 1230 status = "disabled"; 1231 1232 ports { 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 1236 port@0 { 1237 reg = <0>; 1238 mdss_hdmi_in: endpoint { 1239 remote-endpoint = <&mdp5_intf3_out>; 1240 }; 1241 }; 1242 }; 1243 }; 1244 1245 mdss_hdmi_phy: phy@9a0600 { 1246 #phy-cells = <0>; 1247 compatible = "qcom,hdmi-phy-8996"; 1248 reg = <0x009a0600 0x1c4>, 1249 <0x009a0a00 0x124>, 1250 <0x009a0c00 0x124>, 1251 <0x009a0e00 0x124>, 1252 <0x009a1000 0x124>, 1253 <0x009a1200 0x0c8>; 1254 reg-names = "hdmi_pll", 1255 "hdmi_tx_l0", 1256 "hdmi_tx_l1", 1257 "hdmi_tx_l2", 1258 "hdmi_tx_l3", 1259 "hdmi_phy"; 1260 1261 clocks = <&mmcc MDSS_AHB_CLK>, 1262 <&gcc GCC_HDMI_CLKREF_CLK>, 1263 <&xo_board>; 1264 clock-names = "iface", 1265 "ref", 1266 "xo"; 1267 1268 #clock-cells = <0>; 1269 1270 status = "disabled"; 1271 }; 1272 }; 1273 1274 gpu: gpu@b00000 { 1275 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1276 1277 reg = <0x00b00000 0x3f000>; 1278 reg-names = "kgsl_3d0_reg_memory"; 1279 1280 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1281 1282 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1283 <&mmcc GPU_AHB_CLK>, 1284 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1285 <&gcc GCC_BIMC_GFX_CLK>, 1286 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1287 1288 clock-names = "core", 1289 "iface", 1290 "rbbmtimer", 1291 "mem", 1292 "mem_iface"; 1293 1294 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1295 interconnect-names = "gfx-mem"; 1296 1297 power-domains = <&mmcc GPU_GX_GDSC>; 1298 iommus = <&adreno_smmu 0>; 1299 1300 nvmem-cells = <&speedbin_efuse>; 1301 nvmem-cell-names = "speed_bin"; 1302 1303 operating-points-v2 = <&gpu_opp_table>; 1304 1305 status = "disabled"; 1306 1307 #cooling-cells = <2>; 1308 1309 gpu_opp_table: opp-table { 1310 compatible = "operating-points-v2"; 1311 1312 /* 1313 * 624Mhz is only available on speed bins 0 and 3. 1314 * 560Mhz is only available on speed bins 0, 2 and 3. 1315 * All the rest are available on all bins of the hardware. 1316 */ 1317 opp-624000000 { 1318 opp-hz = /bits/ 64 <624000000>; 1319 opp-supported-hw = <0x09>; 1320 }; 1321 opp-560000000 { 1322 opp-hz = /bits/ 64 <560000000>; 1323 opp-supported-hw = <0x0d>; 1324 }; 1325 opp-510000000 { 1326 opp-hz = /bits/ 64 <510000000>; 1327 opp-supported-hw = <0xff>; 1328 }; 1329 opp-401800000 { 1330 opp-hz = /bits/ 64 <401800000>; 1331 opp-supported-hw = <0xff>; 1332 }; 1333 opp-315000000 { 1334 opp-hz = /bits/ 64 <315000000>; 1335 opp-supported-hw = <0xff>; 1336 }; 1337 opp-214000000 { 1338 opp-hz = /bits/ 64 <214000000>; 1339 opp-supported-hw = <0xff>; 1340 }; 1341 opp-133000000 { 1342 opp-hz = /bits/ 64 <133000000>; 1343 opp-supported-hw = <0xff>; 1344 }; 1345 }; 1346 1347 zap-shader { 1348 memory-region = <&gpu_mem>; 1349 }; 1350 }; 1351 1352 tlmm: pinctrl@1010000 { 1353 compatible = "qcom,msm8996-pinctrl"; 1354 reg = <0x01010000 0x300000>; 1355 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1356 gpio-controller; 1357 gpio-ranges = <&tlmm 0 0 150>; 1358 #gpio-cells = <2>; 1359 interrupt-controller; 1360 #interrupt-cells = <2>; 1361 1362 blsp1_spi1_default: blsp1-spi1-default-state { 1363 spi-pins { 1364 pins = "gpio0", "gpio1", "gpio3"; 1365 function = "blsp_spi1"; 1366 drive-strength = <12>; 1367 bias-disable; 1368 }; 1369 1370 cs-pins { 1371 pins = "gpio2"; 1372 function = "gpio"; 1373 drive-strength = <16>; 1374 bias-disable; 1375 output-high; 1376 }; 1377 }; 1378 1379 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1380 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1381 function = "gpio"; 1382 drive-strength = <2>; 1383 bias-pull-down; 1384 }; 1385 1386 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1387 pins = "gpio4", "gpio5"; 1388 function = "blsp_uart8"; 1389 drive-strength = <16>; 1390 bias-disable; 1391 }; 1392 1393 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1394 pins = "gpio4", "gpio5"; 1395 function = "gpio"; 1396 drive-strength = <2>; 1397 bias-disable; 1398 }; 1399 1400 blsp2_i2c2_default: blsp2-i2c2-state { 1401 pins = "gpio6", "gpio7"; 1402 function = "blsp_i2c8"; 1403 drive-strength = <16>; 1404 bias-disable; 1405 }; 1406 1407 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1408 pins = "gpio6", "gpio7"; 1409 function = "gpio"; 1410 drive-strength = <2>; 1411 bias-disable; 1412 }; 1413 1414 blsp1_i2c6_default: blsp1-i2c6-state { 1415 pins = "gpio27", "gpio28"; 1416 function = "blsp_i2c6"; 1417 drive-strength = <16>; 1418 bias-disable; 1419 }; 1420 1421 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1422 pins = "gpio27", "gpio28"; 1423 function = "gpio"; 1424 drive-strength = <2>; 1425 bias-pull-up; 1426 }; 1427 1428 cci0_default: cci0-default-state { 1429 pins = "gpio17", "gpio18"; 1430 function = "cci_i2c"; 1431 drive-strength = <16>; 1432 bias-disable; 1433 }; 1434 1435 camera0_state_on: 1436 camera_rear_default: camera-rear-default-state { 1437 camera0_mclk: mclk0-pins { 1438 pins = "gpio13"; 1439 function = "cam_mclk"; 1440 drive-strength = <16>; 1441 bias-disable; 1442 }; 1443 1444 camera0_rst: rst-pins { 1445 pins = "gpio25"; 1446 function = "gpio"; 1447 drive-strength = <16>; 1448 bias-disable; 1449 }; 1450 1451 camera0_pwdn: pwdn-pins { 1452 pins = "gpio26"; 1453 function = "gpio"; 1454 drive-strength = <16>; 1455 bias-disable; 1456 }; 1457 }; 1458 1459 cci1_default: cci1-default-state { 1460 pins = "gpio19", "gpio20"; 1461 function = "cci_i2c"; 1462 drive-strength = <16>; 1463 bias-disable; 1464 }; 1465 1466 camera1_state_on: 1467 camera_board_default: camera-board-default-state { 1468 mclk1-pins { 1469 pins = "gpio14"; 1470 function = "cam_mclk"; 1471 drive-strength = <16>; 1472 bias-disable; 1473 }; 1474 1475 pwdn-pins { 1476 pins = "gpio98"; 1477 function = "gpio"; 1478 drive-strength = <16>; 1479 bias-disable; 1480 }; 1481 1482 rst-pins { 1483 pins = "gpio104"; 1484 function = "gpio"; 1485 drive-strength = <16>; 1486 bias-disable; 1487 }; 1488 }; 1489 1490 camera2_state_on: 1491 camera_front_default: camera-front-default-state { 1492 camera2_mclk: mclk2-pins { 1493 pins = "gpio15"; 1494 function = "cam_mclk"; 1495 drive-strength = <16>; 1496 bias-disable; 1497 }; 1498 1499 camera2_rst: rst-pins { 1500 pins = "gpio23"; 1501 function = "gpio"; 1502 drive-strength = <16>; 1503 bias-disable; 1504 }; 1505 1506 pwdn-pins { 1507 pins = "gpio133"; 1508 function = "gpio"; 1509 drive-strength = <16>; 1510 bias-disable; 1511 }; 1512 }; 1513 1514 pcie0_state_on: pcie0-state-on-state { 1515 perst-pins { 1516 pins = "gpio35"; 1517 function = "gpio"; 1518 drive-strength = <2>; 1519 bias-pull-down; 1520 }; 1521 1522 clkreq-pins { 1523 pins = "gpio36"; 1524 function = "pci_e0"; 1525 drive-strength = <2>; 1526 bias-pull-up; 1527 }; 1528 1529 wake-pins { 1530 pins = "gpio37"; 1531 function = "gpio"; 1532 drive-strength = <2>; 1533 bias-pull-up; 1534 }; 1535 }; 1536 1537 pcie0_state_off: pcie0-state-off-state { 1538 perst-pins { 1539 pins = "gpio35"; 1540 function = "gpio"; 1541 drive-strength = <2>; 1542 bias-pull-down; 1543 }; 1544 1545 clkreq-pins { 1546 pins = "gpio36"; 1547 function = "gpio"; 1548 drive-strength = <2>; 1549 bias-disable; 1550 }; 1551 1552 wake-pins { 1553 pins = "gpio37"; 1554 function = "gpio"; 1555 drive-strength = <2>; 1556 bias-disable; 1557 }; 1558 }; 1559 1560 blsp1_uart2_default: blsp1-uart2-default-state { 1561 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1562 function = "blsp_uart2"; 1563 drive-strength = <16>; 1564 bias-disable; 1565 }; 1566 1567 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1568 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1569 function = "gpio"; 1570 drive-strength = <2>; 1571 bias-disable; 1572 }; 1573 1574 blsp1_i2c3_default: blsp1-i2c3-default-state { 1575 pins = "gpio47", "gpio48"; 1576 function = "blsp_i2c3"; 1577 drive-strength = <16>; 1578 bias-disable; 1579 }; 1580 1581 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1582 pins = "gpio47", "gpio48"; 1583 function = "gpio"; 1584 drive-strength = <2>; 1585 bias-disable; 1586 }; 1587 1588 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1589 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1590 function = "blsp_uart9"; 1591 drive-strength = <16>; 1592 bias-disable; 1593 }; 1594 1595 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1596 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1597 function = "blsp_uart9"; 1598 drive-strength = <2>; 1599 bias-disable; 1600 }; 1601 1602 blsp2_i2c3_default: blsp2-i2c3-state-state { 1603 pins = "gpio51", "gpio52"; 1604 function = "blsp_i2c9"; 1605 drive-strength = <16>; 1606 bias-disable; 1607 }; 1608 1609 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1610 pins = "gpio51", "gpio52"; 1611 function = "gpio"; 1612 drive-strength = <2>; 1613 bias-disable; 1614 }; 1615 1616 wcd_intr_default: wcd-intr-default-state { 1617 pins = "gpio54"; 1618 function = "gpio"; 1619 drive-strength = <2>; 1620 bias-pull-down; 1621 }; 1622 1623 blsp2_i2c1_default: blsp2-i2c1-state { 1624 pins = "gpio55", "gpio56"; 1625 function = "blsp_i2c7"; 1626 drive-strength = <16>; 1627 bias-disable; 1628 }; 1629 1630 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1631 pins = "gpio55", "gpio56"; 1632 function = "gpio"; 1633 drive-strength = <2>; 1634 bias-disable; 1635 }; 1636 1637 blsp2_i2c5_default: blsp2-i2c5-state { 1638 pins = "gpio60", "gpio61"; 1639 function = "blsp_i2c11"; 1640 drive-strength = <2>; 1641 bias-disable; 1642 }; 1643 1644 /* Sleep state for BLSP2_I2C5 is missing.. */ 1645 1646 cdc_reset_active: cdc-reset-active-state { 1647 pins = "gpio64"; 1648 function = "gpio"; 1649 drive-strength = <16>; 1650 bias-pull-down; 1651 output-high; 1652 }; 1653 1654 cdc_reset_sleep: cdc-reset-sleep-state { 1655 pins = "gpio64"; 1656 function = "gpio"; 1657 drive-strength = <16>; 1658 bias-disable; 1659 output-low; 1660 }; 1661 1662 blsp2_spi6_default: blsp2-spi6-default-state { 1663 spi-pins { 1664 pins = "gpio85", "gpio86", "gpio88"; 1665 function = "blsp_spi12"; 1666 drive-strength = <12>; 1667 bias-disable; 1668 }; 1669 1670 cs-pins { 1671 pins = "gpio87"; 1672 function = "gpio"; 1673 drive-strength = <16>; 1674 bias-disable; 1675 output-high; 1676 }; 1677 }; 1678 1679 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1680 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1681 function = "gpio"; 1682 drive-strength = <2>; 1683 bias-pull-down; 1684 }; 1685 1686 blsp2_i2c6_default: blsp2-i2c6-state { 1687 pins = "gpio87", "gpio88"; 1688 function = "blsp_i2c12"; 1689 drive-strength = <16>; 1690 bias-disable; 1691 }; 1692 1693 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1694 pins = "gpio87", "gpio88"; 1695 function = "gpio"; 1696 drive-strength = <2>; 1697 bias-disable; 1698 }; 1699 1700 pcie1_state_on: pcie1-on-state { 1701 perst-pins { 1702 pins = "gpio130"; 1703 function = "gpio"; 1704 drive-strength = <2>; 1705 bias-pull-down; 1706 }; 1707 1708 clkreq-pins { 1709 pins = "gpio131"; 1710 function = "pci_e1"; 1711 drive-strength = <2>; 1712 bias-pull-up; 1713 }; 1714 1715 wake-pins { 1716 pins = "gpio132"; 1717 function = "gpio"; 1718 drive-strength = <2>; 1719 bias-pull-down; 1720 }; 1721 }; 1722 1723 pcie1_state_off: pcie1-off-state { 1724 /* Perst is missing? */ 1725 clkreq-pins { 1726 pins = "gpio131"; 1727 function = "gpio"; 1728 drive-strength = <2>; 1729 bias-disable; 1730 }; 1731 1732 wake-pins { 1733 pins = "gpio132"; 1734 function = "gpio"; 1735 drive-strength = <2>; 1736 bias-disable; 1737 }; 1738 }; 1739 1740 pcie2_state_on: pcie2-on-state { 1741 perst-pins { 1742 pins = "gpio114"; 1743 function = "gpio"; 1744 drive-strength = <2>; 1745 bias-pull-down; 1746 }; 1747 1748 clkreq-pins { 1749 pins = "gpio115"; 1750 function = "pci_e2"; 1751 drive-strength = <2>; 1752 bias-pull-up; 1753 }; 1754 1755 wake-pins { 1756 pins = "gpio116"; 1757 function = "gpio"; 1758 drive-strength = <2>; 1759 bias-pull-down; 1760 }; 1761 }; 1762 1763 pcie2_state_off: pcie2-off-state { 1764 /* Perst is missing? */ 1765 clkreq-pins { 1766 pins = "gpio115"; 1767 function = "gpio"; 1768 drive-strength = <2>; 1769 bias-disable; 1770 }; 1771 1772 wake-pins { 1773 pins = "gpio116"; 1774 function = "gpio"; 1775 drive-strength = <2>; 1776 bias-disable; 1777 }; 1778 }; 1779 1780 sdc1_state_on: sdc1-on-state { 1781 clk-pins { 1782 pins = "sdc1_clk"; 1783 bias-disable; 1784 drive-strength = <16>; 1785 }; 1786 1787 cmd-pins { 1788 pins = "sdc1_cmd"; 1789 bias-pull-up; 1790 drive-strength = <10>; 1791 }; 1792 1793 data-pins { 1794 pins = "sdc1_data"; 1795 bias-pull-up; 1796 drive-strength = <10>; 1797 }; 1798 1799 rclk-pins { 1800 pins = "sdc1_rclk"; 1801 bias-pull-down; 1802 }; 1803 }; 1804 1805 sdc1_state_off: sdc1-off-state { 1806 clk-pins { 1807 pins = "sdc1_clk"; 1808 bias-disable; 1809 drive-strength = <2>; 1810 }; 1811 1812 cmd-pins { 1813 pins = "sdc1_cmd"; 1814 bias-pull-up; 1815 drive-strength = <2>; 1816 }; 1817 1818 data-pins { 1819 pins = "sdc1_data"; 1820 bias-pull-up; 1821 drive-strength = <2>; 1822 }; 1823 1824 rclk-pins { 1825 pins = "sdc1_rclk"; 1826 bias-pull-down; 1827 }; 1828 }; 1829 1830 sdc2_state_on: sdc2-on-state { 1831 clk-pins { 1832 pins = "sdc2_clk"; 1833 bias-disable; 1834 drive-strength = <16>; 1835 }; 1836 1837 cmd-pins { 1838 pins = "sdc2_cmd"; 1839 bias-pull-up; 1840 drive-strength = <10>; 1841 }; 1842 1843 data-pins { 1844 pins = "sdc2_data"; 1845 bias-pull-up; 1846 drive-strength = <10>; 1847 }; 1848 }; 1849 1850 sdc2_state_off: sdc2-off-state { 1851 clk-pins { 1852 pins = "sdc2_clk"; 1853 bias-disable; 1854 drive-strength = <2>; 1855 }; 1856 1857 cmd-pins { 1858 pins = "sdc2_cmd"; 1859 bias-pull-up; 1860 drive-strength = <2>; 1861 }; 1862 1863 data-pins { 1864 pins = "sdc2_data"; 1865 bias-pull-up; 1866 drive-strength = <2>; 1867 }; 1868 }; 1869 }; 1870 1871 sram@290000 { 1872 compatible = "qcom,rpm-stats"; 1873 reg = <0x00290000 0x10000>; 1874 }; 1875 1876 spmi_bus: spmi@400f000 { 1877 compatible = "qcom,spmi-pmic-arb"; 1878 reg = <0x0400f000 0x1000>, 1879 <0x04400000 0x800000>, 1880 <0x04c00000 0x800000>, 1881 <0x05800000 0x200000>, 1882 <0x0400a000 0x002100>; 1883 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1884 interrupt-names = "periph_irq"; 1885 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1886 qcom,ee = <0>; 1887 qcom,channel = <0>; 1888 #address-cells = <2>; 1889 #size-cells = <0>; 1890 interrupt-controller; 1891 #interrupt-cells = <4>; 1892 }; 1893 1894 bus@0 { 1895 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1896 compatible = "simple-pm-bus"; 1897 #address-cells = <1>; 1898 #size-cells = <1>; 1899 ranges = <0x0 0x0 0xffffffff>; 1900 1901 pcie0: pcie@600000 { 1902 compatible = "qcom,pcie-msm8996"; 1903 status = "disabled"; 1904 power-domains = <&gcc PCIE0_GDSC>; 1905 bus-range = <0x00 0xff>; 1906 num-lanes = <1>; 1907 1908 reg = <0x00600000 0x2000>, 1909 <0x0c000000 0xf1d>, 1910 <0x0c000f20 0xa8>, 1911 <0x0c100000 0x100000>; 1912 reg-names = "parf", "dbi", "elbi","config"; 1913 1914 phys = <&pciephy_0>; 1915 phy-names = "pciephy"; 1916 1917 #address-cells = <3>; 1918 #size-cells = <2>; 1919 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1920 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1921 1922 device_type = "pci"; 1923 1924 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1925 interrupt-names = "msi"; 1926 #interrupt-cells = <1>; 1927 interrupt-map-mask = <0 0 0 0x7>; 1928 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1929 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1930 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1931 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1932 1933 pinctrl-names = "default", "sleep"; 1934 pinctrl-0 = <&pcie0_state_on>; 1935 pinctrl-1 = <&pcie0_state_off>; 1936 1937 linux,pci-domain = <0>; 1938 1939 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1940 <&gcc GCC_PCIE_0_AUX_CLK>, 1941 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1942 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1943 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1944 1945 clock-names = "pipe", 1946 "aux", 1947 "cfg", 1948 "bus_master", 1949 "bus_slave"; 1950 }; 1951 1952 pcie1: pcie@608000 { 1953 compatible = "qcom,pcie-msm8996"; 1954 power-domains = <&gcc PCIE1_GDSC>; 1955 bus-range = <0x00 0xff>; 1956 num-lanes = <1>; 1957 1958 status = "disabled"; 1959 1960 reg = <0x00608000 0x2000>, 1961 <0x0d000000 0xf1d>, 1962 <0x0d000f20 0xa8>, 1963 <0x0d100000 0x100000>; 1964 1965 reg-names = "parf", "dbi", "elbi","config"; 1966 1967 phys = <&pciephy_1>; 1968 phy-names = "pciephy"; 1969 1970 #address-cells = <3>; 1971 #size-cells = <2>; 1972 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 1973 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1974 1975 device_type = "pci"; 1976 1977 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1978 interrupt-names = "msi"; 1979 #interrupt-cells = <1>; 1980 interrupt-map-mask = <0 0 0 0x7>; 1981 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1982 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1983 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1984 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1985 1986 pinctrl-names = "default", "sleep"; 1987 pinctrl-0 = <&pcie1_state_on>; 1988 pinctrl-1 = <&pcie1_state_off>; 1989 1990 linux,pci-domain = <1>; 1991 1992 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1993 <&gcc GCC_PCIE_1_AUX_CLK>, 1994 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1995 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1996 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1997 1998 clock-names = "pipe", 1999 "aux", 2000 "cfg", 2001 "bus_master", 2002 "bus_slave"; 2003 }; 2004 2005 pcie2: pcie@610000 { 2006 compatible = "qcom,pcie-msm8996"; 2007 power-domains = <&gcc PCIE2_GDSC>; 2008 bus-range = <0x00 0xff>; 2009 num-lanes = <1>; 2010 status = "disabled"; 2011 reg = <0x00610000 0x2000>, 2012 <0x0e000000 0xf1d>, 2013 <0x0e000f20 0xa8>, 2014 <0x0e100000 0x100000>; 2015 2016 reg-names = "parf", "dbi", "elbi","config"; 2017 2018 phys = <&pciephy_2>; 2019 phy-names = "pciephy"; 2020 2021 #address-cells = <3>; 2022 #size-cells = <2>; 2023 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 2024 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 2025 2026 device_type = "pci"; 2027 2028 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 2029 interrupt-names = "msi"; 2030 #interrupt-cells = <1>; 2031 interrupt-map-mask = <0 0 0 0x7>; 2032 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2033 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2034 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2035 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2036 2037 pinctrl-names = "default", "sleep"; 2038 pinctrl-0 = <&pcie2_state_on>; 2039 pinctrl-1 = <&pcie2_state_off>; 2040 2041 linux,pci-domain = <2>; 2042 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2043 <&gcc GCC_PCIE_2_AUX_CLK>, 2044 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2045 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2046 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 2047 2048 clock-names = "pipe", 2049 "aux", 2050 "cfg", 2051 "bus_master", 2052 "bus_slave"; 2053 }; 2054 }; 2055 2056 ufshc: ufshc@624000 { 2057 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 2058 "jedec,ufs-2.0"; 2059 reg = <0x00624000 0x2500>; 2060 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2061 2062 phys = <&ufsphy_lane>; 2063 phy-names = "ufsphy"; 2064 2065 power-domains = <&gcc UFS_GDSC>; 2066 2067 clock-names = 2068 "core_clk_src", 2069 "core_clk", 2070 "bus_clk", 2071 "bus_aggr_clk", 2072 "iface_clk", 2073 "core_clk_unipro_src", 2074 "core_clk_unipro", 2075 "core_clk_ice", 2076 "ref_clk", 2077 "tx_lane0_sync_clk", 2078 "rx_lane0_sync_clk"; 2079 clocks = 2080 <&gcc UFS_AXI_CLK_SRC>, 2081 <&gcc GCC_UFS_AXI_CLK>, 2082 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2083 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2084 <&gcc GCC_UFS_AHB_CLK>, 2085 <&gcc UFS_ICE_CORE_CLK_SRC>, 2086 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2087 <&gcc GCC_UFS_ICE_CORE_CLK>, 2088 <&rpmcc RPM_SMD_LN_BB_CLK>, 2089 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2090 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2091 freq-table-hz = 2092 <100000000 200000000>, 2093 <100000000 200000000>, 2094 <0 0>, 2095 <0 0>, 2096 <0 0>, 2097 <150000000 300000000>, 2098 <0 0>, 2099 <0 0>, 2100 <0 0>, 2101 <0 0>, 2102 <0 0>; 2103 2104 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2105 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2106 interconnect-names = "ufs-ddr", "cpu-ufs"; 2107 2108 lanes-per-direction = <1>; 2109 #reset-cells = <1>; 2110 status = "disabled"; 2111 }; 2112 2113 ufsphy: phy@627000 { 2114 compatible = "qcom,msm8996-qmp-ufs-phy"; 2115 reg = <0x00627000 0x1c4>; 2116 #address-cells = <1>; 2117 #size-cells = <1>; 2118 ranges; 2119 2120 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2121 clock-names = "ref"; 2122 2123 resets = <&ufshc 0>; 2124 reset-names = "ufsphy"; 2125 status = "disabled"; 2126 2127 ufsphy_lane: phy@627400 { 2128 reg = <0x627400 0x12c>, 2129 <0x627600 0x200>, 2130 <0x627c00 0x1b4>; 2131 #clock-cells = <1>; 2132 #phy-cells = <0>; 2133 }; 2134 }; 2135 2136 camss: camss@a34000 { 2137 compatible = "qcom,msm8996-camss"; 2138 reg = <0x00a34000 0x1000>, 2139 <0x00a00030 0x4>, 2140 <0x00a35000 0x1000>, 2141 <0x00a00038 0x4>, 2142 <0x00a36000 0x1000>, 2143 <0x00a00040 0x4>, 2144 <0x00a30000 0x100>, 2145 <0x00a30400 0x100>, 2146 <0x00a30800 0x100>, 2147 <0x00a30c00 0x100>, 2148 <0x00a31000 0x500>, 2149 <0x00a00020 0x10>, 2150 <0x00a10000 0x1000>, 2151 <0x00a14000 0x1000>; 2152 reg-names = "csiphy0", 2153 "csiphy0_clk_mux", 2154 "csiphy1", 2155 "csiphy1_clk_mux", 2156 "csiphy2", 2157 "csiphy2_clk_mux", 2158 "csid0", 2159 "csid1", 2160 "csid2", 2161 "csid3", 2162 "ispif", 2163 "csi_clk_mux", 2164 "vfe0", 2165 "vfe1"; 2166 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2176 interrupt-names = "csiphy0", 2177 "csiphy1", 2178 "csiphy2", 2179 "csid0", 2180 "csid1", 2181 "csid2", 2182 "csid3", 2183 "ispif", 2184 "vfe0", 2185 "vfe1"; 2186 power-domains = <&mmcc VFE0_GDSC>, 2187 <&mmcc VFE1_GDSC>; 2188 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2189 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2190 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2191 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2192 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2193 <&mmcc CAMSS_CSI0_AHB_CLK>, 2194 <&mmcc CAMSS_CSI0_CLK>, 2195 <&mmcc CAMSS_CSI0PHY_CLK>, 2196 <&mmcc CAMSS_CSI0PIX_CLK>, 2197 <&mmcc CAMSS_CSI0RDI_CLK>, 2198 <&mmcc CAMSS_CSI1_AHB_CLK>, 2199 <&mmcc CAMSS_CSI1_CLK>, 2200 <&mmcc CAMSS_CSI1PHY_CLK>, 2201 <&mmcc CAMSS_CSI1PIX_CLK>, 2202 <&mmcc CAMSS_CSI1RDI_CLK>, 2203 <&mmcc CAMSS_CSI2_AHB_CLK>, 2204 <&mmcc CAMSS_CSI2_CLK>, 2205 <&mmcc CAMSS_CSI2PHY_CLK>, 2206 <&mmcc CAMSS_CSI2PIX_CLK>, 2207 <&mmcc CAMSS_CSI2RDI_CLK>, 2208 <&mmcc CAMSS_CSI3_AHB_CLK>, 2209 <&mmcc CAMSS_CSI3_CLK>, 2210 <&mmcc CAMSS_CSI3PHY_CLK>, 2211 <&mmcc CAMSS_CSI3PIX_CLK>, 2212 <&mmcc CAMSS_CSI3RDI_CLK>, 2213 <&mmcc CAMSS_AHB_CLK>, 2214 <&mmcc CAMSS_VFE0_CLK>, 2215 <&mmcc CAMSS_CSI_VFE0_CLK>, 2216 <&mmcc CAMSS_VFE0_AHB_CLK>, 2217 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2218 <&mmcc CAMSS_VFE1_CLK>, 2219 <&mmcc CAMSS_CSI_VFE1_CLK>, 2220 <&mmcc CAMSS_VFE1_AHB_CLK>, 2221 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2222 <&mmcc CAMSS_VFE_AHB_CLK>, 2223 <&mmcc CAMSS_VFE_AXI_CLK>; 2224 clock-names = "top_ahb", 2225 "ispif_ahb", 2226 "csiphy0_timer", 2227 "csiphy1_timer", 2228 "csiphy2_timer", 2229 "csi0_ahb", 2230 "csi0", 2231 "csi0_phy", 2232 "csi0_pix", 2233 "csi0_rdi", 2234 "csi1_ahb", 2235 "csi1", 2236 "csi1_phy", 2237 "csi1_pix", 2238 "csi1_rdi", 2239 "csi2_ahb", 2240 "csi2", 2241 "csi2_phy", 2242 "csi2_pix", 2243 "csi2_rdi", 2244 "csi3_ahb", 2245 "csi3", 2246 "csi3_phy", 2247 "csi3_pix", 2248 "csi3_rdi", 2249 "ahb", 2250 "vfe0", 2251 "csi_vfe0", 2252 "vfe0_ahb", 2253 "vfe0_stream", 2254 "vfe1", 2255 "csi_vfe1", 2256 "vfe1_ahb", 2257 "vfe1_stream", 2258 "vfe_ahb", 2259 "vfe_axi"; 2260 iommus = <&vfe_smmu 0>, 2261 <&vfe_smmu 1>, 2262 <&vfe_smmu 2>, 2263 <&vfe_smmu 3>; 2264 status = "disabled"; 2265 ports { 2266 #address-cells = <1>; 2267 #size-cells = <0>; 2268 }; 2269 }; 2270 2271 cci: cci@a0c000 { 2272 compatible = "qcom,msm8996-cci"; 2273 #address-cells = <1>; 2274 #size-cells = <0>; 2275 reg = <0xa0c000 0x1000>; 2276 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2277 power-domains = <&mmcc CAMSS_GDSC>; 2278 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2279 <&mmcc CAMSS_CCI_AHB_CLK>, 2280 <&mmcc CAMSS_CCI_CLK>, 2281 <&mmcc CAMSS_AHB_CLK>; 2282 clock-names = "camss_top_ahb", 2283 "cci_ahb", 2284 "cci", 2285 "camss_ahb"; 2286 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2287 <&mmcc CAMSS_CCI_CLK>; 2288 assigned-clock-rates = <80000000>, <37500000>; 2289 pinctrl-names = "default"; 2290 pinctrl-0 = <&cci0_default &cci1_default>; 2291 status = "disabled"; 2292 2293 cci_i2c0: i2c-bus@0 { 2294 reg = <0>; 2295 clock-frequency = <400000>; 2296 #address-cells = <1>; 2297 #size-cells = <0>; 2298 }; 2299 2300 cci_i2c1: i2c-bus@1 { 2301 reg = <1>; 2302 clock-frequency = <400000>; 2303 #address-cells = <1>; 2304 #size-cells = <0>; 2305 }; 2306 }; 2307 2308 adreno_smmu: iommu@b40000 { 2309 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2310 reg = <0x00b40000 0x10000>; 2311 2312 #global-interrupts = <1>; 2313 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2314 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2315 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2316 #iommu-cells = <1>; 2317 2318 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2319 <&mmcc GPU_AHB_CLK>; 2320 clock-names = "bus", "iface"; 2321 2322 power-domains = <&mmcc GPU_GDSC>; 2323 }; 2324 2325 venus: video-codec@c00000 { 2326 compatible = "qcom,msm8996-venus"; 2327 reg = <0x00c00000 0xff000>; 2328 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2329 power-domains = <&mmcc VENUS_GDSC>; 2330 clocks = <&mmcc VIDEO_CORE_CLK>, 2331 <&mmcc VIDEO_AHB_CLK>, 2332 <&mmcc VIDEO_AXI_CLK>, 2333 <&mmcc VIDEO_MAXI_CLK>; 2334 clock-names = "core", "iface", "bus", "mbus"; 2335 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2336 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2337 interconnect-names = "video-mem", "cpu-cfg"; 2338 iommus = <&venus_smmu 0x00>, 2339 <&venus_smmu 0x01>, 2340 <&venus_smmu 0x0a>, 2341 <&venus_smmu 0x07>, 2342 <&venus_smmu 0x0e>, 2343 <&venus_smmu 0x0f>, 2344 <&venus_smmu 0x08>, 2345 <&venus_smmu 0x09>, 2346 <&venus_smmu 0x0b>, 2347 <&venus_smmu 0x0c>, 2348 <&venus_smmu 0x0d>, 2349 <&venus_smmu 0x10>, 2350 <&venus_smmu 0x11>, 2351 <&venus_smmu 0x21>, 2352 <&venus_smmu 0x28>, 2353 <&venus_smmu 0x29>, 2354 <&venus_smmu 0x2b>, 2355 <&venus_smmu 0x2c>, 2356 <&venus_smmu 0x2d>, 2357 <&venus_smmu 0x31>; 2358 memory-region = <&venus_mem>; 2359 status = "disabled"; 2360 2361 video-decoder { 2362 compatible = "venus-decoder"; 2363 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2364 clock-names = "core"; 2365 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2366 }; 2367 2368 video-encoder { 2369 compatible = "venus-encoder"; 2370 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2371 clock-names = "core"; 2372 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2373 }; 2374 }; 2375 2376 mdp_smmu: iommu@d00000 { 2377 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2378 reg = <0x00d00000 0x10000>; 2379 2380 #global-interrupts = <1>; 2381 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2384 #iommu-cells = <1>; 2385 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2386 <&mmcc SMMU_MDP_AHB_CLK>; 2387 clock-names = "bus", "iface"; 2388 2389 power-domains = <&mmcc MDSS_GDSC>; 2390 }; 2391 2392 venus_smmu: iommu@d40000 { 2393 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2394 reg = <0x00d40000 0x20000>; 2395 #global-interrupts = <1>; 2396 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2404 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2405 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2406 <&mmcc SMMU_VIDEO_AHB_CLK>; 2407 clock-names = "bus", "iface"; 2408 #iommu-cells = <1>; 2409 status = "okay"; 2410 }; 2411 2412 vfe_smmu: iommu@da0000 { 2413 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2414 reg = <0x00da0000 0x10000>; 2415 2416 #global-interrupts = <1>; 2417 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2418 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2419 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2420 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2421 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2422 <&mmcc SMMU_VFE_AHB_CLK>; 2423 clock-names = "bus", "iface"; 2424 #iommu-cells = <1>; 2425 }; 2426 2427 lpass_q6_smmu: iommu@1600000 { 2428 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2429 reg = <0x01600000 0x20000>; 2430 #iommu-cells = <1>; 2431 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2432 2433 #global-interrupts = <1>; 2434 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2447 2448 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2449 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2450 clock-names = "bus", "iface"; 2451 }; 2452 2453 slpi_pil: remoteproc@1c00000 { 2454 compatible = "qcom,msm8996-slpi-pil"; 2455 reg = <0x01c00000 0x4000>; 2456 2457 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2458 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2459 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2460 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2461 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2462 interrupt-names = "wdog", 2463 "fatal", 2464 "ready", 2465 "handover", 2466 "stop-ack"; 2467 2468 clocks = <&xo_board>, 2469 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2470 clock-names = "xo", "aggre2"; 2471 2472 memory-region = <&slpi_mem>; 2473 2474 qcom,smem-states = <&slpi_smp2p_out 0>; 2475 qcom,smem-state-names = "stop"; 2476 2477 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2478 power-domain-names = "ssc_cx"; 2479 2480 status = "disabled"; 2481 2482 smd-edge { 2483 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2484 2485 label = "dsps"; 2486 mboxes = <&apcs_glb 25>; 2487 qcom,smd-edge = <3>; 2488 qcom,remote-pid = <3>; 2489 }; 2490 }; 2491 2492 mss_pil: remoteproc@2080000 { 2493 compatible = "qcom,msm8996-mss-pil"; 2494 reg = <0x2080000 0x100>, 2495 <0x2180000 0x020>; 2496 reg-names = "qdsp6", "rmb"; 2497 2498 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2499 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2500 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2501 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2502 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2503 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2504 interrupt-names = "wdog", "fatal", "ready", 2505 "handover", "stop-ack", 2506 "shutdown-ack"; 2507 2508 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2509 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2510 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2511 <&xo_board>, 2512 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2513 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2514 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2515 <&rpmcc RPM_SMD_PCNOC_CLK>, 2516 <&rpmcc RPM_SMD_QDSS_CLK>; 2517 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2518 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2519 2520 resets = <&gcc GCC_MSS_RESTART>; 2521 reset-names = "mss_restart"; 2522 2523 power-domains = <&rpmpd MSM8996_VDDCX>, 2524 <&rpmpd MSM8996_VDDMX>; 2525 power-domain-names = "cx", "mx"; 2526 2527 qcom,smem-states = <&mpss_smp2p_out 0>; 2528 qcom,smem-state-names = "stop"; 2529 2530 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2531 2532 status = "disabled"; 2533 2534 mba { 2535 memory-region = <&mba_mem>; 2536 }; 2537 2538 mpss { 2539 memory-region = <&mpss_mem>; 2540 }; 2541 2542 metadata { 2543 memory-region = <&mdata_mem>; 2544 }; 2545 2546 smd-edge { 2547 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2548 2549 label = "mpss"; 2550 mboxes = <&apcs_glb 12>; 2551 qcom,smd-edge = <0>; 2552 qcom,remote-pid = <1>; 2553 }; 2554 }; 2555 2556 stm@3002000 { 2557 compatible = "arm,coresight-stm", "arm,primecell"; 2558 reg = <0x3002000 0x1000>, 2559 <0x8280000 0x180000>; 2560 reg-names = "stm-base", "stm-stimulus-base"; 2561 2562 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2563 clock-names = "apb_pclk", "atclk"; 2564 2565 out-ports { 2566 port { 2567 stm_out: endpoint { 2568 remote-endpoint = 2569 <&funnel0_in>; 2570 }; 2571 }; 2572 }; 2573 }; 2574 2575 tpiu@3020000 { 2576 compatible = "arm,coresight-tpiu", "arm,primecell"; 2577 reg = <0x3020000 0x1000>; 2578 2579 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2580 clock-names = "apb_pclk", "atclk"; 2581 2582 in-ports { 2583 port { 2584 tpiu_in: endpoint { 2585 remote-endpoint = 2586 <&replicator_out1>; 2587 }; 2588 }; 2589 }; 2590 }; 2591 2592 funnel@3021000 { 2593 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2594 reg = <0x3021000 0x1000>; 2595 2596 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2597 clock-names = "apb_pclk", "atclk"; 2598 2599 in-ports { 2600 #address-cells = <1>; 2601 #size-cells = <0>; 2602 2603 port@7 { 2604 reg = <7>; 2605 funnel0_in: endpoint { 2606 remote-endpoint = 2607 <&stm_out>; 2608 }; 2609 }; 2610 }; 2611 2612 out-ports { 2613 port { 2614 funnel0_out: endpoint { 2615 remote-endpoint = 2616 <&merge_funnel_in0>; 2617 }; 2618 }; 2619 }; 2620 }; 2621 2622 funnel@3022000 { 2623 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2624 reg = <0x3022000 0x1000>; 2625 2626 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2627 clock-names = "apb_pclk", "atclk"; 2628 2629 in-ports { 2630 #address-cells = <1>; 2631 #size-cells = <0>; 2632 2633 port@6 { 2634 reg = <6>; 2635 funnel1_in: endpoint { 2636 remote-endpoint = 2637 <&apss_merge_funnel_out>; 2638 }; 2639 }; 2640 }; 2641 2642 out-ports { 2643 port { 2644 funnel1_out: endpoint { 2645 remote-endpoint = 2646 <&merge_funnel_in1>; 2647 }; 2648 }; 2649 }; 2650 }; 2651 2652 funnel@3023000 { 2653 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2654 reg = <0x3023000 0x1000>; 2655 2656 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2657 clock-names = "apb_pclk", "atclk"; 2658 2659 in-ports { 2660 port { 2661 funnel_in2_in_modem_etm: endpoint { 2662 remote-endpoint = 2663 <&modem_etm_out_funnel_in2>; 2664 }; 2665 }; 2666 }; 2667 2668 out-ports { 2669 port { 2670 funnel2_out: endpoint { 2671 remote-endpoint = 2672 <&merge_funnel_in2>; 2673 }; 2674 }; 2675 }; 2676 }; 2677 2678 funnel@3025000 { 2679 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2680 reg = <0x3025000 0x1000>; 2681 2682 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2683 clock-names = "apb_pclk", "atclk"; 2684 2685 in-ports { 2686 #address-cells = <1>; 2687 #size-cells = <0>; 2688 2689 port@0 { 2690 reg = <0>; 2691 merge_funnel_in0: endpoint { 2692 remote-endpoint = 2693 <&funnel0_out>; 2694 }; 2695 }; 2696 2697 port@1 { 2698 reg = <1>; 2699 merge_funnel_in1: endpoint { 2700 remote-endpoint = 2701 <&funnel1_out>; 2702 }; 2703 }; 2704 2705 port@2 { 2706 reg = <2>; 2707 merge_funnel_in2: endpoint { 2708 remote-endpoint = 2709 <&funnel2_out>; 2710 }; 2711 }; 2712 }; 2713 2714 out-ports { 2715 port { 2716 merge_funnel_out: endpoint { 2717 remote-endpoint = 2718 <&etf_in>; 2719 }; 2720 }; 2721 }; 2722 }; 2723 2724 replicator@3026000 { 2725 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2726 reg = <0x3026000 0x1000>; 2727 2728 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2729 clock-names = "apb_pclk", "atclk"; 2730 2731 in-ports { 2732 port { 2733 replicator_in: endpoint { 2734 remote-endpoint = 2735 <&etf_out>; 2736 }; 2737 }; 2738 }; 2739 2740 out-ports { 2741 #address-cells = <1>; 2742 #size-cells = <0>; 2743 2744 port@0 { 2745 reg = <0>; 2746 replicator_out0: endpoint { 2747 remote-endpoint = 2748 <&etr_in>; 2749 }; 2750 }; 2751 2752 port@1 { 2753 reg = <1>; 2754 replicator_out1: endpoint { 2755 remote-endpoint = 2756 <&tpiu_in>; 2757 }; 2758 }; 2759 }; 2760 }; 2761 2762 etf@3027000 { 2763 compatible = "arm,coresight-tmc", "arm,primecell"; 2764 reg = <0x3027000 0x1000>; 2765 2766 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2767 clock-names = "apb_pclk", "atclk"; 2768 2769 in-ports { 2770 port { 2771 etf_in: endpoint { 2772 remote-endpoint = 2773 <&merge_funnel_out>; 2774 }; 2775 }; 2776 }; 2777 2778 out-ports { 2779 port { 2780 etf_out: endpoint { 2781 remote-endpoint = 2782 <&replicator_in>; 2783 }; 2784 }; 2785 }; 2786 }; 2787 2788 etr@3028000 { 2789 compatible = "arm,coresight-tmc", "arm,primecell"; 2790 reg = <0x3028000 0x1000>; 2791 2792 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2793 clock-names = "apb_pclk", "atclk"; 2794 arm,scatter-gather; 2795 2796 in-ports { 2797 port { 2798 etr_in: endpoint { 2799 remote-endpoint = 2800 <&replicator_out0>; 2801 }; 2802 }; 2803 }; 2804 }; 2805 2806 debug@3810000 { 2807 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2808 reg = <0x3810000 0x1000>; 2809 2810 clocks = <&rpmcc RPM_QDSS_CLK>; 2811 clock-names = "apb_pclk"; 2812 2813 cpu = <&CPU0>; 2814 }; 2815 2816 etm@3840000 { 2817 compatible = "arm,coresight-etm4x", "arm,primecell"; 2818 reg = <0x3840000 0x1000>; 2819 2820 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2821 clock-names = "apb_pclk", "atclk"; 2822 2823 cpu = <&CPU0>; 2824 2825 out-ports { 2826 port { 2827 etm0_out: endpoint { 2828 remote-endpoint = 2829 <&apss_funnel0_in0>; 2830 }; 2831 }; 2832 }; 2833 }; 2834 2835 debug@3910000 { 2836 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2837 reg = <0x3910000 0x1000>; 2838 2839 clocks = <&rpmcc RPM_QDSS_CLK>; 2840 clock-names = "apb_pclk"; 2841 2842 cpu = <&CPU1>; 2843 }; 2844 2845 etm@3940000 { 2846 compatible = "arm,coresight-etm4x", "arm,primecell"; 2847 reg = <0x3940000 0x1000>; 2848 2849 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2850 clock-names = "apb_pclk", "atclk"; 2851 2852 cpu = <&CPU1>; 2853 2854 out-ports { 2855 port { 2856 etm1_out: endpoint { 2857 remote-endpoint = 2858 <&apss_funnel0_in1>; 2859 }; 2860 }; 2861 }; 2862 }; 2863 2864 funnel@39b0000 { /* APSS Funnel 0 */ 2865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2866 reg = <0x39b0000 0x1000>; 2867 2868 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2869 clock-names = "apb_pclk", "atclk"; 2870 2871 in-ports { 2872 #address-cells = <1>; 2873 #size-cells = <0>; 2874 2875 port@0 { 2876 reg = <0>; 2877 apss_funnel0_in0: endpoint { 2878 remote-endpoint = <&etm0_out>; 2879 }; 2880 }; 2881 2882 port@1 { 2883 reg = <1>; 2884 apss_funnel0_in1: endpoint { 2885 remote-endpoint = <&etm1_out>; 2886 }; 2887 }; 2888 }; 2889 2890 out-ports { 2891 port { 2892 apss_funnel0_out: endpoint { 2893 remote-endpoint = 2894 <&apss_merge_funnel_in0>; 2895 }; 2896 }; 2897 }; 2898 }; 2899 2900 debug@3a10000 { 2901 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2902 reg = <0x3a10000 0x1000>; 2903 2904 clocks = <&rpmcc RPM_QDSS_CLK>; 2905 clock-names = "apb_pclk"; 2906 2907 cpu = <&CPU2>; 2908 }; 2909 2910 etm@3a40000 { 2911 compatible = "arm,coresight-etm4x", "arm,primecell"; 2912 reg = <0x3a40000 0x1000>; 2913 2914 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2915 clock-names = "apb_pclk", "atclk"; 2916 2917 cpu = <&CPU2>; 2918 2919 out-ports { 2920 port { 2921 etm2_out: endpoint { 2922 remote-endpoint = 2923 <&apss_funnel1_in0>; 2924 }; 2925 }; 2926 }; 2927 }; 2928 2929 debug@3b10000 { 2930 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2931 reg = <0x3b10000 0x1000>; 2932 2933 clocks = <&rpmcc RPM_QDSS_CLK>; 2934 clock-names = "apb_pclk"; 2935 2936 cpu = <&CPU3>; 2937 }; 2938 2939 etm@3b40000 { 2940 compatible = "arm,coresight-etm4x", "arm,primecell"; 2941 reg = <0x3b40000 0x1000>; 2942 2943 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2944 clock-names = "apb_pclk", "atclk"; 2945 2946 cpu = <&CPU3>; 2947 2948 out-ports { 2949 port { 2950 etm3_out: endpoint { 2951 remote-endpoint = 2952 <&apss_funnel1_in1>; 2953 }; 2954 }; 2955 }; 2956 }; 2957 2958 funnel@3bb0000 { /* APSS Funnel 1 */ 2959 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2960 reg = <0x3bb0000 0x1000>; 2961 2962 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2963 clock-names = "apb_pclk", "atclk"; 2964 2965 in-ports { 2966 #address-cells = <1>; 2967 #size-cells = <0>; 2968 2969 port@0 { 2970 reg = <0>; 2971 apss_funnel1_in0: endpoint { 2972 remote-endpoint = <&etm2_out>; 2973 }; 2974 }; 2975 2976 port@1 { 2977 reg = <1>; 2978 apss_funnel1_in1: endpoint { 2979 remote-endpoint = <&etm3_out>; 2980 }; 2981 }; 2982 }; 2983 2984 out-ports { 2985 port { 2986 apss_funnel1_out: endpoint { 2987 remote-endpoint = 2988 <&apss_merge_funnel_in1>; 2989 }; 2990 }; 2991 }; 2992 }; 2993 2994 funnel@3bc0000 { 2995 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2996 reg = <0x3bc0000 0x1000>; 2997 2998 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2999 clock-names = "apb_pclk", "atclk"; 3000 3001 in-ports { 3002 #address-cells = <1>; 3003 #size-cells = <0>; 3004 3005 port@0 { 3006 reg = <0>; 3007 apss_merge_funnel_in0: endpoint { 3008 remote-endpoint = 3009 <&apss_funnel0_out>; 3010 }; 3011 }; 3012 3013 port@1 { 3014 reg = <1>; 3015 apss_merge_funnel_in1: endpoint { 3016 remote-endpoint = 3017 <&apss_funnel1_out>; 3018 }; 3019 }; 3020 }; 3021 3022 out-ports { 3023 port { 3024 apss_merge_funnel_out: endpoint { 3025 remote-endpoint = 3026 <&funnel1_in>; 3027 }; 3028 }; 3029 }; 3030 }; 3031 3032 kryocc: clock-controller@6400000 { 3033 compatible = "qcom,msm8996-apcc"; 3034 reg = <0x06400000 0x90000>; 3035 3036 clock-names = "xo", "sys_apcs_aux"; 3037 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3038 3039 #clock-cells = <1>; 3040 }; 3041 3042 usb3: usb@6af8800 { 3043 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3044 reg = <0x06af8800 0x400>; 3045 #address-cells = <1>; 3046 #size-cells = <1>; 3047 ranges; 3048 3049 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 3050 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 3051 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 3052 3053 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 3054 <&gcc GCC_USB30_MASTER_CLK>, 3055 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 3056 <&gcc GCC_USB30_SLEEP_CLK>, 3057 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 3058 clock-names = "cfg_noc", 3059 "core", 3060 "iface", 3061 "sleep", 3062 "mock_utmi"; 3063 3064 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 3065 <&gcc GCC_USB30_MASTER_CLK>; 3066 assigned-clock-rates = <19200000>, <120000000>; 3067 3068 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 3069 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 3070 interconnect-names = "usb-ddr", "apps-usb"; 3071 3072 power-domains = <&gcc USB30_GDSC>; 3073 status = "disabled"; 3074 3075 usb3_dwc3: usb@6a00000 { 3076 compatible = "snps,dwc3"; 3077 reg = <0x06a00000 0xcc00>; 3078 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3079 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 3080 phy-names = "usb2-phy", "usb3-phy"; 3081 snps,hird-threshold = /bits/ 8 <0>; 3082 snps,dis_u2_susphy_quirk; 3083 snps,dis_enblslpm_quirk; 3084 snps,is-utmi-l1-suspend; 3085 snps,parkmode-disable-ss-quirk; 3086 tx-fifo-resize; 3087 }; 3088 }; 3089 3090 usb3phy: phy@7410000 { 3091 compatible = "qcom,msm8996-qmp-usb3-phy"; 3092 reg = <0x07410000 0x1c4>; 3093 #address-cells = <1>; 3094 #size-cells = <1>; 3095 ranges; 3096 3097 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3098 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3099 <&gcc GCC_USB3_CLKREF_CLK>; 3100 clock-names = "aux", "cfg_ahb", "ref"; 3101 3102 resets = <&gcc GCC_USB3_PHY_BCR>, 3103 <&gcc GCC_USB3PHY_PHY_BCR>; 3104 reset-names = "phy", "common"; 3105 status = "disabled"; 3106 3107 ssusb_phy_0: phy@7410200 { 3108 reg = <0x07410200 0x200>, 3109 <0x07410400 0x130>, 3110 <0x07410600 0x1a8>; 3111 #phy-cells = <0>; 3112 3113 #clock-cells = <0>; 3114 clock-output-names = "usb3_phy_pipe_clk_src"; 3115 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3116 clock-names = "pipe0"; 3117 }; 3118 }; 3119 3120 hsusb_phy1: phy@7411000 { 3121 compatible = "qcom,msm8996-qusb2-phy"; 3122 reg = <0x07411000 0x180>; 3123 #phy-cells = <0>; 3124 3125 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3126 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3127 clock-names = "cfg_ahb", "ref"; 3128 3129 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3130 nvmem-cells = <&qusb2p_hstx_trim>; 3131 status = "disabled"; 3132 }; 3133 3134 hsusb_phy2: phy@7412000 { 3135 compatible = "qcom,msm8996-qusb2-phy"; 3136 reg = <0x07412000 0x180>; 3137 #phy-cells = <0>; 3138 3139 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3140 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3141 clock-names = "cfg_ahb", "ref"; 3142 3143 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3144 nvmem-cells = <&qusb2s_hstx_trim>; 3145 status = "disabled"; 3146 }; 3147 3148 sdhc1: mmc@7464900 { 3149 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3150 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3151 reg-names = "hc", "core"; 3152 3153 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3155 interrupt-names = "hc_irq", "pwr_irq"; 3156 3157 clock-names = "iface", "core", "xo"; 3158 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3159 <&gcc GCC_SDCC1_APPS_CLK>, 3160 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3161 resets = <&gcc GCC_SDCC1_BCR>; 3162 3163 pinctrl-names = "default", "sleep"; 3164 pinctrl-0 = <&sdc1_state_on>; 3165 pinctrl-1 = <&sdc1_state_off>; 3166 3167 bus-width = <8>; 3168 non-removable; 3169 status = "disabled"; 3170 }; 3171 3172 sdhc2: mmc@74a4900 { 3173 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3174 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3175 reg-names = "hc", "core"; 3176 3177 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3179 interrupt-names = "hc_irq", "pwr_irq"; 3180 3181 clock-names = "iface", "core", "xo"; 3182 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3183 <&gcc GCC_SDCC2_APPS_CLK>, 3184 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3185 resets = <&gcc GCC_SDCC2_BCR>; 3186 3187 pinctrl-names = "default", "sleep"; 3188 pinctrl-0 = <&sdc2_state_on>; 3189 pinctrl-1 = <&sdc2_state_off>; 3190 3191 bus-width = <4>; 3192 status = "disabled"; 3193 }; 3194 3195 blsp1_dma: dma-controller@7544000 { 3196 compatible = "qcom,bam-v1.7.0"; 3197 reg = <0x07544000 0x2b000>; 3198 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3199 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3200 clock-names = "bam_clk"; 3201 qcom,controlled-remotely; 3202 #dma-cells = <1>; 3203 qcom,ee = <0>; 3204 }; 3205 3206 blsp1_uart2: serial@7570000 { 3207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3208 reg = <0x07570000 0x1000>; 3209 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3210 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3211 <&gcc GCC_BLSP1_AHB_CLK>; 3212 clock-names = "core", "iface"; 3213 pinctrl-names = "default", "sleep"; 3214 pinctrl-0 = <&blsp1_uart2_default>; 3215 pinctrl-1 = <&blsp1_uart2_sleep>; 3216 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3217 dma-names = "tx", "rx"; 3218 status = "disabled"; 3219 }; 3220 3221 blsp1_spi1: spi@7575000 { 3222 compatible = "qcom,spi-qup-v2.2.1"; 3223 reg = <0x07575000 0x600>; 3224 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3225 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3226 <&gcc GCC_BLSP1_AHB_CLK>; 3227 clock-names = "core", "iface"; 3228 pinctrl-names = "default", "sleep"; 3229 pinctrl-0 = <&blsp1_spi1_default>; 3230 pinctrl-1 = <&blsp1_spi1_sleep>; 3231 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3232 dma-names = "tx", "rx"; 3233 #address-cells = <1>; 3234 #size-cells = <0>; 3235 status = "disabled"; 3236 }; 3237 3238 blsp1_i2c3: i2c@7577000 { 3239 compatible = "qcom,i2c-qup-v2.2.1"; 3240 reg = <0x07577000 0x1000>; 3241 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3242 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3243 <&gcc GCC_BLSP1_AHB_CLK>; 3244 clock-names = "core", "iface"; 3245 pinctrl-names = "default", "sleep"; 3246 pinctrl-0 = <&blsp1_i2c3_default>; 3247 pinctrl-1 = <&blsp1_i2c3_sleep>; 3248 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3249 dma-names = "tx", "rx"; 3250 #address-cells = <1>; 3251 #size-cells = <0>; 3252 status = "disabled"; 3253 }; 3254 3255 blsp1_i2c6: i2c@757a000 { 3256 compatible = "qcom,i2c-qup-v2.2.1"; 3257 reg = <0x757a000 0x1000>; 3258 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3259 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3260 <&gcc GCC_BLSP1_AHB_CLK>; 3261 clock-names = "core", "iface"; 3262 pinctrl-names = "default", "sleep"; 3263 pinctrl-0 = <&blsp1_i2c6_default>; 3264 pinctrl-1 = <&blsp1_i2c6_sleep>; 3265 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3266 dma-names = "tx", "rx"; 3267 #address-cells = <1>; 3268 #size-cells = <0>; 3269 status = "disabled"; 3270 }; 3271 3272 blsp2_dma: dma-controller@7584000 { 3273 compatible = "qcom,bam-v1.7.0"; 3274 reg = <0x07584000 0x2b000>; 3275 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3276 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3277 clock-names = "bam_clk"; 3278 qcom,controlled-remotely; 3279 #dma-cells = <1>; 3280 qcom,ee = <0>; 3281 }; 3282 3283 blsp2_uart2: serial@75b0000 { 3284 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3285 reg = <0x075b0000 0x1000>; 3286 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3287 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3288 <&gcc GCC_BLSP2_AHB_CLK>; 3289 clock-names = "core", "iface"; 3290 status = "disabled"; 3291 }; 3292 3293 blsp2_uart3: serial@75b1000 { 3294 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3295 reg = <0x075b1000 0x1000>; 3296 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3297 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3298 <&gcc GCC_BLSP2_AHB_CLK>; 3299 clock-names = "core", "iface"; 3300 status = "disabled"; 3301 }; 3302 3303 blsp2_i2c1: i2c@75b5000 { 3304 compatible = "qcom,i2c-qup-v2.2.1"; 3305 reg = <0x075b5000 0x1000>; 3306 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3307 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3308 <&gcc GCC_BLSP2_AHB_CLK>; 3309 clock-names = "core", "iface"; 3310 pinctrl-names = "default", "sleep"; 3311 pinctrl-0 = <&blsp2_i2c1_default>; 3312 pinctrl-1 = <&blsp2_i2c1_sleep>; 3313 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3314 dma-names = "tx", "rx"; 3315 #address-cells = <1>; 3316 #size-cells = <0>; 3317 status = "disabled"; 3318 }; 3319 3320 blsp2_i2c2: i2c@75b6000 { 3321 compatible = "qcom,i2c-qup-v2.2.1"; 3322 reg = <0x075b6000 0x1000>; 3323 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3324 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3325 <&gcc GCC_BLSP2_AHB_CLK>; 3326 clock-names = "core", "iface"; 3327 pinctrl-names = "default", "sleep"; 3328 pinctrl-0 = <&blsp2_i2c2_default>; 3329 pinctrl-1 = <&blsp2_i2c2_sleep>; 3330 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3331 dma-names = "tx", "rx"; 3332 #address-cells = <1>; 3333 #size-cells = <0>; 3334 status = "disabled"; 3335 }; 3336 3337 blsp2_i2c3: i2c@75b7000 { 3338 compatible = "qcom,i2c-qup-v2.2.1"; 3339 reg = <0x075b7000 0x1000>; 3340 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3341 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3342 <&gcc GCC_BLSP2_AHB_CLK>; 3343 clock-names = "core", "iface"; 3344 clock-frequency = <400000>; 3345 pinctrl-names = "default", "sleep"; 3346 pinctrl-0 = <&blsp2_i2c3_default>; 3347 pinctrl-1 = <&blsp2_i2c3_sleep>; 3348 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3349 dma-names = "tx", "rx"; 3350 #address-cells = <1>; 3351 #size-cells = <0>; 3352 status = "disabled"; 3353 }; 3354 3355 blsp2_i2c5: i2c@75b9000 { 3356 compatible = "qcom,i2c-qup-v2.2.1"; 3357 reg = <0x75b9000 0x1000>; 3358 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3359 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3360 <&gcc GCC_BLSP2_AHB_CLK>; 3361 clock-names = "core", "iface"; 3362 pinctrl-names = "default"; 3363 pinctrl-0 = <&blsp2_i2c5_default>; 3364 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3365 dma-names = "tx", "rx"; 3366 #address-cells = <1>; 3367 #size-cells = <0>; 3368 status = "disabled"; 3369 }; 3370 3371 blsp2_i2c6: i2c@75ba000 { 3372 compatible = "qcom,i2c-qup-v2.2.1"; 3373 reg = <0x75ba000 0x1000>; 3374 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3375 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3376 <&gcc GCC_BLSP2_AHB_CLK>; 3377 clock-names = "core", "iface"; 3378 pinctrl-names = "default", "sleep"; 3379 pinctrl-0 = <&blsp2_i2c6_default>; 3380 pinctrl-1 = <&blsp2_i2c6_sleep>; 3381 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3382 dma-names = "tx", "rx"; 3383 #address-cells = <1>; 3384 #size-cells = <0>; 3385 status = "disabled"; 3386 }; 3387 3388 blsp2_spi6: spi@75ba000 { 3389 compatible = "qcom,spi-qup-v2.2.1"; 3390 reg = <0x075ba000 0x600>; 3391 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3392 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3393 <&gcc GCC_BLSP2_AHB_CLK>; 3394 clock-names = "core", "iface"; 3395 pinctrl-names = "default", "sleep"; 3396 pinctrl-0 = <&blsp2_spi6_default>; 3397 pinctrl-1 = <&blsp2_spi6_sleep>; 3398 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3399 dma-names = "tx", "rx"; 3400 #address-cells = <1>; 3401 #size-cells = <0>; 3402 status = "disabled"; 3403 }; 3404 3405 usb2: usb@76f8800 { 3406 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3407 reg = <0x076f8800 0x400>; 3408 #address-cells = <1>; 3409 #size-cells = <1>; 3410 ranges; 3411 3412 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 3413 interrupt-names = "hs_phy_irq"; 3414 3415 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3416 <&gcc GCC_USB20_MASTER_CLK>, 3417 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3418 <&gcc GCC_USB20_SLEEP_CLK>, 3419 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3420 clock-names = "cfg_noc", 3421 "core", 3422 "iface", 3423 "sleep", 3424 "mock_utmi"; 3425 3426 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3427 <&gcc GCC_USB20_MASTER_CLK>; 3428 assigned-clock-rates = <19200000>, <60000000>; 3429 3430 power-domains = <&gcc USB30_GDSC>; 3431 qcom,select-utmi-as-pipe-clk; 3432 status = "disabled"; 3433 3434 usb2_dwc3: usb@7600000 { 3435 compatible = "snps,dwc3"; 3436 reg = <0x07600000 0xcc00>; 3437 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3438 phys = <&hsusb_phy2>; 3439 phy-names = "usb2-phy"; 3440 maximum-speed = "high-speed"; 3441 snps,dis_u2_susphy_quirk; 3442 snps,dis_enblslpm_quirk; 3443 }; 3444 }; 3445 3446 slimbam: dma-controller@9184000 { 3447 compatible = "qcom,bam-v1.7.0"; 3448 qcom,controlled-remotely; 3449 reg = <0x09184000 0x32000>; 3450 num-channels = <31>; 3451 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3452 #dma-cells = <1>; 3453 qcom,ee = <1>; 3454 qcom,num-ees = <2>; 3455 }; 3456 3457 slim_msm: slim-ngd@91c0000 { 3458 compatible = "qcom,slim-ngd-v1.5.0"; 3459 reg = <0x091c0000 0x2c000>; 3460 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3461 dmas = <&slimbam 3>, <&slimbam 4>; 3462 dma-names = "rx", "tx"; 3463 #address-cells = <1>; 3464 #size-cells = <0>; 3465 3466 status = "disabled"; 3467 }; 3468 3469 adsp_pil: remoteproc@9300000 { 3470 compatible = "qcom,msm8996-adsp-pil"; 3471 reg = <0x09300000 0x80000>; 3472 3473 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3474 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3475 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3476 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3477 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3478 interrupt-names = "wdog", "fatal", "ready", 3479 "handover", "stop-ack"; 3480 3481 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3482 clock-names = "xo"; 3483 3484 memory-region = <&adsp_mem>; 3485 3486 qcom,smem-states = <&adsp_smp2p_out 0>; 3487 qcom,smem-state-names = "stop"; 3488 3489 power-domains = <&rpmpd MSM8996_VDDCX>; 3490 power-domain-names = "cx"; 3491 3492 status = "disabled"; 3493 3494 smd-edge { 3495 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3496 3497 label = "lpass"; 3498 mboxes = <&apcs_glb 8>; 3499 qcom,smd-edge = <1>; 3500 qcom,remote-pid = <2>; 3501 3502 apr { 3503 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3504 compatible = "qcom,apr-v2"; 3505 qcom,smd-channels = "apr_audio_svc"; 3506 qcom,domain = <APR_DOMAIN_ADSP>; 3507 #address-cells = <1>; 3508 #size-cells = <0>; 3509 3510 service@3 { 3511 reg = <APR_SVC_ADSP_CORE>; 3512 compatible = "qcom,q6core"; 3513 }; 3514 3515 q6afe: service@4 { 3516 compatible = "qcom,q6afe"; 3517 reg = <APR_SVC_AFE>; 3518 q6afedai: dais { 3519 compatible = "qcom,q6afe-dais"; 3520 #address-cells = <1>; 3521 #size-cells = <0>; 3522 #sound-dai-cells = <1>; 3523 dai@1 { 3524 reg = <1>; 3525 }; 3526 }; 3527 }; 3528 3529 q6asm: service@7 { 3530 compatible = "qcom,q6asm"; 3531 reg = <APR_SVC_ASM>; 3532 q6asmdai: dais { 3533 compatible = "qcom,q6asm-dais"; 3534 #address-cells = <1>; 3535 #size-cells = <0>; 3536 #sound-dai-cells = <1>; 3537 iommus = <&lpass_q6_smmu 1>; 3538 }; 3539 }; 3540 3541 q6adm: service@8 { 3542 compatible = "qcom,q6adm"; 3543 reg = <APR_SVC_ADM>; 3544 q6routing: routing { 3545 compatible = "qcom,q6adm-routing"; 3546 #sound-dai-cells = <0>; 3547 }; 3548 }; 3549 }; 3550 }; 3551 }; 3552 3553 apcs_glb: mailbox@9820000 { 3554 compatible = "qcom,msm8996-apcs-hmss-global"; 3555 reg = <0x09820000 0x1000>; 3556 3557 #mbox-cells = <1>; 3558 #clock-cells = <0>; 3559 }; 3560 3561 timer@9840000 { 3562 #address-cells = <1>; 3563 #size-cells = <1>; 3564 ranges; 3565 compatible = "arm,armv7-timer-mem"; 3566 reg = <0x09840000 0x1000>; 3567 clock-frequency = <19200000>; 3568 3569 frame@9850000 { 3570 frame-number = <0>; 3571 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3573 reg = <0x09850000 0x1000>, 3574 <0x09860000 0x1000>; 3575 }; 3576 3577 frame@9870000 { 3578 frame-number = <1>; 3579 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3580 reg = <0x09870000 0x1000>; 3581 status = "disabled"; 3582 }; 3583 3584 frame@9880000 { 3585 frame-number = <2>; 3586 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3587 reg = <0x09880000 0x1000>; 3588 status = "disabled"; 3589 }; 3590 3591 frame@9890000 { 3592 frame-number = <3>; 3593 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3594 reg = <0x09890000 0x1000>; 3595 status = "disabled"; 3596 }; 3597 3598 frame@98a0000 { 3599 frame-number = <4>; 3600 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3601 reg = <0x098a0000 0x1000>; 3602 status = "disabled"; 3603 }; 3604 3605 frame@98b0000 { 3606 frame-number = <5>; 3607 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3608 reg = <0x098b0000 0x1000>; 3609 status = "disabled"; 3610 }; 3611 3612 frame@98c0000 { 3613 frame-number = <6>; 3614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3615 reg = <0x098c0000 0x1000>; 3616 status = "disabled"; 3617 }; 3618 }; 3619 3620 saw3: syscon@9a10000 { 3621 compatible = "syscon"; 3622 reg = <0x09a10000 0x1000>; 3623 }; 3624 3625 cbf: clock-controller@9a11000 { 3626 compatible = "qcom,msm8996-cbf"; 3627 reg = <0x09a11000 0x10000>; 3628 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3629 #clock-cells = <0>; 3630 #interconnect-cells = <1>; 3631 }; 3632 3633 intc: interrupt-controller@9bc0000 { 3634 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3635 #interrupt-cells = <3>; 3636 interrupt-controller; 3637 #redistributor-regions = <1>; 3638 redistributor-stride = <0x0 0x40000>; 3639 reg = <0x09bc0000 0x10000>, 3640 <0x09c00000 0x100000>; 3641 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3642 }; 3643 }; 3644 3645 sound: sound { 3646 }; 3647 3648 thermal-zones { 3649 cpu0-thermal { 3650 polling-delay-passive = <250>; 3651 polling-delay = <1000>; 3652 3653 thermal-sensors = <&tsens0 3>; 3654 3655 trips { 3656 cpu0_alert0: trip-point0 { 3657 temperature = <75000>; 3658 hysteresis = <2000>; 3659 type = "passive"; 3660 }; 3661 3662 cpu0_crit: cpu-crit { 3663 temperature = <110000>; 3664 hysteresis = <2000>; 3665 type = "critical"; 3666 }; 3667 }; 3668 }; 3669 3670 cpu1-thermal { 3671 polling-delay-passive = <250>; 3672 polling-delay = <1000>; 3673 3674 thermal-sensors = <&tsens0 5>; 3675 3676 trips { 3677 cpu1_alert0: trip-point0 { 3678 temperature = <75000>; 3679 hysteresis = <2000>; 3680 type = "passive"; 3681 }; 3682 3683 cpu1_crit: cpu-crit { 3684 temperature = <110000>; 3685 hysteresis = <2000>; 3686 type = "critical"; 3687 }; 3688 }; 3689 }; 3690 3691 cpu2-thermal { 3692 polling-delay-passive = <250>; 3693 polling-delay = <1000>; 3694 3695 thermal-sensors = <&tsens0 8>; 3696 3697 trips { 3698 cpu2_alert0: trip-point0 { 3699 temperature = <75000>; 3700 hysteresis = <2000>; 3701 type = "passive"; 3702 }; 3703 3704 cpu2_crit: cpu-crit { 3705 temperature = <110000>; 3706 hysteresis = <2000>; 3707 type = "critical"; 3708 }; 3709 }; 3710 }; 3711 3712 cpu3-thermal { 3713 polling-delay-passive = <250>; 3714 polling-delay = <1000>; 3715 3716 thermal-sensors = <&tsens0 10>; 3717 3718 trips { 3719 cpu3_alert0: trip-point0 { 3720 temperature = <75000>; 3721 hysteresis = <2000>; 3722 type = "passive"; 3723 }; 3724 3725 cpu3_crit: cpu-crit { 3726 temperature = <110000>; 3727 hysteresis = <2000>; 3728 type = "critical"; 3729 }; 3730 }; 3731 }; 3732 3733 gpu-top-thermal { 3734 polling-delay-passive = <250>; 3735 polling-delay = <1000>; 3736 3737 thermal-sensors = <&tsens1 6>; 3738 3739 trips { 3740 gpu1_alert0: trip-point0 { 3741 temperature = <90000>; 3742 hysteresis = <2000>; 3743 type = "passive"; 3744 }; 3745 }; 3746 3747 cooling-maps { 3748 map0 { 3749 trip = <&gpu1_alert0>; 3750 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3751 }; 3752 }; 3753 }; 3754 3755 gpu-bottom-thermal { 3756 polling-delay-passive = <250>; 3757 polling-delay = <1000>; 3758 3759 thermal-sensors = <&tsens1 7>; 3760 3761 trips { 3762 gpu2_alert0: trip-point0 { 3763 temperature = <90000>; 3764 hysteresis = <2000>; 3765 type = "passive"; 3766 }; 3767 }; 3768 3769 cooling-maps { 3770 map0 { 3771 trip = <&gpu2_alert0>; 3772 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3773 }; 3774 }; 3775 }; 3776 3777 m4m-thermal { 3778 polling-delay-passive = <250>; 3779 polling-delay = <1000>; 3780 3781 thermal-sensors = <&tsens0 1>; 3782 3783 trips { 3784 m4m_alert0: trip-point0 { 3785 temperature = <90000>; 3786 hysteresis = <2000>; 3787 type = "hot"; 3788 }; 3789 }; 3790 }; 3791 3792 l3-or-venus-thermal { 3793 polling-delay-passive = <250>; 3794 polling-delay = <1000>; 3795 3796 thermal-sensors = <&tsens0 2>; 3797 3798 trips { 3799 l3_or_venus_alert0: trip-point0 { 3800 temperature = <90000>; 3801 hysteresis = <2000>; 3802 type = "hot"; 3803 }; 3804 }; 3805 }; 3806 3807 cluster0-l2-thermal { 3808 polling-delay-passive = <250>; 3809 polling-delay = <1000>; 3810 3811 thermal-sensors = <&tsens0 7>; 3812 3813 trips { 3814 cluster0_l2_alert0: trip-point0 { 3815 temperature = <90000>; 3816 hysteresis = <2000>; 3817 type = "hot"; 3818 }; 3819 }; 3820 }; 3821 3822 cluster1-l2-thermal { 3823 polling-delay-passive = <250>; 3824 polling-delay = <1000>; 3825 3826 thermal-sensors = <&tsens0 12>; 3827 3828 trips { 3829 cluster1_l2_alert0: trip-point0 { 3830 temperature = <90000>; 3831 hysteresis = <2000>; 3832 type = "hot"; 3833 }; 3834 }; 3835 }; 3836 3837 camera-thermal { 3838 polling-delay-passive = <250>; 3839 polling-delay = <1000>; 3840 3841 thermal-sensors = <&tsens1 1>; 3842 3843 trips { 3844 camera_alert0: trip-point0 { 3845 temperature = <90000>; 3846 hysteresis = <2000>; 3847 type = "hot"; 3848 }; 3849 }; 3850 }; 3851 3852 q6-dsp-thermal { 3853 polling-delay-passive = <250>; 3854 polling-delay = <1000>; 3855 3856 thermal-sensors = <&tsens1 2>; 3857 3858 trips { 3859 q6_dsp_alert0: trip-point0 { 3860 temperature = <90000>; 3861 hysteresis = <2000>; 3862 type = "hot"; 3863 }; 3864 }; 3865 }; 3866 3867 mem-thermal { 3868 polling-delay-passive = <250>; 3869 polling-delay = <1000>; 3870 3871 thermal-sensors = <&tsens1 3>; 3872 3873 trips { 3874 mem_alert0: trip-point0 { 3875 temperature = <90000>; 3876 hysteresis = <2000>; 3877 type = "hot"; 3878 }; 3879 }; 3880 }; 3881 3882 modemtx-thermal { 3883 polling-delay-passive = <250>; 3884 polling-delay = <1000>; 3885 3886 thermal-sensors = <&tsens1 4>; 3887 3888 trips { 3889 modemtx_alert0: trip-point0 { 3890 temperature = <90000>; 3891 hysteresis = <2000>; 3892 type = "hot"; 3893 }; 3894 }; 3895 }; 3896 }; 3897 3898 timer { 3899 compatible = "arm,armv8-timer"; 3900 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3901 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3902 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3903 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3904 }; 3905}; 3906