1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,apr.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 cpu-idle-states = <&CPU_SLEEP_0>; 50 capacity-dmips-mhz = <1024>; 51 clocks = <&kryocc 0>; 52 operating-points-v2 = <&cluster0_opp>; 53 #cooling-cells = <2>; 54 next-level-cache = <&L2_0>; 55 L2_0: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 }; 59 }; 60 61 CPU1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "qcom,kryo"; 64 reg = <0x0 0x1>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 capacity-dmips-mhz = <1024>; 68 clocks = <&kryocc 0>; 69 operating-points-v2 = <&cluster0_opp>; 70 #cooling-cells = <2>; 71 next-level-cache = <&L2_0>; 72 }; 73 74 CPU2: cpu@100 { 75 device_type = "cpu"; 76 compatible = "qcom,kryo"; 77 reg = <0x0 0x100>; 78 enable-method = "psci"; 79 cpu-idle-states = <&CPU_SLEEP_0>; 80 capacity-dmips-mhz = <1024>; 81 clocks = <&kryocc 1>; 82 operating-points-v2 = <&cluster1_opp>; 83 #cooling-cells = <2>; 84 next-level-cache = <&L2_1>; 85 L2_1: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 }; 89 }; 90 91 CPU3: cpu@101 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo"; 94 reg = <0x0 0x101>; 95 enable-method = "psci"; 96 cpu-idle-states = <&CPU_SLEEP_0>; 97 capacity-dmips-mhz = <1024>; 98 clocks = <&kryocc 1>; 99 operating-points-v2 = <&cluster1_opp>; 100 #cooling-cells = <2>; 101 next-level-cache = <&L2_1>; 102 }; 103 104 cpu-map { 105 cluster0 { 106 core0 { 107 cpu = <&CPU0>; 108 }; 109 110 core1 { 111 cpu = <&CPU1>; 112 }; 113 }; 114 115 cluster1 { 116 core0 { 117 cpu = <&CPU2>; 118 }; 119 120 core1 { 121 cpu = <&CPU3>; 122 }; 123 }; 124 }; 125 126 idle-states { 127 entry-method = "psci"; 128 129 CPU_SLEEP_0: cpu-sleep-0 { 130 compatible = "arm,idle-state"; 131 idle-state-name = "standalone-power-collapse"; 132 arm,psci-suspend-param = <0x00000004>; 133 entry-latency-us = <130>; 134 exit-latency-us = <80>; 135 min-residency-us = <300>; 136 }; 137 }; 138 }; 139 140 cluster0_opp: opp-table-cluster0 { 141 compatible = "operating-points-v2-kryo-cpu"; 142 nvmem-cells = <&speedbin_efuse>; 143 opp-shared; 144 145 /* Nominal fmax for now */ 146 opp-307200000 { 147 opp-hz = /bits/ 64 <307200000>; 148 opp-supported-hw = <0xf>; 149 clock-latency-ns = <200000>; 150 }; 151 opp-422400000 { 152 opp-hz = /bits/ 64 <422400000>; 153 opp-supported-hw = <0xf>; 154 clock-latency-ns = <200000>; 155 }; 156 opp-480000000 { 157 opp-hz = /bits/ 64 <480000000>; 158 opp-supported-hw = <0xf>; 159 clock-latency-ns = <200000>; 160 }; 161 opp-556800000 { 162 opp-hz = /bits/ 64 <556800000>; 163 opp-supported-hw = <0xf>; 164 clock-latency-ns = <200000>; 165 }; 166 opp-652800000 { 167 opp-hz = /bits/ 64 <652800000>; 168 opp-supported-hw = <0xf>; 169 clock-latency-ns = <200000>; 170 }; 171 opp-729600000 { 172 opp-hz = /bits/ 64 <729600000>; 173 opp-supported-hw = <0xf>; 174 clock-latency-ns = <200000>; 175 }; 176 opp-844800000 { 177 opp-hz = /bits/ 64 <844800000>; 178 opp-supported-hw = <0xf>; 179 clock-latency-ns = <200000>; 180 }; 181 opp-960000000 { 182 opp-hz = /bits/ 64 <960000000>; 183 opp-supported-hw = <0xf>; 184 clock-latency-ns = <200000>; 185 }; 186 opp-1036800000 { 187 opp-hz = /bits/ 64 <1036800000>; 188 opp-supported-hw = <0xf>; 189 clock-latency-ns = <200000>; 190 }; 191 opp-1113600000 { 192 opp-hz = /bits/ 64 <1113600000>; 193 opp-supported-hw = <0xf>; 194 clock-latency-ns = <200000>; 195 }; 196 opp-1190400000 { 197 opp-hz = /bits/ 64 <1190400000>; 198 opp-supported-hw = <0xf>; 199 clock-latency-ns = <200000>; 200 }; 201 opp-1228800000 { 202 opp-hz = /bits/ 64 <1228800000>; 203 opp-supported-hw = <0xf>; 204 clock-latency-ns = <200000>; 205 }; 206 opp-1324800000 { 207 opp-hz = /bits/ 64 <1324800000>; 208 opp-supported-hw = <0xd>; 209 clock-latency-ns = <200000>; 210 }; 211 opp-1363200000 { 212 opp-hz = /bits/ 64 <1363200000>; 213 opp-supported-hw = <0x2>; 214 clock-latency-ns = <200000>; 215 }; 216 opp-1401600000 { 217 opp-hz = /bits/ 64 <1401600000>; 218 opp-supported-hw = <0xd>; 219 clock-latency-ns = <200000>; 220 }; 221 opp-1478400000 { 222 opp-hz = /bits/ 64 <1478400000>; 223 opp-supported-hw = <0x9>; 224 clock-latency-ns = <200000>; 225 }; 226 opp-1497600000 { 227 opp-hz = /bits/ 64 <1497600000>; 228 opp-supported-hw = <0x04>; 229 clock-latency-ns = <200000>; 230 }; 231 opp-1593600000 { 232 opp-hz = /bits/ 64 <1593600000>; 233 opp-supported-hw = <0x9>; 234 clock-latency-ns = <200000>; 235 }; 236 }; 237 238 cluster1_opp: opp-table-cluster1 { 239 compatible = "operating-points-v2-kryo-cpu"; 240 nvmem-cells = <&speedbin_efuse>; 241 opp-shared; 242 243 /* Nominal fmax for now */ 244 opp-307200000 { 245 opp-hz = /bits/ 64 <307200000>; 246 opp-supported-hw = <0xf>; 247 clock-latency-ns = <200000>; 248 }; 249 opp-403200000 { 250 opp-hz = /bits/ 64 <403200000>; 251 opp-supported-hw = <0xf>; 252 clock-latency-ns = <200000>; 253 }; 254 opp-480000000 { 255 opp-hz = /bits/ 64 <480000000>; 256 opp-supported-hw = <0xf>; 257 clock-latency-ns = <200000>; 258 }; 259 opp-556800000 { 260 opp-hz = /bits/ 64 <556800000>; 261 opp-supported-hw = <0xf>; 262 clock-latency-ns = <200000>; 263 }; 264 opp-652800000 { 265 opp-hz = /bits/ 64 <652800000>; 266 opp-supported-hw = <0xf>; 267 clock-latency-ns = <200000>; 268 }; 269 opp-729600000 { 270 opp-hz = /bits/ 64 <729600000>; 271 opp-supported-hw = <0xf>; 272 clock-latency-ns = <200000>; 273 }; 274 opp-806400000 { 275 opp-hz = /bits/ 64 <806400000>; 276 opp-supported-hw = <0xf>; 277 clock-latency-ns = <200000>; 278 }; 279 opp-883200000 { 280 opp-hz = /bits/ 64 <883200000>; 281 opp-supported-hw = <0xf>; 282 clock-latency-ns = <200000>; 283 }; 284 opp-940800000 { 285 opp-hz = /bits/ 64 <940800000>; 286 opp-supported-hw = <0xf>; 287 clock-latency-ns = <200000>; 288 }; 289 opp-1036800000 { 290 opp-hz = /bits/ 64 <1036800000>; 291 opp-supported-hw = <0xf>; 292 clock-latency-ns = <200000>; 293 }; 294 opp-1113600000 { 295 opp-hz = /bits/ 64 <1113600000>; 296 opp-supported-hw = <0xf>; 297 clock-latency-ns = <200000>; 298 }; 299 opp-1190400000 { 300 opp-hz = /bits/ 64 <1190400000>; 301 opp-supported-hw = <0xf>; 302 clock-latency-ns = <200000>; 303 }; 304 opp-1248000000 { 305 opp-hz = /bits/ 64 <1248000000>; 306 opp-supported-hw = <0xf>; 307 clock-latency-ns = <200000>; 308 }; 309 opp-1324800000 { 310 opp-hz = /bits/ 64 <1324800000>; 311 opp-supported-hw = <0xf>; 312 clock-latency-ns = <200000>; 313 }; 314 opp-1401600000 { 315 opp-hz = /bits/ 64 <1401600000>; 316 opp-supported-hw = <0xf>; 317 clock-latency-ns = <200000>; 318 }; 319 opp-1478400000 { 320 opp-hz = /bits/ 64 <1478400000>; 321 opp-supported-hw = <0xf>; 322 clock-latency-ns = <200000>; 323 }; 324 opp-1555200000 { 325 opp-hz = /bits/ 64 <1555200000>; 326 opp-supported-hw = <0xf>; 327 clock-latency-ns = <200000>; 328 }; 329 opp-1632000000 { 330 opp-hz = /bits/ 64 <1632000000>; 331 opp-supported-hw = <0xf>; 332 clock-latency-ns = <200000>; 333 }; 334 opp-1708800000 { 335 opp-hz = /bits/ 64 <1708800000>; 336 opp-supported-hw = <0xf>; 337 clock-latency-ns = <200000>; 338 }; 339 opp-1785600000 { 340 opp-hz = /bits/ 64 <1785600000>; 341 opp-supported-hw = <0xf>; 342 clock-latency-ns = <200000>; 343 }; 344 opp-1804800000 { 345 opp-hz = /bits/ 64 <1804800000>; 346 opp-supported-hw = <0xe>; 347 clock-latency-ns = <200000>; 348 }; 349 opp-1824000000 { 350 opp-hz = /bits/ 64 <1824000000>; 351 opp-supported-hw = <0x1>; 352 clock-latency-ns = <200000>; 353 }; 354 opp-1900800000 { 355 opp-hz = /bits/ 64 <1900800000>; 356 opp-supported-hw = <0x4>; 357 clock-latency-ns = <200000>; 358 }; 359 opp-1920000000 { 360 opp-hz = /bits/ 64 <1920000000>; 361 opp-supported-hw = <0x1>; 362 clock-latency-ns = <200000>; 363 }; 364 opp-1996800000 { 365 opp-hz = /bits/ 64 <1996800000>; 366 opp-supported-hw = <0x1>; 367 clock-latency-ns = <200000>; 368 }; 369 opp-2073600000 { 370 opp-hz = /bits/ 64 <2073600000>; 371 opp-supported-hw = <0x1>; 372 clock-latency-ns = <200000>; 373 }; 374 opp-2150400000 { 375 opp-hz = /bits/ 64 <2150400000>; 376 opp-supported-hw = <0x1>; 377 clock-latency-ns = <200000>; 378 }; 379 }; 380 381 firmware { 382 scm { 383 compatible = "qcom,scm-msm8996", "qcom,scm"; 384 qcom,dload-mode = <&tcsr_2 0x13000>; 385 }; 386 }; 387 388 memory@80000000 { 389 device_type = "memory"; 390 /* We expect the bootloader to fill in the reg */ 391 reg = <0x0 0x80000000 0x0 0x0>; 392 }; 393 394 psci { 395 compatible = "arm,psci-1.0"; 396 method = "smc"; 397 }; 398 399 reserved-memory { 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 404 hyp_mem: memory@85800000 { 405 reg = <0x0 0x85800000 0x0 0x600000>; 406 no-map; 407 }; 408 409 xbl_mem: memory@85e00000 { 410 reg = <0x0 0x85e00000 0x0 0x200000>; 411 no-map; 412 }; 413 414 smem_mem: smem-mem@86000000 { 415 reg = <0x0 0x86000000 0x0 0x200000>; 416 no-map; 417 }; 418 419 tz_mem: memory@86200000 { 420 reg = <0x0 0x86200000 0x0 0x2600000>; 421 no-map; 422 }; 423 424 rmtfs_mem: rmtfs { 425 compatible = "qcom,rmtfs-mem"; 426 427 size = <0x0 0x200000>; 428 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 429 no-map; 430 431 qcom,client-id = <1>; 432 qcom,vmid = <15>; 433 }; 434 435 mpss_mem: mpss@88800000 { 436 reg = <0x0 0x88800000 0x0 0x6200000>; 437 no-map; 438 }; 439 440 adsp_mem: adsp@8ea00000 { 441 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 442 no-map; 443 }; 444 445 slpi_mem: slpi@90500000 { 446 reg = <0x0 0x90500000 0x0 0xa00000>; 447 no-map; 448 }; 449 450 gpu_mem: gpu@90f00000 { 451 compatible = "shared-dma-pool"; 452 reg = <0x0 0x90f00000 0x0 0x100000>; 453 no-map; 454 }; 455 456 venus_mem: venus@91000000 { 457 reg = <0x0 0x91000000 0x0 0x500000>; 458 no-map; 459 }; 460 461 mba_mem: mba@91500000 { 462 reg = <0x0 0x91500000 0x0 0x200000>; 463 no-map; 464 }; 465 466 mdata_mem: mpss-metadata { 467 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 468 size = <0x0 0x4000>; 469 no-map; 470 }; 471 }; 472 473 rpm-glink { 474 compatible = "qcom,glink-rpm"; 475 476 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 477 478 qcom,rpm-msg-ram = <&rpm_msg_ram>; 479 480 mboxes = <&apcs_glb 0>; 481 482 rpm_requests: rpm-requests { 483 compatible = "qcom,rpm-msm8996"; 484 qcom,glink-channels = "rpm_requests"; 485 486 rpmcc: clock-controller { 487 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 488 #clock-cells = <1>; 489 clocks = <&xo_board>; 490 clock-names = "xo"; 491 }; 492 493 rpmpd: power-controller { 494 compatible = "qcom,msm8996-rpmpd"; 495 #power-domain-cells = <1>; 496 operating-points-v2 = <&rpmpd_opp_table>; 497 498 rpmpd_opp_table: opp-table { 499 compatible = "operating-points-v2"; 500 501 rpmpd_opp1: opp1 { 502 opp-level = <1>; 503 }; 504 505 rpmpd_opp2: opp2 { 506 opp-level = <2>; 507 }; 508 509 rpmpd_opp3: opp3 { 510 opp-level = <3>; 511 }; 512 513 rpmpd_opp4: opp4 { 514 opp-level = <4>; 515 }; 516 517 rpmpd_opp5: opp5 { 518 opp-level = <5>; 519 }; 520 521 rpmpd_opp6: opp6 { 522 opp-level = <6>; 523 }; 524 }; 525 }; 526 }; 527 }; 528 529 smem { 530 compatible = "qcom,smem"; 531 memory-region = <&smem_mem>; 532 hwlocks = <&tcsr_mutex 3>; 533 }; 534 535 smp2p-adsp { 536 compatible = "qcom,smp2p"; 537 qcom,smem = <443>, <429>; 538 539 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 540 541 mboxes = <&apcs_glb 10>; 542 543 qcom,local-pid = <0>; 544 qcom,remote-pid = <2>; 545 546 adsp_smp2p_out: master-kernel { 547 qcom,entry-name = "master-kernel"; 548 #qcom,smem-state-cells = <1>; 549 }; 550 551 adsp_smp2p_in: slave-kernel { 552 qcom,entry-name = "slave-kernel"; 553 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 }; 557 }; 558 559 smp2p-mpss { 560 compatible = "qcom,smp2p"; 561 qcom,smem = <435>, <428>; 562 563 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 564 565 mboxes = <&apcs_glb 14>; 566 567 qcom,local-pid = <0>; 568 qcom,remote-pid = <1>; 569 570 mpss_smp2p_out: master-kernel { 571 qcom,entry-name = "master-kernel"; 572 #qcom,smem-state-cells = <1>; 573 }; 574 575 mpss_smp2p_in: slave-kernel { 576 qcom,entry-name = "slave-kernel"; 577 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 }; 581 }; 582 583 smp2p-slpi { 584 compatible = "qcom,smp2p"; 585 qcom,smem = <481>, <430>; 586 587 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 588 589 mboxes = <&apcs_glb 26>; 590 591 qcom,local-pid = <0>; 592 qcom,remote-pid = <3>; 593 594 slpi_smp2p_out: master-kernel { 595 qcom,entry-name = "master-kernel"; 596 #qcom,smem-state-cells = <1>; 597 }; 598 599 slpi_smp2p_in: slave-kernel { 600 qcom,entry-name = "slave-kernel"; 601 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 }; 606 607 soc: soc { 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0 0 0 0xffffffff>; 611 compatible = "simple-bus"; 612 613 pcie_phy: phy-wrapper@34000 { 614 compatible = "qcom,msm8996-qmp-pcie-phy"; 615 reg = <0x00034000 0x488>; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0x0 0x00034000 0x4000>; 619 620 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 621 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 622 <&gcc GCC_PCIE_CLKREF_CLK>; 623 clock-names = "aux", "cfg_ahb", "ref"; 624 625 resets = <&gcc GCC_PCIE_PHY_BCR>, 626 <&gcc GCC_PCIE_PHY_COM_BCR>, 627 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 628 reset-names = "phy", "common", "cfg"; 629 630 status = "disabled"; 631 632 pciephy_0: phy@1000 { 633 reg = <0x1000 0x130>, 634 <0x1200 0x200>, 635 <0x1400 0x1dc>; 636 637 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 638 clock-names = "pipe0"; 639 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 640 reset-names = "lane0"; 641 642 #clock-cells = <0>; 643 clock-output-names = "pcie_0_pipe_clk_src"; 644 645 #phy-cells = <0>; 646 }; 647 648 pciephy_1: phy@2000 { 649 reg = <0x2000 0x130>, 650 <0x2200 0x200>, 651 <0x2400 0x1dc>; 652 653 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 654 clock-names = "pipe1"; 655 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 656 reset-names = "lane1"; 657 658 #clock-cells = <0>; 659 clock-output-names = "pcie_1_pipe_clk_src"; 660 661 #phy-cells = <0>; 662 }; 663 664 pciephy_2: phy@3000 { 665 reg = <0x3000 0x130>, 666 <0x3200 0x200>, 667 <0x3400 0x1dc>; 668 669 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 670 clock-names = "pipe2"; 671 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 672 reset-names = "lane2"; 673 674 #clock-cells = <0>; 675 clock-output-names = "pcie_2_pipe_clk_src"; 676 677 #phy-cells = <0>; 678 }; 679 }; 680 681 rpm_msg_ram: sram@68000 { 682 compatible = "qcom,rpm-msg-ram"; 683 reg = <0x00068000 0x6000>; 684 }; 685 686 qfprom@74000 { 687 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 688 reg = <0x00074000 0x8ff>; 689 #address-cells = <1>; 690 #size-cells = <1>; 691 692 qusb2p_hstx_trim: hstx_trim@24e { 693 reg = <0x24e 0x2>; 694 bits = <5 4>; 695 }; 696 697 qusb2s_hstx_trim: hstx_trim@24f { 698 reg = <0x24f 0x1>; 699 bits = <1 4>; 700 }; 701 702 speedbin_efuse: speedbin@133 { 703 reg = <0x133 0x1>; 704 bits = <5 3>; 705 }; 706 }; 707 708 rng: rng@83000 { 709 compatible = "qcom,prng-ee"; 710 reg = <0x00083000 0x1000>; 711 clocks = <&gcc GCC_PRNG_AHB_CLK>; 712 clock-names = "core"; 713 }; 714 715 gcc: clock-controller@300000 { 716 compatible = "qcom,gcc-msm8996"; 717 #clock-cells = <1>; 718 #reset-cells = <1>; 719 #power-domain-cells = <1>; 720 reg = <0x00300000 0x90000>; 721 722 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 723 <&rpmcc RPM_SMD_LN_BB_CLK>, 724 <&sleep_clk>, 725 <&pciephy_0>, 726 <&pciephy_1>, 727 <&pciephy_2>, 728 <&ssusb_phy_0>, 729 <&ufsphy_lane 0>, 730 <&ufsphy_lane 1>, 731 <&ufsphy_lane 2>; 732 clock-names = "cxo", 733 "cxo2", 734 "sleep_clk", 735 "pcie_0_pipe_clk_src", 736 "pcie_1_pipe_clk_src", 737 "pcie_2_pipe_clk_src", 738 "usb3_phy_pipe_clk_src", 739 "ufs_rx_symbol_0_clk_src", 740 "ufs_rx_symbol_1_clk_src", 741 "ufs_tx_symbol_0_clk_src"; 742 }; 743 744 bimc: interconnect@408000 { 745 compatible = "qcom,msm8996-bimc"; 746 reg = <0x00408000 0x5a000>; 747 #interconnect-cells = <1>; 748 clock-names = "bus", "bus_a"; 749 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 750 <&rpmcc RPM_SMD_BIMC_A_CLK>; 751 }; 752 753 tsens0: thermal-sensor@4a9000 { 754 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 755 reg = <0x004a9000 0x1000>, /* TM */ 756 <0x004a8000 0x1000>; /* SROT */ 757 #qcom,sensors = <13>; 758 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 760 interrupt-names = "uplow", "critical"; 761 #thermal-sensor-cells = <1>; 762 }; 763 764 tsens1: thermal-sensor@4ad000 { 765 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 766 reg = <0x004ad000 0x1000>, /* TM */ 767 <0x004ac000 0x1000>; /* SROT */ 768 #qcom,sensors = <8>; 769 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 771 interrupt-names = "uplow", "critical"; 772 #thermal-sensor-cells = <1>; 773 }; 774 775 cryptobam: dma-controller@644000 { 776 compatible = "qcom,bam-v1.7.0"; 777 reg = <0x00644000 0x24000>; 778 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&gcc GCC_CE1_CLK>; 780 clock-names = "bam_clk"; 781 #dma-cells = <1>; 782 qcom,ee = <0>; 783 qcom,controlled-remotely; 784 }; 785 786 crypto: crypto@67a000 { 787 compatible = "qcom,crypto-v5.4"; 788 reg = <0x0067a000 0x6000>; 789 clocks = <&gcc GCC_CE1_AHB_CLK>, 790 <&gcc GCC_CE1_AXI_CLK>, 791 <&gcc GCC_CE1_CLK>; 792 clock-names = "iface", "bus", "core"; 793 dmas = <&cryptobam 6>, <&cryptobam 7>; 794 dma-names = "rx", "tx"; 795 }; 796 797 cnoc: interconnect@500000 { 798 compatible = "qcom,msm8996-cnoc"; 799 reg = <0x00500000 0x1000>; 800 #interconnect-cells = <1>; 801 clock-names = "bus", "bus_a"; 802 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 803 <&rpmcc RPM_SMD_CNOC_A_CLK>; 804 }; 805 806 snoc: interconnect@524000 { 807 compatible = "qcom,msm8996-snoc"; 808 reg = <0x00524000 0x1c000>; 809 #interconnect-cells = <1>; 810 clock-names = "bus", "bus_a"; 811 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 812 <&rpmcc RPM_SMD_SNOC_A_CLK>; 813 }; 814 815 a0noc: interconnect@543000 { 816 compatible = "qcom,msm8996-a0noc"; 817 reg = <0x00543000 0x6000>; 818 #interconnect-cells = <1>; 819 clock-names = "aggre0_snoc_axi", 820 "aggre0_cnoc_ahb", 821 "aggre0_noc_mpu_cfg"; 822 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 823 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 824 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 825 power-domains = <&gcc AGGRE0_NOC_GDSC>; 826 }; 827 828 a1noc: interconnect@562000 { 829 compatible = "qcom,msm8996-a1noc"; 830 reg = <0x00562000 0x5000>; 831 #interconnect-cells = <1>; 832 clock-names = "bus", "bus_a"; 833 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 834 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 835 }; 836 837 a2noc: interconnect@583000 { 838 compatible = "qcom,msm8996-a2noc"; 839 reg = <0x00583000 0x7000>; 840 #interconnect-cells = <1>; 841 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; 842 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 843 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 844 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 845 <&gcc GCC_UFS_AXI_CLK>; 846 }; 847 848 mnoc: interconnect@5a4000 { 849 compatible = "qcom,msm8996-mnoc"; 850 reg = <0x005a4000 0x1c000>; 851 #interconnect-cells = <1>; 852 clock-names = "bus", "bus_a", "iface"; 853 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 854 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 855 <&mmcc AHB_CLK_SRC>; 856 }; 857 858 pnoc: interconnect@5c0000 { 859 compatible = "qcom,msm8996-pnoc"; 860 reg = <0x005c0000 0x3000>; 861 #interconnect-cells = <1>; 862 clock-names = "bus", "bus_a"; 863 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 864 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 865 }; 866 867 tcsr_mutex: hwlock@740000 { 868 compatible = "qcom,tcsr-mutex"; 869 reg = <0x00740000 0x20000>; 870 #hwlock-cells = <1>; 871 }; 872 873 tcsr_1: syscon@760000 { 874 compatible = "qcom,tcsr-msm8996", "syscon"; 875 reg = <0x00760000 0x20000>; 876 }; 877 878 tcsr_2: syscon@7a0000 { 879 compatible = "qcom,tcsr-msm8996", "syscon"; 880 reg = <0x007a0000 0x18000>; 881 }; 882 883 mmcc: clock-controller@8c0000 { 884 compatible = "qcom,mmcc-msm8996"; 885 #clock-cells = <1>; 886 #reset-cells = <1>; 887 #power-domain-cells = <1>; 888 reg = <0x008c0000 0x40000>; 889 clocks = <&xo_board>, 890 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 891 <&gcc GPLL0>, 892 <&dsi0_phy 1>, 893 <&dsi0_phy 0>, 894 <&dsi1_phy 1>, 895 <&dsi1_phy 0>, 896 <&hdmi_phy>; 897 clock-names = "xo", 898 "gcc_mmss_noc_cfg_ahb_clk", 899 "gpll0", 900 "dsi0pll", 901 "dsi0pllbyte", 902 "dsi1pll", 903 "dsi1pllbyte", 904 "hdmipll"; 905 assigned-clocks = <&mmcc MMPLL9_PLL>, 906 <&mmcc MMPLL1_PLL>, 907 <&mmcc MMPLL3_PLL>, 908 <&mmcc MMPLL4_PLL>, 909 <&mmcc MMPLL5_PLL>; 910 assigned-clock-rates = <624000000>, 911 <810000000>, 912 <980000000>, 913 <960000000>, 914 <825000000>; 915 }; 916 917 mdss: display-subsystem@900000 { 918 compatible = "qcom,mdss"; 919 920 reg = <0x00900000 0x1000>, 921 <0x009b0000 0x1040>, 922 <0x009b8000 0x1040>; 923 reg-names = "mdss_phys", 924 "vbif_phys", 925 "vbif_nrt_phys"; 926 927 power-domains = <&mmcc MDSS_GDSC>; 928 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 929 930 interrupt-controller; 931 #interrupt-cells = <1>; 932 933 clocks = <&mmcc MDSS_AHB_CLK>, 934 <&mmcc MDSS_MDP_CLK>; 935 clock-names = "iface", "core"; 936 937 #address-cells = <1>; 938 #size-cells = <1>; 939 ranges; 940 941 status = "disabled"; 942 943 mdp: display-controller@901000 { 944 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 945 reg = <0x00901000 0x90000>; 946 reg-names = "mdp_phys"; 947 948 interrupt-parent = <&mdss>; 949 interrupts = <0>; 950 951 clocks = <&mmcc MDSS_AHB_CLK>, 952 <&mmcc MDSS_AXI_CLK>, 953 <&mmcc MDSS_MDP_CLK>, 954 <&mmcc SMMU_MDP_AXI_CLK>, 955 <&mmcc MDSS_VSYNC_CLK>; 956 clock-names = "iface", 957 "bus", 958 "core", 959 "iommu", 960 "vsync"; 961 962 iommus = <&mdp_smmu 0>; 963 964 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 965 <&mmcc MDSS_VSYNC_CLK>; 966 assigned-clock-rates = <300000000>, 967 <19200000>; 968 969 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 970 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 971 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 972 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 973 974 ports { 975 #address-cells = <1>; 976 #size-cells = <0>; 977 978 port@0 { 979 reg = <0>; 980 mdp5_intf3_out: endpoint { 981 remote-endpoint = <&hdmi_in>; 982 }; 983 }; 984 985 port@1 { 986 reg = <1>; 987 mdp5_intf1_out: endpoint { 988 remote-endpoint = <&dsi0_in>; 989 }; 990 }; 991 992 port@2 { 993 reg = <2>; 994 mdp5_intf2_out: endpoint { 995 remote-endpoint = <&dsi1_in>; 996 }; 997 }; 998 }; 999 }; 1000 1001 dsi0: dsi@994000 { 1002 compatible = "qcom,msm8996-dsi-ctrl", 1003 "qcom,mdss-dsi-ctrl"; 1004 reg = <0x00994000 0x400>; 1005 reg-names = "dsi_ctrl"; 1006 1007 interrupt-parent = <&mdss>; 1008 interrupts = <4>; 1009 1010 clocks = <&mmcc MDSS_MDP_CLK>, 1011 <&mmcc MDSS_BYTE0_CLK>, 1012 <&mmcc MDSS_AHB_CLK>, 1013 <&mmcc MDSS_AXI_CLK>, 1014 <&mmcc MMSS_MISC_AHB_CLK>, 1015 <&mmcc MDSS_PCLK0_CLK>, 1016 <&mmcc MDSS_ESC0_CLK>; 1017 clock-names = "mdp_core", 1018 "byte", 1019 "iface", 1020 "bus", 1021 "core_mmss", 1022 "pixel", 1023 "core"; 1024 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1025 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1026 1027 phys = <&dsi0_phy>; 1028 status = "disabled"; 1029 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 1033 ports { 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 port@0 { 1038 reg = <0>; 1039 dsi0_in: endpoint { 1040 remote-endpoint = <&mdp5_intf1_out>; 1041 }; 1042 }; 1043 1044 port@1 { 1045 reg = <1>; 1046 dsi0_out: endpoint { 1047 }; 1048 }; 1049 }; 1050 }; 1051 1052 dsi0_phy: phy@994400 { 1053 compatible = "qcom,dsi-phy-14nm"; 1054 reg = <0x00994400 0x100>, 1055 <0x00994500 0x300>, 1056 <0x00994800 0x188>; 1057 reg-names = "dsi_phy", 1058 "dsi_phy_lane", 1059 "dsi_pll"; 1060 1061 #clock-cells = <1>; 1062 #phy-cells = <0>; 1063 1064 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1065 clock-names = "iface", "ref"; 1066 status = "disabled"; 1067 }; 1068 1069 dsi1: dsi@996000 { 1070 compatible = "qcom,msm8996-dsi-ctrl", 1071 "qcom,mdss-dsi-ctrl"; 1072 reg = <0x00996000 0x400>; 1073 reg-names = "dsi_ctrl"; 1074 1075 interrupt-parent = <&mdss>; 1076 interrupts = <4>; 1077 1078 clocks = <&mmcc MDSS_MDP_CLK>, 1079 <&mmcc MDSS_BYTE1_CLK>, 1080 <&mmcc MDSS_AHB_CLK>, 1081 <&mmcc MDSS_AXI_CLK>, 1082 <&mmcc MMSS_MISC_AHB_CLK>, 1083 <&mmcc MDSS_PCLK1_CLK>, 1084 <&mmcc MDSS_ESC1_CLK>; 1085 clock-names = "mdp_core", 1086 "byte", 1087 "iface", 1088 "bus", 1089 "core_mmss", 1090 "pixel", 1091 "core"; 1092 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1093 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 1094 1095 phys = <&dsi1_phy>; 1096 status = "disabled"; 1097 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 1101 ports { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 1105 port@0 { 1106 reg = <0>; 1107 dsi1_in: endpoint { 1108 remote-endpoint = <&mdp5_intf2_out>; 1109 }; 1110 }; 1111 1112 port@1 { 1113 reg = <1>; 1114 dsi1_out: endpoint { 1115 }; 1116 }; 1117 }; 1118 }; 1119 1120 dsi1_phy: phy@996400 { 1121 compatible = "qcom,dsi-phy-14nm"; 1122 reg = <0x00996400 0x100>, 1123 <0x00996500 0x300>, 1124 <0x00996800 0x188>; 1125 reg-names = "dsi_phy", 1126 "dsi_phy_lane", 1127 "dsi_pll"; 1128 1129 #clock-cells = <1>; 1130 #phy-cells = <0>; 1131 1132 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1133 clock-names = "iface", "ref"; 1134 status = "disabled"; 1135 }; 1136 1137 hdmi: hdmi-tx@9a0000 { 1138 compatible = "qcom,hdmi-tx-8996"; 1139 reg = <0x009a0000 0x50c>, 1140 <0x00070000 0x6158>, 1141 <0x009e0000 0xfff>; 1142 reg-names = "core_physical", 1143 "qfprom_physical", 1144 "hdcp_physical"; 1145 1146 interrupt-parent = <&mdss>; 1147 interrupts = <8>; 1148 1149 clocks = <&mmcc MDSS_MDP_CLK>, 1150 <&mmcc MDSS_AHB_CLK>, 1151 <&mmcc MDSS_HDMI_CLK>, 1152 <&mmcc MDSS_HDMI_AHB_CLK>, 1153 <&mmcc MDSS_EXTPCLK_CLK>; 1154 clock-names = 1155 "mdp_core", 1156 "iface", 1157 "core", 1158 "alt_iface", 1159 "extp"; 1160 1161 phys = <&hdmi_phy>; 1162 #sound-dai-cells = <1>; 1163 1164 status = "disabled"; 1165 1166 ports { 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 1170 port@0 { 1171 reg = <0>; 1172 hdmi_in: endpoint { 1173 remote-endpoint = <&mdp5_intf3_out>; 1174 }; 1175 }; 1176 }; 1177 }; 1178 1179 hdmi_phy: phy@9a0600 { 1180 #phy-cells = <0>; 1181 compatible = "qcom,hdmi-phy-8996"; 1182 reg = <0x009a0600 0x1c4>, 1183 <0x009a0a00 0x124>, 1184 <0x009a0c00 0x124>, 1185 <0x009a0e00 0x124>, 1186 <0x009a1000 0x124>, 1187 <0x009a1200 0x0c8>; 1188 reg-names = "hdmi_pll", 1189 "hdmi_tx_l0", 1190 "hdmi_tx_l1", 1191 "hdmi_tx_l2", 1192 "hdmi_tx_l3", 1193 "hdmi_phy"; 1194 1195 clocks = <&mmcc MDSS_AHB_CLK>, 1196 <&gcc GCC_HDMI_CLKREF_CLK>, 1197 <&xo_board>; 1198 clock-names = "iface", 1199 "ref", 1200 "xo"; 1201 1202 #clock-cells = <0>; 1203 1204 status = "disabled"; 1205 }; 1206 }; 1207 1208 gpu: gpu@b00000 { 1209 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1210 1211 reg = <0x00b00000 0x3f000>; 1212 reg-names = "kgsl_3d0_reg_memory"; 1213 1214 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1215 1216 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1217 <&mmcc GPU_AHB_CLK>, 1218 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1219 <&gcc GCC_BIMC_GFX_CLK>, 1220 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1221 1222 clock-names = "core", 1223 "iface", 1224 "rbbmtimer", 1225 "mem", 1226 "mem_iface"; 1227 1228 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1229 interconnect-names = "gfx-mem"; 1230 1231 power-domains = <&mmcc GPU_GX_GDSC>; 1232 iommus = <&adreno_smmu 0>; 1233 1234 nvmem-cells = <&speedbin_efuse>; 1235 nvmem-cell-names = "speed_bin"; 1236 1237 operating-points-v2 = <&gpu_opp_table>; 1238 1239 status = "disabled"; 1240 1241 #cooling-cells = <2>; 1242 1243 gpu_opp_table: opp-table { 1244 compatible = "operating-points-v2"; 1245 1246 /* 1247 * 624Mhz is only available on speed bins 0 and 3. 1248 * 560Mhz is only available on speed bins 0, 2 and 3. 1249 * All the rest are available on all bins of the hardware. 1250 */ 1251 opp-624000000 { 1252 opp-hz = /bits/ 64 <624000000>; 1253 opp-supported-hw = <0x09>; 1254 }; 1255 opp-560000000 { 1256 opp-hz = /bits/ 64 <560000000>; 1257 opp-supported-hw = <0x0d>; 1258 }; 1259 opp-510000000 { 1260 opp-hz = /bits/ 64 <510000000>; 1261 opp-supported-hw = <0xff>; 1262 }; 1263 opp-401800000 { 1264 opp-hz = /bits/ 64 <401800000>; 1265 opp-supported-hw = <0xff>; 1266 }; 1267 opp-315000000 { 1268 opp-hz = /bits/ 64 <315000000>; 1269 opp-supported-hw = <0xff>; 1270 }; 1271 opp-214000000 { 1272 opp-hz = /bits/ 64 <214000000>; 1273 opp-supported-hw = <0xff>; 1274 }; 1275 opp-133000000 { 1276 opp-hz = /bits/ 64 <133000000>; 1277 opp-supported-hw = <0xff>; 1278 }; 1279 }; 1280 1281 zap-shader { 1282 memory-region = <&gpu_mem>; 1283 }; 1284 }; 1285 1286 tlmm: pinctrl@1010000 { 1287 compatible = "qcom,msm8996-pinctrl"; 1288 reg = <0x01010000 0x300000>; 1289 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1290 gpio-controller; 1291 gpio-ranges = <&tlmm 0 0 150>; 1292 #gpio-cells = <2>; 1293 interrupt-controller; 1294 #interrupt-cells = <2>; 1295 1296 blsp1_spi1_default: blsp1-spi1-default-state { 1297 spi-pins { 1298 pins = "gpio0", "gpio1", "gpio3"; 1299 function = "blsp_spi1"; 1300 drive-strength = <12>; 1301 bias-disable; 1302 }; 1303 1304 cs-pins { 1305 pins = "gpio2"; 1306 function = "gpio"; 1307 drive-strength = <16>; 1308 bias-disable; 1309 output-high; 1310 }; 1311 }; 1312 1313 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1314 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1315 function = "gpio"; 1316 drive-strength = <2>; 1317 bias-pull-down; 1318 }; 1319 1320 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1321 pins = "gpio4", "gpio5"; 1322 function = "blsp_uart8"; 1323 drive-strength = <16>; 1324 bias-disable; 1325 }; 1326 1327 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1328 pins = "gpio4", "gpio5"; 1329 function = "gpio"; 1330 drive-strength = <2>; 1331 bias-disable; 1332 }; 1333 1334 blsp2_i2c2_default: blsp2-i2c2-state { 1335 pins = "gpio6", "gpio7"; 1336 function = "blsp_i2c8"; 1337 drive-strength = <16>; 1338 bias-disable; 1339 }; 1340 1341 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1342 pins = "gpio6", "gpio7"; 1343 function = "gpio"; 1344 drive-strength = <2>; 1345 bias-disable; 1346 }; 1347 1348 blsp1_i2c6_default: blsp1-i2c6-state { 1349 pins = "gpio27", "gpio28"; 1350 function = "blsp_i2c6"; 1351 drive-strength = <16>; 1352 bias-disable; 1353 }; 1354 1355 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1356 pins = "gpio27", "gpio28"; 1357 function = "gpio"; 1358 drive-strength = <2>; 1359 bias-pull-up; 1360 }; 1361 1362 cci0_default: cci0-default-state { 1363 pins = "gpio17", "gpio18"; 1364 function = "cci_i2c"; 1365 drive-strength = <16>; 1366 bias-disable; 1367 }; 1368 1369 camera0_state_on: 1370 camera_rear_default: camera-rear-default-state { 1371 camera0_mclk: mclk0-pins { 1372 pins = "gpio13"; 1373 function = "cam_mclk"; 1374 drive-strength = <16>; 1375 bias-disable; 1376 }; 1377 1378 camera0_rst: rst-pins { 1379 pins = "gpio25"; 1380 function = "gpio"; 1381 drive-strength = <16>; 1382 bias-disable; 1383 }; 1384 1385 camera0_pwdn: pwdn-pins { 1386 pins = "gpio26"; 1387 function = "gpio"; 1388 drive-strength = <16>; 1389 bias-disable; 1390 }; 1391 }; 1392 1393 cci1_default: cci1-default-state { 1394 pins = "gpio19", "gpio20"; 1395 function = "cci_i2c"; 1396 drive-strength = <16>; 1397 bias-disable; 1398 }; 1399 1400 camera1_state_on: 1401 camera_board_default: camera-board-default-state { 1402 mclk1-pins { 1403 pins = "gpio14"; 1404 function = "cam_mclk"; 1405 drive-strength = <16>; 1406 bias-disable; 1407 }; 1408 1409 pwdn-pins { 1410 pins = "gpio98"; 1411 function = "gpio"; 1412 drive-strength = <16>; 1413 bias-disable; 1414 }; 1415 1416 rst-pins { 1417 pins = "gpio104"; 1418 function = "gpio"; 1419 drive-strength = <16>; 1420 bias-disable; 1421 }; 1422 }; 1423 1424 camera2_state_on: 1425 camera_front_default: camera-front-default-state { 1426 camera2_mclk: mclk2-pins { 1427 pins = "gpio15"; 1428 function = "cam_mclk"; 1429 drive-strength = <16>; 1430 bias-disable; 1431 }; 1432 1433 camera2_rst: rst-pins { 1434 pins = "gpio23"; 1435 function = "gpio"; 1436 drive-strength = <16>; 1437 bias-disable; 1438 }; 1439 1440 pwdn-pins { 1441 pins = "gpio133"; 1442 function = "gpio"; 1443 drive-strength = <16>; 1444 bias-disable; 1445 }; 1446 }; 1447 1448 pcie0_state_on: pcie0-state-on-state { 1449 perst-pins { 1450 pins = "gpio35"; 1451 function = "gpio"; 1452 drive-strength = <2>; 1453 bias-pull-down; 1454 }; 1455 1456 clkreq-pins { 1457 pins = "gpio36"; 1458 function = "pci_e0"; 1459 drive-strength = <2>; 1460 bias-pull-up; 1461 }; 1462 1463 wake-pins { 1464 pins = "gpio37"; 1465 function = "gpio"; 1466 drive-strength = <2>; 1467 bias-pull-up; 1468 }; 1469 }; 1470 1471 pcie0_state_off: pcie0-state-off-state { 1472 perst-pins { 1473 pins = "gpio35"; 1474 function = "gpio"; 1475 drive-strength = <2>; 1476 bias-pull-down; 1477 }; 1478 1479 clkreq-pins { 1480 pins = "gpio36"; 1481 function = "gpio"; 1482 drive-strength = <2>; 1483 bias-disable; 1484 }; 1485 1486 wake-pins { 1487 pins = "gpio37"; 1488 function = "gpio"; 1489 drive-strength = <2>; 1490 bias-disable; 1491 }; 1492 }; 1493 1494 blsp1_uart2_default: blsp1-uart2-default-state { 1495 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1496 function = "blsp_uart2"; 1497 drive-strength = <16>; 1498 bias-disable; 1499 }; 1500 1501 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1502 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1503 function = "gpio"; 1504 drive-strength = <2>; 1505 bias-disable; 1506 }; 1507 1508 blsp1_i2c3_default: blsp1-i2c3-default-state { 1509 pins = "gpio47", "gpio48"; 1510 function = "blsp_i2c3"; 1511 drive-strength = <16>; 1512 bias-disable; 1513 }; 1514 1515 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1516 pins = "gpio47", "gpio48"; 1517 function = "gpio"; 1518 drive-strength = <2>; 1519 bias-disable; 1520 }; 1521 1522 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1523 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1524 function = "blsp_uart9"; 1525 drive-strength = <16>; 1526 bias-disable; 1527 }; 1528 1529 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1530 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1531 function = "blsp_uart9"; 1532 drive-strength = <2>; 1533 bias-disable; 1534 }; 1535 1536 blsp2_i2c3_default: blsp2-i2c3-state-state { 1537 pins = "gpio51", "gpio52"; 1538 function = "blsp_i2c9"; 1539 drive-strength = <16>; 1540 bias-disable; 1541 }; 1542 1543 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1544 pins = "gpio51", "gpio52"; 1545 function = "gpio"; 1546 drive-strength = <2>; 1547 bias-disable; 1548 }; 1549 1550 wcd_intr_default: wcd-intr-default-state { 1551 pins = "gpio54"; 1552 function = "gpio"; 1553 drive-strength = <2>; 1554 bias-pull-down; 1555 input-enable; 1556 }; 1557 1558 blsp2_i2c1_default: blsp2-i2c1-state { 1559 pins = "gpio55", "gpio56"; 1560 function = "blsp_i2c7"; 1561 drive-strength = <16>; 1562 bias-disable; 1563 }; 1564 1565 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1566 pins = "gpio55", "gpio56"; 1567 function = "gpio"; 1568 drive-strength = <2>; 1569 bias-disable; 1570 }; 1571 1572 blsp2_i2c5_default: blsp2-i2c5-state { 1573 pins = "gpio60", "gpio61"; 1574 function = "blsp_i2c11"; 1575 drive-strength = <2>; 1576 bias-disable; 1577 }; 1578 1579 /* Sleep state for BLSP2_I2C5 is missing.. */ 1580 1581 cdc_reset_active: cdc-reset-active-state { 1582 pins = "gpio64"; 1583 function = "gpio"; 1584 drive-strength = <16>; 1585 bias-pull-down; 1586 output-high; 1587 }; 1588 1589 cdc_reset_sleep: cdc-reset-sleep-state { 1590 pins = "gpio64"; 1591 function = "gpio"; 1592 drive-strength = <16>; 1593 bias-disable; 1594 output-low; 1595 }; 1596 1597 blsp2_spi6_default: blsp2-spi6-default-state { 1598 spi-pins { 1599 pins = "gpio85", "gpio86", "gpio88"; 1600 function = "blsp_spi12"; 1601 drive-strength = <12>; 1602 bias-disable; 1603 }; 1604 1605 cs-pins { 1606 pins = "gpio87"; 1607 function = "gpio"; 1608 drive-strength = <16>; 1609 bias-disable; 1610 output-high; 1611 }; 1612 }; 1613 1614 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1615 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1616 function = "gpio"; 1617 drive-strength = <2>; 1618 bias-pull-down; 1619 }; 1620 1621 blsp2_i2c6_default: blsp2-i2c6-state { 1622 pins = "gpio87", "gpio88"; 1623 function = "blsp_i2c12"; 1624 drive-strength = <16>; 1625 bias-disable; 1626 }; 1627 1628 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1629 pins = "gpio87", "gpio88"; 1630 function = "gpio"; 1631 drive-strength = <2>; 1632 bias-disable; 1633 }; 1634 1635 pcie1_state_on: pcie1-on-state { 1636 perst-pins { 1637 pins = "gpio130"; 1638 function = "gpio"; 1639 drive-strength = <2>; 1640 bias-pull-down; 1641 }; 1642 1643 clkreq-pins { 1644 pins = "gpio131"; 1645 function = "pci_e1"; 1646 drive-strength = <2>; 1647 bias-pull-up; 1648 }; 1649 1650 wake-pins { 1651 pins = "gpio132"; 1652 function = "gpio"; 1653 drive-strength = <2>; 1654 bias-pull-down; 1655 }; 1656 }; 1657 1658 pcie1_state_off: pcie1-off-state { 1659 /* Perst is missing? */ 1660 clkreq-pins { 1661 pins = "gpio131"; 1662 function = "gpio"; 1663 drive-strength = <2>; 1664 bias-disable; 1665 }; 1666 1667 wake-pins { 1668 pins = "gpio132"; 1669 function = "gpio"; 1670 drive-strength = <2>; 1671 bias-disable; 1672 }; 1673 }; 1674 1675 pcie2_state_on: pcie2-on-state { 1676 perst-pins { 1677 pins = "gpio114"; 1678 function = "gpio"; 1679 drive-strength = <2>; 1680 bias-pull-down; 1681 }; 1682 1683 clkreq-pins { 1684 pins = "gpio115"; 1685 function = "pci_e2"; 1686 drive-strength = <2>; 1687 bias-pull-up; 1688 }; 1689 1690 wake-pins { 1691 pins = "gpio116"; 1692 function = "gpio"; 1693 drive-strength = <2>; 1694 bias-pull-down; 1695 }; 1696 }; 1697 1698 pcie2_state_off: pcie2-off-state { 1699 /* Perst is missing? */ 1700 clkreq-pins { 1701 pins = "gpio115"; 1702 function = "gpio"; 1703 drive-strength = <2>; 1704 bias-disable; 1705 }; 1706 1707 wake-pins { 1708 pins = "gpio116"; 1709 function = "gpio"; 1710 drive-strength = <2>; 1711 bias-disable; 1712 }; 1713 }; 1714 1715 sdc1_state_on: sdc1-on-state { 1716 clk-pins { 1717 pins = "sdc1_clk"; 1718 bias-disable; 1719 drive-strength = <16>; 1720 }; 1721 1722 cmd-pins { 1723 pins = "sdc1_cmd"; 1724 bias-pull-up; 1725 drive-strength = <10>; 1726 }; 1727 1728 data-pins { 1729 pins = "sdc1_data"; 1730 bias-pull-up; 1731 drive-strength = <10>; 1732 }; 1733 1734 rclk-pins { 1735 pins = "sdc1_rclk"; 1736 bias-pull-down; 1737 }; 1738 }; 1739 1740 sdc1_state_off: sdc1-off-state { 1741 clk-pins { 1742 pins = "sdc1_clk"; 1743 bias-disable; 1744 drive-strength = <2>; 1745 }; 1746 1747 cmd-pins { 1748 pins = "sdc1_cmd"; 1749 bias-pull-up; 1750 drive-strength = <2>; 1751 }; 1752 1753 data-pins { 1754 pins = "sdc1_data"; 1755 bias-pull-up; 1756 drive-strength = <2>; 1757 }; 1758 1759 rclk-pins { 1760 pins = "sdc1_rclk"; 1761 bias-pull-down; 1762 }; 1763 }; 1764 1765 sdc2_state_on: sdc2-on-state { 1766 clk-pins { 1767 pins = "sdc2_clk"; 1768 bias-disable; 1769 drive-strength = <16>; 1770 }; 1771 1772 cmd-pins { 1773 pins = "sdc2_cmd"; 1774 bias-pull-up; 1775 drive-strength = <10>; 1776 }; 1777 1778 data-pins { 1779 pins = "sdc2_data"; 1780 bias-pull-up; 1781 drive-strength = <10>; 1782 }; 1783 }; 1784 1785 sdc2_state_off: sdc2-off-state { 1786 clk-pins { 1787 pins = "sdc2_clk"; 1788 bias-disable; 1789 drive-strength = <2>; 1790 }; 1791 1792 cmd-pins { 1793 pins = "sdc2_cmd"; 1794 bias-pull-up; 1795 drive-strength = <2>; 1796 }; 1797 1798 data-pins { 1799 pins = "sdc2_data"; 1800 bias-pull-up; 1801 drive-strength = <2>; 1802 }; 1803 }; 1804 }; 1805 1806 sram@290000 { 1807 compatible = "qcom,rpm-stats"; 1808 reg = <0x00290000 0x10000>; 1809 }; 1810 1811 spmi_bus: spmi@400f000 { 1812 compatible = "qcom,spmi-pmic-arb"; 1813 reg = <0x0400f000 0x1000>, 1814 <0x04400000 0x800000>, 1815 <0x04c00000 0x800000>, 1816 <0x05800000 0x200000>, 1817 <0x0400a000 0x002100>; 1818 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1819 interrupt-names = "periph_irq"; 1820 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1821 qcom,ee = <0>; 1822 qcom,channel = <0>; 1823 #address-cells = <2>; 1824 #size-cells = <0>; 1825 interrupt-controller; 1826 #interrupt-cells = <4>; 1827 }; 1828 1829 bus@0 { 1830 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1831 compatible = "simple-pm-bus"; 1832 #address-cells = <1>; 1833 #size-cells = <1>; 1834 ranges; 1835 1836 pcie0: pcie@600000 { 1837 compatible = "qcom,pcie-msm8996"; 1838 status = "disabled"; 1839 power-domains = <&gcc PCIE0_GDSC>; 1840 bus-range = <0x00 0xff>; 1841 num-lanes = <1>; 1842 1843 reg = <0x00600000 0x2000>, 1844 <0x0c000000 0xf1d>, 1845 <0x0c000f20 0xa8>, 1846 <0x0c100000 0x100000>; 1847 reg-names = "parf", "dbi", "elbi","config"; 1848 1849 phys = <&pciephy_0>; 1850 phy-names = "pciephy"; 1851 1852 #address-cells = <3>; 1853 #size-cells = <2>; 1854 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1855 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1856 1857 device_type = "pci"; 1858 1859 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1860 interrupt-names = "msi"; 1861 #interrupt-cells = <1>; 1862 interrupt-map-mask = <0 0 0 0x7>; 1863 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1864 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1865 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1866 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1867 1868 pinctrl-names = "default", "sleep"; 1869 pinctrl-0 = <&pcie0_state_on>; 1870 pinctrl-1 = <&pcie0_state_off>; 1871 1872 linux,pci-domain = <0>; 1873 1874 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1875 <&gcc GCC_PCIE_0_AUX_CLK>, 1876 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1877 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1878 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1879 1880 clock-names = "pipe", 1881 "aux", 1882 "cfg", 1883 "bus_master", 1884 "bus_slave"; 1885 1886 }; 1887 1888 pcie1: pcie@608000 { 1889 compatible = "qcom,pcie-msm8996"; 1890 power-domains = <&gcc PCIE1_GDSC>; 1891 bus-range = <0x00 0xff>; 1892 num-lanes = <1>; 1893 1894 status = "disabled"; 1895 1896 reg = <0x00608000 0x2000>, 1897 <0x0d000000 0xf1d>, 1898 <0x0d000f20 0xa8>, 1899 <0x0d100000 0x100000>; 1900 1901 reg-names = "parf", "dbi", "elbi","config"; 1902 1903 phys = <&pciephy_1>; 1904 phy-names = "pciephy"; 1905 1906 #address-cells = <3>; 1907 #size-cells = <2>; 1908 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1909 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1910 1911 device_type = "pci"; 1912 1913 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1914 interrupt-names = "msi"; 1915 #interrupt-cells = <1>; 1916 interrupt-map-mask = <0 0 0 0x7>; 1917 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1918 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1919 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1920 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1921 1922 pinctrl-names = "default", "sleep"; 1923 pinctrl-0 = <&pcie1_state_on>; 1924 pinctrl-1 = <&pcie1_state_off>; 1925 1926 linux,pci-domain = <1>; 1927 1928 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1929 <&gcc GCC_PCIE_1_AUX_CLK>, 1930 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1931 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1932 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1933 1934 clock-names = "pipe", 1935 "aux", 1936 "cfg", 1937 "bus_master", 1938 "bus_slave"; 1939 }; 1940 1941 pcie2: pcie@610000 { 1942 compatible = "qcom,pcie-msm8996"; 1943 power-domains = <&gcc PCIE2_GDSC>; 1944 bus-range = <0x00 0xff>; 1945 num-lanes = <1>; 1946 status = "disabled"; 1947 reg = <0x00610000 0x2000>, 1948 <0x0e000000 0xf1d>, 1949 <0x0e000f20 0xa8>, 1950 <0x0e100000 0x100000>; 1951 1952 reg-names = "parf", "dbi", "elbi","config"; 1953 1954 phys = <&pciephy_2>; 1955 phy-names = "pciephy"; 1956 1957 #address-cells = <3>; 1958 #size-cells = <2>; 1959 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1960 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1961 1962 device_type = "pci"; 1963 1964 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1965 interrupt-names = "msi"; 1966 #interrupt-cells = <1>; 1967 interrupt-map-mask = <0 0 0 0x7>; 1968 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1969 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1970 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1971 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1972 1973 pinctrl-names = "default", "sleep"; 1974 pinctrl-0 = <&pcie2_state_on>; 1975 pinctrl-1 = <&pcie2_state_off>; 1976 1977 linux,pci-domain = <2>; 1978 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1979 <&gcc GCC_PCIE_2_AUX_CLK>, 1980 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1981 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1982 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1983 1984 clock-names = "pipe", 1985 "aux", 1986 "cfg", 1987 "bus_master", 1988 "bus_slave"; 1989 }; 1990 }; 1991 1992 ufshc: ufshc@624000 { 1993 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1994 "jedec,ufs-2.0"; 1995 reg = <0x00624000 0x2500>; 1996 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1997 1998 phys = <&ufsphy_lane>; 1999 phy-names = "ufsphy"; 2000 2001 power-domains = <&gcc UFS_GDSC>; 2002 2003 clock-names = 2004 "core_clk_src", 2005 "core_clk", 2006 "bus_clk", 2007 "bus_aggr_clk", 2008 "iface_clk", 2009 "core_clk_unipro_src", 2010 "core_clk_unipro", 2011 "core_clk_ice", 2012 "ref_clk", 2013 "tx_lane0_sync_clk", 2014 "rx_lane0_sync_clk"; 2015 clocks = 2016 <&gcc UFS_AXI_CLK_SRC>, 2017 <&gcc GCC_UFS_AXI_CLK>, 2018 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2019 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2020 <&gcc GCC_UFS_AHB_CLK>, 2021 <&gcc UFS_ICE_CORE_CLK_SRC>, 2022 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2023 <&gcc GCC_UFS_ICE_CORE_CLK>, 2024 <&rpmcc RPM_SMD_LN_BB_CLK>, 2025 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2026 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2027 freq-table-hz = 2028 <100000000 200000000>, 2029 <0 0>, 2030 <0 0>, 2031 <0 0>, 2032 <0 0>, 2033 <150000000 300000000>, 2034 <0 0>, 2035 <0 0>, 2036 <0 0>, 2037 <0 0>, 2038 <0 0>; 2039 2040 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2041 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2042 interconnect-names = "ufs-ddr", "cpu-ufs"; 2043 2044 lanes-per-direction = <1>; 2045 #reset-cells = <1>; 2046 status = "disabled"; 2047 }; 2048 2049 ufsphy: phy@627000 { 2050 compatible = "qcom,msm8996-qmp-ufs-phy"; 2051 reg = <0x00627000 0x1c4>; 2052 #address-cells = <1>; 2053 #size-cells = <1>; 2054 ranges; 2055 2056 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2057 clock-names = "ref"; 2058 2059 resets = <&ufshc 0>; 2060 reset-names = "ufsphy"; 2061 status = "disabled"; 2062 2063 ufsphy_lane: phy@627400 { 2064 reg = <0x627400 0x12c>, 2065 <0x627600 0x200>, 2066 <0x627c00 0x1b4>; 2067 #clock-cells = <1>; 2068 #phy-cells = <0>; 2069 }; 2070 }; 2071 2072 camss: camss@a00000 { 2073 compatible = "qcom,msm8996-camss"; 2074 reg = <0x00a34000 0x1000>, 2075 <0x00a00030 0x4>, 2076 <0x00a35000 0x1000>, 2077 <0x00a00038 0x4>, 2078 <0x00a36000 0x1000>, 2079 <0x00a00040 0x4>, 2080 <0x00a30000 0x100>, 2081 <0x00a30400 0x100>, 2082 <0x00a30800 0x100>, 2083 <0x00a30c00 0x100>, 2084 <0x00a31000 0x500>, 2085 <0x00a00020 0x10>, 2086 <0x00a10000 0x1000>, 2087 <0x00a14000 0x1000>; 2088 reg-names = "csiphy0", 2089 "csiphy0_clk_mux", 2090 "csiphy1", 2091 "csiphy1_clk_mux", 2092 "csiphy2", 2093 "csiphy2_clk_mux", 2094 "csid0", 2095 "csid1", 2096 "csid2", 2097 "csid3", 2098 "ispif", 2099 "csi_clk_mux", 2100 "vfe0", 2101 "vfe1"; 2102 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2103 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2104 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2105 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2106 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2107 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2108 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2109 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2110 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2111 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2112 interrupt-names = "csiphy0", 2113 "csiphy1", 2114 "csiphy2", 2115 "csid0", 2116 "csid1", 2117 "csid2", 2118 "csid3", 2119 "ispif", 2120 "vfe0", 2121 "vfe1"; 2122 power-domains = <&mmcc VFE0_GDSC>, 2123 <&mmcc VFE1_GDSC>; 2124 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2125 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2126 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2127 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2128 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2129 <&mmcc CAMSS_CSI0_AHB_CLK>, 2130 <&mmcc CAMSS_CSI0_CLK>, 2131 <&mmcc CAMSS_CSI0PHY_CLK>, 2132 <&mmcc CAMSS_CSI0PIX_CLK>, 2133 <&mmcc CAMSS_CSI0RDI_CLK>, 2134 <&mmcc CAMSS_CSI1_AHB_CLK>, 2135 <&mmcc CAMSS_CSI1_CLK>, 2136 <&mmcc CAMSS_CSI1PHY_CLK>, 2137 <&mmcc CAMSS_CSI1PIX_CLK>, 2138 <&mmcc CAMSS_CSI1RDI_CLK>, 2139 <&mmcc CAMSS_CSI2_AHB_CLK>, 2140 <&mmcc CAMSS_CSI2_CLK>, 2141 <&mmcc CAMSS_CSI2PHY_CLK>, 2142 <&mmcc CAMSS_CSI2PIX_CLK>, 2143 <&mmcc CAMSS_CSI2RDI_CLK>, 2144 <&mmcc CAMSS_CSI3_AHB_CLK>, 2145 <&mmcc CAMSS_CSI3_CLK>, 2146 <&mmcc CAMSS_CSI3PHY_CLK>, 2147 <&mmcc CAMSS_CSI3PIX_CLK>, 2148 <&mmcc CAMSS_CSI3RDI_CLK>, 2149 <&mmcc CAMSS_AHB_CLK>, 2150 <&mmcc CAMSS_VFE0_CLK>, 2151 <&mmcc CAMSS_CSI_VFE0_CLK>, 2152 <&mmcc CAMSS_VFE0_AHB_CLK>, 2153 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2154 <&mmcc CAMSS_VFE1_CLK>, 2155 <&mmcc CAMSS_CSI_VFE1_CLK>, 2156 <&mmcc CAMSS_VFE1_AHB_CLK>, 2157 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2158 <&mmcc CAMSS_VFE_AHB_CLK>, 2159 <&mmcc CAMSS_VFE_AXI_CLK>; 2160 clock-names = "top_ahb", 2161 "ispif_ahb", 2162 "csiphy0_timer", 2163 "csiphy1_timer", 2164 "csiphy2_timer", 2165 "csi0_ahb", 2166 "csi0", 2167 "csi0_phy", 2168 "csi0_pix", 2169 "csi0_rdi", 2170 "csi1_ahb", 2171 "csi1", 2172 "csi1_phy", 2173 "csi1_pix", 2174 "csi1_rdi", 2175 "csi2_ahb", 2176 "csi2", 2177 "csi2_phy", 2178 "csi2_pix", 2179 "csi2_rdi", 2180 "csi3_ahb", 2181 "csi3", 2182 "csi3_phy", 2183 "csi3_pix", 2184 "csi3_rdi", 2185 "ahb", 2186 "vfe0", 2187 "csi_vfe0", 2188 "vfe0_ahb", 2189 "vfe0_stream", 2190 "vfe1", 2191 "csi_vfe1", 2192 "vfe1_ahb", 2193 "vfe1_stream", 2194 "vfe_ahb", 2195 "vfe_axi"; 2196 iommus = <&vfe_smmu 0>, 2197 <&vfe_smmu 1>, 2198 <&vfe_smmu 2>, 2199 <&vfe_smmu 3>; 2200 status = "disabled"; 2201 ports { 2202 #address-cells = <1>; 2203 #size-cells = <0>; 2204 }; 2205 }; 2206 2207 cci: cci@a0c000 { 2208 compatible = "qcom,msm8996-cci"; 2209 #address-cells = <1>; 2210 #size-cells = <0>; 2211 reg = <0xa0c000 0x1000>; 2212 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2213 power-domains = <&mmcc CAMSS_GDSC>; 2214 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2215 <&mmcc CAMSS_CCI_AHB_CLK>, 2216 <&mmcc CAMSS_CCI_CLK>, 2217 <&mmcc CAMSS_AHB_CLK>; 2218 clock-names = "camss_top_ahb", 2219 "cci_ahb", 2220 "cci", 2221 "camss_ahb"; 2222 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2223 <&mmcc CAMSS_CCI_CLK>; 2224 assigned-clock-rates = <80000000>, <37500000>; 2225 pinctrl-names = "default"; 2226 pinctrl-0 = <&cci0_default &cci1_default>; 2227 status = "disabled"; 2228 2229 cci_i2c0: i2c-bus@0 { 2230 reg = <0>; 2231 clock-frequency = <400000>; 2232 #address-cells = <1>; 2233 #size-cells = <0>; 2234 }; 2235 2236 cci_i2c1: i2c-bus@1 { 2237 reg = <1>; 2238 clock-frequency = <400000>; 2239 #address-cells = <1>; 2240 #size-cells = <0>; 2241 }; 2242 }; 2243 2244 adreno_smmu: iommu@b40000 { 2245 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2246 reg = <0x00b40000 0x10000>; 2247 2248 #global-interrupts = <1>; 2249 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2252 #iommu-cells = <1>; 2253 2254 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2255 <&mmcc GPU_AHB_CLK>; 2256 clock-names = "bus", "iface"; 2257 2258 power-domains = <&mmcc GPU_GDSC>; 2259 }; 2260 2261 venus: video-codec@c00000 { 2262 compatible = "qcom,msm8996-venus"; 2263 reg = <0x00c00000 0xff000>; 2264 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2265 power-domains = <&mmcc VENUS_GDSC>; 2266 clocks = <&mmcc VIDEO_CORE_CLK>, 2267 <&mmcc VIDEO_AHB_CLK>, 2268 <&mmcc VIDEO_AXI_CLK>, 2269 <&mmcc VIDEO_MAXI_CLK>; 2270 clock-names = "core", "iface", "bus", "mbus"; 2271 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2272 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2273 interconnect-names = "video-mem", "cpu-cfg"; 2274 iommus = <&venus_smmu 0x00>, 2275 <&venus_smmu 0x01>, 2276 <&venus_smmu 0x0a>, 2277 <&venus_smmu 0x07>, 2278 <&venus_smmu 0x0e>, 2279 <&venus_smmu 0x0f>, 2280 <&venus_smmu 0x08>, 2281 <&venus_smmu 0x09>, 2282 <&venus_smmu 0x0b>, 2283 <&venus_smmu 0x0c>, 2284 <&venus_smmu 0x0d>, 2285 <&venus_smmu 0x10>, 2286 <&venus_smmu 0x11>, 2287 <&venus_smmu 0x21>, 2288 <&venus_smmu 0x28>, 2289 <&venus_smmu 0x29>, 2290 <&venus_smmu 0x2b>, 2291 <&venus_smmu 0x2c>, 2292 <&venus_smmu 0x2d>, 2293 <&venus_smmu 0x31>; 2294 memory-region = <&venus_mem>; 2295 status = "disabled"; 2296 2297 video-decoder { 2298 compatible = "venus-decoder"; 2299 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2300 clock-names = "core"; 2301 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2302 }; 2303 2304 video-encoder { 2305 compatible = "venus-encoder"; 2306 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2307 clock-names = "core"; 2308 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2309 }; 2310 }; 2311 2312 mdp_smmu: iommu@d00000 { 2313 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2314 reg = <0x00d00000 0x10000>; 2315 2316 #global-interrupts = <1>; 2317 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2318 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2319 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2320 #iommu-cells = <1>; 2321 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2322 <&mmcc SMMU_MDP_AHB_CLK>; 2323 clock-names = "bus", "iface"; 2324 2325 power-domains = <&mmcc MDSS_GDSC>; 2326 }; 2327 2328 venus_smmu: iommu@d40000 { 2329 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2330 reg = <0x00d40000 0x20000>; 2331 #global-interrupts = <1>; 2332 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2333 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2340 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2341 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2342 <&mmcc SMMU_VIDEO_AHB_CLK>; 2343 clock-names = "bus", "iface"; 2344 #iommu-cells = <1>; 2345 status = "okay"; 2346 }; 2347 2348 vfe_smmu: iommu@da0000 { 2349 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2350 reg = <0x00da0000 0x10000>; 2351 2352 #global-interrupts = <1>; 2353 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2356 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2357 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2358 <&mmcc SMMU_VFE_AHB_CLK>; 2359 clock-names = "bus", "iface"; 2360 #iommu-cells = <1>; 2361 }; 2362 2363 lpass_q6_smmu: iommu@1600000 { 2364 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2365 reg = <0x01600000 0x20000>; 2366 #iommu-cells = <1>; 2367 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2368 2369 #global-interrupts = <1>; 2370 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2383 2384 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2385 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2386 clock-names = "bus", "iface"; 2387 }; 2388 2389 slpi_pil: remoteproc@1c00000 { 2390 compatible = "qcom,msm8996-slpi-pil"; 2391 reg = <0x01c00000 0x4000>; 2392 2393 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2394 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2395 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2396 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2397 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2398 interrupt-names = "wdog", 2399 "fatal", 2400 "ready", 2401 "handover", 2402 "stop-ack"; 2403 2404 clocks = <&xo_board>, 2405 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2406 clock-names = "xo", "aggre2"; 2407 2408 memory-region = <&slpi_mem>; 2409 2410 qcom,smem-states = <&slpi_smp2p_out 0>; 2411 qcom,smem-state-names = "stop"; 2412 2413 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2414 power-domain-names = "ssc_cx"; 2415 2416 status = "disabled"; 2417 2418 smd-edge { 2419 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2420 2421 label = "dsps"; 2422 mboxes = <&apcs_glb 25>; 2423 qcom,smd-edge = <3>; 2424 qcom,remote-pid = <3>; 2425 }; 2426 }; 2427 2428 mss_pil: remoteproc@2080000 { 2429 compatible = "qcom,msm8996-mss-pil"; 2430 reg = <0x2080000 0x100>, 2431 <0x2180000 0x020>; 2432 reg-names = "qdsp6", "rmb"; 2433 2434 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2435 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2436 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2437 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2438 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2439 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2440 interrupt-names = "wdog", "fatal", "ready", 2441 "handover", "stop-ack", 2442 "shutdown-ack"; 2443 2444 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2445 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2446 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2447 <&xo_board>, 2448 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2449 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2450 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2451 <&rpmcc RPM_SMD_PCNOC_CLK>, 2452 <&rpmcc RPM_SMD_QDSS_CLK>; 2453 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2454 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2455 2456 resets = <&gcc GCC_MSS_RESTART>; 2457 reset-names = "mss_restart"; 2458 2459 power-domains = <&rpmpd MSM8996_VDDCX>, 2460 <&rpmpd MSM8996_VDDMX>; 2461 power-domain-names = "cx", "mx"; 2462 2463 qcom,smem-states = <&mpss_smp2p_out 0>; 2464 qcom,smem-state-names = "stop"; 2465 2466 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2467 2468 status = "disabled"; 2469 2470 mba { 2471 memory-region = <&mba_mem>; 2472 }; 2473 2474 mpss { 2475 memory-region = <&mpss_mem>; 2476 }; 2477 2478 metadata { 2479 memory-region = <&mdata_mem>; 2480 }; 2481 2482 smd-edge { 2483 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2484 2485 label = "mpss"; 2486 mboxes = <&apcs_glb 12>; 2487 qcom,smd-edge = <0>; 2488 qcom,remote-pid = <1>; 2489 }; 2490 }; 2491 2492 stm@3002000 { 2493 compatible = "arm,coresight-stm", "arm,primecell"; 2494 reg = <0x3002000 0x1000>, 2495 <0x8280000 0x180000>; 2496 reg-names = "stm-base", "stm-stimulus-base"; 2497 2498 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2499 clock-names = "apb_pclk", "atclk"; 2500 2501 out-ports { 2502 port { 2503 stm_out: endpoint { 2504 remote-endpoint = 2505 <&funnel0_in>; 2506 }; 2507 }; 2508 }; 2509 }; 2510 2511 tpiu@3020000 { 2512 compatible = "arm,coresight-tpiu", "arm,primecell"; 2513 reg = <0x3020000 0x1000>; 2514 2515 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2516 clock-names = "apb_pclk", "atclk"; 2517 2518 in-ports { 2519 port { 2520 tpiu_in: endpoint { 2521 remote-endpoint = 2522 <&replicator_out1>; 2523 }; 2524 }; 2525 }; 2526 }; 2527 2528 funnel@3021000 { 2529 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2530 reg = <0x3021000 0x1000>; 2531 2532 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2533 clock-names = "apb_pclk", "atclk"; 2534 2535 in-ports { 2536 #address-cells = <1>; 2537 #size-cells = <0>; 2538 2539 port@7 { 2540 reg = <7>; 2541 funnel0_in: endpoint { 2542 remote-endpoint = 2543 <&stm_out>; 2544 }; 2545 }; 2546 }; 2547 2548 out-ports { 2549 port { 2550 funnel0_out: endpoint { 2551 remote-endpoint = 2552 <&merge_funnel_in0>; 2553 }; 2554 }; 2555 }; 2556 }; 2557 2558 funnel@3022000 { 2559 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2560 reg = <0x3022000 0x1000>; 2561 2562 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2563 clock-names = "apb_pclk", "atclk"; 2564 2565 in-ports { 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 2569 port@6 { 2570 reg = <6>; 2571 funnel1_in: endpoint { 2572 remote-endpoint = 2573 <&apss_merge_funnel_out>; 2574 }; 2575 }; 2576 }; 2577 2578 out-ports { 2579 port { 2580 funnel1_out: endpoint { 2581 remote-endpoint = 2582 <&merge_funnel_in1>; 2583 }; 2584 }; 2585 }; 2586 }; 2587 2588 funnel@3023000 { 2589 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2590 reg = <0x3023000 0x1000>; 2591 2592 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2593 clock-names = "apb_pclk", "atclk"; 2594 2595 2596 out-ports { 2597 port { 2598 funnel2_out: endpoint { 2599 remote-endpoint = 2600 <&merge_funnel_in2>; 2601 }; 2602 }; 2603 }; 2604 }; 2605 2606 funnel@3025000 { 2607 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2608 reg = <0x3025000 0x1000>; 2609 2610 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2611 clock-names = "apb_pclk", "atclk"; 2612 2613 in-ports { 2614 #address-cells = <1>; 2615 #size-cells = <0>; 2616 2617 port@0 { 2618 reg = <0>; 2619 merge_funnel_in0: endpoint { 2620 remote-endpoint = 2621 <&funnel0_out>; 2622 }; 2623 }; 2624 2625 port@1 { 2626 reg = <1>; 2627 merge_funnel_in1: endpoint { 2628 remote-endpoint = 2629 <&funnel1_out>; 2630 }; 2631 }; 2632 2633 port@2 { 2634 reg = <2>; 2635 merge_funnel_in2: endpoint { 2636 remote-endpoint = 2637 <&funnel2_out>; 2638 }; 2639 }; 2640 }; 2641 2642 out-ports { 2643 port { 2644 merge_funnel_out: endpoint { 2645 remote-endpoint = 2646 <&etf_in>; 2647 }; 2648 }; 2649 }; 2650 }; 2651 2652 replicator@3026000 { 2653 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2654 reg = <0x3026000 0x1000>; 2655 2656 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2657 clock-names = "apb_pclk", "atclk"; 2658 2659 in-ports { 2660 port { 2661 replicator_in: endpoint { 2662 remote-endpoint = 2663 <&etf_out>; 2664 }; 2665 }; 2666 }; 2667 2668 out-ports { 2669 #address-cells = <1>; 2670 #size-cells = <0>; 2671 2672 port@0 { 2673 reg = <0>; 2674 replicator_out0: endpoint { 2675 remote-endpoint = 2676 <&etr_in>; 2677 }; 2678 }; 2679 2680 port@1 { 2681 reg = <1>; 2682 replicator_out1: endpoint { 2683 remote-endpoint = 2684 <&tpiu_in>; 2685 }; 2686 }; 2687 }; 2688 }; 2689 2690 etf@3027000 { 2691 compatible = "arm,coresight-tmc", "arm,primecell"; 2692 reg = <0x3027000 0x1000>; 2693 2694 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2695 clock-names = "apb_pclk", "atclk"; 2696 2697 in-ports { 2698 port { 2699 etf_in: endpoint { 2700 remote-endpoint = 2701 <&merge_funnel_out>; 2702 }; 2703 }; 2704 }; 2705 2706 out-ports { 2707 port { 2708 etf_out: endpoint { 2709 remote-endpoint = 2710 <&replicator_in>; 2711 }; 2712 }; 2713 }; 2714 }; 2715 2716 etr@3028000 { 2717 compatible = "arm,coresight-tmc", "arm,primecell"; 2718 reg = <0x3028000 0x1000>; 2719 2720 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2721 clock-names = "apb_pclk", "atclk"; 2722 arm,scatter-gather; 2723 2724 in-ports { 2725 port { 2726 etr_in: endpoint { 2727 remote-endpoint = 2728 <&replicator_out0>; 2729 }; 2730 }; 2731 }; 2732 }; 2733 2734 debug@3810000 { 2735 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2736 reg = <0x3810000 0x1000>; 2737 2738 clocks = <&rpmcc RPM_QDSS_CLK>; 2739 clock-names = "apb_pclk"; 2740 2741 cpu = <&CPU0>; 2742 }; 2743 2744 etm@3840000 { 2745 compatible = "arm,coresight-etm4x", "arm,primecell"; 2746 reg = <0x3840000 0x1000>; 2747 2748 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2749 clock-names = "apb_pclk", "atclk"; 2750 2751 cpu = <&CPU0>; 2752 2753 out-ports { 2754 port { 2755 etm0_out: endpoint { 2756 remote-endpoint = 2757 <&apss_funnel0_in0>; 2758 }; 2759 }; 2760 }; 2761 }; 2762 2763 debug@3910000 { 2764 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2765 reg = <0x3910000 0x1000>; 2766 2767 clocks = <&rpmcc RPM_QDSS_CLK>; 2768 clock-names = "apb_pclk"; 2769 2770 cpu = <&CPU1>; 2771 }; 2772 2773 etm@3940000 { 2774 compatible = "arm,coresight-etm4x", "arm,primecell"; 2775 reg = <0x3940000 0x1000>; 2776 2777 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2778 clock-names = "apb_pclk", "atclk"; 2779 2780 cpu = <&CPU1>; 2781 2782 out-ports { 2783 port { 2784 etm1_out: endpoint { 2785 remote-endpoint = 2786 <&apss_funnel0_in1>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 funnel@39b0000 { /* APSS Funnel 0 */ 2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2794 reg = <0x39b0000 0x1000>; 2795 2796 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2797 clock-names = "apb_pclk", "atclk"; 2798 2799 in-ports { 2800 #address-cells = <1>; 2801 #size-cells = <0>; 2802 2803 port@0 { 2804 reg = <0>; 2805 apss_funnel0_in0: endpoint { 2806 remote-endpoint = <&etm0_out>; 2807 }; 2808 }; 2809 2810 port@1 { 2811 reg = <1>; 2812 apss_funnel0_in1: endpoint { 2813 remote-endpoint = <&etm1_out>; 2814 }; 2815 }; 2816 }; 2817 2818 out-ports { 2819 port { 2820 apss_funnel0_out: endpoint { 2821 remote-endpoint = 2822 <&apss_merge_funnel_in0>; 2823 }; 2824 }; 2825 }; 2826 }; 2827 2828 debug@3a10000 { 2829 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2830 reg = <0x3a10000 0x1000>; 2831 2832 clocks = <&rpmcc RPM_QDSS_CLK>; 2833 clock-names = "apb_pclk"; 2834 2835 cpu = <&CPU2>; 2836 }; 2837 2838 etm@3a40000 { 2839 compatible = "arm,coresight-etm4x", "arm,primecell"; 2840 reg = <0x3a40000 0x1000>; 2841 2842 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2843 clock-names = "apb_pclk", "atclk"; 2844 2845 cpu = <&CPU2>; 2846 2847 out-ports { 2848 port { 2849 etm2_out: endpoint { 2850 remote-endpoint = 2851 <&apss_funnel1_in0>; 2852 }; 2853 }; 2854 }; 2855 }; 2856 2857 debug@3b10000 { 2858 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2859 reg = <0x3b10000 0x1000>; 2860 2861 clocks = <&rpmcc RPM_QDSS_CLK>; 2862 clock-names = "apb_pclk"; 2863 2864 cpu = <&CPU3>; 2865 }; 2866 2867 etm@3b40000 { 2868 compatible = "arm,coresight-etm4x", "arm,primecell"; 2869 reg = <0x3b40000 0x1000>; 2870 2871 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2872 clock-names = "apb_pclk", "atclk"; 2873 2874 cpu = <&CPU3>; 2875 2876 out-ports { 2877 port { 2878 etm3_out: endpoint { 2879 remote-endpoint = 2880 <&apss_funnel1_in1>; 2881 }; 2882 }; 2883 }; 2884 }; 2885 2886 funnel@3bb0000 { /* APSS Funnel 1 */ 2887 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2888 reg = <0x3bb0000 0x1000>; 2889 2890 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2891 clock-names = "apb_pclk", "atclk"; 2892 2893 in-ports { 2894 #address-cells = <1>; 2895 #size-cells = <0>; 2896 2897 port@0 { 2898 reg = <0>; 2899 apss_funnel1_in0: endpoint { 2900 remote-endpoint = <&etm2_out>; 2901 }; 2902 }; 2903 2904 port@1 { 2905 reg = <1>; 2906 apss_funnel1_in1: endpoint { 2907 remote-endpoint = <&etm3_out>; 2908 }; 2909 }; 2910 }; 2911 2912 out-ports { 2913 port { 2914 apss_funnel1_out: endpoint { 2915 remote-endpoint = 2916 <&apss_merge_funnel_in1>; 2917 }; 2918 }; 2919 }; 2920 }; 2921 2922 funnel@3bc0000 { 2923 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2924 reg = <0x3bc0000 0x1000>; 2925 2926 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2927 clock-names = "apb_pclk", "atclk"; 2928 2929 in-ports { 2930 #address-cells = <1>; 2931 #size-cells = <0>; 2932 2933 port@0 { 2934 reg = <0>; 2935 apss_merge_funnel_in0: endpoint { 2936 remote-endpoint = 2937 <&apss_funnel0_out>; 2938 }; 2939 }; 2940 2941 port@1 { 2942 reg = <1>; 2943 apss_merge_funnel_in1: endpoint { 2944 remote-endpoint = 2945 <&apss_funnel1_out>; 2946 }; 2947 }; 2948 }; 2949 2950 out-ports { 2951 port { 2952 apss_merge_funnel_out: endpoint { 2953 remote-endpoint = 2954 <&funnel1_in>; 2955 }; 2956 }; 2957 }; 2958 }; 2959 2960 kryocc: clock-controller@6400000 { 2961 compatible = "qcom,msm8996-apcc"; 2962 reg = <0x06400000 0x90000>; 2963 2964 clock-names = "xo", "sys_apcs_aux"; 2965 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 2966 2967 #clock-cells = <1>; 2968 }; 2969 2970 usb3: usb@6af8800 { 2971 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2972 reg = <0x06af8800 0x400>; 2973 #address-cells = <1>; 2974 #size-cells = <1>; 2975 ranges; 2976 2977 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2979 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2980 2981 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2982 <&gcc GCC_USB30_MASTER_CLK>, 2983 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2984 <&gcc GCC_USB30_SLEEP_CLK>, 2985 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2986 clock-names = "cfg_noc", 2987 "core", 2988 "iface", 2989 "sleep", 2990 "mock_utmi"; 2991 2992 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2993 <&gcc GCC_USB30_MASTER_CLK>; 2994 assigned-clock-rates = <19200000>, <120000000>; 2995 2996 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2997 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2998 interconnect-names = "usb-ddr", "apps-usb"; 2999 3000 power-domains = <&gcc USB30_GDSC>; 3001 status = "disabled"; 3002 3003 usb3_dwc3: usb@6a00000 { 3004 compatible = "snps,dwc3"; 3005 reg = <0x06a00000 0xcc00>; 3006 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 3007 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 3008 phy-names = "usb2-phy", "usb3-phy"; 3009 snps,dis_u2_susphy_quirk; 3010 snps,dis_enblslpm_quirk; 3011 }; 3012 }; 3013 3014 usb3phy: phy@7410000 { 3015 compatible = "qcom,msm8996-qmp-usb3-phy"; 3016 reg = <0x07410000 0x1c4>; 3017 #address-cells = <1>; 3018 #size-cells = <1>; 3019 ranges; 3020 3021 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3022 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3023 <&gcc GCC_USB3_CLKREF_CLK>; 3024 clock-names = "aux", "cfg_ahb", "ref"; 3025 3026 resets = <&gcc GCC_USB3_PHY_BCR>, 3027 <&gcc GCC_USB3PHY_PHY_BCR>; 3028 reset-names = "phy", "common"; 3029 status = "disabled"; 3030 3031 ssusb_phy_0: phy@7410200 { 3032 reg = <0x07410200 0x200>, 3033 <0x07410400 0x130>, 3034 <0x07410600 0x1a8>; 3035 #phy-cells = <0>; 3036 3037 #clock-cells = <0>; 3038 clock-output-names = "usb3_phy_pipe_clk_src"; 3039 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3040 clock-names = "pipe0"; 3041 }; 3042 }; 3043 3044 hsusb_phy1: phy@7411000 { 3045 compatible = "qcom,msm8996-qusb2-phy"; 3046 reg = <0x07411000 0x180>; 3047 #phy-cells = <0>; 3048 3049 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3050 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3051 clock-names = "cfg_ahb", "ref"; 3052 3053 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3054 nvmem-cells = <&qusb2p_hstx_trim>; 3055 status = "disabled"; 3056 }; 3057 3058 hsusb_phy2: phy@7412000 { 3059 compatible = "qcom,msm8996-qusb2-phy"; 3060 reg = <0x07412000 0x180>; 3061 #phy-cells = <0>; 3062 3063 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3064 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3065 clock-names = "cfg_ahb", "ref"; 3066 3067 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3068 nvmem-cells = <&qusb2s_hstx_trim>; 3069 status = "disabled"; 3070 }; 3071 3072 sdhc1: mmc@7464900 { 3073 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3074 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3075 reg-names = "hc", "core"; 3076 3077 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3079 interrupt-names = "hc_irq", "pwr_irq"; 3080 3081 clock-names = "iface", "core", "xo"; 3082 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3083 <&gcc GCC_SDCC1_APPS_CLK>, 3084 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3085 resets = <&gcc GCC_SDCC1_BCR>; 3086 3087 pinctrl-names = "default", "sleep"; 3088 pinctrl-0 = <&sdc1_state_on>; 3089 pinctrl-1 = <&sdc1_state_off>; 3090 3091 bus-width = <8>; 3092 non-removable; 3093 status = "disabled"; 3094 }; 3095 3096 sdhc2: mmc@74a4900 { 3097 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3098 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3099 reg-names = "hc", "core"; 3100 3101 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3103 interrupt-names = "hc_irq", "pwr_irq"; 3104 3105 clock-names = "iface", "core", "xo"; 3106 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3107 <&gcc GCC_SDCC2_APPS_CLK>, 3108 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3109 resets = <&gcc GCC_SDCC2_BCR>; 3110 3111 pinctrl-names = "default", "sleep"; 3112 pinctrl-0 = <&sdc2_state_on>; 3113 pinctrl-1 = <&sdc2_state_off>; 3114 3115 bus-width = <4>; 3116 status = "disabled"; 3117 }; 3118 3119 blsp1_dma: dma-controller@7544000 { 3120 compatible = "qcom,bam-v1.7.0"; 3121 reg = <0x07544000 0x2b000>; 3122 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3123 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3124 clock-names = "bam_clk"; 3125 qcom,controlled-remotely; 3126 #dma-cells = <1>; 3127 qcom,ee = <0>; 3128 }; 3129 3130 blsp1_uart2: serial@7570000 { 3131 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3132 reg = <0x07570000 0x1000>; 3133 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3134 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3135 <&gcc GCC_BLSP1_AHB_CLK>; 3136 clock-names = "core", "iface"; 3137 pinctrl-names = "default", "sleep"; 3138 pinctrl-0 = <&blsp1_uart2_default>; 3139 pinctrl-1 = <&blsp1_uart2_sleep>; 3140 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3141 dma-names = "tx", "rx"; 3142 status = "disabled"; 3143 }; 3144 3145 blsp1_spi1: spi@7575000 { 3146 compatible = "qcom,spi-qup-v2.2.1"; 3147 reg = <0x07575000 0x600>; 3148 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3149 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3150 <&gcc GCC_BLSP1_AHB_CLK>; 3151 clock-names = "core", "iface"; 3152 pinctrl-names = "default", "sleep"; 3153 pinctrl-0 = <&blsp1_spi1_default>; 3154 pinctrl-1 = <&blsp1_spi1_sleep>; 3155 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3156 dma-names = "tx", "rx"; 3157 #address-cells = <1>; 3158 #size-cells = <0>; 3159 status = "disabled"; 3160 }; 3161 3162 blsp1_i2c3: i2c@7577000 { 3163 compatible = "qcom,i2c-qup-v2.2.1"; 3164 reg = <0x07577000 0x1000>; 3165 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3166 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3167 <&gcc GCC_BLSP1_AHB_CLK>; 3168 clock-names = "core", "iface"; 3169 pinctrl-names = "default", "sleep"; 3170 pinctrl-0 = <&blsp1_i2c3_default>; 3171 pinctrl-1 = <&blsp1_i2c3_sleep>; 3172 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3173 dma-names = "tx", "rx"; 3174 #address-cells = <1>; 3175 #size-cells = <0>; 3176 status = "disabled"; 3177 }; 3178 3179 blsp1_i2c6: i2c@757a000 { 3180 compatible = "qcom,i2c-qup-v2.2.1"; 3181 reg = <0x757a000 0x1000>; 3182 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3183 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3184 <&gcc GCC_BLSP1_AHB_CLK>; 3185 clock-names = "core", "iface"; 3186 pinctrl-names = "default", "sleep"; 3187 pinctrl-0 = <&blsp1_i2c6_default>; 3188 pinctrl-1 = <&blsp1_i2c6_sleep>; 3189 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3190 dma-names = "tx", "rx"; 3191 #address-cells = <1>; 3192 #size-cells = <0>; 3193 status = "disabled"; 3194 }; 3195 3196 blsp2_dma: dma-controller@7584000 { 3197 compatible = "qcom,bam-v1.7.0"; 3198 reg = <0x07584000 0x2b000>; 3199 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3200 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3201 clock-names = "bam_clk"; 3202 qcom,controlled-remotely; 3203 #dma-cells = <1>; 3204 qcom,ee = <0>; 3205 }; 3206 3207 blsp2_uart2: serial@75b0000 { 3208 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3209 reg = <0x075b0000 0x1000>; 3210 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3211 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3212 <&gcc GCC_BLSP2_AHB_CLK>; 3213 clock-names = "core", "iface"; 3214 status = "disabled"; 3215 }; 3216 3217 blsp2_uart3: serial@75b1000 { 3218 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3219 reg = <0x075b1000 0x1000>; 3220 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3221 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3222 <&gcc GCC_BLSP2_AHB_CLK>; 3223 clock-names = "core", "iface"; 3224 status = "disabled"; 3225 }; 3226 3227 blsp2_i2c1: i2c@75b5000 { 3228 compatible = "qcom,i2c-qup-v2.2.1"; 3229 reg = <0x075b5000 0x1000>; 3230 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3231 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3232 <&gcc GCC_BLSP2_AHB_CLK>; 3233 clock-names = "core", "iface"; 3234 pinctrl-names = "default", "sleep"; 3235 pinctrl-0 = <&blsp2_i2c1_default>; 3236 pinctrl-1 = <&blsp2_i2c1_sleep>; 3237 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3238 dma-names = "tx", "rx"; 3239 #address-cells = <1>; 3240 #size-cells = <0>; 3241 status = "disabled"; 3242 }; 3243 3244 blsp2_i2c2: i2c@75b6000 { 3245 compatible = "qcom,i2c-qup-v2.2.1"; 3246 reg = <0x075b6000 0x1000>; 3247 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3248 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3249 <&gcc GCC_BLSP2_AHB_CLK>; 3250 clock-names = "core", "iface"; 3251 pinctrl-names = "default", "sleep"; 3252 pinctrl-0 = <&blsp2_i2c2_default>; 3253 pinctrl-1 = <&blsp2_i2c2_sleep>; 3254 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3255 dma-names = "tx", "rx"; 3256 #address-cells = <1>; 3257 #size-cells = <0>; 3258 status = "disabled"; 3259 }; 3260 3261 blsp2_i2c3: i2c@75b7000 { 3262 compatible = "qcom,i2c-qup-v2.2.1"; 3263 reg = <0x075b7000 0x1000>; 3264 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3265 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3266 <&gcc GCC_BLSP2_AHB_CLK>; 3267 clock-names = "core", "iface"; 3268 clock-frequency = <400000>; 3269 pinctrl-names = "default", "sleep"; 3270 pinctrl-0 = <&blsp2_i2c3_default>; 3271 pinctrl-1 = <&blsp2_i2c3_sleep>; 3272 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3273 dma-names = "tx", "rx"; 3274 #address-cells = <1>; 3275 #size-cells = <0>; 3276 status = "disabled"; 3277 }; 3278 3279 blsp2_i2c5: i2c@75b9000 { 3280 compatible = "qcom,i2c-qup-v2.2.1"; 3281 reg = <0x75b9000 0x1000>; 3282 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3283 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3284 <&gcc GCC_BLSP2_AHB_CLK>; 3285 clock-names = "core", "iface"; 3286 pinctrl-names = "default"; 3287 pinctrl-0 = <&blsp2_i2c5_default>; 3288 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3289 dma-names = "tx", "rx"; 3290 #address-cells = <1>; 3291 #size-cells = <0>; 3292 status = "disabled"; 3293 }; 3294 3295 blsp2_i2c6: i2c@75ba000 { 3296 compatible = "qcom,i2c-qup-v2.2.1"; 3297 reg = <0x75ba000 0x1000>; 3298 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3299 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3300 <&gcc GCC_BLSP2_AHB_CLK>; 3301 clock-names = "core", "iface"; 3302 pinctrl-names = "default", "sleep"; 3303 pinctrl-0 = <&blsp2_i2c6_default>; 3304 pinctrl-1 = <&blsp2_i2c6_sleep>; 3305 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3306 dma-names = "tx", "rx"; 3307 #address-cells = <1>; 3308 #size-cells = <0>; 3309 status = "disabled"; 3310 }; 3311 3312 blsp2_spi6: spi@75ba000 { 3313 compatible = "qcom,spi-qup-v2.2.1"; 3314 reg = <0x075ba000 0x600>; 3315 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3316 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3317 <&gcc GCC_BLSP2_AHB_CLK>; 3318 clock-names = "core", "iface"; 3319 pinctrl-names = "default", "sleep"; 3320 pinctrl-0 = <&blsp2_spi6_default>; 3321 pinctrl-1 = <&blsp2_spi6_sleep>; 3322 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3323 dma-names = "tx", "rx"; 3324 #address-cells = <1>; 3325 #size-cells = <0>; 3326 status = "disabled"; 3327 }; 3328 3329 usb2: usb@76f8800 { 3330 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3331 reg = <0x076f8800 0x400>; 3332 #address-cells = <1>; 3333 #size-cells = <1>; 3334 ranges; 3335 3336 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3337 <&gcc GCC_USB20_MASTER_CLK>, 3338 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3339 <&gcc GCC_USB20_SLEEP_CLK>, 3340 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3341 clock-names = "cfg_noc", 3342 "core", 3343 "iface", 3344 "sleep", 3345 "mock_utmi"; 3346 3347 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3348 <&gcc GCC_USB20_MASTER_CLK>; 3349 assigned-clock-rates = <19200000>, <60000000>; 3350 3351 power-domains = <&gcc USB30_GDSC>; 3352 qcom,select-utmi-as-pipe-clk; 3353 status = "disabled"; 3354 3355 usb2_dwc3: usb@7600000 { 3356 compatible = "snps,dwc3"; 3357 reg = <0x07600000 0xcc00>; 3358 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3359 phys = <&hsusb_phy2>; 3360 phy-names = "usb2-phy"; 3361 maximum-speed = "high-speed"; 3362 snps,dis_u2_susphy_quirk; 3363 snps,dis_enblslpm_quirk; 3364 }; 3365 }; 3366 3367 slimbam: dma-controller@9184000 { 3368 compatible = "qcom,bam-v1.7.0"; 3369 qcom,controlled-remotely; 3370 reg = <0x09184000 0x32000>; 3371 num-channels = <31>; 3372 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3373 #dma-cells = <1>; 3374 qcom,ee = <1>; 3375 qcom,num-ees = <2>; 3376 }; 3377 3378 slim_msm: slim-ngd@91c0000 { 3379 compatible = "qcom,slim-ngd-v1.5.0"; 3380 reg = <0x091c0000 0x2c000>; 3381 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3382 dmas = <&slimbam 3>, <&slimbam 4>; 3383 dma-names = "rx", "tx"; 3384 #address-cells = <1>; 3385 #size-cells = <0>; 3386 slim@1 { 3387 reg = <1>; 3388 #address-cells = <2>; 3389 #size-cells = <0>; 3390 3391 tasha_ifd: tas-ifd@0,0 { 3392 compatible = "slim217,1a0"; 3393 reg = <0 0>; 3394 }; 3395 3396 wcd9335: codec@1,0 { 3397 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 3398 pinctrl-names = "default"; 3399 3400 compatible = "slim217,1a0"; 3401 reg = <1 0>; 3402 3403 interrupt-parent = <&tlmm>; 3404 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3405 <53 IRQ_TYPE_LEVEL_HIGH>; 3406 interrupt-names = "intr1", "intr2"; 3407 interrupt-controller; 3408 #interrupt-cells = <1>; 3409 reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; 3410 3411 slim-ifc-dev = <&tasha_ifd>; 3412 3413 #sound-dai-cells = <1>; 3414 }; 3415 }; 3416 }; 3417 3418 adsp_pil: remoteproc@9300000 { 3419 compatible = "qcom,msm8996-adsp-pil"; 3420 reg = <0x09300000 0x80000>; 3421 3422 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3423 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3424 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3425 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3426 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3427 interrupt-names = "wdog", "fatal", "ready", 3428 "handover", "stop-ack"; 3429 3430 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3431 clock-names = "xo"; 3432 3433 memory-region = <&adsp_mem>; 3434 3435 qcom,smem-states = <&adsp_smp2p_out 0>; 3436 qcom,smem-state-names = "stop"; 3437 3438 power-domains = <&rpmpd MSM8996_VDDCX>; 3439 power-domain-names = "cx"; 3440 3441 status = "disabled"; 3442 3443 smd-edge { 3444 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3445 3446 label = "lpass"; 3447 mboxes = <&apcs_glb 8>; 3448 qcom,smd-edge = <1>; 3449 qcom,remote-pid = <2>; 3450 3451 apr { 3452 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3453 compatible = "qcom,apr-v2"; 3454 qcom,smd-channels = "apr_audio_svc"; 3455 qcom,domain = <APR_DOMAIN_ADSP>; 3456 #address-cells = <1>; 3457 #size-cells = <0>; 3458 3459 service@3 { 3460 reg = <APR_SVC_ADSP_CORE>; 3461 compatible = "qcom,q6core"; 3462 }; 3463 3464 q6afe: service@4 { 3465 compatible = "qcom,q6afe"; 3466 reg = <APR_SVC_AFE>; 3467 q6afedai: dais { 3468 compatible = "qcom,q6afe-dais"; 3469 #address-cells = <1>; 3470 #size-cells = <0>; 3471 #sound-dai-cells = <1>; 3472 dai@1 { 3473 reg = <1>; 3474 }; 3475 }; 3476 }; 3477 3478 q6asm: service@7 { 3479 compatible = "qcom,q6asm"; 3480 reg = <APR_SVC_ASM>; 3481 q6asmdai: dais { 3482 compatible = "qcom,q6asm-dais"; 3483 #address-cells = <1>; 3484 #size-cells = <0>; 3485 #sound-dai-cells = <1>; 3486 iommus = <&lpass_q6_smmu 1>; 3487 }; 3488 }; 3489 3490 q6adm: service@8 { 3491 compatible = "qcom,q6adm"; 3492 reg = <APR_SVC_ADM>; 3493 q6routing: routing { 3494 compatible = "qcom,q6adm-routing"; 3495 #sound-dai-cells = <0>; 3496 }; 3497 }; 3498 }; 3499 3500 }; 3501 }; 3502 3503 apcs_glb: mailbox@9820000 { 3504 compatible = "qcom,msm8996-apcs-hmss-global"; 3505 reg = <0x09820000 0x1000>; 3506 3507 #mbox-cells = <1>; 3508 #clock-cells = <0>; 3509 }; 3510 3511 timer@9840000 { 3512 #address-cells = <1>; 3513 #size-cells = <1>; 3514 ranges; 3515 compatible = "arm,armv7-timer-mem"; 3516 reg = <0x09840000 0x1000>; 3517 clock-frequency = <19200000>; 3518 3519 frame@9850000 { 3520 frame-number = <0>; 3521 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3523 reg = <0x09850000 0x1000>, 3524 <0x09860000 0x1000>; 3525 }; 3526 3527 frame@9870000 { 3528 frame-number = <1>; 3529 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3530 reg = <0x09870000 0x1000>; 3531 status = "disabled"; 3532 }; 3533 3534 frame@9880000 { 3535 frame-number = <2>; 3536 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3537 reg = <0x09880000 0x1000>; 3538 status = "disabled"; 3539 }; 3540 3541 frame@9890000 { 3542 frame-number = <3>; 3543 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3544 reg = <0x09890000 0x1000>; 3545 status = "disabled"; 3546 }; 3547 3548 frame@98a0000 { 3549 frame-number = <4>; 3550 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3551 reg = <0x098a0000 0x1000>; 3552 status = "disabled"; 3553 }; 3554 3555 frame@98b0000 { 3556 frame-number = <5>; 3557 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3558 reg = <0x098b0000 0x1000>; 3559 status = "disabled"; 3560 }; 3561 3562 frame@98c0000 { 3563 frame-number = <6>; 3564 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3565 reg = <0x098c0000 0x1000>; 3566 status = "disabled"; 3567 }; 3568 }; 3569 3570 saw3: syscon@9a10000 { 3571 compatible = "syscon"; 3572 reg = <0x09a10000 0x1000>; 3573 }; 3574 3575 cbf: clock-controller@9a11000 { 3576 compatible = "qcom,msm8996-cbf"; 3577 reg = <0x09a11000 0x10000>; 3578 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3579 #clock-cells = <0>; 3580 }; 3581 3582 intc: interrupt-controller@9bc0000 { 3583 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3584 #interrupt-cells = <3>; 3585 interrupt-controller; 3586 #redistributor-regions = <1>; 3587 redistributor-stride = <0x0 0x40000>; 3588 reg = <0x09bc0000 0x10000>, 3589 <0x09c00000 0x100000>; 3590 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3591 }; 3592 }; 3593 3594 sound: sound { 3595 }; 3596 3597 thermal-zones { 3598 cpu0-thermal { 3599 polling-delay-passive = <250>; 3600 polling-delay = <1000>; 3601 3602 thermal-sensors = <&tsens0 3>; 3603 3604 trips { 3605 cpu0_alert0: trip-point0 { 3606 temperature = <75000>; 3607 hysteresis = <2000>; 3608 type = "passive"; 3609 }; 3610 3611 cpu0_crit: cpu-crit { 3612 temperature = <110000>; 3613 hysteresis = <2000>; 3614 type = "critical"; 3615 }; 3616 }; 3617 }; 3618 3619 cpu1-thermal { 3620 polling-delay-passive = <250>; 3621 polling-delay = <1000>; 3622 3623 thermal-sensors = <&tsens0 5>; 3624 3625 trips { 3626 cpu1_alert0: trip-point0 { 3627 temperature = <75000>; 3628 hysteresis = <2000>; 3629 type = "passive"; 3630 }; 3631 3632 cpu1_crit: cpu-crit { 3633 temperature = <110000>; 3634 hysteresis = <2000>; 3635 type = "critical"; 3636 }; 3637 }; 3638 }; 3639 3640 cpu2-thermal { 3641 polling-delay-passive = <250>; 3642 polling-delay = <1000>; 3643 3644 thermal-sensors = <&tsens0 8>; 3645 3646 trips { 3647 cpu2_alert0: trip-point0 { 3648 temperature = <75000>; 3649 hysteresis = <2000>; 3650 type = "passive"; 3651 }; 3652 3653 cpu2_crit: cpu-crit { 3654 temperature = <110000>; 3655 hysteresis = <2000>; 3656 type = "critical"; 3657 }; 3658 }; 3659 }; 3660 3661 cpu3-thermal { 3662 polling-delay-passive = <250>; 3663 polling-delay = <1000>; 3664 3665 thermal-sensors = <&tsens0 10>; 3666 3667 trips { 3668 cpu3_alert0: trip-point0 { 3669 temperature = <75000>; 3670 hysteresis = <2000>; 3671 type = "passive"; 3672 }; 3673 3674 cpu3_crit: cpu-crit { 3675 temperature = <110000>; 3676 hysteresis = <2000>; 3677 type = "critical"; 3678 }; 3679 }; 3680 }; 3681 3682 gpu-top-thermal { 3683 polling-delay-passive = <250>; 3684 polling-delay = <1000>; 3685 3686 thermal-sensors = <&tsens1 6>; 3687 3688 trips { 3689 gpu1_alert0: trip-point0 { 3690 temperature = <90000>; 3691 hysteresis = <2000>; 3692 type = "passive"; 3693 }; 3694 }; 3695 3696 cooling-maps { 3697 map0 { 3698 trip = <&gpu1_alert0>; 3699 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3700 }; 3701 }; 3702 }; 3703 3704 gpu-bottom-thermal { 3705 polling-delay-passive = <250>; 3706 polling-delay = <1000>; 3707 3708 thermal-sensors = <&tsens1 7>; 3709 3710 trips { 3711 gpu2_alert0: trip-point0 { 3712 temperature = <90000>; 3713 hysteresis = <2000>; 3714 type = "passive"; 3715 }; 3716 }; 3717 3718 cooling-maps { 3719 map0 { 3720 trip = <&gpu2_alert0>; 3721 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3722 }; 3723 }; 3724 }; 3725 3726 m4m-thermal { 3727 polling-delay-passive = <250>; 3728 polling-delay = <1000>; 3729 3730 thermal-sensors = <&tsens0 1>; 3731 3732 trips { 3733 m4m_alert0: trip-point0 { 3734 temperature = <90000>; 3735 hysteresis = <2000>; 3736 type = "hot"; 3737 }; 3738 }; 3739 }; 3740 3741 l3-or-venus-thermal { 3742 polling-delay-passive = <250>; 3743 polling-delay = <1000>; 3744 3745 thermal-sensors = <&tsens0 2>; 3746 3747 trips { 3748 l3_or_venus_alert0: trip-point0 { 3749 temperature = <90000>; 3750 hysteresis = <2000>; 3751 type = "hot"; 3752 }; 3753 }; 3754 }; 3755 3756 cluster0-l2-thermal { 3757 polling-delay-passive = <250>; 3758 polling-delay = <1000>; 3759 3760 thermal-sensors = <&tsens0 7>; 3761 3762 trips { 3763 cluster0_l2_alert0: trip-point0 { 3764 temperature = <90000>; 3765 hysteresis = <2000>; 3766 type = "hot"; 3767 }; 3768 }; 3769 }; 3770 3771 cluster1-l2-thermal { 3772 polling-delay-passive = <250>; 3773 polling-delay = <1000>; 3774 3775 thermal-sensors = <&tsens0 12>; 3776 3777 trips { 3778 cluster1_l2_alert0: trip-point0 { 3779 temperature = <90000>; 3780 hysteresis = <2000>; 3781 type = "hot"; 3782 }; 3783 }; 3784 }; 3785 3786 camera-thermal { 3787 polling-delay-passive = <250>; 3788 polling-delay = <1000>; 3789 3790 thermal-sensors = <&tsens1 1>; 3791 3792 trips { 3793 camera_alert0: trip-point0 { 3794 temperature = <90000>; 3795 hysteresis = <2000>; 3796 type = "hot"; 3797 }; 3798 }; 3799 }; 3800 3801 q6-dsp-thermal { 3802 polling-delay-passive = <250>; 3803 polling-delay = <1000>; 3804 3805 thermal-sensors = <&tsens1 2>; 3806 3807 trips { 3808 q6_dsp_alert0: trip-point0 { 3809 temperature = <90000>; 3810 hysteresis = <2000>; 3811 type = "hot"; 3812 }; 3813 }; 3814 }; 3815 3816 mem-thermal { 3817 polling-delay-passive = <250>; 3818 polling-delay = <1000>; 3819 3820 thermal-sensors = <&tsens1 3>; 3821 3822 trips { 3823 mem_alert0: trip-point0 { 3824 temperature = <90000>; 3825 hysteresis = <2000>; 3826 type = "hot"; 3827 }; 3828 }; 3829 }; 3830 3831 modemtx-thermal { 3832 polling-delay-passive = <250>; 3833 polling-delay = <1000>; 3834 3835 thermal-sensors = <&tsens1 4>; 3836 3837 trips { 3838 modemtx_alert0: trip-point0 { 3839 temperature = <90000>; 3840 hysteresis = <2000>; 3841 type = "hot"; 3842 }; 3843 }; 3844 }; 3845 }; 3846 3847 timer { 3848 compatible = "arm,armv8-timer"; 3849 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3850 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3851 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3852 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3853 }; 3854}; 3855